intel_display.c 176 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include "drm_dp_helper.h"
  37. #include "drm_crtc_helper.h"
  38. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  39. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  40. static void intel_update_watermarks(struct drm_device *dev);
  41. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  42. static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  43. typedef struct {
  44. /* given values */
  45. int n;
  46. int m1, m2;
  47. int p1, p2;
  48. /* derived values */
  49. int dot;
  50. int vco;
  51. int m;
  52. int p;
  53. } intel_clock_t;
  54. typedef struct {
  55. int min, max;
  56. } intel_range_t;
  57. typedef struct {
  58. int dot_limit;
  59. int p2_slow, p2_fast;
  60. } intel_p2_t;
  61. #define INTEL_P2_NUM 2
  62. typedef struct intel_limit intel_limit_t;
  63. struct intel_limit {
  64. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  65. intel_p2_t p2;
  66. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  67. int, int, intel_clock_t *);
  68. };
  69. #define I8XX_DOT_MIN 25000
  70. #define I8XX_DOT_MAX 350000
  71. #define I8XX_VCO_MIN 930000
  72. #define I8XX_VCO_MAX 1400000
  73. #define I8XX_N_MIN 3
  74. #define I8XX_N_MAX 16
  75. #define I8XX_M_MIN 96
  76. #define I8XX_M_MAX 140
  77. #define I8XX_M1_MIN 18
  78. #define I8XX_M1_MAX 26
  79. #define I8XX_M2_MIN 6
  80. #define I8XX_M2_MAX 16
  81. #define I8XX_P_MIN 4
  82. #define I8XX_P_MAX 128
  83. #define I8XX_P1_MIN 2
  84. #define I8XX_P1_MAX 33
  85. #define I8XX_P1_LVDS_MIN 1
  86. #define I8XX_P1_LVDS_MAX 6
  87. #define I8XX_P2_SLOW 4
  88. #define I8XX_P2_FAST 2
  89. #define I8XX_P2_LVDS_SLOW 14
  90. #define I8XX_P2_LVDS_FAST 7
  91. #define I8XX_P2_SLOW_LIMIT 165000
  92. #define I9XX_DOT_MIN 20000
  93. #define I9XX_DOT_MAX 400000
  94. #define I9XX_VCO_MIN 1400000
  95. #define I9XX_VCO_MAX 2800000
  96. #define PINEVIEW_VCO_MIN 1700000
  97. #define PINEVIEW_VCO_MAX 3500000
  98. #define I9XX_N_MIN 1
  99. #define I9XX_N_MAX 6
  100. /* Pineview's Ncounter is a ring counter */
  101. #define PINEVIEW_N_MIN 3
  102. #define PINEVIEW_N_MAX 6
  103. #define I9XX_M_MIN 70
  104. #define I9XX_M_MAX 120
  105. #define PINEVIEW_M_MIN 2
  106. #define PINEVIEW_M_MAX 256
  107. #define I9XX_M1_MIN 10
  108. #define I9XX_M1_MAX 22
  109. #define I9XX_M2_MIN 5
  110. #define I9XX_M2_MAX 9
  111. /* Pineview M1 is reserved, and must be 0 */
  112. #define PINEVIEW_M1_MIN 0
  113. #define PINEVIEW_M1_MAX 0
  114. #define PINEVIEW_M2_MIN 0
  115. #define PINEVIEW_M2_MAX 254
  116. #define I9XX_P_SDVO_DAC_MIN 5
  117. #define I9XX_P_SDVO_DAC_MAX 80
  118. #define I9XX_P_LVDS_MIN 7
  119. #define I9XX_P_LVDS_MAX 98
  120. #define PINEVIEW_P_LVDS_MIN 7
  121. #define PINEVIEW_P_LVDS_MAX 112
  122. #define I9XX_P1_MIN 1
  123. #define I9XX_P1_MAX 8
  124. #define I9XX_P2_SDVO_DAC_SLOW 10
  125. #define I9XX_P2_SDVO_DAC_FAST 5
  126. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  127. #define I9XX_P2_LVDS_SLOW 14
  128. #define I9XX_P2_LVDS_FAST 7
  129. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  130. /*The parameter is for SDVO on G4x platform*/
  131. #define G4X_DOT_SDVO_MIN 25000
  132. #define G4X_DOT_SDVO_MAX 270000
  133. #define G4X_VCO_MIN 1750000
  134. #define G4X_VCO_MAX 3500000
  135. #define G4X_N_SDVO_MIN 1
  136. #define G4X_N_SDVO_MAX 4
  137. #define G4X_M_SDVO_MIN 104
  138. #define G4X_M_SDVO_MAX 138
  139. #define G4X_M1_SDVO_MIN 17
  140. #define G4X_M1_SDVO_MAX 23
  141. #define G4X_M2_SDVO_MIN 5
  142. #define G4X_M2_SDVO_MAX 11
  143. #define G4X_P_SDVO_MIN 10
  144. #define G4X_P_SDVO_MAX 30
  145. #define G4X_P1_SDVO_MIN 1
  146. #define G4X_P1_SDVO_MAX 3
  147. #define G4X_P2_SDVO_SLOW 10
  148. #define G4X_P2_SDVO_FAST 10
  149. #define G4X_P2_SDVO_LIMIT 270000
  150. /*The parameter is for HDMI_DAC on G4x platform*/
  151. #define G4X_DOT_HDMI_DAC_MIN 22000
  152. #define G4X_DOT_HDMI_DAC_MAX 400000
  153. #define G4X_N_HDMI_DAC_MIN 1
  154. #define G4X_N_HDMI_DAC_MAX 4
  155. #define G4X_M_HDMI_DAC_MIN 104
  156. #define G4X_M_HDMI_DAC_MAX 138
  157. #define G4X_M1_HDMI_DAC_MIN 16
  158. #define G4X_M1_HDMI_DAC_MAX 23
  159. #define G4X_M2_HDMI_DAC_MIN 5
  160. #define G4X_M2_HDMI_DAC_MAX 11
  161. #define G4X_P_HDMI_DAC_MIN 5
  162. #define G4X_P_HDMI_DAC_MAX 80
  163. #define G4X_P1_HDMI_DAC_MIN 1
  164. #define G4X_P1_HDMI_DAC_MAX 8
  165. #define G4X_P2_HDMI_DAC_SLOW 10
  166. #define G4X_P2_HDMI_DAC_FAST 5
  167. #define G4X_P2_HDMI_DAC_LIMIT 165000
  168. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  169. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  170. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  171. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  172. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  173. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  174. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  175. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  176. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  177. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  178. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  179. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  180. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  181. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  182. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  183. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  184. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  185. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  186. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  187. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  188. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  189. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  190. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  191. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  192. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  193. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  194. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  195. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  196. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  197. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  198. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  199. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  200. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  201. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  202. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  203. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  204. /*The parameter is for DISPLAY PORT on G4x platform*/
  205. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  206. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  207. #define G4X_N_DISPLAY_PORT_MIN 1
  208. #define G4X_N_DISPLAY_PORT_MAX 2
  209. #define G4X_M_DISPLAY_PORT_MIN 97
  210. #define G4X_M_DISPLAY_PORT_MAX 108
  211. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  212. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  213. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  214. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  215. #define G4X_P_DISPLAY_PORT_MIN 10
  216. #define G4X_P_DISPLAY_PORT_MAX 20
  217. #define G4X_P1_DISPLAY_PORT_MIN 1
  218. #define G4X_P1_DISPLAY_PORT_MAX 2
  219. #define G4X_P2_DISPLAY_PORT_SLOW 10
  220. #define G4X_P2_DISPLAY_PORT_FAST 10
  221. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  222. /* Ironlake / Sandybridge */
  223. /* as we calculate clock using (register_value + 2) for
  224. N/M1/M2, so here the range value for them is (actual_value-2).
  225. */
  226. #define IRONLAKE_DOT_MIN 25000
  227. #define IRONLAKE_DOT_MAX 350000
  228. #define IRONLAKE_VCO_MIN 1760000
  229. #define IRONLAKE_VCO_MAX 3510000
  230. #define IRONLAKE_M1_MIN 12
  231. #define IRONLAKE_M1_MAX 22
  232. #define IRONLAKE_M2_MIN 5
  233. #define IRONLAKE_M2_MAX 9
  234. #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
  235. /* We have parameter ranges for different type of outputs. */
  236. /* DAC & HDMI Refclk 120Mhz */
  237. #define IRONLAKE_DAC_N_MIN 1
  238. #define IRONLAKE_DAC_N_MAX 5
  239. #define IRONLAKE_DAC_M_MIN 79
  240. #define IRONLAKE_DAC_M_MAX 127
  241. #define IRONLAKE_DAC_P_MIN 5
  242. #define IRONLAKE_DAC_P_MAX 80
  243. #define IRONLAKE_DAC_P1_MIN 1
  244. #define IRONLAKE_DAC_P1_MAX 8
  245. #define IRONLAKE_DAC_P2_SLOW 10
  246. #define IRONLAKE_DAC_P2_FAST 5
  247. /* LVDS single-channel 120Mhz refclk */
  248. #define IRONLAKE_LVDS_S_N_MIN 1
  249. #define IRONLAKE_LVDS_S_N_MAX 3
  250. #define IRONLAKE_LVDS_S_M_MIN 79
  251. #define IRONLAKE_LVDS_S_M_MAX 118
  252. #define IRONLAKE_LVDS_S_P_MIN 28
  253. #define IRONLAKE_LVDS_S_P_MAX 112
  254. #define IRONLAKE_LVDS_S_P1_MIN 2
  255. #define IRONLAKE_LVDS_S_P1_MAX 8
  256. #define IRONLAKE_LVDS_S_P2_SLOW 14
  257. #define IRONLAKE_LVDS_S_P2_FAST 14
  258. /* LVDS dual-channel 120Mhz refclk */
  259. #define IRONLAKE_LVDS_D_N_MIN 1
  260. #define IRONLAKE_LVDS_D_N_MAX 3
  261. #define IRONLAKE_LVDS_D_M_MIN 79
  262. #define IRONLAKE_LVDS_D_M_MAX 127
  263. #define IRONLAKE_LVDS_D_P_MIN 14
  264. #define IRONLAKE_LVDS_D_P_MAX 56
  265. #define IRONLAKE_LVDS_D_P1_MIN 2
  266. #define IRONLAKE_LVDS_D_P1_MAX 8
  267. #define IRONLAKE_LVDS_D_P2_SLOW 7
  268. #define IRONLAKE_LVDS_D_P2_FAST 7
  269. /* LVDS single-channel 100Mhz refclk */
  270. #define IRONLAKE_LVDS_S_SSC_N_MIN 1
  271. #define IRONLAKE_LVDS_S_SSC_N_MAX 2
  272. #define IRONLAKE_LVDS_S_SSC_M_MIN 79
  273. #define IRONLAKE_LVDS_S_SSC_M_MAX 126
  274. #define IRONLAKE_LVDS_S_SSC_P_MIN 28
  275. #define IRONLAKE_LVDS_S_SSC_P_MAX 112
  276. #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
  277. #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
  278. #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
  279. #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
  280. /* LVDS dual-channel 100Mhz refclk */
  281. #define IRONLAKE_LVDS_D_SSC_N_MIN 1
  282. #define IRONLAKE_LVDS_D_SSC_N_MAX 3
  283. #define IRONLAKE_LVDS_D_SSC_M_MIN 79
  284. #define IRONLAKE_LVDS_D_SSC_M_MAX 126
  285. #define IRONLAKE_LVDS_D_SSC_P_MIN 14
  286. #define IRONLAKE_LVDS_D_SSC_P_MAX 42
  287. #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
  288. #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
  289. #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
  290. #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
  291. /* DisplayPort */
  292. #define IRONLAKE_DP_N_MIN 1
  293. #define IRONLAKE_DP_N_MAX 2
  294. #define IRONLAKE_DP_M_MIN 81
  295. #define IRONLAKE_DP_M_MAX 90
  296. #define IRONLAKE_DP_P_MIN 10
  297. #define IRONLAKE_DP_P_MAX 20
  298. #define IRONLAKE_DP_P2_FAST 10
  299. #define IRONLAKE_DP_P2_SLOW 10
  300. #define IRONLAKE_DP_P2_LIMIT 0
  301. #define IRONLAKE_DP_P1_MIN 1
  302. #define IRONLAKE_DP_P1_MAX 2
  303. /* FDI */
  304. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  305. static bool
  306. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  307. int target, int refclk, intel_clock_t *best_clock);
  308. static bool
  309. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  310. int target, int refclk, intel_clock_t *best_clock);
  311. static bool
  312. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  313. int target, int refclk, intel_clock_t *best_clock);
  314. static bool
  315. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  316. int target, int refclk, intel_clock_t *best_clock);
  317. static const intel_limit_t intel_limits_i8xx_dvo = {
  318. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  319. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  320. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  321. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  322. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  323. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  324. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  325. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  326. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  327. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  328. .find_pll = intel_find_best_PLL,
  329. };
  330. static const intel_limit_t intel_limits_i8xx_lvds = {
  331. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  332. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  333. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  334. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  335. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  336. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  337. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  338. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  339. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  340. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  341. .find_pll = intel_find_best_PLL,
  342. };
  343. static const intel_limit_t intel_limits_i9xx_sdvo = {
  344. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  345. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  346. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  347. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  348. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  349. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  350. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  351. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  352. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  353. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  354. .find_pll = intel_find_best_PLL,
  355. };
  356. static const intel_limit_t intel_limits_i9xx_lvds = {
  357. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  358. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  359. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  360. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  361. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  362. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  363. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  364. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  365. /* The single-channel range is 25-112Mhz, and dual-channel
  366. * is 80-224Mhz. Prefer single channel as much as possible.
  367. */
  368. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  369. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  370. .find_pll = intel_find_best_PLL,
  371. };
  372. /* below parameter and function is for G4X Chipset Family*/
  373. static const intel_limit_t intel_limits_g4x_sdvo = {
  374. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  375. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  376. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  377. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  378. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  379. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  380. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  381. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  382. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  383. .p2_slow = G4X_P2_SDVO_SLOW,
  384. .p2_fast = G4X_P2_SDVO_FAST
  385. },
  386. .find_pll = intel_g4x_find_best_PLL,
  387. };
  388. static const intel_limit_t intel_limits_g4x_hdmi = {
  389. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  390. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  391. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  392. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  393. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  394. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  395. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  396. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  397. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  398. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  399. .p2_fast = G4X_P2_HDMI_DAC_FAST
  400. },
  401. .find_pll = intel_g4x_find_best_PLL,
  402. };
  403. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  404. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  405. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  406. .vco = { .min = G4X_VCO_MIN,
  407. .max = G4X_VCO_MAX },
  408. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  409. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  410. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  411. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  412. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  413. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  414. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  415. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  416. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  417. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  418. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  419. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  420. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  421. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  422. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  423. },
  424. .find_pll = intel_g4x_find_best_PLL,
  425. };
  426. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  427. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  428. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  429. .vco = { .min = G4X_VCO_MIN,
  430. .max = G4X_VCO_MAX },
  431. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  432. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  433. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  434. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  435. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  436. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  437. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  438. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  439. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  440. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  441. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  442. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  443. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  444. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  445. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  446. },
  447. .find_pll = intel_g4x_find_best_PLL,
  448. };
  449. static const intel_limit_t intel_limits_g4x_display_port = {
  450. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  451. .max = G4X_DOT_DISPLAY_PORT_MAX },
  452. .vco = { .min = G4X_VCO_MIN,
  453. .max = G4X_VCO_MAX},
  454. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  455. .max = G4X_N_DISPLAY_PORT_MAX },
  456. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  457. .max = G4X_M_DISPLAY_PORT_MAX },
  458. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  459. .max = G4X_M1_DISPLAY_PORT_MAX },
  460. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  461. .max = G4X_M2_DISPLAY_PORT_MAX },
  462. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  463. .max = G4X_P_DISPLAY_PORT_MAX },
  464. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  465. .max = G4X_P1_DISPLAY_PORT_MAX},
  466. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  467. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  468. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  469. .find_pll = intel_find_pll_g4x_dp,
  470. };
  471. static const intel_limit_t intel_limits_pineview_sdvo = {
  472. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  473. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  474. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  475. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  476. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  477. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  478. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  479. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  480. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  481. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  482. .find_pll = intel_find_best_PLL,
  483. };
  484. static const intel_limit_t intel_limits_pineview_lvds = {
  485. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  486. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  487. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  488. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  489. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  490. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  491. .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
  492. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  493. /* Pineview only supports single-channel mode. */
  494. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  495. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  496. .find_pll = intel_find_best_PLL,
  497. };
  498. static const intel_limit_t intel_limits_ironlake_dac = {
  499. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  500. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  501. .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
  502. .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
  503. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  504. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  505. .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
  506. .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
  507. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  508. .p2_slow = IRONLAKE_DAC_P2_SLOW,
  509. .p2_fast = IRONLAKE_DAC_P2_FAST },
  510. .find_pll = intel_g4x_find_best_PLL,
  511. };
  512. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  513. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  514. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  515. .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
  516. .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
  517. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  518. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  519. .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
  520. .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
  521. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  522. .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
  523. .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
  524. .find_pll = intel_g4x_find_best_PLL,
  525. };
  526. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  527. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  528. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  529. .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
  530. .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
  531. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  532. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  533. .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
  534. .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
  535. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  536. .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
  537. .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
  538. .find_pll = intel_g4x_find_best_PLL,
  539. };
  540. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  541. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  542. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  543. .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
  544. .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
  545. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  546. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  547. .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
  548. .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
  549. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  550. .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
  551. .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
  552. .find_pll = intel_g4x_find_best_PLL,
  553. };
  554. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  555. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  556. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  557. .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
  558. .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
  559. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  560. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  561. .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
  562. .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
  563. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  564. .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
  565. .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
  566. .find_pll = intel_g4x_find_best_PLL,
  567. };
  568. static const intel_limit_t intel_limits_ironlake_display_port = {
  569. .dot = { .min = IRONLAKE_DOT_MIN,
  570. .max = IRONLAKE_DOT_MAX },
  571. .vco = { .min = IRONLAKE_VCO_MIN,
  572. .max = IRONLAKE_VCO_MAX},
  573. .n = { .min = IRONLAKE_DP_N_MIN,
  574. .max = IRONLAKE_DP_N_MAX },
  575. .m = { .min = IRONLAKE_DP_M_MIN,
  576. .max = IRONLAKE_DP_M_MAX },
  577. .m1 = { .min = IRONLAKE_M1_MIN,
  578. .max = IRONLAKE_M1_MAX },
  579. .m2 = { .min = IRONLAKE_M2_MIN,
  580. .max = IRONLAKE_M2_MAX },
  581. .p = { .min = IRONLAKE_DP_P_MIN,
  582. .max = IRONLAKE_DP_P_MAX },
  583. .p1 = { .min = IRONLAKE_DP_P1_MIN,
  584. .max = IRONLAKE_DP_P1_MAX},
  585. .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
  586. .p2_slow = IRONLAKE_DP_P2_SLOW,
  587. .p2_fast = IRONLAKE_DP_P2_FAST },
  588. .find_pll = intel_find_pll_ironlake_dp,
  589. };
  590. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
  591. {
  592. struct drm_device *dev = crtc->dev;
  593. struct drm_i915_private *dev_priv = dev->dev_private;
  594. const intel_limit_t *limit;
  595. int refclk = 120;
  596. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  597. if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
  598. refclk = 100;
  599. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  600. LVDS_CLKB_POWER_UP) {
  601. /* LVDS dual channel */
  602. if (refclk == 100)
  603. limit = &intel_limits_ironlake_dual_lvds_100m;
  604. else
  605. limit = &intel_limits_ironlake_dual_lvds;
  606. } else {
  607. if (refclk == 100)
  608. limit = &intel_limits_ironlake_single_lvds_100m;
  609. else
  610. limit = &intel_limits_ironlake_single_lvds;
  611. }
  612. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  613. HAS_eDP)
  614. limit = &intel_limits_ironlake_display_port;
  615. else
  616. limit = &intel_limits_ironlake_dac;
  617. return limit;
  618. }
  619. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  620. {
  621. struct drm_device *dev = crtc->dev;
  622. struct drm_i915_private *dev_priv = dev->dev_private;
  623. const intel_limit_t *limit;
  624. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  625. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  626. LVDS_CLKB_POWER_UP)
  627. /* LVDS with dual channel */
  628. limit = &intel_limits_g4x_dual_channel_lvds;
  629. else
  630. /* LVDS with dual channel */
  631. limit = &intel_limits_g4x_single_channel_lvds;
  632. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  633. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  634. limit = &intel_limits_g4x_hdmi;
  635. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  636. limit = &intel_limits_g4x_sdvo;
  637. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  638. limit = &intel_limits_g4x_display_port;
  639. } else /* The option is for other outputs */
  640. limit = &intel_limits_i9xx_sdvo;
  641. return limit;
  642. }
  643. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  644. {
  645. struct drm_device *dev = crtc->dev;
  646. const intel_limit_t *limit;
  647. if (HAS_PCH_SPLIT(dev))
  648. limit = intel_ironlake_limit(crtc);
  649. else if (IS_G4X(dev)) {
  650. limit = intel_g4x_limit(crtc);
  651. } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
  652. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  653. limit = &intel_limits_i9xx_lvds;
  654. else
  655. limit = &intel_limits_i9xx_sdvo;
  656. } else if (IS_PINEVIEW(dev)) {
  657. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  658. limit = &intel_limits_pineview_lvds;
  659. else
  660. limit = &intel_limits_pineview_sdvo;
  661. } else {
  662. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  663. limit = &intel_limits_i8xx_lvds;
  664. else
  665. limit = &intel_limits_i8xx_dvo;
  666. }
  667. return limit;
  668. }
  669. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  670. static void pineview_clock(int refclk, intel_clock_t *clock)
  671. {
  672. clock->m = clock->m2 + 2;
  673. clock->p = clock->p1 * clock->p2;
  674. clock->vco = refclk * clock->m / clock->n;
  675. clock->dot = clock->vco / clock->p;
  676. }
  677. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  678. {
  679. if (IS_PINEVIEW(dev)) {
  680. pineview_clock(refclk, clock);
  681. return;
  682. }
  683. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  684. clock->p = clock->p1 * clock->p2;
  685. clock->vco = refclk * clock->m / (clock->n + 2);
  686. clock->dot = clock->vco / clock->p;
  687. }
  688. /**
  689. * Returns whether any output on the specified pipe is of the specified type
  690. */
  691. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  692. {
  693. struct drm_device *dev = crtc->dev;
  694. struct drm_mode_config *mode_config = &dev->mode_config;
  695. struct drm_encoder *l_entry;
  696. list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
  697. if (l_entry && l_entry->crtc == crtc) {
  698. struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
  699. if (intel_encoder->type == type)
  700. return true;
  701. }
  702. }
  703. return false;
  704. }
  705. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  706. /**
  707. * Returns whether the given set of divisors are valid for a given refclk with
  708. * the given connectors.
  709. */
  710. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  711. {
  712. const intel_limit_t *limit = intel_limit (crtc);
  713. struct drm_device *dev = crtc->dev;
  714. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  715. INTELPllInvalid ("p1 out of range\n");
  716. if (clock->p < limit->p.min || limit->p.max < clock->p)
  717. INTELPllInvalid ("p out of range\n");
  718. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  719. INTELPllInvalid ("m2 out of range\n");
  720. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  721. INTELPllInvalid ("m1 out of range\n");
  722. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  723. INTELPllInvalid ("m1 <= m2\n");
  724. if (clock->m < limit->m.min || limit->m.max < clock->m)
  725. INTELPllInvalid ("m out of range\n");
  726. if (clock->n < limit->n.min || limit->n.max < clock->n)
  727. INTELPllInvalid ("n out of range\n");
  728. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  729. INTELPllInvalid ("vco out of range\n");
  730. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  731. * connector, etc., rather than just a single range.
  732. */
  733. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  734. INTELPllInvalid ("dot out of range\n");
  735. return true;
  736. }
  737. static bool
  738. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  739. int target, int refclk, intel_clock_t *best_clock)
  740. {
  741. struct drm_device *dev = crtc->dev;
  742. struct drm_i915_private *dev_priv = dev->dev_private;
  743. intel_clock_t clock;
  744. int err = target;
  745. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  746. (I915_READ(LVDS)) != 0) {
  747. /*
  748. * For LVDS, if the panel is on, just rely on its current
  749. * settings for dual-channel. We haven't figured out how to
  750. * reliably set up different single/dual channel state, if we
  751. * even can.
  752. */
  753. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  754. LVDS_CLKB_POWER_UP)
  755. clock.p2 = limit->p2.p2_fast;
  756. else
  757. clock.p2 = limit->p2.p2_slow;
  758. } else {
  759. if (target < limit->p2.dot_limit)
  760. clock.p2 = limit->p2.p2_slow;
  761. else
  762. clock.p2 = limit->p2.p2_fast;
  763. }
  764. memset (best_clock, 0, sizeof (*best_clock));
  765. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  766. clock.m1++) {
  767. for (clock.m2 = limit->m2.min;
  768. clock.m2 <= limit->m2.max; clock.m2++) {
  769. /* m1 is always 0 in Pineview */
  770. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  771. break;
  772. for (clock.n = limit->n.min;
  773. clock.n <= limit->n.max; clock.n++) {
  774. for (clock.p1 = limit->p1.min;
  775. clock.p1 <= limit->p1.max; clock.p1++) {
  776. int this_err;
  777. intel_clock(dev, refclk, &clock);
  778. if (!intel_PLL_is_valid(crtc, &clock))
  779. continue;
  780. this_err = abs(clock.dot - target);
  781. if (this_err < err) {
  782. *best_clock = clock;
  783. err = this_err;
  784. }
  785. }
  786. }
  787. }
  788. }
  789. return (err != target);
  790. }
  791. static bool
  792. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  793. int target, int refclk, intel_clock_t *best_clock)
  794. {
  795. struct drm_device *dev = crtc->dev;
  796. struct drm_i915_private *dev_priv = dev->dev_private;
  797. intel_clock_t clock;
  798. int max_n;
  799. bool found;
  800. /* approximately equals target * 0.00585 */
  801. int err_most = (target >> 8) + (target >> 9);
  802. found = false;
  803. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  804. int lvds_reg;
  805. if (HAS_PCH_SPLIT(dev))
  806. lvds_reg = PCH_LVDS;
  807. else
  808. lvds_reg = LVDS;
  809. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  810. LVDS_CLKB_POWER_UP)
  811. clock.p2 = limit->p2.p2_fast;
  812. else
  813. clock.p2 = limit->p2.p2_slow;
  814. } else {
  815. if (target < limit->p2.dot_limit)
  816. clock.p2 = limit->p2.p2_slow;
  817. else
  818. clock.p2 = limit->p2.p2_fast;
  819. }
  820. memset(best_clock, 0, sizeof(*best_clock));
  821. max_n = limit->n.max;
  822. /* based on hardware requirement, prefer smaller n to precision */
  823. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  824. /* based on hardware requirement, prefere larger m1,m2 */
  825. for (clock.m1 = limit->m1.max;
  826. clock.m1 >= limit->m1.min; clock.m1--) {
  827. for (clock.m2 = limit->m2.max;
  828. clock.m2 >= limit->m2.min; clock.m2--) {
  829. for (clock.p1 = limit->p1.max;
  830. clock.p1 >= limit->p1.min; clock.p1--) {
  831. int this_err;
  832. intel_clock(dev, refclk, &clock);
  833. if (!intel_PLL_is_valid(crtc, &clock))
  834. continue;
  835. this_err = abs(clock.dot - target) ;
  836. if (this_err < err_most) {
  837. *best_clock = clock;
  838. err_most = this_err;
  839. max_n = clock.n;
  840. found = true;
  841. }
  842. }
  843. }
  844. }
  845. }
  846. return found;
  847. }
  848. static bool
  849. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  850. int target, int refclk, intel_clock_t *best_clock)
  851. {
  852. struct drm_device *dev = crtc->dev;
  853. intel_clock_t clock;
  854. /* return directly when it is eDP */
  855. if (HAS_eDP)
  856. return true;
  857. if (target < 200000) {
  858. clock.n = 1;
  859. clock.p1 = 2;
  860. clock.p2 = 10;
  861. clock.m1 = 12;
  862. clock.m2 = 9;
  863. } else {
  864. clock.n = 2;
  865. clock.p1 = 1;
  866. clock.p2 = 10;
  867. clock.m1 = 14;
  868. clock.m2 = 8;
  869. }
  870. intel_clock(dev, refclk, &clock);
  871. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  872. return true;
  873. }
  874. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  875. static bool
  876. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  877. int target, int refclk, intel_clock_t *best_clock)
  878. {
  879. intel_clock_t clock;
  880. if (target < 200000) {
  881. clock.p1 = 2;
  882. clock.p2 = 10;
  883. clock.n = 2;
  884. clock.m1 = 23;
  885. clock.m2 = 8;
  886. } else {
  887. clock.p1 = 1;
  888. clock.p2 = 10;
  889. clock.n = 1;
  890. clock.m1 = 14;
  891. clock.m2 = 2;
  892. }
  893. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  894. clock.p = (clock.p1 * clock.p2);
  895. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  896. clock.vco = 0;
  897. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  898. return true;
  899. }
  900. void
  901. intel_wait_for_vblank(struct drm_device *dev)
  902. {
  903. /* Wait for 20ms, i.e. one cycle at 50hz. */
  904. if (in_dbg_master())
  905. mdelay(20); /* The kernel debugger cannot call msleep() */
  906. else
  907. msleep(20);
  908. }
  909. /* Parameters have changed, update FBC info */
  910. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  911. {
  912. struct drm_device *dev = crtc->dev;
  913. struct drm_i915_private *dev_priv = dev->dev_private;
  914. struct drm_framebuffer *fb = crtc->fb;
  915. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  916. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  917. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  918. int plane, i;
  919. u32 fbc_ctl, fbc_ctl2;
  920. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  921. if (fb->pitch < dev_priv->cfb_pitch)
  922. dev_priv->cfb_pitch = fb->pitch;
  923. /* FBC_CTL wants 64B units */
  924. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  925. dev_priv->cfb_fence = obj_priv->fence_reg;
  926. dev_priv->cfb_plane = intel_crtc->plane;
  927. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  928. /* Clear old tags */
  929. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  930. I915_WRITE(FBC_TAG + (i * 4), 0);
  931. /* Set it up... */
  932. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  933. if (obj_priv->tiling_mode != I915_TILING_NONE)
  934. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  935. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  936. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  937. /* enable it... */
  938. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  939. if (IS_I945GM(dev))
  940. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  941. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  942. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  943. if (obj_priv->tiling_mode != I915_TILING_NONE)
  944. fbc_ctl |= dev_priv->cfb_fence;
  945. I915_WRITE(FBC_CONTROL, fbc_ctl);
  946. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  947. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  948. }
  949. void i8xx_disable_fbc(struct drm_device *dev)
  950. {
  951. struct drm_i915_private *dev_priv = dev->dev_private;
  952. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  953. u32 fbc_ctl;
  954. if (!I915_HAS_FBC(dev))
  955. return;
  956. if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
  957. return; /* Already off, just return */
  958. /* Disable compression */
  959. fbc_ctl = I915_READ(FBC_CONTROL);
  960. fbc_ctl &= ~FBC_CTL_EN;
  961. I915_WRITE(FBC_CONTROL, fbc_ctl);
  962. /* Wait for compressing bit to clear */
  963. while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
  964. if (time_after(jiffies, timeout)) {
  965. DRM_DEBUG_DRIVER("FBC idle timed out\n");
  966. break;
  967. }
  968. ; /* do nothing */
  969. }
  970. intel_wait_for_vblank(dev);
  971. DRM_DEBUG_KMS("disabled FBC\n");
  972. }
  973. static bool i8xx_fbc_enabled(struct drm_device *dev)
  974. {
  975. struct drm_i915_private *dev_priv = dev->dev_private;
  976. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  977. }
  978. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  979. {
  980. struct drm_device *dev = crtc->dev;
  981. struct drm_i915_private *dev_priv = dev->dev_private;
  982. struct drm_framebuffer *fb = crtc->fb;
  983. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  984. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  985. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  986. int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
  987. DPFC_CTL_PLANEB);
  988. unsigned long stall_watermark = 200;
  989. u32 dpfc_ctl;
  990. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  991. dev_priv->cfb_fence = obj_priv->fence_reg;
  992. dev_priv->cfb_plane = intel_crtc->plane;
  993. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  994. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  995. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  996. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  997. } else {
  998. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  999. }
  1000. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1001. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1002. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1003. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1004. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  1005. /* enable it... */
  1006. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1007. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1008. }
  1009. void g4x_disable_fbc(struct drm_device *dev)
  1010. {
  1011. struct drm_i915_private *dev_priv = dev->dev_private;
  1012. u32 dpfc_ctl;
  1013. /* Disable compression */
  1014. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1015. dpfc_ctl &= ~DPFC_CTL_EN;
  1016. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1017. intel_wait_for_vblank(dev);
  1018. DRM_DEBUG_KMS("disabled FBC\n");
  1019. }
  1020. static bool g4x_fbc_enabled(struct drm_device *dev)
  1021. {
  1022. struct drm_i915_private *dev_priv = dev->dev_private;
  1023. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1024. }
  1025. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1026. {
  1027. struct drm_device *dev = crtc->dev;
  1028. struct drm_i915_private *dev_priv = dev->dev_private;
  1029. struct drm_framebuffer *fb = crtc->fb;
  1030. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1031. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  1032. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1033. int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
  1034. DPFC_CTL_PLANEB;
  1035. unsigned long stall_watermark = 200;
  1036. u32 dpfc_ctl;
  1037. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  1038. dev_priv->cfb_fence = obj_priv->fence_reg;
  1039. dev_priv->cfb_plane = intel_crtc->plane;
  1040. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1041. dpfc_ctl &= DPFC_RESERVED;
  1042. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  1043. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  1044. dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
  1045. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  1046. } else {
  1047. I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  1048. }
  1049. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1050. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1051. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1052. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1053. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  1054. I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
  1055. /* enable it... */
  1056. I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
  1057. DPFC_CTL_EN);
  1058. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1059. }
  1060. void ironlake_disable_fbc(struct drm_device *dev)
  1061. {
  1062. struct drm_i915_private *dev_priv = dev->dev_private;
  1063. u32 dpfc_ctl;
  1064. /* Disable compression */
  1065. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1066. dpfc_ctl &= ~DPFC_CTL_EN;
  1067. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1068. intel_wait_for_vblank(dev);
  1069. DRM_DEBUG_KMS("disabled FBC\n");
  1070. }
  1071. static bool ironlake_fbc_enabled(struct drm_device *dev)
  1072. {
  1073. struct drm_i915_private *dev_priv = dev->dev_private;
  1074. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  1075. }
  1076. bool intel_fbc_enabled(struct drm_device *dev)
  1077. {
  1078. struct drm_i915_private *dev_priv = dev->dev_private;
  1079. if (!dev_priv->display.fbc_enabled)
  1080. return false;
  1081. return dev_priv->display.fbc_enabled(dev);
  1082. }
  1083. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1084. {
  1085. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1086. if (!dev_priv->display.enable_fbc)
  1087. return;
  1088. dev_priv->display.enable_fbc(crtc, interval);
  1089. }
  1090. void intel_disable_fbc(struct drm_device *dev)
  1091. {
  1092. struct drm_i915_private *dev_priv = dev->dev_private;
  1093. if (!dev_priv->display.disable_fbc)
  1094. return;
  1095. dev_priv->display.disable_fbc(dev);
  1096. }
  1097. /**
  1098. * intel_update_fbc - enable/disable FBC as needed
  1099. * @crtc: CRTC to point the compressor at
  1100. * @mode: mode in use
  1101. *
  1102. * Set up the framebuffer compression hardware at mode set time. We
  1103. * enable it if possible:
  1104. * - plane A only (on pre-965)
  1105. * - no pixel mulitply/line duplication
  1106. * - no alpha buffer discard
  1107. * - no dual wide
  1108. * - framebuffer <= 2048 in width, 1536 in height
  1109. *
  1110. * We can't assume that any compression will take place (worst case),
  1111. * so the compressed buffer has to be the same size as the uncompressed
  1112. * one. It also must reside (along with the line length buffer) in
  1113. * stolen memory.
  1114. *
  1115. * We need to enable/disable FBC on a global basis.
  1116. */
  1117. static void intel_update_fbc(struct drm_crtc *crtc,
  1118. struct drm_display_mode *mode)
  1119. {
  1120. struct drm_device *dev = crtc->dev;
  1121. struct drm_i915_private *dev_priv = dev->dev_private;
  1122. struct drm_framebuffer *fb = crtc->fb;
  1123. struct intel_framebuffer *intel_fb;
  1124. struct drm_i915_gem_object *obj_priv;
  1125. struct drm_crtc *tmp_crtc;
  1126. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1127. int plane = intel_crtc->plane;
  1128. int crtcs_enabled = 0;
  1129. DRM_DEBUG_KMS("\n");
  1130. if (!i915_powersave)
  1131. return;
  1132. if (!I915_HAS_FBC(dev))
  1133. return;
  1134. if (!crtc->fb)
  1135. return;
  1136. intel_fb = to_intel_framebuffer(fb);
  1137. obj_priv = to_intel_bo(intel_fb->obj);
  1138. /*
  1139. * If FBC is already on, we just have to verify that we can
  1140. * keep it that way...
  1141. * Need to disable if:
  1142. * - more than one pipe is active
  1143. * - changing FBC params (stride, fence, mode)
  1144. * - new fb is too large to fit in compressed buffer
  1145. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1146. */
  1147. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  1148. if (tmp_crtc->enabled)
  1149. crtcs_enabled++;
  1150. }
  1151. DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
  1152. if (crtcs_enabled > 1) {
  1153. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  1154. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  1155. goto out_disable;
  1156. }
  1157. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1158. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1159. "compression\n");
  1160. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1161. goto out_disable;
  1162. }
  1163. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  1164. (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
  1165. DRM_DEBUG_KMS("mode incompatible with compression, "
  1166. "disabling\n");
  1167. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1168. goto out_disable;
  1169. }
  1170. if ((mode->hdisplay > 2048) ||
  1171. (mode->vdisplay > 1536)) {
  1172. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1173. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1174. goto out_disable;
  1175. }
  1176. if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
  1177. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1178. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1179. goto out_disable;
  1180. }
  1181. if (obj_priv->tiling_mode != I915_TILING_X) {
  1182. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1183. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1184. goto out_disable;
  1185. }
  1186. /* If the kernel debugger is active, always disable compression */
  1187. if (in_dbg_master())
  1188. goto out_disable;
  1189. if (intel_fbc_enabled(dev)) {
  1190. /* We can re-enable it in this case, but need to update pitch */
  1191. if ((fb->pitch > dev_priv->cfb_pitch) ||
  1192. (obj_priv->fence_reg != dev_priv->cfb_fence) ||
  1193. (plane != dev_priv->cfb_plane))
  1194. intel_disable_fbc(dev);
  1195. }
  1196. /* Now try to turn it back on if possible */
  1197. if (!intel_fbc_enabled(dev))
  1198. intel_enable_fbc(crtc, 500);
  1199. return;
  1200. out_disable:
  1201. /* Multiple disables should be harmless */
  1202. if (intel_fbc_enabled(dev)) {
  1203. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1204. intel_disable_fbc(dev);
  1205. }
  1206. }
  1207. int
  1208. intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
  1209. {
  1210. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  1211. u32 alignment;
  1212. int ret;
  1213. switch (obj_priv->tiling_mode) {
  1214. case I915_TILING_NONE:
  1215. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1216. alignment = 128 * 1024;
  1217. else if (IS_I965G(dev))
  1218. alignment = 4 * 1024;
  1219. else
  1220. alignment = 64 * 1024;
  1221. break;
  1222. case I915_TILING_X:
  1223. /* pin() will align the object as required by fence */
  1224. alignment = 0;
  1225. break;
  1226. case I915_TILING_Y:
  1227. /* FIXME: Is this true? */
  1228. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1229. return -EINVAL;
  1230. default:
  1231. BUG();
  1232. }
  1233. ret = i915_gem_object_pin(obj, alignment);
  1234. if (ret != 0)
  1235. return ret;
  1236. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1237. * fence, whereas 965+ only requires a fence if using
  1238. * framebuffer compression. For simplicity, we always install
  1239. * a fence as the cost is not that onerous.
  1240. */
  1241. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1242. obj_priv->tiling_mode != I915_TILING_NONE) {
  1243. ret = i915_gem_object_get_fence_reg(obj);
  1244. if (ret != 0) {
  1245. i915_gem_object_unpin(obj);
  1246. return ret;
  1247. }
  1248. }
  1249. return 0;
  1250. }
  1251. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1252. static int
  1253. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1254. int x, int y)
  1255. {
  1256. struct drm_device *dev = crtc->dev;
  1257. struct drm_i915_private *dev_priv = dev->dev_private;
  1258. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1259. struct intel_framebuffer *intel_fb;
  1260. struct drm_i915_gem_object *obj_priv;
  1261. struct drm_gem_object *obj;
  1262. int plane = intel_crtc->plane;
  1263. unsigned long Start, Offset;
  1264. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1265. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1266. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1267. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1268. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1269. u32 dspcntr;
  1270. switch (plane) {
  1271. case 0:
  1272. case 1:
  1273. break;
  1274. default:
  1275. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1276. return -EINVAL;
  1277. }
  1278. intel_fb = to_intel_framebuffer(fb);
  1279. obj = intel_fb->obj;
  1280. obj_priv = to_intel_bo(obj);
  1281. dspcntr = I915_READ(dspcntr_reg);
  1282. /* Mask out pixel format bits in case we change it */
  1283. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1284. switch (fb->bits_per_pixel) {
  1285. case 8:
  1286. dspcntr |= DISPPLANE_8BPP;
  1287. break;
  1288. case 16:
  1289. if (fb->depth == 15)
  1290. dspcntr |= DISPPLANE_15_16BPP;
  1291. else
  1292. dspcntr |= DISPPLANE_16BPP;
  1293. break;
  1294. case 24:
  1295. case 32:
  1296. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1297. break;
  1298. default:
  1299. DRM_ERROR("Unknown color depth\n");
  1300. return -EINVAL;
  1301. }
  1302. if (IS_I965G(dev)) {
  1303. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1304. dspcntr |= DISPPLANE_TILED;
  1305. else
  1306. dspcntr &= ~DISPPLANE_TILED;
  1307. }
  1308. if (IS_IRONLAKE(dev))
  1309. /* must disable */
  1310. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1311. I915_WRITE(dspcntr_reg, dspcntr);
  1312. Start = obj_priv->gtt_offset;
  1313. Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
  1314. DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
  1315. I915_WRITE(dspstride, fb->pitch);
  1316. if (IS_I965G(dev)) {
  1317. I915_WRITE(dspbase, Offset);
  1318. I915_READ(dspbase);
  1319. I915_WRITE(dspsurf, Start);
  1320. I915_READ(dspsurf);
  1321. I915_WRITE(dsptileoff, (y << 16) | x);
  1322. } else {
  1323. I915_WRITE(dspbase, Start + Offset);
  1324. I915_READ(dspbase);
  1325. }
  1326. if ((IS_I965G(dev) || plane == 0))
  1327. intel_update_fbc(crtc, &crtc->mode);
  1328. intel_wait_for_vblank(dev);
  1329. intel_increase_pllclock(crtc, true);
  1330. return 0;
  1331. }
  1332. static int
  1333. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1334. struct drm_framebuffer *old_fb)
  1335. {
  1336. struct drm_device *dev = crtc->dev;
  1337. struct drm_i915_private *dev_priv = dev->dev_private;
  1338. struct drm_i915_master_private *master_priv;
  1339. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1340. struct intel_framebuffer *intel_fb;
  1341. struct drm_i915_gem_object *obj_priv;
  1342. struct drm_gem_object *obj;
  1343. int pipe = intel_crtc->pipe;
  1344. int plane = intel_crtc->plane;
  1345. unsigned long Start, Offset;
  1346. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1347. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1348. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1349. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1350. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1351. u32 dspcntr;
  1352. int ret;
  1353. /* no fb bound */
  1354. if (!crtc->fb) {
  1355. DRM_DEBUG_KMS("No FB bound\n");
  1356. return 0;
  1357. }
  1358. switch (plane) {
  1359. case 0:
  1360. case 1:
  1361. break;
  1362. default:
  1363. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1364. return -EINVAL;
  1365. }
  1366. intel_fb = to_intel_framebuffer(crtc->fb);
  1367. obj = intel_fb->obj;
  1368. obj_priv = to_intel_bo(obj);
  1369. mutex_lock(&dev->struct_mutex);
  1370. ret = intel_pin_and_fence_fb_obj(dev, obj);
  1371. if (ret != 0) {
  1372. mutex_unlock(&dev->struct_mutex);
  1373. return ret;
  1374. }
  1375. ret = i915_gem_object_set_to_display_plane(obj);
  1376. if (ret != 0) {
  1377. i915_gem_object_unpin(obj);
  1378. mutex_unlock(&dev->struct_mutex);
  1379. return ret;
  1380. }
  1381. dspcntr = I915_READ(dspcntr_reg);
  1382. /* Mask out pixel format bits in case we change it */
  1383. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1384. switch (crtc->fb->bits_per_pixel) {
  1385. case 8:
  1386. dspcntr |= DISPPLANE_8BPP;
  1387. break;
  1388. case 16:
  1389. if (crtc->fb->depth == 15)
  1390. dspcntr |= DISPPLANE_15_16BPP;
  1391. else
  1392. dspcntr |= DISPPLANE_16BPP;
  1393. break;
  1394. case 24:
  1395. case 32:
  1396. if (crtc->fb->depth == 30)
  1397. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1398. else
  1399. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1400. break;
  1401. default:
  1402. DRM_ERROR("Unknown color depth\n");
  1403. i915_gem_object_unpin(obj);
  1404. mutex_unlock(&dev->struct_mutex);
  1405. return -EINVAL;
  1406. }
  1407. if (IS_I965G(dev)) {
  1408. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1409. dspcntr |= DISPPLANE_TILED;
  1410. else
  1411. dspcntr &= ~DISPPLANE_TILED;
  1412. }
  1413. if (HAS_PCH_SPLIT(dev))
  1414. /* must disable */
  1415. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1416. I915_WRITE(dspcntr_reg, dspcntr);
  1417. Start = obj_priv->gtt_offset;
  1418. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  1419. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1420. Start, Offset, x, y, crtc->fb->pitch);
  1421. I915_WRITE(dspstride, crtc->fb->pitch);
  1422. if (IS_I965G(dev)) {
  1423. I915_WRITE(dspbase, Offset);
  1424. I915_READ(dspbase);
  1425. I915_WRITE(dspsurf, Start);
  1426. I915_READ(dspsurf);
  1427. I915_WRITE(dsptileoff, (y << 16) | x);
  1428. } else {
  1429. I915_WRITE(dspbase, Start + Offset);
  1430. I915_READ(dspbase);
  1431. }
  1432. if ((IS_I965G(dev) || plane == 0))
  1433. intel_update_fbc(crtc, &crtc->mode);
  1434. intel_wait_for_vblank(dev);
  1435. if (old_fb) {
  1436. intel_fb = to_intel_framebuffer(old_fb);
  1437. obj_priv = to_intel_bo(intel_fb->obj);
  1438. i915_gem_object_unpin(intel_fb->obj);
  1439. }
  1440. intel_increase_pllclock(crtc, true);
  1441. mutex_unlock(&dev->struct_mutex);
  1442. if (!dev->primary->master)
  1443. return 0;
  1444. master_priv = dev->primary->master->driver_priv;
  1445. if (!master_priv->sarea_priv)
  1446. return 0;
  1447. if (pipe) {
  1448. master_priv->sarea_priv->pipeB_x = x;
  1449. master_priv->sarea_priv->pipeB_y = y;
  1450. } else {
  1451. master_priv->sarea_priv->pipeA_x = x;
  1452. master_priv->sarea_priv->pipeA_y = y;
  1453. }
  1454. return 0;
  1455. }
  1456. /* Disable the VGA plane that we never use */
  1457. static void i915_disable_vga (struct drm_device *dev)
  1458. {
  1459. struct drm_i915_private *dev_priv = dev->dev_private;
  1460. u8 sr1;
  1461. u32 vga_reg;
  1462. if (HAS_PCH_SPLIT(dev))
  1463. vga_reg = CPU_VGACNTRL;
  1464. else
  1465. vga_reg = VGACNTRL;
  1466. if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
  1467. return;
  1468. I915_WRITE8(VGA_SR_INDEX, 1);
  1469. sr1 = I915_READ8(VGA_SR_DATA);
  1470. I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
  1471. udelay(100);
  1472. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  1473. }
  1474. static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
  1475. {
  1476. struct drm_device *dev = crtc->dev;
  1477. struct drm_i915_private *dev_priv = dev->dev_private;
  1478. u32 dpa_ctl;
  1479. DRM_DEBUG_KMS("\n");
  1480. dpa_ctl = I915_READ(DP_A);
  1481. dpa_ctl &= ~DP_PLL_ENABLE;
  1482. I915_WRITE(DP_A, dpa_ctl);
  1483. }
  1484. static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
  1485. {
  1486. struct drm_device *dev = crtc->dev;
  1487. struct drm_i915_private *dev_priv = dev->dev_private;
  1488. u32 dpa_ctl;
  1489. dpa_ctl = I915_READ(DP_A);
  1490. dpa_ctl |= DP_PLL_ENABLE;
  1491. I915_WRITE(DP_A, dpa_ctl);
  1492. udelay(200);
  1493. }
  1494. static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
  1495. {
  1496. struct drm_device *dev = crtc->dev;
  1497. struct drm_i915_private *dev_priv = dev->dev_private;
  1498. u32 dpa_ctl;
  1499. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1500. dpa_ctl = I915_READ(DP_A);
  1501. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1502. if (clock < 200000) {
  1503. u32 temp;
  1504. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1505. /* workaround for 160Mhz:
  1506. 1) program 0x4600c bits 15:0 = 0x8124
  1507. 2) program 0x46010 bit 0 = 1
  1508. 3) program 0x46034 bit 24 = 1
  1509. 4) program 0x64000 bit 14 = 1
  1510. */
  1511. temp = I915_READ(0x4600c);
  1512. temp &= 0xffff0000;
  1513. I915_WRITE(0x4600c, temp | 0x8124);
  1514. temp = I915_READ(0x46010);
  1515. I915_WRITE(0x46010, temp | 1);
  1516. temp = I915_READ(0x46034);
  1517. I915_WRITE(0x46034, temp | (1 << 24));
  1518. } else {
  1519. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1520. }
  1521. I915_WRITE(DP_A, dpa_ctl);
  1522. udelay(500);
  1523. }
  1524. /* The FDI link training functions for ILK/Ibexpeak. */
  1525. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1526. {
  1527. struct drm_device *dev = crtc->dev;
  1528. struct drm_i915_private *dev_priv = dev->dev_private;
  1529. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1530. int pipe = intel_crtc->pipe;
  1531. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1532. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1533. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1534. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1535. u32 temp, tries = 0;
  1536. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1537. for train result */
  1538. temp = I915_READ(fdi_rx_imr_reg);
  1539. temp &= ~FDI_RX_SYMBOL_LOCK;
  1540. temp &= ~FDI_RX_BIT_LOCK;
  1541. I915_WRITE(fdi_rx_imr_reg, temp);
  1542. I915_READ(fdi_rx_imr_reg);
  1543. udelay(150);
  1544. /* enable CPU FDI TX and PCH FDI RX */
  1545. temp = I915_READ(fdi_tx_reg);
  1546. temp |= FDI_TX_ENABLE;
  1547. temp &= ~(7 << 19);
  1548. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1549. temp &= ~FDI_LINK_TRAIN_NONE;
  1550. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1551. I915_WRITE(fdi_tx_reg, temp);
  1552. I915_READ(fdi_tx_reg);
  1553. temp = I915_READ(fdi_rx_reg);
  1554. temp &= ~FDI_LINK_TRAIN_NONE;
  1555. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1556. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1557. I915_READ(fdi_rx_reg);
  1558. udelay(150);
  1559. for (tries = 0; tries < 5; tries++) {
  1560. temp = I915_READ(fdi_rx_iir_reg);
  1561. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1562. if ((temp & FDI_RX_BIT_LOCK)) {
  1563. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1564. I915_WRITE(fdi_rx_iir_reg,
  1565. temp | FDI_RX_BIT_LOCK);
  1566. break;
  1567. }
  1568. }
  1569. if (tries == 5)
  1570. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1571. /* Train 2 */
  1572. temp = I915_READ(fdi_tx_reg);
  1573. temp &= ~FDI_LINK_TRAIN_NONE;
  1574. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1575. I915_WRITE(fdi_tx_reg, temp);
  1576. temp = I915_READ(fdi_rx_reg);
  1577. temp &= ~FDI_LINK_TRAIN_NONE;
  1578. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1579. I915_WRITE(fdi_rx_reg, temp);
  1580. udelay(150);
  1581. tries = 0;
  1582. for (tries = 0; tries < 5; tries++) {
  1583. temp = I915_READ(fdi_rx_iir_reg);
  1584. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1585. if (temp & FDI_RX_SYMBOL_LOCK) {
  1586. I915_WRITE(fdi_rx_iir_reg,
  1587. temp | FDI_RX_SYMBOL_LOCK);
  1588. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1589. break;
  1590. }
  1591. }
  1592. if (tries == 5)
  1593. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1594. DRM_DEBUG_KMS("FDI train done\n");
  1595. }
  1596. static int snb_b_fdi_train_param [] = {
  1597. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  1598. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  1599. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  1600. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  1601. };
  1602. /* The FDI link training functions for SNB/Cougarpoint. */
  1603. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  1604. {
  1605. struct drm_device *dev = crtc->dev;
  1606. struct drm_i915_private *dev_priv = dev->dev_private;
  1607. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1608. int pipe = intel_crtc->pipe;
  1609. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1610. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1611. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1612. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1613. u32 temp, i;
  1614. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1615. for train result */
  1616. temp = I915_READ(fdi_rx_imr_reg);
  1617. temp &= ~FDI_RX_SYMBOL_LOCK;
  1618. temp &= ~FDI_RX_BIT_LOCK;
  1619. I915_WRITE(fdi_rx_imr_reg, temp);
  1620. I915_READ(fdi_rx_imr_reg);
  1621. udelay(150);
  1622. /* enable CPU FDI TX and PCH FDI RX */
  1623. temp = I915_READ(fdi_tx_reg);
  1624. temp |= FDI_TX_ENABLE;
  1625. temp &= ~(7 << 19);
  1626. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1627. temp &= ~FDI_LINK_TRAIN_NONE;
  1628. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1629. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1630. /* SNB-B */
  1631. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1632. I915_WRITE(fdi_tx_reg, temp);
  1633. I915_READ(fdi_tx_reg);
  1634. temp = I915_READ(fdi_rx_reg);
  1635. if (HAS_PCH_CPT(dev)) {
  1636. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1637. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1638. } else {
  1639. temp &= ~FDI_LINK_TRAIN_NONE;
  1640. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1641. }
  1642. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1643. I915_READ(fdi_rx_reg);
  1644. udelay(150);
  1645. for (i = 0; i < 4; i++ ) {
  1646. temp = I915_READ(fdi_tx_reg);
  1647. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1648. temp |= snb_b_fdi_train_param[i];
  1649. I915_WRITE(fdi_tx_reg, temp);
  1650. udelay(500);
  1651. temp = I915_READ(fdi_rx_iir_reg);
  1652. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1653. if (temp & FDI_RX_BIT_LOCK) {
  1654. I915_WRITE(fdi_rx_iir_reg,
  1655. temp | FDI_RX_BIT_LOCK);
  1656. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1657. break;
  1658. }
  1659. }
  1660. if (i == 4)
  1661. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1662. /* Train 2 */
  1663. temp = I915_READ(fdi_tx_reg);
  1664. temp &= ~FDI_LINK_TRAIN_NONE;
  1665. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1666. if (IS_GEN6(dev)) {
  1667. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1668. /* SNB-B */
  1669. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1670. }
  1671. I915_WRITE(fdi_tx_reg, temp);
  1672. temp = I915_READ(fdi_rx_reg);
  1673. if (HAS_PCH_CPT(dev)) {
  1674. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1675. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  1676. } else {
  1677. temp &= ~FDI_LINK_TRAIN_NONE;
  1678. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1679. }
  1680. I915_WRITE(fdi_rx_reg, temp);
  1681. udelay(150);
  1682. for (i = 0; i < 4; i++ ) {
  1683. temp = I915_READ(fdi_tx_reg);
  1684. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1685. temp |= snb_b_fdi_train_param[i];
  1686. I915_WRITE(fdi_tx_reg, temp);
  1687. udelay(500);
  1688. temp = I915_READ(fdi_rx_iir_reg);
  1689. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1690. if (temp & FDI_RX_SYMBOL_LOCK) {
  1691. I915_WRITE(fdi_rx_iir_reg,
  1692. temp | FDI_RX_SYMBOL_LOCK);
  1693. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1694. break;
  1695. }
  1696. }
  1697. if (i == 4)
  1698. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1699. DRM_DEBUG_KMS("FDI train done.\n");
  1700. }
  1701. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  1702. {
  1703. struct drm_device *dev = crtc->dev;
  1704. struct drm_i915_private *dev_priv = dev->dev_private;
  1705. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1706. int pipe = intel_crtc->pipe;
  1707. int plane = intel_crtc->plane;
  1708. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1709. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1710. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1711. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1712. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1713. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1714. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1715. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  1716. int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
  1717. int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
  1718. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1719. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1720. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1721. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1722. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1723. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1724. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  1725. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  1726. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  1727. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  1728. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  1729. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  1730. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  1731. u32 temp;
  1732. int n;
  1733. u32 pipe_bpc;
  1734. temp = I915_READ(pipeconf_reg);
  1735. pipe_bpc = temp & PIPE_BPC_MASK;
  1736. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1737. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1738. */
  1739. switch (mode) {
  1740. case DRM_MODE_DPMS_ON:
  1741. case DRM_MODE_DPMS_STANDBY:
  1742. case DRM_MODE_DPMS_SUSPEND:
  1743. DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
  1744. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1745. temp = I915_READ(PCH_LVDS);
  1746. if ((temp & LVDS_PORT_EN) == 0) {
  1747. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  1748. POSTING_READ(PCH_LVDS);
  1749. }
  1750. }
  1751. if (HAS_eDP) {
  1752. /* enable eDP PLL */
  1753. ironlake_enable_pll_edp(crtc);
  1754. } else {
  1755. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1756. temp = I915_READ(fdi_rx_reg);
  1757. /*
  1758. * make the BPC in FDI Rx be consistent with that in
  1759. * pipeconf reg.
  1760. */
  1761. temp &= ~(0x7 << 16);
  1762. temp |= (pipe_bpc << 11);
  1763. temp &= ~(7 << 19);
  1764. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1765. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  1766. I915_READ(fdi_rx_reg);
  1767. udelay(200);
  1768. /* Switch from Rawclk to PCDclk */
  1769. temp = I915_READ(fdi_rx_reg);
  1770. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  1771. I915_READ(fdi_rx_reg);
  1772. udelay(200);
  1773. /* Enable CPU FDI TX PLL, always on for Ironlake */
  1774. temp = I915_READ(fdi_tx_reg);
  1775. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1776. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  1777. I915_READ(fdi_tx_reg);
  1778. udelay(100);
  1779. }
  1780. }
  1781. /* Enable panel fitting for LVDS */
  1782. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
  1783. || HAS_eDP || intel_pch_has_edp(crtc)) {
  1784. temp = I915_READ(pf_ctl_reg);
  1785. I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
  1786. /* currently full aspect */
  1787. I915_WRITE(pf_win_pos, 0);
  1788. I915_WRITE(pf_win_size,
  1789. (dev_priv->panel_fixed_mode->hdisplay << 16) |
  1790. (dev_priv->panel_fixed_mode->vdisplay));
  1791. }
  1792. /* Enable CPU pipe */
  1793. temp = I915_READ(pipeconf_reg);
  1794. if ((temp & PIPEACONF_ENABLE) == 0) {
  1795. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1796. I915_READ(pipeconf_reg);
  1797. udelay(100);
  1798. }
  1799. /* configure and enable CPU plane */
  1800. temp = I915_READ(dspcntr_reg);
  1801. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1802. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1803. /* Flush the plane changes */
  1804. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1805. }
  1806. if (!HAS_eDP) {
  1807. /* For PCH output, training FDI link */
  1808. if (IS_GEN6(dev))
  1809. gen6_fdi_link_train(crtc);
  1810. else
  1811. ironlake_fdi_link_train(crtc);
  1812. /* enable PCH DPLL */
  1813. temp = I915_READ(pch_dpll_reg);
  1814. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1815. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  1816. I915_READ(pch_dpll_reg);
  1817. }
  1818. udelay(200);
  1819. if (HAS_PCH_CPT(dev)) {
  1820. /* Be sure PCH DPLL SEL is set */
  1821. temp = I915_READ(PCH_DPLL_SEL);
  1822. if (trans_dpll_sel == 0 &&
  1823. (temp & TRANSA_DPLL_ENABLE) == 0)
  1824. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  1825. else if (trans_dpll_sel == 1 &&
  1826. (temp & TRANSB_DPLL_ENABLE) == 0)
  1827. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1828. I915_WRITE(PCH_DPLL_SEL, temp);
  1829. I915_READ(PCH_DPLL_SEL);
  1830. }
  1831. /* set transcoder timing */
  1832. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1833. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1834. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1835. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1836. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1837. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1838. /* enable normal train */
  1839. temp = I915_READ(fdi_tx_reg);
  1840. temp &= ~FDI_LINK_TRAIN_NONE;
  1841. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1842. FDI_TX_ENHANCE_FRAME_ENABLE);
  1843. I915_READ(fdi_tx_reg);
  1844. temp = I915_READ(fdi_rx_reg);
  1845. if (HAS_PCH_CPT(dev)) {
  1846. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1847. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1848. } else {
  1849. temp &= ~FDI_LINK_TRAIN_NONE;
  1850. temp |= FDI_LINK_TRAIN_NONE;
  1851. }
  1852. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1853. I915_READ(fdi_rx_reg);
  1854. /* wait one idle pattern time */
  1855. udelay(100);
  1856. /* For PCH DP, enable TRANS_DP_CTL */
  1857. if (HAS_PCH_CPT(dev) &&
  1858. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  1859. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1860. int reg;
  1861. reg = I915_READ(trans_dp_ctl);
  1862. reg &= ~TRANS_DP_PORT_SEL_MASK;
  1863. reg = TRANS_DP_OUTPUT_ENABLE |
  1864. TRANS_DP_ENH_FRAMING;
  1865. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  1866. reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  1867. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  1868. reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  1869. switch (intel_trans_dp_port_sel(crtc)) {
  1870. case PCH_DP_B:
  1871. reg |= TRANS_DP_PORT_SEL_B;
  1872. break;
  1873. case PCH_DP_C:
  1874. reg |= TRANS_DP_PORT_SEL_C;
  1875. break;
  1876. case PCH_DP_D:
  1877. reg |= TRANS_DP_PORT_SEL_D;
  1878. break;
  1879. default:
  1880. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  1881. reg |= TRANS_DP_PORT_SEL_B;
  1882. break;
  1883. }
  1884. I915_WRITE(trans_dp_ctl, reg);
  1885. POSTING_READ(trans_dp_ctl);
  1886. }
  1887. /* enable PCH transcoder */
  1888. temp = I915_READ(transconf_reg);
  1889. /*
  1890. * make the BPC in transcoder be consistent with
  1891. * that in pipeconf reg.
  1892. */
  1893. temp &= ~PIPE_BPC_MASK;
  1894. temp |= pipe_bpc;
  1895. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1896. I915_READ(transconf_reg);
  1897. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1898. ;
  1899. }
  1900. intel_crtc_load_lut(crtc);
  1901. intel_update_fbc(crtc, &crtc->mode);
  1902. break;
  1903. case DRM_MODE_DPMS_OFF:
  1904. DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
  1905. drm_vblank_off(dev, pipe);
  1906. /* Disable display plane */
  1907. temp = I915_READ(dspcntr_reg);
  1908. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1909. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1910. /* Flush the plane changes */
  1911. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1912. I915_READ(dspbase_reg);
  1913. }
  1914. if (dev_priv->cfb_plane == plane &&
  1915. dev_priv->display.disable_fbc)
  1916. dev_priv->display.disable_fbc(dev);
  1917. i915_disable_vga(dev);
  1918. /* disable cpu pipe, disable after all planes disabled */
  1919. temp = I915_READ(pipeconf_reg);
  1920. if ((temp & PIPEACONF_ENABLE) != 0) {
  1921. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1922. I915_READ(pipeconf_reg);
  1923. n = 0;
  1924. /* wait for cpu pipe off, pipe state */
  1925. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
  1926. n++;
  1927. if (n < 60) {
  1928. udelay(500);
  1929. continue;
  1930. } else {
  1931. DRM_DEBUG_KMS("pipe %d off delay\n",
  1932. pipe);
  1933. break;
  1934. }
  1935. }
  1936. } else
  1937. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  1938. udelay(100);
  1939. /* Disable PF */
  1940. temp = I915_READ(pf_ctl_reg);
  1941. if ((temp & PF_ENABLE) != 0) {
  1942. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1943. I915_READ(pf_ctl_reg);
  1944. }
  1945. I915_WRITE(pf_win_size, 0);
  1946. POSTING_READ(pf_win_size);
  1947. /* disable CPU FDI tx and PCH FDI rx */
  1948. temp = I915_READ(fdi_tx_reg);
  1949. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1950. I915_READ(fdi_tx_reg);
  1951. temp = I915_READ(fdi_rx_reg);
  1952. /* BPC in FDI rx is consistent with that in pipeconf */
  1953. temp &= ~(0x07 << 16);
  1954. temp |= (pipe_bpc << 11);
  1955. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1956. I915_READ(fdi_rx_reg);
  1957. udelay(100);
  1958. /* still set train pattern 1 */
  1959. temp = I915_READ(fdi_tx_reg);
  1960. temp &= ~FDI_LINK_TRAIN_NONE;
  1961. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1962. I915_WRITE(fdi_tx_reg, temp);
  1963. POSTING_READ(fdi_tx_reg);
  1964. temp = I915_READ(fdi_rx_reg);
  1965. if (HAS_PCH_CPT(dev)) {
  1966. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1967. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1968. } else {
  1969. temp &= ~FDI_LINK_TRAIN_NONE;
  1970. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1971. }
  1972. I915_WRITE(fdi_rx_reg, temp);
  1973. POSTING_READ(fdi_rx_reg);
  1974. udelay(100);
  1975. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1976. temp = I915_READ(PCH_LVDS);
  1977. I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
  1978. I915_READ(PCH_LVDS);
  1979. udelay(100);
  1980. }
  1981. /* disable PCH transcoder */
  1982. temp = I915_READ(transconf_reg);
  1983. if ((temp & TRANS_ENABLE) != 0) {
  1984. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1985. I915_READ(transconf_reg);
  1986. n = 0;
  1987. /* wait for PCH transcoder off, transcoder state */
  1988. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
  1989. n++;
  1990. if (n < 60) {
  1991. udelay(500);
  1992. continue;
  1993. } else {
  1994. DRM_DEBUG_KMS("transcoder %d off "
  1995. "delay\n", pipe);
  1996. break;
  1997. }
  1998. }
  1999. }
  2000. temp = I915_READ(transconf_reg);
  2001. /* BPC in transcoder is consistent with that in pipeconf */
  2002. temp &= ~PIPE_BPC_MASK;
  2003. temp |= pipe_bpc;
  2004. I915_WRITE(transconf_reg, temp);
  2005. I915_READ(transconf_reg);
  2006. udelay(100);
  2007. if (HAS_PCH_CPT(dev)) {
  2008. /* disable TRANS_DP_CTL */
  2009. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  2010. int reg;
  2011. reg = I915_READ(trans_dp_ctl);
  2012. reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2013. I915_WRITE(trans_dp_ctl, reg);
  2014. POSTING_READ(trans_dp_ctl);
  2015. /* disable DPLL_SEL */
  2016. temp = I915_READ(PCH_DPLL_SEL);
  2017. if (trans_dpll_sel == 0)
  2018. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  2019. else
  2020. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2021. I915_WRITE(PCH_DPLL_SEL, temp);
  2022. I915_READ(PCH_DPLL_SEL);
  2023. }
  2024. /* disable PCH DPLL */
  2025. temp = I915_READ(pch_dpll_reg);
  2026. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  2027. I915_READ(pch_dpll_reg);
  2028. if (HAS_eDP) {
  2029. ironlake_disable_pll_edp(crtc);
  2030. }
  2031. /* Switch from PCDclk to Rawclk */
  2032. temp = I915_READ(fdi_rx_reg);
  2033. temp &= ~FDI_SEL_PCDCLK;
  2034. I915_WRITE(fdi_rx_reg, temp);
  2035. I915_READ(fdi_rx_reg);
  2036. /* Disable CPU FDI TX PLL */
  2037. temp = I915_READ(fdi_tx_reg);
  2038. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
  2039. I915_READ(fdi_tx_reg);
  2040. udelay(100);
  2041. temp = I915_READ(fdi_rx_reg);
  2042. temp &= ~FDI_RX_PLL_ENABLE;
  2043. I915_WRITE(fdi_rx_reg, temp);
  2044. I915_READ(fdi_rx_reg);
  2045. /* Wait for the clocks to turn off. */
  2046. udelay(100);
  2047. break;
  2048. }
  2049. }
  2050. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2051. {
  2052. struct intel_overlay *overlay;
  2053. int ret;
  2054. if (!enable && intel_crtc->overlay) {
  2055. overlay = intel_crtc->overlay;
  2056. mutex_lock(&overlay->dev->struct_mutex);
  2057. for (;;) {
  2058. ret = intel_overlay_switch_off(overlay);
  2059. if (ret == 0)
  2060. break;
  2061. ret = intel_overlay_recover_from_interrupt(overlay, 0);
  2062. if (ret != 0) {
  2063. /* overlay doesn't react anymore. Usually
  2064. * results in a black screen and an unkillable
  2065. * X server. */
  2066. BUG();
  2067. overlay->hw_wedged = HW_WEDGED;
  2068. break;
  2069. }
  2070. }
  2071. mutex_unlock(&overlay->dev->struct_mutex);
  2072. }
  2073. /* Let userspace switch the overlay on again. In most cases userspace
  2074. * has to recompute where to put it anyway. */
  2075. return;
  2076. }
  2077. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  2078. {
  2079. struct drm_device *dev = crtc->dev;
  2080. struct drm_i915_private *dev_priv = dev->dev_private;
  2081. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2082. int pipe = intel_crtc->pipe;
  2083. int plane = intel_crtc->plane;
  2084. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2085. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2086. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  2087. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2088. u32 temp;
  2089. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2090. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2091. */
  2092. switch (mode) {
  2093. case DRM_MODE_DPMS_ON:
  2094. case DRM_MODE_DPMS_STANDBY:
  2095. case DRM_MODE_DPMS_SUSPEND:
  2096. intel_update_watermarks(dev);
  2097. /* Enable the DPLL */
  2098. temp = I915_READ(dpll_reg);
  2099. if ((temp & DPLL_VCO_ENABLE) == 0) {
  2100. I915_WRITE(dpll_reg, temp);
  2101. I915_READ(dpll_reg);
  2102. /* Wait for the clocks to stabilize. */
  2103. udelay(150);
  2104. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  2105. I915_READ(dpll_reg);
  2106. /* Wait for the clocks to stabilize. */
  2107. udelay(150);
  2108. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  2109. I915_READ(dpll_reg);
  2110. /* Wait for the clocks to stabilize. */
  2111. udelay(150);
  2112. }
  2113. /* Enable the pipe */
  2114. temp = I915_READ(pipeconf_reg);
  2115. if ((temp & PIPEACONF_ENABLE) == 0)
  2116. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  2117. /* Enable the plane */
  2118. temp = I915_READ(dspcntr_reg);
  2119. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  2120. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  2121. /* Flush the plane changes */
  2122. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  2123. }
  2124. intel_crtc_load_lut(crtc);
  2125. if ((IS_I965G(dev) || plane == 0))
  2126. intel_update_fbc(crtc, &crtc->mode);
  2127. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2128. intel_crtc_dpms_overlay(intel_crtc, true);
  2129. break;
  2130. case DRM_MODE_DPMS_OFF:
  2131. intel_update_watermarks(dev);
  2132. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2133. intel_crtc_dpms_overlay(intel_crtc, false);
  2134. drm_vblank_off(dev, pipe);
  2135. if (dev_priv->cfb_plane == plane &&
  2136. dev_priv->display.disable_fbc)
  2137. dev_priv->display.disable_fbc(dev);
  2138. /* Disable the VGA plane that we never use */
  2139. i915_disable_vga(dev);
  2140. /* Disable display plane */
  2141. temp = I915_READ(dspcntr_reg);
  2142. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  2143. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  2144. /* Flush the plane changes */
  2145. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  2146. I915_READ(dspbase_reg);
  2147. }
  2148. if (!IS_I9XX(dev)) {
  2149. /* Wait for vblank for the disable to take effect */
  2150. intel_wait_for_vblank(dev);
  2151. }
  2152. /* Don't disable pipe A or pipe A PLLs if needed */
  2153. if (pipeconf_reg == PIPEACONF &&
  2154. (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  2155. goto skip_pipe_off;
  2156. /* Next, disable display pipes */
  2157. temp = I915_READ(pipeconf_reg);
  2158. if ((temp & PIPEACONF_ENABLE) != 0) {
  2159. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  2160. I915_READ(pipeconf_reg);
  2161. }
  2162. /* Wait for vblank for the disable to take effect. */
  2163. intel_wait_for_vblank(dev);
  2164. temp = I915_READ(dpll_reg);
  2165. if ((temp & DPLL_VCO_ENABLE) != 0) {
  2166. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  2167. I915_READ(dpll_reg);
  2168. }
  2169. skip_pipe_off:
  2170. /* Wait for the clocks to turn off. */
  2171. udelay(150);
  2172. break;
  2173. }
  2174. }
  2175. /**
  2176. * Sets the power management mode of the pipe and plane.
  2177. *
  2178. * This code should probably grow support for turning the cursor off and back
  2179. * on appropriately at the same time as we're turning the pipe off/on.
  2180. */
  2181. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2182. {
  2183. struct drm_device *dev = crtc->dev;
  2184. struct drm_i915_private *dev_priv = dev->dev_private;
  2185. struct drm_i915_master_private *master_priv;
  2186. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2187. int pipe = intel_crtc->pipe;
  2188. bool enabled;
  2189. dev_priv->display.dpms(crtc, mode);
  2190. intel_crtc->dpms_mode = mode;
  2191. if (!dev->primary->master)
  2192. return;
  2193. master_priv = dev->primary->master->driver_priv;
  2194. if (!master_priv->sarea_priv)
  2195. return;
  2196. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2197. switch (pipe) {
  2198. case 0:
  2199. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2200. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2201. break;
  2202. case 1:
  2203. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2204. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2205. break;
  2206. default:
  2207. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  2208. break;
  2209. }
  2210. }
  2211. static void intel_crtc_prepare (struct drm_crtc *crtc)
  2212. {
  2213. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2214. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2215. }
  2216. static void intel_crtc_commit (struct drm_crtc *crtc)
  2217. {
  2218. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2219. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  2220. }
  2221. void intel_encoder_prepare (struct drm_encoder *encoder)
  2222. {
  2223. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2224. /* lvds has its own version of prepare see intel_lvds_prepare */
  2225. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2226. }
  2227. void intel_encoder_commit (struct drm_encoder *encoder)
  2228. {
  2229. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2230. /* lvds has its own version of commit see intel_lvds_commit */
  2231. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2232. }
  2233. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2234. struct drm_display_mode *mode,
  2235. struct drm_display_mode *adjusted_mode)
  2236. {
  2237. struct drm_device *dev = crtc->dev;
  2238. if (HAS_PCH_SPLIT(dev)) {
  2239. /* FDI link clock is fixed at 2.7G */
  2240. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  2241. return false;
  2242. }
  2243. return true;
  2244. }
  2245. static int i945_get_display_clock_speed(struct drm_device *dev)
  2246. {
  2247. return 400000;
  2248. }
  2249. static int i915_get_display_clock_speed(struct drm_device *dev)
  2250. {
  2251. return 333000;
  2252. }
  2253. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2254. {
  2255. return 200000;
  2256. }
  2257. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2258. {
  2259. u16 gcfgc = 0;
  2260. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2261. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2262. return 133000;
  2263. else {
  2264. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2265. case GC_DISPLAY_CLOCK_333_MHZ:
  2266. return 333000;
  2267. default:
  2268. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2269. return 190000;
  2270. }
  2271. }
  2272. }
  2273. static int i865_get_display_clock_speed(struct drm_device *dev)
  2274. {
  2275. return 266000;
  2276. }
  2277. static int i855_get_display_clock_speed(struct drm_device *dev)
  2278. {
  2279. u16 hpllcc = 0;
  2280. /* Assume that the hardware is in the high speed state. This
  2281. * should be the default.
  2282. */
  2283. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2284. case GC_CLOCK_133_200:
  2285. case GC_CLOCK_100_200:
  2286. return 200000;
  2287. case GC_CLOCK_166_250:
  2288. return 250000;
  2289. case GC_CLOCK_100_133:
  2290. return 133000;
  2291. }
  2292. /* Shouldn't happen */
  2293. return 0;
  2294. }
  2295. static int i830_get_display_clock_speed(struct drm_device *dev)
  2296. {
  2297. return 133000;
  2298. }
  2299. /**
  2300. * Return the pipe currently connected to the panel fitter,
  2301. * or -1 if the panel fitter is not present or not in use
  2302. */
  2303. int intel_panel_fitter_pipe (struct drm_device *dev)
  2304. {
  2305. struct drm_i915_private *dev_priv = dev->dev_private;
  2306. u32 pfit_control;
  2307. /* i830 doesn't have a panel fitter */
  2308. if (IS_I830(dev))
  2309. return -1;
  2310. pfit_control = I915_READ(PFIT_CONTROL);
  2311. /* See if the panel fitter is in use */
  2312. if ((pfit_control & PFIT_ENABLE) == 0)
  2313. return -1;
  2314. /* 965 can place panel fitter on either pipe */
  2315. if (IS_I965G(dev))
  2316. return (pfit_control >> 29) & 0x3;
  2317. /* older chips can only use pipe 1 */
  2318. return 1;
  2319. }
  2320. struct fdi_m_n {
  2321. u32 tu;
  2322. u32 gmch_m;
  2323. u32 gmch_n;
  2324. u32 link_m;
  2325. u32 link_n;
  2326. };
  2327. static void
  2328. fdi_reduce_ratio(u32 *num, u32 *den)
  2329. {
  2330. while (*num > 0xffffff || *den > 0xffffff) {
  2331. *num >>= 1;
  2332. *den >>= 1;
  2333. }
  2334. }
  2335. #define DATA_N 0x800000
  2336. #define LINK_N 0x80000
  2337. static void
  2338. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2339. int link_clock, struct fdi_m_n *m_n)
  2340. {
  2341. u64 temp;
  2342. m_n->tu = 64; /* default size */
  2343. temp = (u64) DATA_N * pixel_clock;
  2344. temp = div_u64(temp, link_clock);
  2345. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  2346. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  2347. m_n->gmch_n = DATA_N;
  2348. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2349. temp = (u64) LINK_N * pixel_clock;
  2350. m_n->link_m = div_u64(temp, link_clock);
  2351. m_n->link_n = LINK_N;
  2352. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2353. }
  2354. struct intel_watermark_params {
  2355. unsigned long fifo_size;
  2356. unsigned long max_wm;
  2357. unsigned long default_wm;
  2358. unsigned long guard_size;
  2359. unsigned long cacheline_size;
  2360. };
  2361. /* Pineview has different values for various configs */
  2362. static struct intel_watermark_params pineview_display_wm = {
  2363. PINEVIEW_DISPLAY_FIFO,
  2364. PINEVIEW_MAX_WM,
  2365. PINEVIEW_DFT_WM,
  2366. PINEVIEW_GUARD_WM,
  2367. PINEVIEW_FIFO_LINE_SIZE
  2368. };
  2369. static struct intel_watermark_params pineview_display_hplloff_wm = {
  2370. PINEVIEW_DISPLAY_FIFO,
  2371. PINEVIEW_MAX_WM,
  2372. PINEVIEW_DFT_HPLLOFF_WM,
  2373. PINEVIEW_GUARD_WM,
  2374. PINEVIEW_FIFO_LINE_SIZE
  2375. };
  2376. static struct intel_watermark_params pineview_cursor_wm = {
  2377. PINEVIEW_CURSOR_FIFO,
  2378. PINEVIEW_CURSOR_MAX_WM,
  2379. PINEVIEW_CURSOR_DFT_WM,
  2380. PINEVIEW_CURSOR_GUARD_WM,
  2381. PINEVIEW_FIFO_LINE_SIZE,
  2382. };
  2383. static struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2384. PINEVIEW_CURSOR_FIFO,
  2385. PINEVIEW_CURSOR_MAX_WM,
  2386. PINEVIEW_CURSOR_DFT_WM,
  2387. PINEVIEW_CURSOR_GUARD_WM,
  2388. PINEVIEW_FIFO_LINE_SIZE
  2389. };
  2390. static struct intel_watermark_params g4x_wm_info = {
  2391. G4X_FIFO_SIZE,
  2392. G4X_MAX_WM,
  2393. G4X_MAX_WM,
  2394. 2,
  2395. G4X_FIFO_LINE_SIZE,
  2396. };
  2397. static struct intel_watermark_params g4x_cursor_wm_info = {
  2398. I965_CURSOR_FIFO,
  2399. I965_CURSOR_MAX_WM,
  2400. I965_CURSOR_DFT_WM,
  2401. 2,
  2402. G4X_FIFO_LINE_SIZE,
  2403. };
  2404. static struct intel_watermark_params i965_cursor_wm_info = {
  2405. I965_CURSOR_FIFO,
  2406. I965_CURSOR_MAX_WM,
  2407. I965_CURSOR_DFT_WM,
  2408. 2,
  2409. I915_FIFO_LINE_SIZE,
  2410. };
  2411. static struct intel_watermark_params i945_wm_info = {
  2412. I945_FIFO_SIZE,
  2413. I915_MAX_WM,
  2414. 1,
  2415. 2,
  2416. I915_FIFO_LINE_SIZE
  2417. };
  2418. static struct intel_watermark_params i915_wm_info = {
  2419. I915_FIFO_SIZE,
  2420. I915_MAX_WM,
  2421. 1,
  2422. 2,
  2423. I915_FIFO_LINE_SIZE
  2424. };
  2425. static struct intel_watermark_params i855_wm_info = {
  2426. I855GM_FIFO_SIZE,
  2427. I915_MAX_WM,
  2428. 1,
  2429. 2,
  2430. I830_FIFO_LINE_SIZE
  2431. };
  2432. static struct intel_watermark_params i830_wm_info = {
  2433. I830_FIFO_SIZE,
  2434. I915_MAX_WM,
  2435. 1,
  2436. 2,
  2437. I830_FIFO_LINE_SIZE
  2438. };
  2439. static struct intel_watermark_params ironlake_display_wm_info = {
  2440. ILK_DISPLAY_FIFO,
  2441. ILK_DISPLAY_MAXWM,
  2442. ILK_DISPLAY_DFTWM,
  2443. 2,
  2444. ILK_FIFO_LINE_SIZE
  2445. };
  2446. static struct intel_watermark_params ironlake_cursor_wm_info = {
  2447. ILK_CURSOR_FIFO,
  2448. ILK_CURSOR_MAXWM,
  2449. ILK_CURSOR_DFTWM,
  2450. 2,
  2451. ILK_FIFO_LINE_SIZE
  2452. };
  2453. static struct intel_watermark_params ironlake_display_srwm_info = {
  2454. ILK_DISPLAY_SR_FIFO,
  2455. ILK_DISPLAY_MAX_SRWM,
  2456. ILK_DISPLAY_DFT_SRWM,
  2457. 2,
  2458. ILK_FIFO_LINE_SIZE
  2459. };
  2460. static struct intel_watermark_params ironlake_cursor_srwm_info = {
  2461. ILK_CURSOR_SR_FIFO,
  2462. ILK_CURSOR_MAX_SRWM,
  2463. ILK_CURSOR_DFT_SRWM,
  2464. 2,
  2465. ILK_FIFO_LINE_SIZE
  2466. };
  2467. /**
  2468. * intel_calculate_wm - calculate watermark level
  2469. * @clock_in_khz: pixel clock
  2470. * @wm: chip FIFO params
  2471. * @pixel_size: display pixel size
  2472. * @latency_ns: memory latency for the platform
  2473. *
  2474. * Calculate the watermark level (the level at which the display plane will
  2475. * start fetching from memory again). Each chip has a different display
  2476. * FIFO size and allocation, so the caller needs to figure that out and pass
  2477. * in the correct intel_watermark_params structure.
  2478. *
  2479. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  2480. * on the pixel size. When it reaches the watermark level, it'll start
  2481. * fetching FIFO line sized based chunks from memory until the FIFO fills
  2482. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  2483. * will occur, and a display engine hang could result.
  2484. */
  2485. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  2486. struct intel_watermark_params *wm,
  2487. int pixel_size,
  2488. unsigned long latency_ns)
  2489. {
  2490. long entries_required, wm_size;
  2491. /*
  2492. * Note: we need to make sure we don't overflow for various clock &
  2493. * latency values.
  2494. * clocks go from a few thousand to several hundred thousand.
  2495. * latency is usually a few thousand
  2496. */
  2497. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  2498. 1000;
  2499. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  2500. DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
  2501. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  2502. DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
  2503. /* Don't promote wm_size to unsigned... */
  2504. if (wm_size > (long)wm->max_wm)
  2505. wm_size = wm->max_wm;
  2506. if (wm_size <= 0) {
  2507. wm_size = wm->default_wm;
  2508. DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
  2509. " entries required = %ld, available = %lu.\n",
  2510. entries_required + wm->guard_size,
  2511. wm->fifo_size);
  2512. }
  2513. return wm_size;
  2514. }
  2515. struct cxsr_latency {
  2516. int is_desktop;
  2517. int is_ddr3;
  2518. unsigned long fsb_freq;
  2519. unsigned long mem_freq;
  2520. unsigned long display_sr;
  2521. unsigned long display_hpll_disable;
  2522. unsigned long cursor_sr;
  2523. unsigned long cursor_hpll_disable;
  2524. };
  2525. static struct cxsr_latency cxsr_latency_table[] = {
  2526. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2527. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2528. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2529. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  2530. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  2531. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2532. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2533. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2534. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  2535. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  2536. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2537. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2538. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2539. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  2540. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  2541. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2542. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2543. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2544. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  2545. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  2546. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2547. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2548. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2549. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  2550. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  2551. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2552. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2553. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2554. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  2555. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  2556. };
  2557. static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
  2558. int fsb, int mem)
  2559. {
  2560. int i;
  2561. struct cxsr_latency *latency;
  2562. if (fsb == 0 || mem == 0)
  2563. return NULL;
  2564. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2565. latency = &cxsr_latency_table[i];
  2566. if (is_desktop == latency->is_desktop &&
  2567. is_ddr3 == latency->is_ddr3 &&
  2568. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2569. return latency;
  2570. }
  2571. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2572. return NULL;
  2573. }
  2574. static void pineview_disable_cxsr(struct drm_device *dev)
  2575. {
  2576. struct drm_i915_private *dev_priv = dev->dev_private;
  2577. u32 reg;
  2578. /* deactivate cxsr */
  2579. reg = I915_READ(DSPFW3);
  2580. reg &= ~(PINEVIEW_SELF_REFRESH_EN);
  2581. I915_WRITE(DSPFW3, reg);
  2582. DRM_INFO("Big FIFO is disabled\n");
  2583. }
  2584. /*
  2585. * Latency for FIFO fetches is dependent on several factors:
  2586. * - memory configuration (speed, channels)
  2587. * - chipset
  2588. * - current MCH state
  2589. * It can be fairly high in some situations, so here we assume a fairly
  2590. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2591. * set this value too high, the FIFO will fetch frequently to stay full)
  2592. * and power consumption (set it too low to save power and we might see
  2593. * FIFO underruns and display "flicker").
  2594. *
  2595. * A value of 5us seems to be a good balance; safe for very low end
  2596. * platforms but not overly aggressive on lower latency configs.
  2597. */
  2598. static const int latency_ns = 5000;
  2599. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2600. {
  2601. struct drm_i915_private *dev_priv = dev->dev_private;
  2602. uint32_t dsparb = I915_READ(DSPARB);
  2603. int size;
  2604. size = dsparb & 0x7f;
  2605. if (plane)
  2606. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  2607. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2608. plane ? "B" : "A", size);
  2609. return size;
  2610. }
  2611. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2612. {
  2613. struct drm_i915_private *dev_priv = dev->dev_private;
  2614. uint32_t dsparb = I915_READ(DSPARB);
  2615. int size;
  2616. size = dsparb & 0x1ff;
  2617. if (plane)
  2618. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  2619. size >>= 1; /* Convert to cachelines */
  2620. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2621. plane ? "B" : "A", size);
  2622. return size;
  2623. }
  2624. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2625. {
  2626. struct drm_i915_private *dev_priv = dev->dev_private;
  2627. uint32_t dsparb = I915_READ(DSPARB);
  2628. int size;
  2629. size = dsparb & 0x7f;
  2630. size >>= 2; /* Convert to cachelines */
  2631. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2632. plane ? "B" : "A",
  2633. size);
  2634. return size;
  2635. }
  2636. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2637. {
  2638. struct drm_i915_private *dev_priv = dev->dev_private;
  2639. uint32_t dsparb = I915_READ(DSPARB);
  2640. int size;
  2641. size = dsparb & 0x7f;
  2642. size >>= 1; /* Convert to cachelines */
  2643. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2644. plane ? "B" : "A", size);
  2645. return size;
  2646. }
  2647. static void pineview_update_wm(struct drm_device *dev, int planea_clock,
  2648. int planeb_clock, int sr_hdisplay, int unused,
  2649. int pixel_size)
  2650. {
  2651. struct drm_i915_private *dev_priv = dev->dev_private;
  2652. u32 reg;
  2653. unsigned long wm;
  2654. struct cxsr_latency *latency;
  2655. int sr_clock;
  2656. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  2657. dev_priv->fsb_freq, dev_priv->mem_freq);
  2658. if (!latency) {
  2659. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2660. pineview_disable_cxsr(dev);
  2661. return;
  2662. }
  2663. if (!planea_clock || !planeb_clock) {
  2664. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2665. /* Display SR */
  2666. wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
  2667. pixel_size, latency->display_sr);
  2668. reg = I915_READ(DSPFW1);
  2669. reg &= ~DSPFW_SR_MASK;
  2670. reg |= wm << DSPFW_SR_SHIFT;
  2671. I915_WRITE(DSPFW1, reg);
  2672. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  2673. /* cursor SR */
  2674. wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
  2675. pixel_size, latency->cursor_sr);
  2676. reg = I915_READ(DSPFW3);
  2677. reg &= ~DSPFW_CURSOR_SR_MASK;
  2678. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  2679. I915_WRITE(DSPFW3, reg);
  2680. /* Display HPLL off SR */
  2681. wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
  2682. pixel_size, latency->display_hpll_disable);
  2683. reg = I915_READ(DSPFW3);
  2684. reg &= ~DSPFW_HPLL_SR_MASK;
  2685. reg |= wm & DSPFW_HPLL_SR_MASK;
  2686. I915_WRITE(DSPFW3, reg);
  2687. /* cursor HPLL off SR */
  2688. wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
  2689. pixel_size, latency->cursor_hpll_disable);
  2690. reg = I915_READ(DSPFW3);
  2691. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  2692. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  2693. I915_WRITE(DSPFW3, reg);
  2694. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  2695. /* activate cxsr */
  2696. reg = I915_READ(DSPFW3);
  2697. reg |= PINEVIEW_SELF_REFRESH_EN;
  2698. I915_WRITE(DSPFW3, reg);
  2699. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  2700. } else {
  2701. pineview_disable_cxsr(dev);
  2702. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  2703. }
  2704. }
  2705. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2706. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2707. int pixel_size)
  2708. {
  2709. struct drm_i915_private *dev_priv = dev->dev_private;
  2710. int total_size, cacheline_size;
  2711. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2712. struct intel_watermark_params planea_params, planeb_params;
  2713. unsigned long line_time_us;
  2714. int sr_clock, sr_entries = 0, entries_required;
  2715. /* Create copies of the base settings for each pipe */
  2716. planea_params = planeb_params = g4x_wm_info;
  2717. /* Grab a couple of global values before we overwrite them */
  2718. total_size = planea_params.fifo_size;
  2719. cacheline_size = planea_params.cacheline_size;
  2720. /*
  2721. * Note: we need to make sure we don't overflow for various clock &
  2722. * latency values.
  2723. * clocks go from a few thousand to several hundred thousand.
  2724. * latency is usually a few thousand
  2725. */
  2726. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2727. 1000;
  2728. entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
  2729. planea_wm = entries_required + planea_params.guard_size;
  2730. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2731. 1000;
  2732. entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
  2733. planeb_wm = entries_required + planeb_params.guard_size;
  2734. cursora_wm = cursorb_wm = 16;
  2735. cursor_sr = 32;
  2736. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2737. /* Calc sr entries for one plane configs */
  2738. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2739. /* self-refresh has much higher latency */
  2740. static const int sr_latency_ns = 12000;
  2741. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2742. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2743. /* Use ns/us then divide to preserve precision */
  2744. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2745. pixel_size * sr_hdisplay;
  2746. sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
  2747. entries_required = (((sr_latency_ns / line_time_us) +
  2748. 1000) / 1000) * pixel_size * 64;
  2749. entries_required = DIV_ROUND_UP(entries_required,
  2750. g4x_cursor_wm_info.cacheline_size);
  2751. cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
  2752. if (cursor_sr > g4x_cursor_wm_info.max_wm)
  2753. cursor_sr = g4x_cursor_wm_info.max_wm;
  2754. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2755. "cursor %d\n", sr_entries, cursor_sr);
  2756. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2757. } else {
  2758. /* Turn off self refresh if both pipes are enabled */
  2759. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2760. & ~FW_BLC_SELF_EN);
  2761. }
  2762. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2763. planea_wm, planeb_wm, sr_entries);
  2764. planea_wm &= 0x3f;
  2765. planeb_wm &= 0x3f;
  2766. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2767. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2768. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2769. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2770. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2771. /* HPLL off in SR has some issues on G4x... disable it */
  2772. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2773. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2774. }
  2775. static void i965_update_wm(struct drm_device *dev, int planea_clock,
  2776. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2777. int pixel_size)
  2778. {
  2779. struct drm_i915_private *dev_priv = dev->dev_private;
  2780. unsigned long line_time_us;
  2781. int sr_clock, sr_entries, srwm = 1;
  2782. int cursor_sr = 16;
  2783. /* Calc sr entries for one plane configs */
  2784. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2785. /* self-refresh has much higher latency */
  2786. static const int sr_latency_ns = 12000;
  2787. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2788. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2789. /* Use ns/us then divide to preserve precision */
  2790. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2791. pixel_size * sr_hdisplay;
  2792. sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
  2793. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2794. srwm = I965_FIFO_SIZE - sr_entries;
  2795. if (srwm < 0)
  2796. srwm = 1;
  2797. srwm &= 0x1ff;
  2798. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2799. pixel_size * 64;
  2800. sr_entries = DIV_ROUND_UP(sr_entries,
  2801. i965_cursor_wm_info.cacheline_size);
  2802. cursor_sr = i965_cursor_wm_info.fifo_size -
  2803. (sr_entries + i965_cursor_wm_info.guard_size);
  2804. if (cursor_sr > i965_cursor_wm_info.max_wm)
  2805. cursor_sr = i965_cursor_wm_info.max_wm;
  2806. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2807. "cursor %d\n", srwm, cursor_sr);
  2808. if (IS_I965GM(dev))
  2809. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2810. } else {
  2811. /* Turn off self refresh if both pipes are enabled */
  2812. if (IS_I965GM(dev))
  2813. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2814. & ~FW_BLC_SELF_EN);
  2815. }
  2816. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  2817. srwm);
  2818. /* 965 has limitations... */
  2819. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
  2820. (8 << 0));
  2821. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2822. /* update cursor SR watermark */
  2823. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2824. }
  2825. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2826. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2827. int pixel_size)
  2828. {
  2829. struct drm_i915_private *dev_priv = dev->dev_private;
  2830. uint32_t fwater_lo;
  2831. uint32_t fwater_hi;
  2832. int total_size, cacheline_size, cwm, srwm = 1;
  2833. int planea_wm, planeb_wm;
  2834. struct intel_watermark_params planea_params, planeb_params;
  2835. unsigned long line_time_us;
  2836. int sr_clock, sr_entries = 0;
  2837. /* Create copies of the base settings for each pipe */
  2838. if (IS_I965GM(dev) || IS_I945GM(dev))
  2839. planea_params = planeb_params = i945_wm_info;
  2840. else if (IS_I9XX(dev))
  2841. planea_params = planeb_params = i915_wm_info;
  2842. else
  2843. planea_params = planeb_params = i855_wm_info;
  2844. /* Grab a couple of global values before we overwrite them */
  2845. total_size = planea_params.fifo_size;
  2846. cacheline_size = planea_params.cacheline_size;
  2847. /* Update per-plane FIFO sizes */
  2848. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2849. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2850. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2851. pixel_size, latency_ns);
  2852. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2853. pixel_size, latency_ns);
  2854. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2855. /*
  2856. * Overlay gets an aggressive default since video jitter is bad.
  2857. */
  2858. cwm = 2;
  2859. /* Calc sr entries for one plane configs */
  2860. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2861. (!planea_clock || !planeb_clock)) {
  2862. /* self-refresh has much higher latency */
  2863. static const int sr_latency_ns = 6000;
  2864. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2865. line_time_us = ((sr_htotal * 1000) / sr_clock);
  2866. /* Use ns/us then divide to preserve precision */
  2867. sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  2868. pixel_size * sr_hdisplay;
  2869. sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
  2870. DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
  2871. srwm = total_size - sr_entries;
  2872. if (srwm < 0)
  2873. srwm = 1;
  2874. if (IS_I945G(dev) || IS_I945GM(dev))
  2875. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  2876. else if (IS_I915GM(dev)) {
  2877. /* 915M has a smaller SRWM field */
  2878. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  2879. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  2880. }
  2881. } else {
  2882. /* Turn off self refresh if both pipes are enabled */
  2883. if (IS_I945G(dev) || IS_I945GM(dev)) {
  2884. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2885. & ~FW_BLC_SELF_EN);
  2886. } else if (IS_I915GM(dev)) {
  2887. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  2888. }
  2889. }
  2890. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2891. planea_wm, planeb_wm, cwm, srwm);
  2892. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2893. fwater_hi = (cwm & 0x1f);
  2894. /* Set request length to 8 cachelines per fetch */
  2895. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2896. fwater_hi = fwater_hi | (1 << 8);
  2897. I915_WRITE(FW_BLC, fwater_lo);
  2898. I915_WRITE(FW_BLC2, fwater_hi);
  2899. }
  2900. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2901. int unused2, int unused3, int pixel_size)
  2902. {
  2903. struct drm_i915_private *dev_priv = dev->dev_private;
  2904. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2905. int planea_wm;
  2906. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2907. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2908. pixel_size, latency_ns);
  2909. fwater_lo |= (3<<8) | planea_wm;
  2910. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  2911. I915_WRITE(FW_BLC, fwater_lo);
  2912. }
  2913. #define ILK_LP0_PLANE_LATENCY 700
  2914. #define ILK_LP0_CURSOR_LATENCY 1300
  2915. static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
  2916. int planeb_clock, int sr_hdisplay, int sr_htotal,
  2917. int pixel_size)
  2918. {
  2919. struct drm_i915_private *dev_priv = dev->dev_private;
  2920. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  2921. int sr_wm, cursor_wm;
  2922. unsigned long line_time_us;
  2923. int sr_clock, entries_required;
  2924. u32 reg_value;
  2925. int line_count;
  2926. int planea_htotal = 0, planeb_htotal = 0;
  2927. struct drm_crtc *crtc;
  2928. struct intel_crtc *intel_crtc;
  2929. /* Need htotal for all active display plane */
  2930. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2931. intel_crtc = to_intel_crtc(crtc);
  2932. if (crtc->enabled) {
  2933. if (intel_crtc->plane == 0)
  2934. planea_htotal = crtc->mode.htotal;
  2935. else
  2936. planeb_htotal = crtc->mode.htotal;
  2937. }
  2938. }
  2939. /* Calculate and update the watermark for plane A */
  2940. if (planea_clock) {
  2941. entries_required = ((planea_clock / 1000) * pixel_size *
  2942. ILK_LP0_PLANE_LATENCY) / 1000;
  2943. entries_required = DIV_ROUND_UP(entries_required,
  2944. ironlake_display_wm_info.cacheline_size);
  2945. planea_wm = entries_required +
  2946. ironlake_display_wm_info.guard_size;
  2947. if (planea_wm > (int)ironlake_display_wm_info.max_wm)
  2948. planea_wm = ironlake_display_wm_info.max_wm;
  2949. /* Use the large buffer method to calculate cursor watermark */
  2950. line_time_us = (planea_htotal * 1000) / planea_clock;
  2951. /* Use ns/us then divide to preserve precision */
  2952. line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
  2953. /* calculate the cursor watermark for cursor A */
  2954. entries_required = line_count * 64 * pixel_size;
  2955. entries_required = DIV_ROUND_UP(entries_required,
  2956. ironlake_cursor_wm_info.cacheline_size);
  2957. cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
  2958. if (cursora_wm > ironlake_cursor_wm_info.max_wm)
  2959. cursora_wm = ironlake_cursor_wm_info.max_wm;
  2960. reg_value = I915_READ(WM0_PIPEA_ILK);
  2961. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2962. reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
  2963. (cursora_wm & WM0_PIPE_CURSOR_MASK);
  2964. I915_WRITE(WM0_PIPEA_ILK, reg_value);
  2965. DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
  2966. "cursor: %d\n", planea_wm, cursora_wm);
  2967. }
  2968. /* Calculate and update the watermark for plane B */
  2969. if (planeb_clock) {
  2970. entries_required = ((planeb_clock / 1000) * pixel_size *
  2971. ILK_LP0_PLANE_LATENCY) / 1000;
  2972. entries_required = DIV_ROUND_UP(entries_required,
  2973. ironlake_display_wm_info.cacheline_size);
  2974. planeb_wm = entries_required +
  2975. ironlake_display_wm_info.guard_size;
  2976. if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
  2977. planeb_wm = ironlake_display_wm_info.max_wm;
  2978. /* Use the large buffer method to calculate cursor watermark */
  2979. line_time_us = (planeb_htotal * 1000) / planeb_clock;
  2980. /* Use ns/us then divide to preserve precision */
  2981. line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
  2982. /* calculate the cursor watermark for cursor B */
  2983. entries_required = line_count * 64 * pixel_size;
  2984. entries_required = DIV_ROUND_UP(entries_required,
  2985. ironlake_cursor_wm_info.cacheline_size);
  2986. cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
  2987. if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
  2988. cursorb_wm = ironlake_cursor_wm_info.max_wm;
  2989. reg_value = I915_READ(WM0_PIPEB_ILK);
  2990. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2991. reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
  2992. (cursorb_wm & WM0_PIPE_CURSOR_MASK);
  2993. I915_WRITE(WM0_PIPEB_ILK, reg_value);
  2994. DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
  2995. "cursor: %d\n", planeb_wm, cursorb_wm);
  2996. }
  2997. /*
  2998. * Calculate and update the self-refresh watermark only when one
  2999. * display plane is used.
  3000. */
  3001. if (!planea_clock || !planeb_clock) {
  3002. /* Read the self-refresh latency. The unit is 0.5us */
  3003. int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
  3004. sr_clock = planea_clock ? planea_clock : planeb_clock;
  3005. line_time_us = ((sr_htotal * 1000) / sr_clock);
  3006. /* Use ns/us then divide to preserve precision */
  3007. line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
  3008. / 1000;
  3009. /* calculate the self-refresh watermark for display plane */
  3010. entries_required = line_count * sr_hdisplay * pixel_size;
  3011. entries_required = DIV_ROUND_UP(entries_required,
  3012. ironlake_display_srwm_info.cacheline_size);
  3013. sr_wm = entries_required +
  3014. ironlake_display_srwm_info.guard_size;
  3015. /* calculate the self-refresh watermark for display cursor */
  3016. entries_required = line_count * pixel_size * 64;
  3017. entries_required = DIV_ROUND_UP(entries_required,
  3018. ironlake_cursor_srwm_info.cacheline_size);
  3019. cursor_wm = entries_required +
  3020. ironlake_cursor_srwm_info.guard_size;
  3021. /* configure watermark and enable self-refresh */
  3022. reg_value = I915_READ(WM1_LP_ILK);
  3023. reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
  3024. WM1_LP_CURSOR_MASK);
  3025. reg_value |= WM1_LP_SR_EN |
  3026. (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
  3027. (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
  3028. I915_WRITE(WM1_LP_ILK, reg_value);
  3029. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  3030. "cursor %d\n", sr_wm, cursor_wm);
  3031. } else {
  3032. /* Turn off self refresh if both pipes are enabled */
  3033. I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
  3034. }
  3035. }
  3036. /**
  3037. * intel_update_watermarks - update FIFO watermark values based on current modes
  3038. *
  3039. * Calculate watermark values for the various WM regs based on current mode
  3040. * and plane configuration.
  3041. *
  3042. * There are several cases to deal with here:
  3043. * - normal (i.e. non-self-refresh)
  3044. * - self-refresh (SR) mode
  3045. * - lines are large relative to FIFO size (buffer can hold up to 2)
  3046. * - lines are small relative to FIFO size (buffer can hold more than 2
  3047. * lines), so need to account for TLB latency
  3048. *
  3049. * The normal calculation is:
  3050. * watermark = dotclock * bytes per pixel * latency
  3051. * where latency is platform & configuration dependent (we assume pessimal
  3052. * values here).
  3053. *
  3054. * The SR calculation is:
  3055. * watermark = (trunc(latency/line time)+1) * surface width *
  3056. * bytes per pixel
  3057. * where
  3058. * line time = htotal / dotclock
  3059. * surface width = hdisplay for normal plane and 64 for cursor
  3060. * and latency is assumed to be high, as above.
  3061. *
  3062. * The final value programmed to the register should always be rounded up,
  3063. * and include an extra 2 entries to account for clock crossings.
  3064. *
  3065. * We don't use the sprite, so we can ignore that. And on Crestline we have
  3066. * to set the non-SR watermarks to 8.
  3067. */
  3068. static void intel_update_watermarks(struct drm_device *dev)
  3069. {
  3070. struct drm_i915_private *dev_priv = dev->dev_private;
  3071. struct drm_crtc *crtc;
  3072. struct intel_crtc *intel_crtc;
  3073. int sr_hdisplay = 0;
  3074. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  3075. int enabled = 0, pixel_size = 0;
  3076. int sr_htotal = 0;
  3077. if (!dev_priv->display.update_wm)
  3078. return;
  3079. /* Get the clock config from both planes */
  3080. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3081. intel_crtc = to_intel_crtc(crtc);
  3082. if (crtc->enabled) {
  3083. enabled++;
  3084. if (intel_crtc->plane == 0) {
  3085. DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
  3086. intel_crtc->pipe, crtc->mode.clock);
  3087. planea_clock = crtc->mode.clock;
  3088. } else {
  3089. DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
  3090. intel_crtc->pipe, crtc->mode.clock);
  3091. planeb_clock = crtc->mode.clock;
  3092. }
  3093. sr_hdisplay = crtc->mode.hdisplay;
  3094. sr_clock = crtc->mode.clock;
  3095. sr_htotal = crtc->mode.htotal;
  3096. if (crtc->fb)
  3097. pixel_size = crtc->fb->bits_per_pixel / 8;
  3098. else
  3099. pixel_size = 4; /* by default */
  3100. }
  3101. }
  3102. if (enabled <= 0)
  3103. return;
  3104. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  3105. sr_hdisplay, sr_htotal, pixel_size);
  3106. }
  3107. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  3108. struct drm_display_mode *mode,
  3109. struct drm_display_mode *adjusted_mode,
  3110. int x, int y,
  3111. struct drm_framebuffer *old_fb)
  3112. {
  3113. struct drm_device *dev = crtc->dev;
  3114. struct drm_i915_private *dev_priv = dev->dev_private;
  3115. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3116. int pipe = intel_crtc->pipe;
  3117. int plane = intel_crtc->plane;
  3118. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  3119. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3120. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  3121. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  3122. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  3123. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  3124. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  3125. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  3126. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  3127. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  3128. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  3129. int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
  3130. int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
  3131. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  3132. int refclk, num_connectors = 0;
  3133. intel_clock_t clock, reduced_clock;
  3134. u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
  3135. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  3136. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  3137. bool is_edp = false;
  3138. struct drm_mode_config *mode_config = &dev->mode_config;
  3139. struct drm_encoder *encoder;
  3140. struct intel_encoder *intel_encoder = NULL;
  3141. const intel_limit_t *limit;
  3142. int ret;
  3143. struct fdi_m_n m_n = {0};
  3144. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  3145. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  3146. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  3147. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  3148. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  3149. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  3150. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  3151. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  3152. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  3153. int lvds_reg = LVDS;
  3154. u32 temp;
  3155. int sdvo_pixel_multiply;
  3156. int target_clock;
  3157. drm_vblank_pre_modeset(dev, pipe);
  3158. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  3159. if (!encoder || encoder->crtc != crtc)
  3160. continue;
  3161. intel_encoder = enc_to_intel_encoder(encoder);
  3162. switch (intel_encoder->type) {
  3163. case INTEL_OUTPUT_LVDS:
  3164. is_lvds = true;
  3165. break;
  3166. case INTEL_OUTPUT_SDVO:
  3167. case INTEL_OUTPUT_HDMI:
  3168. is_sdvo = true;
  3169. if (intel_encoder->needs_tv_clock)
  3170. is_tv = true;
  3171. break;
  3172. case INTEL_OUTPUT_DVO:
  3173. is_dvo = true;
  3174. break;
  3175. case INTEL_OUTPUT_TVOUT:
  3176. is_tv = true;
  3177. break;
  3178. case INTEL_OUTPUT_ANALOG:
  3179. is_crt = true;
  3180. break;
  3181. case INTEL_OUTPUT_DISPLAYPORT:
  3182. is_dp = true;
  3183. break;
  3184. case INTEL_OUTPUT_EDP:
  3185. is_edp = true;
  3186. break;
  3187. }
  3188. num_connectors++;
  3189. }
  3190. if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
  3191. refclk = dev_priv->lvds_ssc_freq * 1000;
  3192. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3193. refclk / 1000);
  3194. } else if (IS_I9XX(dev)) {
  3195. refclk = 96000;
  3196. if (HAS_PCH_SPLIT(dev))
  3197. refclk = 120000; /* 120Mhz refclk */
  3198. } else {
  3199. refclk = 48000;
  3200. }
  3201. /*
  3202. * Returns a set of divisors for the desired target clock with the given
  3203. * refclk, or FALSE. The returned values represent the clock equation:
  3204. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3205. */
  3206. limit = intel_limit(crtc);
  3207. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  3208. if (!ok) {
  3209. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3210. drm_vblank_post_modeset(dev, pipe);
  3211. return -EINVAL;
  3212. }
  3213. /* Ensure that the cursor is valid for the new mode before changing... */
  3214. intel_crtc_update_cursor(crtc);
  3215. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3216. has_reduced_clock = limit->find_pll(limit, crtc,
  3217. dev_priv->lvds_downclock,
  3218. refclk,
  3219. &reduced_clock);
  3220. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  3221. /*
  3222. * If the different P is found, it means that we can't
  3223. * switch the display clock by using the FP0/FP1.
  3224. * In such case we will disable the LVDS downclock
  3225. * feature.
  3226. */
  3227. DRM_DEBUG_KMS("Different P is found for "
  3228. "LVDS clock/downclock\n");
  3229. has_reduced_clock = 0;
  3230. }
  3231. }
  3232. /* SDVO TV has fixed PLL values depend on its clock range,
  3233. this mirrors vbios setting. */
  3234. if (is_sdvo && is_tv) {
  3235. if (adjusted_mode->clock >= 100000
  3236. && adjusted_mode->clock < 140500) {
  3237. clock.p1 = 2;
  3238. clock.p2 = 10;
  3239. clock.n = 3;
  3240. clock.m1 = 16;
  3241. clock.m2 = 8;
  3242. } else if (adjusted_mode->clock >= 140500
  3243. && adjusted_mode->clock <= 200000) {
  3244. clock.p1 = 1;
  3245. clock.p2 = 10;
  3246. clock.n = 6;
  3247. clock.m1 = 12;
  3248. clock.m2 = 8;
  3249. }
  3250. }
  3251. /* FDI link */
  3252. if (HAS_PCH_SPLIT(dev)) {
  3253. int lane = 0, link_bw, bpp;
  3254. /* eDP doesn't require FDI link, so just set DP M/N
  3255. according to current link config */
  3256. if (is_edp) {
  3257. target_clock = mode->clock;
  3258. intel_edp_link_config(intel_encoder,
  3259. &lane, &link_bw);
  3260. } else {
  3261. /* DP over FDI requires target mode clock
  3262. instead of link clock */
  3263. if (is_dp)
  3264. target_clock = mode->clock;
  3265. else
  3266. target_clock = adjusted_mode->clock;
  3267. link_bw = 270000;
  3268. }
  3269. /* determine panel color depth */
  3270. temp = I915_READ(pipeconf_reg);
  3271. temp &= ~PIPE_BPC_MASK;
  3272. if (is_lvds) {
  3273. int lvds_reg = I915_READ(PCH_LVDS);
  3274. /* the BPC will be 6 if it is 18-bit LVDS panel */
  3275. if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
  3276. temp |= PIPE_8BPC;
  3277. else
  3278. temp |= PIPE_6BPC;
  3279. } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
  3280. switch (dev_priv->edp_bpp/3) {
  3281. case 8:
  3282. temp |= PIPE_8BPC;
  3283. break;
  3284. case 10:
  3285. temp |= PIPE_10BPC;
  3286. break;
  3287. case 6:
  3288. temp |= PIPE_6BPC;
  3289. break;
  3290. case 12:
  3291. temp |= PIPE_12BPC;
  3292. break;
  3293. }
  3294. } else
  3295. temp |= PIPE_8BPC;
  3296. I915_WRITE(pipeconf_reg, temp);
  3297. I915_READ(pipeconf_reg);
  3298. switch (temp & PIPE_BPC_MASK) {
  3299. case PIPE_8BPC:
  3300. bpp = 24;
  3301. break;
  3302. case PIPE_10BPC:
  3303. bpp = 30;
  3304. break;
  3305. case PIPE_6BPC:
  3306. bpp = 18;
  3307. break;
  3308. case PIPE_12BPC:
  3309. bpp = 36;
  3310. break;
  3311. default:
  3312. DRM_ERROR("unknown pipe bpc value\n");
  3313. bpp = 24;
  3314. }
  3315. if (!lane) {
  3316. /*
  3317. * Account for spread spectrum to avoid
  3318. * oversubscribing the link. Max center spread
  3319. * is 2.5%; use 5% for safety's sake.
  3320. */
  3321. u32 bps = target_clock * bpp * 21 / 20;
  3322. lane = bps / (link_bw * 8) + 1;
  3323. }
  3324. intel_crtc->fdi_lanes = lane;
  3325. ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
  3326. }
  3327. /* Ironlake: try to setup display ref clock before DPLL
  3328. * enabling. This is only under driver's control after
  3329. * PCH B stepping, previous chipset stepping should be
  3330. * ignoring this setting.
  3331. */
  3332. if (HAS_PCH_SPLIT(dev)) {
  3333. temp = I915_READ(PCH_DREF_CONTROL);
  3334. /* Always enable nonspread source */
  3335. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3336. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3337. I915_WRITE(PCH_DREF_CONTROL, temp);
  3338. POSTING_READ(PCH_DREF_CONTROL);
  3339. temp &= ~DREF_SSC_SOURCE_MASK;
  3340. temp |= DREF_SSC_SOURCE_ENABLE;
  3341. I915_WRITE(PCH_DREF_CONTROL, temp);
  3342. POSTING_READ(PCH_DREF_CONTROL);
  3343. udelay(200);
  3344. if (is_edp) {
  3345. if (dev_priv->lvds_use_ssc) {
  3346. temp |= DREF_SSC1_ENABLE;
  3347. I915_WRITE(PCH_DREF_CONTROL, temp);
  3348. POSTING_READ(PCH_DREF_CONTROL);
  3349. udelay(200);
  3350. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3351. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3352. I915_WRITE(PCH_DREF_CONTROL, temp);
  3353. POSTING_READ(PCH_DREF_CONTROL);
  3354. } else {
  3355. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3356. I915_WRITE(PCH_DREF_CONTROL, temp);
  3357. POSTING_READ(PCH_DREF_CONTROL);
  3358. }
  3359. }
  3360. }
  3361. if (IS_PINEVIEW(dev)) {
  3362. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  3363. if (has_reduced_clock)
  3364. fp2 = (1 << reduced_clock.n) << 16 |
  3365. reduced_clock.m1 << 8 | reduced_clock.m2;
  3366. } else {
  3367. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  3368. if (has_reduced_clock)
  3369. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  3370. reduced_clock.m2;
  3371. }
  3372. if (!HAS_PCH_SPLIT(dev))
  3373. dpll = DPLL_VGA_MODE_DIS;
  3374. if (IS_I9XX(dev)) {
  3375. if (is_lvds)
  3376. dpll |= DPLLB_MODE_LVDS;
  3377. else
  3378. dpll |= DPLLB_MODE_DAC_SERIAL;
  3379. if (is_sdvo) {
  3380. dpll |= DPLL_DVO_HIGH_SPEED;
  3381. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  3382. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3383. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3384. else if (HAS_PCH_SPLIT(dev))
  3385. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  3386. }
  3387. if (is_dp)
  3388. dpll |= DPLL_DVO_HIGH_SPEED;
  3389. /* compute bitmask from p1 value */
  3390. if (IS_PINEVIEW(dev))
  3391. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3392. else {
  3393. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3394. /* also FPA1 */
  3395. if (HAS_PCH_SPLIT(dev))
  3396. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3397. if (IS_G4X(dev) && has_reduced_clock)
  3398. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3399. }
  3400. switch (clock.p2) {
  3401. case 5:
  3402. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3403. break;
  3404. case 7:
  3405. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3406. break;
  3407. case 10:
  3408. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3409. break;
  3410. case 14:
  3411. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3412. break;
  3413. }
  3414. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
  3415. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3416. } else {
  3417. if (is_lvds) {
  3418. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3419. } else {
  3420. if (clock.p1 == 2)
  3421. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3422. else
  3423. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3424. if (clock.p2 == 4)
  3425. dpll |= PLL_P2_DIVIDE_BY_4;
  3426. }
  3427. }
  3428. if (is_sdvo && is_tv)
  3429. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3430. else if (is_tv)
  3431. /* XXX: just matching BIOS for now */
  3432. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3433. dpll |= 3;
  3434. else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
  3435. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3436. else
  3437. dpll |= PLL_REF_INPUT_DREFCLK;
  3438. /* setup pipeconf */
  3439. pipeconf = I915_READ(pipeconf_reg);
  3440. /* Set up the display plane register */
  3441. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3442. /* Ironlake's plane is forced to pipe, bit 24 is to
  3443. enable color space conversion */
  3444. if (!HAS_PCH_SPLIT(dev)) {
  3445. if (pipe == 0)
  3446. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3447. else
  3448. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3449. }
  3450. if (pipe == 0 && !IS_I965G(dev)) {
  3451. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3452. * core speed.
  3453. *
  3454. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3455. * pipe == 0 check?
  3456. */
  3457. if (mode->clock >
  3458. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3459. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  3460. else
  3461. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  3462. }
  3463. dspcntr |= DISPLAY_PLANE_ENABLE;
  3464. pipeconf |= PIPEACONF_ENABLE;
  3465. dpll |= DPLL_VCO_ENABLE;
  3466. /* Disable the panel fitter if it was on our pipe */
  3467. if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
  3468. I915_WRITE(PFIT_CONTROL, 0);
  3469. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3470. drm_mode_debug_printmodeline(mode);
  3471. /* assign to Ironlake registers */
  3472. if (HAS_PCH_SPLIT(dev)) {
  3473. fp_reg = pch_fp_reg;
  3474. dpll_reg = pch_dpll_reg;
  3475. }
  3476. if (is_edp) {
  3477. ironlake_disable_pll_edp(crtc);
  3478. } else if ((dpll & DPLL_VCO_ENABLE)) {
  3479. I915_WRITE(fp_reg, fp);
  3480. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  3481. I915_READ(dpll_reg);
  3482. udelay(150);
  3483. }
  3484. /* enable transcoder DPLL */
  3485. if (HAS_PCH_CPT(dev)) {
  3486. temp = I915_READ(PCH_DPLL_SEL);
  3487. if (trans_dpll_sel == 0)
  3488. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  3489. else
  3490. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  3491. I915_WRITE(PCH_DPLL_SEL, temp);
  3492. I915_READ(PCH_DPLL_SEL);
  3493. udelay(150);
  3494. }
  3495. if (HAS_PCH_SPLIT(dev)) {
  3496. pipeconf &= ~PIPE_ENABLE_DITHER;
  3497. pipeconf &= ~PIPE_DITHER_TYPE_MASK;
  3498. }
  3499. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3500. * This is an exception to the general rule that mode_set doesn't turn
  3501. * things on.
  3502. */
  3503. if (is_lvds) {
  3504. u32 lvds;
  3505. if (HAS_PCH_SPLIT(dev))
  3506. lvds_reg = PCH_LVDS;
  3507. lvds = I915_READ(lvds_reg);
  3508. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3509. if (pipe == 1) {
  3510. if (HAS_PCH_CPT(dev))
  3511. lvds |= PORT_TRANS_B_SEL_CPT;
  3512. else
  3513. lvds |= LVDS_PIPEB_SELECT;
  3514. } else {
  3515. if (HAS_PCH_CPT(dev))
  3516. lvds &= ~PORT_TRANS_SEL_MASK;
  3517. else
  3518. lvds &= ~LVDS_PIPEB_SELECT;
  3519. }
  3520. /* set the corresponsding LVDS_BORDER bit */
  3521. lvds |= dev_priv->lvds_border_bits;
  3522. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3523. * set the DPLLs for dual-channel mode or not.
  3524. */
  3525. if (clock.p2 == 7)
  3526. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3527. else
  3528. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3529. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3530. * appropriately here, but we need to look more thoroughly into how
  3531. * panels behave in the two modes.
  3532. */
  3533. /* set the dithering flag */
  3534. if (IS_I965G(dev)) {
  3535. if (dev_priv->lvds_dither) {
  3536. if (HAS_PCH_SPLIT(dev)) {
  3537. pipeconf |= PIPE_ENABLE_DITHER;
  3538. pipeconf |= PIPE_DITHER_TYPE_ST01;
  3539. } else
  3540. lvds |= LVDS_ENABLE_DITHER;
  3541. } else {
  3542. if (!HAS_PCH_SPLIT(dev)) {
  3543. lvds &= ~LVDS_ENABLE_DITHER;
  3544. }
  3545. }
  3546. }
  3547. I915_WRITE(lvds_reg, lvds);
  3548. I915_READ(lvds_reg);
  3549. }
  3550. if (is_dp)
  3551. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3552. else if (HAS_PCH_SPLIT(dev)) {
  3553. /* For non-DP output, clear any trans DP clock recovery setting.*/
  3554. if (pipe == 0) {
  3555. I915_WRITE(TRANSA_DATA_M1, 0);
  3556. I915_WRITE(TRANSA_DATA_N1, 0);
  3557. I915_WRITE(TRANSA_DP_LINK_M1, 0);
  3558. I915_WRITE(TRANSA_DP_LINK_N1, 0);
  3559. } else {
  3560. I915_WRITE(TRANSB_DATA_M1, 0);
  3561. I915_WRITE(TRANSB_DATA_N1, 0);
  3562. I915_WRITE(TRANSB_DP_LINK_M1, 0);
  3563. I915_WRITE(TRANSB_DP_LINK_N1, 0);
  3564. }
  3565. }
  3566. if (!is_edp) {
  3567. I915_WRITE(fp_reg, fp);
  3568. I915_WRITE(dpll_reg, dpll);
  3569. I915_READ(dpll_reg);
  3570. /* Wait for the clocks to stabilize. */
  3571. udelay(150);
  3572. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
  3573. if (is_sdvo) {
  3574. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  3575. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  3576. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  3577. } else
  3578. I915_WRITE(dpll_md_reg, 0);
  3579. } else {
  3580. /* write it again -- the BIOS does, after all */
  3581. I915_WRITE(dpll_reg, dpll);
  3582. }
  3583. I915_READ(dpll_reg);
  3584. /* Wait for the clocks to stabilize. */
  3585. udelay(150);
  3586. }
  3587. if (is_lvds && has_reduced_clock && i915_powersave) {
  3588. I915_WRITE(fp_reg + 4, fp2);
  3589. intel_crtc->lowfreq_avail = true;
  3590. if (HAS_PIPE_CXSR(dev)) {
  3591. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3592. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3593. }
  3594. } else {
  3595. I915_WRITE(fp_reg + 4, fp);
  3596. intel_crtc->lowfreq_avail = false;
  3597. if (HAS_PIPE_CXSR(dev)) {
  3598. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3599. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3600. }
  3601. }
  3602. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3603. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  3604. /* the chip adds 2 halflines automatically */
  3605. adjusted_mode->crtc_vdisplay -= 1;
  3606. adjusted_mode->crtc_vtotal -= 1;
  3607. adjusted_mode->crtc_vblank_start -= 1;
  3608. adjusted_mode->crtc_vblank_end -= 1;
  3609. adjusted_mode->crtc_vsync_end -= 1;
  3610. adjusted_mode->crtc_vsync_start -= 1;
  3611. } else
  3612. pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
  3613. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  3614. ((adjusted_mode->crtc_htotal - 1) << 16));
  3615. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  3616. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3617. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  3618. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3619. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  3620. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3621. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  3622. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3623. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  3624. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3625. /* pipesrc and dspsize control the size that is scaled from, which should
  3626. * always be the user's requested size.
  3627. */
  3628. if (!HAS_PCH_SPLIT(dev)) {
  3629. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  3630. (mode->hdisplay - 1));
  3631. I915_WRITE(dsppos_reg, 0);
  3632. }
  3633. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3634. if (HAS_PCH_SPLIT(dev)) {
  3635. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  3636. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  3637. I915_WRITE(link_m1_reg, m_n.link_m);
  3638. I915_WRITE(link_n1_reg, m_n.link_n);
  3639. if (is_edp) {
  3640. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  3641. } else {
  3642. /* enable FDI RX PLL too */
  3643. temp = I915_READ(fdi_rx_reg);
  3644. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  3645. I915_READ(fdi_rx_reg);
  3646. udelay(200);
  3647. /* enable FDI TX PLL too */
  3648. temp = I915_READ(fdi_tx_reg);
  3649. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  3650. I915_READ(fdi_tx_reg);
  3651. /* enable FDI RX PCDCLK */
  3652. temp = I915_READ(fdi_rx_reg);
  3653. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  3654. I915_READ(fdi_rx_reg);
  3655. udelay(200);
  3656. }
  3657. }
  3658. I915_WRITE(pipeconf_reg, pipeconf);
  3659. I915_READ(pipeconf_reg);
  3660. intel_wait_for_vblank(dev);
  3661. if (IS_IRONLAKE(dev)) {
  3662. /* enable address swizzle for tiling buffer */
  3663. temp = I915_READ(DISP_ARB_CTL);
  3664. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  3665. }
  3666. I915_WRITE(dspcntr_reg, dspcntr);
  3667. /* Flush the plane changes */
  3668. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  3669. if ((IS_I965G(dev) || plane == 0))
  3670. intel_update_fbc(crtc, &crtc->mode);
  3671. intel_update_watermarks(dev);
  3672. drm_vblank_post_modeset(dev, pipe);
  3673. return ret;
  3674. }
  3675. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  3676. void intel_crtc_load_lut(struct drm_crtc *crtc)
  3677. {
  3678. struct drm_device *dev = crtc->dev;
  3679. struct drm_i915_private *dev_priv = dev->dev_private;
  3680. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3681. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  3682. int i;
  3683. /* The clocks have to be on to load the palette. */
  3684. if (!crtc->enabled)
  3685. return;
  3686. /* use legacy palette for Ironlake */
  3687. if (HAS_PCH_SPLIT(dev))
  3688. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  3689. LGC_PALETTE_B;
  3690. for (i = 0; i < 256; i++) {
  3691. I915_WRITE(palreg + 4 * i,
  3692. (intel_crtc->lut_r[i] << 16) |
  3693. (intel_crtc->lut_g[i] << 8) |
  3694. intel_crtc->lut_b[i]);
  3695. }
  3696. }
  3697. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  3698. static void intel_crtc_update_cursor(struct drm_crtc *crtc)
  3699. {
  3700. struct drm_device *dev = crtc->dev;
  3701. struct drm_i915_private *dev_priv = dev->dev_private;
  3702. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3703. int pipe = intel_crtc->pipe;
  3704. int x = intel_crtc->cursor_x;
  3705. int y = intel_crtc->cursor_y;
  3706. uint32_t base, pos;
  3707. bool visible;
  3708. pos = 0;
  3709. if (crtc->fb) {
  3710. base = intel_crtc->cursor_addr;
  3711. if (x > (int) crtc->fb->width)
  3712. base = 0;
  3713. if (y > (int) crtc->fb->height)
  3714. base = 0;
  3715. } else
  3716. base = 0;
  3717. if (x < 0) {
  3718. if (x + intel_crtc->cursor_width < 0)
  3719. base = 0;
  3720. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  3721. x = -x;
  3722. }
  3723. pos |= x << CURSOR_X_SHIFT;
  3724. if (y < 0) {
  3725. if (y + intel_crtc->cursor_height < 0)
  3726. base = 0;
  3727. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  3728. y = -y;
  3729. }
  3730. pos |= y << CURSOR_Y_SHIFT;
  3731. visible = base != 0;
  3732. if (!visible && !intel_crtc->cursor_visble)
  3733. return;
  3734. I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
  3735. if (intel_crtc->cursor_visble != visible) {
  3736. uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
  3737. if (base) {
  3738. /* Hooray for CUR*CNTR differences */
  3739. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  3740. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  3741. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  3742. cntl |= pipe << 28; /* Connect to correct pipe */
  3743. } else {
  3744. cntl &= ~(CURSOR_FORMAT_MASK);
  3745. cntl |= CURSOR_ENABLE;
  3746. cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  3747. }
  3748. } else {
  3749. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  3750. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  3751. cntl |= CURSOR_MODE_DISABLE;
  3752. } else {
  3753. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  3754. }
  3755. }
  3756. I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
  3757. intel_crtc->cursor_visble = visible;
  3758. }
  3759. /* and commit changes on next vblank */
  3760. I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
  3761. if (visible)
  3762. intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
  3763. }
  3764. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  3765. struct drm_file *file_priv,
  3766. uint32_t handle,
  3767. uint32_t width, uint32_t height)
  3768. {
  3769. struct drm_device *dev = crtc->dev;
  3770. struct drm_i915_private *dev_priv = dev->dev_private;
  3771. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3772. struct drm_gem_object *bo;
  3773. struct drm_i915_gem_object *obj_priv;
  3774. uint32_t addr;
  3775. int ret;
  3776. DRM_DEBUG_KMS("\n");
  3777. /* if we want to turn off the cursor ignore width and height */
  3778. if (!handle) {
  3779. DRM_DEBUG_KMS("cursor off\n");
  3780. addr = 0;
  3781. bo = NULL;
  3782. mutex_lock(&dev->struct_mutex);
  3783. goto finish;
  3784. }
  3785. /* Currently we only support 64x64 cursors */
  3786. if (width != 64 || height != 64) {
  3787. DRM_ERROR("we currently only support 64x64 cursors\n");
  3788. return -EINVAL;
  3789. }
  3790. bo = drm_gem_object_lookup(dev, file_priv, handle);
  3791. if (!bo)
  3792. return -ENOENT;
  3793. obj_priv = to_intel_bo(bo);
  3794. if (bo->size < width * height * 4) {
  3795. DRM_ERROR("buffer is to small\n");
  3796. ret = -ENOMEM;
  3797. goto fail;
  3798. }
  3799. /* we only need to pin inside GTT if cursor is non-phy */
  3800. mutex_lock(&dev->struct_mutex);
  3801. if (!dev_priv->info->cursor_needs_physical) {
  3802. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  3803. if (ret) {
  3804. DRM_ERROR("failed to pin cursor bo\n");
  3805. goto fail_locked;
  3806. }
  3807. ret = i915_gem_object_set_to_gtt_domain(bo, 0);
  3808. if (ret) {
  3809. DRM_ERROR("failed to move cursor bo into the GTT\n");
  3810. goto fail_unpin;
  3811. }
  3812. addr = obj_priv->gtt_offset;
  3813. } else {
  3814. ret = i915_gem_attach_phys_object(dev, bo,
  3815. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  3816. if (ret) {
  3817. DRM_ERROR("failed to attach phys object\n");
  3818. goto fail_locked;
  3819. }
  3820. addr = obj_priv->phys_obj->handle->busaddr;
  3821. }
  3822. if (!IS_I9XX(dev))
  3823. I915_WRITE(CURSIZE, (height << 12) | width);
  3824. finish:
  3825. if (intel_crtc->cursor_bo) {
  3826. if (dev_priv->info->cursor_needs_physical) {
  3827. if (intel_crtc->cursor_bo != bo)
  3828. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  3829. } else
  3830. i915_gem_object_unpin(intel_crtc->cursor_bo);
  3831. drm_gem_object_unreference(intel_crtc->cursor_bo);
  3832. }
  3833. mutex_unlock(&dev->struct_mutex);
  3834. intel_crtc->cursor_addr = addr;
  3835. intel_crtc->cursor_bo = bo;
  3836. intel_crtc->cursor_width = width;
  3837. intel_crtc->cursor_height = height;
  3838. intel_crtc_update_cursor(crtc);
  3839. return 0;
  3840. fail_unpin:
  3841. i915_gem_object_unpin(bo);
  3842. fail_locked:
  3843. mutex_unlock(&dev->struct_mutex);
  3844. fail:
  3845. drm_gem_object_unreference_unlocked(bo);
  3846. return ret;
  3847. }
  3848. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  3849. {
  3850. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3851. intel_crtc->cursor_x = x;
  3852. intel_crtc->cursor_y = y;
  3853. intel_crtc_update_cursor(crtc);
  3854. return 0;
  3855. }
  3856. /** Sets the color ramps on behalf of RandR */
  3857. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  3858. u16 blue, int regno)
  3859. {
  3860. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3861. intel_crtc->lut_r[regno] = red >> 8;
  3862. intel_crtc->lut_g[regno] = green >> 8;
  3863. intel_crtc->lut_b[regno] = blue >> 8;
  3864. }
  3865. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  3866. u16 *blue, int regno)
  3867. {
  3868. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3869. *red = intel_crtc->lut_r[regno] << 8;
  3870. *green = intel_crtc->lut_g[regno] << 8;
  3871. *blue = intel_crtc->lut_b[regno] << 8;
  3872. }
  3873. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  3874. u16 *blue, uint32_t start, uint32_t size)
  3875. {
  3876. int end = (start + size > 256) ? 256 : start + size, i;
  3877. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3878. for (i = start; i < end; i++) {
  3879. intel_crtc->lut_r[i] = red[i] >> 8;
  3880. intel_crtc->lut_g[i] = green[i] >> 8;
  3881. intel_crtc->lut_b[i] = blue[i] >> 8;
  3882. }
  3883. intel_crtc_load_lut(crtc);
  3884. }
  3885. /**
  3886. * Get a pipe with a simple mode set on it for doing load-based monitor
  3887. * detection.
  3888. *
  3889. * It will be up to the load-detect code to adjust the pipe as appropriate for
  3890. * its requirements. The pipe will be connected to no other encoders.
  3891. *
  3892. * Currently this code will only succeed if there is a pipe with no encoders
  3893. * configured for it. In the future, it could choose to temporarily disable
  3894. * some outputs to free up a pipe for its use.
  3895. *
  3896. * \return crtc, or NULL if no pipes are available.
  3897. */
  3898. /* VESA 640x480x72Hz mode to set on the pipe */
  3899. static struct drm_display_mode load_detect_mode = {
  3900. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  3901. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  3902. };
  3903. struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  3904. struct drm_connector *connector,
  3905. struct drm_display_mode *mode,
  3906. int *dpms_mode)
  3907. {
  3908. struct intel_crtc *intel_crtc;
  3909. struct drm_crtc *possible_crtc;
  3910. struct drm_crtc *supported_crtc =NULL;
  3911. struct drm_encoder *encoder = &intel_encoder->enc;
  3912. struct drm_crtc *crtc = NULL;
  3913. struct drm_device *dev = encoder->dev;
  3914. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3915. struct drm_crtc_helper_funcs *crtc_funcs;
  3916. int i = -1;
  3917. /*
  3918. * Algorithm gets a little messy:
  3919. * - if the connector already has an assigned crtc, use it (but make
  3920. * sure it's on first)
  3921. * - try to find the first unused crtc that can drive this connector,
  3922. * and use that if we find one
  3923. * - if there are no unused crtcs available, try to use the first
  3924. * one we found that supports the connector
  3925. */
  3926. /* See if we already have a CRTC for this connector */
  3927. if (encoder->crtc) {
  3928. crtc = encoder->crtc;
  3929. /* Make sure the crtc and connector are running */
  3930. intel_crtc = to_intel_crtc(crtc);
  3931. *dpms_mode = intel_crtc->dpms_mode;
  3932. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3933. crtc_funcs = crtc->helper_private;
  3934. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3935. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3936. }
  3937. return crtc;
  3938. }
  3939. /* Find an unused one (if possible) */
  3940. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3941. i++;
  3942. if (!(encoder->possible_crtcs & (1 << i)))
  3943. continue;
  3944. if (!possible_crtc->enabled) {
  3945. crtc = possible_crtc;
  3946. break;
  3947. }
  3948. if (!supported_crtc)
  3949. supported_crtc = possible_crtc;
  3950. }
  3951. /*
  3952. * If we didn't find an unused CRTC, don't use any.
  3953. */
  3954. if (!crtc) {
  3955. return NULL;
  3956. }
  3957. encoder->crtc = crtc;
  3958. connector->encoder = encoder;
  3959. intel_encoder->load_detect_temp = true;
  3960. intel_crtc = to_intel_crtc(crtc);
  3961. *dpms_mode = intel_crtc->dpms_mode;
  3962. if (!crtc->enabled) {
  3963. if (!mode)
  3964. mode = &load_detect_mode;
  3965. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  3966. } else {
  3967. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3968. crtc_funcs = crtc->helper_private;
  3969. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3970. }
  3971. /* Add this connector to the crtc */
  3972. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  3973. encoder_funcs->commit(encoder);
  3974. }
  3975. /* let the connector get through one full cycle before testing */
  3976. intel_wait_for_vblank(dev);
  3977. return crtc;
  3978. }
  3979. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  3980. struct drm_connector *connector, int dpms_mode)
  3981. {
  3982. struct drm_encoder *encoder = &intel_encoder->enc;
  3983. struct drm_device *dev = encoder->dev;
  3984. struct drm_crtc *crtc = encoder->crtc;
  3985. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3986. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  3987. if (intel_encoder->load_detect_temp) {
  3988. encoder->crtc = NULL;
  3989. connector->encoder = NULL;
  3990. intel_encoder->load_detect_temp = false;
  3991. crtc->enabled = drm_helper_crtc_in_use(crtc);
  3992. drm_helper_disable_unused_functions(dev);
  3993. }
  3994. /* Switch crtc and encoder back off if necessary */
  3995. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  3996. if (encoder->crtc == crtc)
  3997. encoder_funcs->dpms(encoder, dpms_mode);
  3998. crtc_funcs->dpms(crtc, dpms_mode);
  3999. }
  4000. }
  4001. /* Returns the clock of the currently programmed mode of the given pipe. */
  4002. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  4003. {
  4004. struct drm_i915_private *dev_priv = dev->dev_private;
  4005. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4006. int pipe = intel_crtc->pipe;
  4007. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  4008. u32 fp;
  4009. intel_clock_t clock;
  4010. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  4011. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  4012. else
  4013. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  4014. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  4015. if (IS_PINEVIEW(dev)) {
  4016. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  4017. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  4018. } else {
  4019. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  4020. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  4021. }
  4022. if (IS_I9XX(dev)) {
  4023. if (IS_PINEVIEW(dev))
  4024. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  4025. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  4026. else
  4027. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  4028. DPLL_FPA01_P1_POST_DIV_SHIFT);
  4029. switch (dpll & DPLL_MODE_MASK) {
  4030. case DPLLB_MODE_DAC_SERIAL:
  4031. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  4032. 5 : 10;
  4033. break;
  4034. case DPLLB_MODE_LVDS:
  4035. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  4036. 7 : 14;
  4037. break;
  4038. default:
  4039. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  4040. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  4041. return 0;
  4042. }
  4043. /* XXX: Handle the 100Mhz refclk */
  4044. intel_clock(dev, 96000, &clock);
  4045. } else {
  4046. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  4047. if (is_lvds) {
  4048. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  4049. DPLL_FPA01_P1_POST_DIV_SHIFT);
  4050. clock.p2 = 14;
  4051. if ((dpll & PLL_REF_INPUT_MASK) ==
  4052. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  4053. /* XXX: might not be 66MHz */
  4054. intel_clock(dev, 66000, &clock);
  4055. } else
  4056. intel_clock(dev, 48000, &clock);
  4057. } else {
  4058. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  4059. clock.p1 = 2;
  4060. else {
  4061. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  4062. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  4063. }
  4064. if (dpll & PLL_P2_DIVIDE_BY_4)
  4065. clock.p2 = 4;
  4066. else
  4067. clock.p2 = 2;
  4068. intel_clock(dev, 48000, &clock);
  4069. }
  4070. }
  4071. /* XXX: It would be nice to validate the clocks, but we can't reuse
  4072. * i830PllIsValid() because it relies on the xf86_config connector
  4073. * configuration being accurate, which it isn't necessarily.
  4074. */
  4075. return clock.dot;
  4076. }
  4077. /** Returns the currently programmed mode of the given pipe. */
  4078. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  4079. struct drm_crtc *crtc)
  4080. {
  4081. struct drm_i915_private *dev_priv = dev->dev_private;
  4082. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4083. int pipe = intel_crtc->pipe;
  4084. struct drm_display_mode *mode;
  4085. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  4086. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  4087. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  4088. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  4089. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  4090. if (!mode)
  4091. return NULL;
  4092. mode->clock = intel_crtc_clock_get(dev, crtc);
  4093. mode->hdisplay = (htot & 0xffff) + 1;
  4094. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  4095. mode->hsync_start = (hsync & 0xffff) + 1;
  4096. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  4097. mode->vdisplay = (vtot & 0xffff) + 1;
  4098. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  4099. mode->vsync_start = (vsync & 0xffff) + 1;
  4100. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  4101. drm_mode_set_name(mode);
  4102. drm_mode_set_crtcinfo(mode, 0);
  4103. return mode;
  4104. }
  4105. #define GPU_IDLE_TIMEOUT 500 /* ms */
  4106. /* When this timer fires, we've been idle for awhile */
  4107. static void intel_gpu_idle_timer(unsigned long arg)
  4108. {
  4109. struct drm_device *dev = (struct drm_device *)arg;
  4110. drm_i915_private_t *dev_priv = dev->dev_private;
  4111. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  4112. dev_priv->busy = false;
  4113. queue_work(dev_priv->wq, &dev_priv->idle_work);
  4114. }
  4115. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  4116. static void intel_crtc_idle_timer(unsigned long arg)
  4117. {
  4118. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  4119. struct drm_crtc *crtc = &intel_crtc->base;
  4120. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  4121. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  4122. intel_crtc->busy = false;
  4123. queue_work(dev_priv->wq, &dev_priv->idle_work);
  4124. }
  4125. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
  4126. {
  4127. struct drm_device *dev = crtc->dev;
  4128. drm_i915_private_t *dev_priv = dev->dev_private;
  4129. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4130. int pipe = intel_crtc->pipe;
  4131. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  4132. int dpll = I915_READ(dpll_reg);
  4133. if (HAS_PCH_SPLIT(dev))
  4134. return;
  4135. if (!dev_priv->lvds_downclock_avail)
  4136. return;
  4137. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  4138. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  4139. /* Unlock panel regs */
  4140. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  4141. PANEL_UNLOCK_REGS);
  4142. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  4143. I915_WRITE(dpll_reg, dpll);
  4144. dpll = I915_READ(dpll_reg);
  4145. intel_wait_for_vblank(dev);
  4146. dpll = I915_READ(dpll_reg);
  4147. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  4148. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  4149. /* ...and lock them again */
  4150. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  4151. }
  4152. /* Schedule downclock */
  4153. if (schedule)
  4154. mod_timer(&intel_crtc->idle_timer, jiffies +
  4155. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  4156. }
  4157. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  4158. {
  4159. struct drm_device *dev = crtc->dev;
  4160. drm_i915_private_t *dev_priv = dev->dev_private;
  4161. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4162. int pipe = intel_crtc->pipe;
  4163. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  4164. int dpll = I915_READ(dpll_reg);
  4165. if (HAS_PCH_SPLIT(dev))
  4166. return;
  4167. if (!dev_priv->lvds_downclock_avail)
  4168. return;
  4169. /*
  4170. * Since this is called by a timer, we should never get here in
  4171. * the manual case.
  4172. */
  4173. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  4174. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  4175. /* Unlock panel regs */
  4176. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  4177. PANEL_UNLOCK_REGS);
  4178. dpll |= DISPLAY_RATE_SELECT_FPA1;
  4179. I915_WRITE(dpll_reg, dpll);
  4180. dpll = I915_READ(dpll_reg);
  4181. intel_wait_for_vblank(dev);
  4182. dpll = I915_READ(dpll_reg);
  4183. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  4184. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  4185. /* ...and lock them again */
  4186. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  4187. }
  4188. }
  4189. /**
  4190. * intel_idle_update - adjust clocks for idleness
  4191. * @work: work struct
  4192. *
  4193. * Either the GPU or display (or both) went idle. Check the busy status
  4194. * here and adjust the CRTC and GPU clocks as necessary.
  4195. */
  4196. static void intel_idle_update(struct work_struct *work)
  4197. {
  4198. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  4199. idle_work);
  4200. struct drm_device *dev = dev_priv->dev;
  4201. struct drm_crtc *crtc;
  4202. struct intel_crtc *intel_crtc;
  4203. int enabled = 0;
  4204. if (!i915_powersave)
  4205. return;
  4206. mutex_lock(&dev->struct_mutex);
  4207. i915_update_gfx_val(dev_priv);
  4208. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4209. /* Skip inactive CRTCs */
  4210. if (!crtc->fb)
  4211. continue;
  4212. enabled++;
  4213. intel_crtc = to_intel_crtc(crtc);
  4214. if (!intel_crtc->busy)
  4215. intel_decrease_pllclock(crtc);
  4216. }
  4217. if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
  4218. DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
  4219. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  4220. }
  4221. mutex_unlock(&dev->struct_mutex);
  4222. }
  4223. /**
  4224. * intel_mark_busy - mark the GPU and possibly the display busy
  4225. * @dev: drm device
  4226. * @obj: object we're operating on
  4227. *
  4228. * Callers can use this function to indicate that the GPU is busy processing
  4229. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  4230. * buffer), we'll also mark the display as busy, so we know to increase its
  4231. * clock frequency.
  4232. */
  4233. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  4234. {
  4235. drm_i915_private_t *dev_priv = dev->dev_private;
  4236. struct drm_crtc *crtc = NULL;
  4237. struct intel_framebuffer *intel_fb;
  4238. struct intel_crtc *intel_crtc;
  4239. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  4240. return;
  4241. if (!dev_priv->busy) {
  4242. if (IS_I945G(dev) || IS_I945GM(dev)) {
  4243. u32 fw_blc_self;
  4244. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  4245. fw_blc_self = I915_READ(FW_BLC_SELF);
  4246. fw_blc_self &= ~FW_BLC_SELF_EN;
  4247. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  4248. }
  4249. dev_priv->busy = true;
  4250. } else
  4251. mod_timer(&dev_priv->idle_timer, jiffies +
  4252. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  4253. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4254. if (!crtc->fb)
  4255. continue;
  4256. intel_crtc = to_intel_crtc(crtc);
  4257. intel_fb = to_intel_framebuffer(crtc->fb);
  4258. if (intel_fb->obj == obj) {
  4259. if (!intel_crtc->busy) {
  4260. if (IS_I945G(dev) || IS_I945GM(dev)) {
  4261. u32 fw_blc_self;
  4262. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  4263. fw_blc_self = I915_READ(FW_BLC_SELF);
  4264. fw_blc_self &= ~FW_BLC_SELF_EN;
  4265. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  4266. }
  4267. /* Non-busy -> busy, upclock */
  4268. intel_increase_pllclock(crtc, true);
  4269. intel_crtc->busy = true;
  4270. } else {
  4271. /* Busy -> busy, put off timer */
  4272. mod_timer(&intel_crtc->idle_timer, jiffies +
  4273. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  4274. }
  4275. }
  4276. }
  4277. }
  4278. static void intel_crtc_destroy(struct drm_crtc *crtc)
  4279. {
  4280. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4281. drm_crtc_cleanup(crtc);
  4282. kfree(intel_crtc);
  4283. }
  4284. struct intel_unpin_work {
  4285. struct work_struct work;
  4286. struct drm_device *dev;
  4287. struct drm_gem_object *old_fb_obj;
  4288. struct drm_gem_object *pending_flip_obj;
  4289. struct drm_pending_vblank_event *event;
  4290. int pending;
  4291. };
  4292. static void intel_unpin_work_fn(struct work_struct *__work)
  4293. {
  4294. struct intel_unpin_work *work =
  4295. container_of(__work, struct intel_unpin_work, work);
  4296. mutex_lock(&work->dev->struct_mutex);
  4297. i915_gem_object_unpin(work->old_fb_obj);
  4298. drm_gem_object_unreference(work->pending_flip_obj);
  4299. drm_gem_object_unreference(work->old_fb_obj);
  4300. mutex_unlock(&work->dev->struct_mutex);
  4301. kfree(work);
  4302. }
  4303. static void do_intel_finish_page_flip(struct drm_device *dev,
  4304. struct drm_crtc *crtc)
  4305. {
  4306. drm_i915_private_t *dev_priv = dev->dev_private;
  4307. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4308. struct intel_unpin_work *work;
  4309. struct drm_i915_gem_object *obj_priv;
  4310. struct drm_pending_vblank_event *e;
  4311. struct timeval now;
  4312. unsigned long flags;
  4313. /* Ignore early vblank irqs */
  4314. if (intel_crtc == NULL)
  4315. return;
  4316. spin_lock_irqsave(&dev->event_lock, flags);
  4317. work = intel_crtc->unpin_work;
  4318. if (work == NULL || !work->pending) {
  4319. spin_unlock_irqrestore(&dev->event_lock, flags);
  4320. return;
  4321. }
  4322. intel_crtc->unpin_work = NULL;
  4323. drm_vblank_put(dev, intel_crtc->pipe);
  4324. if (work->event) {
  4325. e = work->event;
  4326. do_gettimeofday(&now);
  4327. e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
  4328. e->event.tv_sec = now.tv_sec;
  4329. e->event.tv_usec = now.tv_usec;
  4330. list_add_tail(&e->base.link,
  4331. &e->base.file_priv->event_list);
  4332. wake_up_interruptible(&e->base.file_priv->event_wait);
  4333. }
  4334. spin_unlock_irqrestore(&dev->event_lock, flags);
  4335. obj_priv = to_intel_bo(work->pending_flip_obj);
  4336. /* Initial scanout buffer will have a 0 pending flip count */
  4337. if ((atomic_read(&obj_priv->pending_flip) == 0) ||
  4338. atomic_dec_and_test(&obj_priv->pending_flip))
  4339. DRM_WAKEUP(&dev_priv->pending_flip_queue);
  4340. schedule_work(&work->work);
  4341. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  4342. }
  4343. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  4344. {
  4345. drm_i915_private_t *dev_priv = dev->dev_private;
  4346. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  4347. do_intel_finish_page_flip(dev, crtc);
  4348. }
  4349. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  4350. {
  4351. drm_i915_private_t *dev_priv = dev->dev_private;
  4352. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  4353. do_intel_finish_page_flip(dev, crtc);
  4354. }
  4355. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  4356. {
  4357. drm_i915_private_t *dev_priv = dev->dev_private;
  4358. struct intel_crtc *intel_crtc =
  4359. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  4360. unsigned long flags;
  4361. spin_lock_irqsave(&dev->event_lock, flags);
  4362. if (intel_crtc->unpin_work) {
  4363. intel_crtc->unpin_work->pending = 1;
  4364. } else {
  4365. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  4366. }
  4367. spin_unlock_irqrestore(&dev->event_lock, flags);
  4368. }
  4369. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  4370. struct drm_framebuffer *fb,
  4371. struct drm_pending_vblank_event *event)
  4372. {
  4373. struct drm_device *dev = crtc->dev;
  4374. struct drm_i915_private *dev_priv = dev->dev_private;
  4375. struct intel_framebuffer *intel_fb;
  4376. struct drm_i915_gem_object *obj_priv;
  4377. struct drm_gem_object *obj;
  4378. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4379. struct intel_unpin_work *work;
  4380. unsigned long flags, offset;
  4381. int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
  4382. int ret, pipesrc;
  4383. u32 flip_mask;
  4384. work = kzalloc(sizeof *work, GFP_KERNEL);
  4385. if (work == NULL)
  4386. return -ENOMEM;
  4387. work->event = event;
  4388. work->dev = crtc->dev;
  4389. intel_fb = to_intel_framebuffer(crtc->fb);
  4390. work->old_fb_obj = intel_fb->obj;
  4391. INIT_WORK(&work->work, intel_unpin_work_fn);
  4392. /* We borrow the event spin lock for protecting unpin_work */
  4393. spin_lock_irqsave(&dev->event_lock, flags);
  4394. if (intel_crtc->unpin_work) {
  4395. spin_unlock_irqrestore(&dev->event_lock, flags);
  4396. kfree(work);
  4397. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  4398. return -EBUSY;
  4399. }
  4400. intel_crtc->unpin_work = work;
  4401. spin_unlock_irqrestore(&dev->event_lock, flags);
  4402. intel_fb = to_intel_framebuffer(fb);
  4403. obj = intel_fb->obj;
  4404. mutex_lock(&dev->struct_mutex);
  4405. ret = intel_pin_and_fence_fb_obj(dev, obj);
  4406. if (ret)
  4407. goto cleanup_work;
  4408. /* Reference the objects for the scheduled work. */
  4409. drm_gem_object_reference(work->old_fb_obj);
  4410. drm_gem_object_reference(obj);
  4411. crtc->fb = fb;
  4412. ret = i915_gem_object_flush_write_domain(obj);
  4413. if (ret)
  4414. goto cleanup_objs;
  4415. ret = drm_vblank_get(dev, intel_crtc->pipe);
  4416. if (ret)
  4417. goto cleanup_objs;
  4418. obj_priv = to_intel_bo(obj);
  4419. atomic_inc(&obj_priv->pending_flip);
  4420. work->pending_flip_obj = obj;
  4421. if (intel_crtc->plane)
  4422. flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  4423. else
  4424. flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
  4425. /* Wait for any previous flip to finish */
  4426. if (IS_GEN3(dev))
  4427. while (I915_READ(ISR) & flip_mask)
  4428. ;
  4429. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  4430. offset = obj_priv->gtt_offset;
  4431. offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
  4432. BEGIN_LP_RING(4);
  4433. if (IS_I965G(dev)) {
  4434. OUT_RING(MI_DISPLAY_FLIP |
  4435. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4436. OUT_RING(fb->pitch);
  4437. OUT_RING(offset | obj_priv->tiling_mode);
  4438. pipesrc = I915_READ(pipesrc_reg);
  4439. OUT_RING(pipesrc & 0x0fff0fff);
  4440. } else {
  4441. OUT_RING(MI_DISPLAY_FLIP_I915 |
  4442. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4443. OUT_RING(fb->pitch);
  4444. OUT_RING(offset);
  4445. OUT_RING(MI_NOOP);
  4446. }
  4447. ADVANCE_LP_RING();
  4448. mutex_unlock(&dev->struct_mutex);
  4449. trace_i915_flip_request(intel_crtc->plane, obj);
  4450. return 0;
  4451. cleanup_objs:
  4452. drm_gem_object_unreference(work->old_fb_obj);
  4453. drm_gem_object_unreference(obj);
  4454. cleanup_work:
  4455. mutex_unlock(&dev->struct_mutex);
  4456. spin_lock_irqsave(&dev->event_lock, flags);
  4457. intel_crtc->unpin_work = NULL;
  4458. spin_unlock_irqrestore(&dev->event_lock, flags);
  4459. kfree(work);
  4460. return ret;
  4461. }
  4462. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  4463. .dpms = intel_crtc_dpms,
  4464. .mode_fixup = intel_crtc_mode_fixup,
  4465. .mode_set = intel_crtc_mode_set,
  4466. .mode_set_base = intel_pipe_set_base,
  4467. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  4468. .prepare = intel_crtc_prepare,
  4469. .commit = intel_crtc_commit,
  4470. .load_lut = intel_crtc_load_lut,
  4471. };
  4472. static const struct drm_crtc_funcs intel_crtc_funcs = {
  4473. .cursor_set = intel_crtc_cursor_set,
  4474. .cursor_move = intel_crtc_cursor_move,
  4475. .gamma_set = intel_crtc_gamma_set,
  4476. .set_config = drm_crtc_helper_set_config,
  4477. .destroy = intel_crtc_destroy,
  4478. .page_flip = intel_crtc_page_flip,
  4479. };
  4480. static void intel_crtc_init(struct drm_device *dev, int pipe)
  4481. {
  4482. drm_i915_private_t *dev_priv = dev->dev_private;
  4483. struct intel_crtc *intel_crtc;
  4484. int i;
  4485. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  4486. if (intel_crtc == NULL)
  4487. return;
  4488. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  4489. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  4490. intel_crtc->pipe = pipe;
  4491. intel_crtc->plane = pipe;
  4492. for (i = 0; i < 256; i++) {
  4493. intel_crtc->lut_r[i] = i;
  4494. intel_crtc->lut_g[i] = i;
  4495. intel_crtc->lut_b[i] = i;
  4496. }
  4497. /* Swap pipes & planes for FBC on pre-965 */
  4498. intel_crtc->pipe = pipe;
  4499. intel_crtc->plane = pipe;
  4500. if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
  4501. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  4502. intel_crtc->plane = ((pipe == 0) ? 1 : 0);
  4503. }
  4504. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  4505. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  4506. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  4507. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  4508. intel_crtc->cursor_addr = 0;
  4509. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  4510. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  4511. intel_crtc->busy = false;
  4512. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  4513. (unsigned long)intel_crtc);
  4514. }
  4515. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  4516. struct drm_file *file_priv)
  4517. {
  4518. drm_i915_private_t *dev_priv = dev->dev_private;
  4519. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  4520. struct drm_mode_object *drmmode_obj;
  4521. struct intel_crtc *crtc;
  4522. if (!dev_priv) {
  4523. DRM_ERROR("called with no initialization\n");
  4524. return -EINVAL;
  4525. }
  4526. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  4527. DRM_MODE_OBJECT_CRTC);
  4528. if (!drmmode_obj) {
  4529. DRM_ERROR("no such CRTC id\n");
  4530. return -EINVAL;
  4531. }
  4532. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  4533. pipe_from_crtc_id->pipe = crtc->pipe;
  4534. return 0;
  4535. }
  4536. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  4537. {
  4538. struct drm_crtc *crtc = NULL;
  4539. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4540. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4541. if (intel_crtc->pipe == pipe)
  4542. break;
  4543. }
  4544. return crtc;
  4545. }
  4546. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  4547. {
  4548. int index_mask = 0;
  4549. struct drm_encoder *encoder;
  4550. int entry = 0;
  4551. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4552. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  4553. if (type_mask & intel_encoder->clone_mask)
  4554. index_mask |= (1 << entry);
  4555. entry++;
  4556. }
  4557. return index_mask;
  4558. }
  4559. static void intel_setup_outputs(struct drm_device *dev)
  4560. {
  4561. struct drm_i915_private *dev_priv = dev->dev_private;
  4562. struct drm_encoder *encoder;
  4563. bool dpd_is_edp = false;
  4564. if (IS_MOBILE(dev) && !IS_I830(dev))
  4565. intel_lvds_init(dev);
  4566. if (HAS_PCH_SPLIT(dev)) {
  4567. dpd_is_edp = intel_dpd_is_edp(dev);
  4568. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  4569. intel_dp_init(dev, DP_A);
  4570. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  4571. intel_dp_init(dev, PCH_DP_D);
  4572. }
  4573. intel_crt_init(dev);
  4574. if (HAS_PCH_SPLIT(dev)) {
  4575. int found;
  4576. if (I915_READ(HDMIB) & PORT_DETECTED) {
  4577. /* PCH SDVOB multiplex with HDMIB */
  4578. found = intel_sdvo_init(dev, PCH_SDVOB);
  4579. if (!found)
  4580. intel_hdmi_init(dev, HDMIB);
  4581. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  4582. intel_dp_init(dev, PCH_DP_B);
  4583. }
  4584. if (I915_READ(HDMIC) & PORT_DETECTED)
  4585. intel_hdmi_init(dev, HDMIC);
  4586. if (I915_READ(HDMID) & PORT_DETECTED)
  4587. intel_hdmi_init(dev, HDMID);
  4588. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  4589. intel_dp_init(dev, PCH_DP_C);
  4590. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  4591. intel_dp_init(dev, PCH_DP_D);
  4592. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  4593. bool found = false;
  4594. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4595. DRM_DEBUG_KMS("probing SDVOB\n");
  4596. found = intel_sdvo_init(dev, SDVOB);
  4597. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  4598. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  4599. intel_hdmi_init(dev, SDVOB);
  4600. }
  4601. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  4602. DRM_DEBUG_KMS("probing DP_B\n");
  4603. intel_dp_init(dev, DP_B);
  4604. }
  4605. }
  4606. /* Before G4X SDVOC doesn't have its own detect register */
  4607. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4608. DRM_DEBUG_KMS("probing SDVOC\n");
  4609. found = intel_sdvo_init(dev, SDVOC);
  4610. }
  4611. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  4612. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  4613. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  4614. intel_hdmi_init(dev, SDVOC);
  4615. }
  4616. if (SUPPORTS_INTEGRATED_DP(dev)) {
  4617. DRM_DEBUG_KMS("probing DP_C\n");
  4618. intel_dp_init(dev, DP_C);
  4619. }
  4620. }
  4621. if (SUPPORTS_INTEGRATED_DP(dev) &&
  4622. (I915_READ(DP_D) & DP_DETECTED)) {
  4623. DRM_DEBUG_KMS("probing DP_D\n");
  4624. intel_dp_init(dev, DP_D);
  4625. }
  4626. } else if (IS_GEN2(dev))
  4627. intel_dvo_init(dev);
  4628. if (SUPPORTS_TV(dev))
  4629. intel_tv_init(dev);
  4630. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4631. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  4632. encoder->possible_crtcs = intel_encoder->crtc_mask;
  4633. encoder->possible_clones = intel_encoder_clones(dev,
  4634. intel_encoder->clone_mask);
  4635. }
  4636. }
  4637. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  4638. {
  4639. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4640. drm_framebuffer_cleanup(fb);
  4641. drm_gem_object_unreference_unlocked(intel_fb->obj);
  4642. kfree(intel_fb);
  4643. }
  4644. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  4645. struct drm_file *file_priv,
  4646. unsigned int *handle)
  4647. {
  4648. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4649. struct drm_gem_object *object = intel_fb->obj;
  4650. return drm_gem_handle_create(file_priv, object, handle);
  4651. }
  4652. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  4653. .destroy = intel_user_framebuffer_destroy,
  4654. .create_handle = intel_user_framebuffer_create_handle,
  4655. };
  4656. int intel_framebuffer_init(struct drm_device *dev,
  4657. struct intel_framebuffer *intel_fb,
  4658. struct drm_mode_fb_cmd *mode_cmd,
  4659. struct drm_gem_object *obj)
  4660. {
  4661. int ret;
  4662. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  4663. if (ret) {
  4664. DRM_ERROR("framebuffer init failed %d\n", ret);
  4665. return ret;
  4666. }
  4667. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  4668. intel_fb->obj = obj;
  4669. return 0;
  4670. }
  4671. static struct drm_framebuffer *
  4672. intel_user_framebuffer_create(struct drm_device *dev,
  4673. struct drm_file *filp,
  4674. struct drm_mode_fb_cmd *mode_cmd)
  4675. {
  4676. struct drm_gem_object *obj;
  4677. struct intel_framebuffer *intel_fb;
  4678. int ret;
  4679. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  4680. if (!obj)
  4681. return ERR_PTR(-ENOENT);
  4682. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4683. if (!intel_fb)
  4684. return ERR_PTR(-ENOMEM);
  4685. ret = intel_framebuffer_init(dev, intel_fb,
  4686. mode_cmd, obj);
  4687. if (ret) {
  4688. drm_gem_object_unreference_unlocked(obj);
  4689. kfree(intel_fb);
  4690. return ERR_PTR(ret);
  4691. }
  4692. return &intel_fb->base;
  4693. }
  4694. static const struct drm_mode_config_funcs intel_mode_funcs = {
  4695. .fb_create = intel_user_framebuffer_create,
  4696. .output_poll_changed = intel_fb_output_poll_changed,
  4697. };
  4698. static struct drm_gem_object *
  4699. intel_alloc_power_context(struct drm_device *dev)
  4700. {
  4701. struct drm_gem_object *pwrctx;
  4702. int ret;
  4703. pwrctx = i915_gem_alloc_object(dev, 4096);
  4704. if (!pwrctx) {
  4705. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  4706. return NULL;
  4707. }
  4708. mutex_lock(&dev->struct_mutex);
  4709. ret = i915_gem_object_pin(pwrctx, 4096);
  4710. if (ret) {
  4711. DRM_ERROR("failed to pin power context: %d\n", ret);
  4712. goto err_unref;
  4713. }
  4714. ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
  4715. if (ret) {
  4716. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  4717. goto err_unpin;
  4718. }
  4719. mutex_unlock(&dev->struct_mutex);
  4720. return pwrctx;
  4721. err_unpin:
  4722. i915_gem_object_unpin(pwrctx);
  4723. err_unref:
  4724. drm_gem_object_unreference(pwrctx);
  4725. mutex_unlock(&dev->struct_mutex);
  4726. return NULL;
  4727. }
  4728. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  4729. {
  4730. struct drm_i915_private *dev_priv = dev->dev_private;
  4731. u16 rgvswctl;
  4732. rgvswctl = I915_READ16(MEMSWCTL);
  4733. if (rgvswctl & MEMCTL_CMD_STS) {
  4734. DRM_DEBUG("gpu busy, RCS change rejected\n");
  4735. return false; /* still busy with another command */
  4736. }
  4737. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  4738. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  4739. I915_WRITE16(MEMSWCTL, rgvswctl);
  4740. POSTING_READ16(MEMSWCTL);
  4741. rgvswctl |= MEMCTL_CMD_STS;
  4742. I915_WRITE16(MEMSWCTL, rgvswctl);
  4743. return true;
  4744. }
  4745. void ironlake_enable_drps(struct drm_device *dev)
  4746. {
  4747. struct drm_i915_private *dev_priv = dev->dev_private;
  4748. u32 rgvmodectl = I915_READ(MEMMODECTL);
  4749. u8 fmax, fmin, fstart, vstart;
  4750. int i = 0;
  4751. /* 100ms RC evaluation intervals */
  4752. I915_WRITE(RCUPEI, 100000);
  4753. I915_WRITE(RCDNEI, 100000);
  4754. /* Set max/min thresholds to 90ms and 80ms respectively */
  4755. I915_WRITE(RCBMAXAVG, 90000);
  4756. I915_WRITE(RCBMINAVG, 80000);
  4757. I915_WRITE(MEMIHYST, 1);
  4758. /* Set up min, max, and cur for interrupt handling */
  4759. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  4760. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  4761. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  4762. MEMMODE_FSTART_SHIFT;
  4763. fstart = fmax;
  4764. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  4765. PXVFREQ_PX_SHIFT;
  4766. dev_priv->fmax = fstart; /* IPS callback will increase this */
  4767. dev_priv->fstart = fstart;
  4768. dev_priv->max_delay = fmax;
  4769. dev_priv->min_delay = fmin;
  4770. dev_priv->cur_delay = fstart;
  4771. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
  4772. fstart);
  4773. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  4774. /*
  4775. * Interrupts will be enabled in ironlake_irq_postinstall
  4776. */
  4777. I915_WRITE(VIDSTART, vstart);
  4778. POSTING_READ(VIDSTART);
  4779. rgvmodectl |= MEMMODE_SWMODE_EN;
  4780. I915_WRITE(MEMMODECTL, rgvmodectl);
  4781. while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
  4782. if (i++ > 100) {
  4783. DRM_ERROR("stuck trying to change perf mode\n");
  4784. break;
  4785. }
  4786. msleep(1);
  4787. }
  4788. msleep(1);
  4789. ironlake_set_drps(dev, fstart);
  4790. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  4791. I915_READ(0x112e0);
  4792. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  4793. dev_priv->last_count2 = I915_READ(0x112f4);
  4794. getrawmonotonic(&dev_priv->last_time2);
  4795. }
  4796. void ironlake_disable_drps(struct drm_device *dev)
  4797. {
  4798. struct drm_i915_private *dev_priv = dev->dev_private;
  4799. u16 rgvswctl = I915_READ16(MEMSWCTL);
  4800. /* Ack interrupts, disable EFC interrupt */
  4801. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  4802. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  4803. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  4804. I915_WRITE(DEIIR, DE_PCU_EVENT);
  4805. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  4806. /* Go back to the starting frequency */
  4807. ironlake_set_drps(dev, dev_priv->fstart);
  4808. msleep(1);
  4809. rgvswctl |= MEMCTL_CMD_STS;
  4810. I915_WRITE(MEMSWCTL, rgvswctl);
  4811. msleep(1);
  4812. }
  4813. static unsigned long intel_pxfreq(u32 vidfreq)
  4814. {
  4815. unsigned long freq;
  4816. int div = (vidfreq & 0x3f0000) >> 16;
  4817. int post = (vidfreq & 0x3000) >> 12;
  4818. int pre = (vidfreq & 0x7);
  4819. if (!pre)
  4820. return 0;
  4821. freq = ((div * 133333) / ((1<<post) * pre));
  4822. return freq;
  4823. }
  4824. void intel_init_emon(struct drm_device *dev)
  4825. {
  4826. struct drm_i915_private *dev_priv = dev->dev_private;
  4827. u32 lcfuse;
  4828. u8 pxw[16];
  4829. int i;
  4830. /* Disable to program */
  4831. I915_WRITE(ECR, 0);
  4832. POSTING_READ(ECR);
  4833. /* Program energy weights for various events */
  4834. I915_WRITE(SDEW, 0x15040d00);
  4835. I915_WRITE(CSIEW0, 0x007f0000);
  4836. I915_WRITE(CSIEW1, 0x1e220004);
  4837. I915_WRITE(CSIEW2, 0x04000004);
  4838. for (i = 0; i < 5; i++)
  4839. I915_WRITE(PEW + (i * 4), 0);
  4840. for (i = 0; i < 3; i++)
  4841. I915_WRITE(DEW + (i * 4), 0);
  4842. /* Program P-state weights to account for frequency power adjustment */
  4843. for (i = 0; i < 16; i++) {
  4844. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  4845. unsigned long freq = intel_pxfreq(pxvidfreq);
  4846. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  4847. PXVFREQ_PX_SHIFT;
  4848. unsigned long val;
  4849. val = vid * vid;
  4850. val *= (freq / 1000);
  4851. val *= 255;
  4852. val /= (127*127*900);
  4853. if (val > 0xff)
  4854. DRM_ERROR("bad pxval: %ld\n", val);
  4855. pxw[i] = val;
  4856. }
  4857. /* Render standby states get 0 weight */
  4858. pxw[14] = 0;
  4859. pxw[15] = 0;
  4860. for (i = 0; i < 4; i++) {
  4861. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  4862. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  4863. I915_WRITE(PXW + (i * 4), val);
  4864. }
  4865. /* Adjust magic regs to magic values (more experimental results) */
  4866. I915_WRITE(OGW0, 0);
  4867. I915_WRITE(OGW1, 0);
  4868. I915_WRITE(EG0, 0x00007f00);
  4869. I915_WRITE(EG1, 0x0000000e);
  4870. I915_WRITE(EG2, 0x000e0000);
  4871. I915_WRITE(EG3, 0x68000300);
  4872. I915_WRITE(EG4, 0x42000000);
  4873. I915_WRITE(EG5, 0x00140031);
  4874. I915_WRITE(EG6, 0);
  4875. I915_WRITE(EG7, 0);
  4876. for (i = 0; i < 8; i++)
  4877. I915_WRITE(PXWL + (i * 4), 0);
  4878. /* Enable PMON + select events */
  4879. I915_WRITE(ECR, 0x80000019);
  4880. lcfuse = I915_READ(LCFUSE02);
  4881. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  4882. }
  4883. void intel_init_clock_gating(struct drm_device *dev)
  4884. {
  4885. struct drm_i915_private *dev_priv = dev->dev_private;
  4886. /*
  4887. * Disable clock gating reported to work incorrectly according to the
  4888. * specs, but enable as much else as we can.
  4889. */
  4890. if (HAS_PCH_SPLIT(dev)) {
  4891. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  4892. if (IS_IRONLAKE(dev)) {
  4893. /* Required for FBC */
  4894. dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
  4895. /* Required for CxSR */
  4896. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  4897. I915_WRITE(PCH_3DCGDIS0,
  4898. MARIUNIT_CLOCK_GATE_DISABLE |
  4899. SVSMUNIT_CLOCK_GATE_DISABLE);
  4900. }
  4901. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  4902. /*
  4903. * According to the spec the following bits should be set in
  4904. * order to enable memory self-refresh
  4905. * The bit 22/21 of 0x42004
  4906. * The bit 5 of 0x42020
  4907. * The bit 15 of 0x45000
  4908. */
  4909. if (IS_IRONLAKE(dev)) {
  4910. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4911. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  4912. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  4913. I915_WRITE(ILK_DSPCLK_GATE,
  4914. (I915_READ(ILK_DSPCLK_GATE) |
  4915. ILK_DPARB_CLK_GATE));
  4916. I915_WRITE(DISP_ARB_CTL,
  4917. (I915_READ(DISP_ARB_CTL) |
  4918. DISP_FBC_WM_DIS));
  4919. }
  4920. /*
  4921. * Based on the document from hardware guys the following bits
  4922. * should be set unconditionally in order to enable FBC.
  4923. * The bit 22 of 0x42000
  4924. * The bit 22 of 0x42004
  4925. * The bit 7,8,9 of 0x42020.
  4926. */
  4927. if (IS_IRONLAKE_M(dev)) {
  4928. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  4929. I915_READ(ILK_DISPLAY_CHICKEN1) |
  4930. ILK_FBCQ_DIS);
  4931. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4932. I915_READ(ILK_DISPLAY_CHICKEN2) |
  4933. ILK_DPARB_GATE);
  4934. I915_WRITE(ILK_DSPCLK_GATE,
  4935. I915_READ(ILK_DSPCLK_GATE) |
  4936. ILK_DPFC_DIS1 |
  4937. ILK_DPFC_DIS2 |
  4938. ILK_CLK_FBC);
  4939. }
  4940. return;
  4941. } else if (IS_G4X(dev)) {
  4942. uint32_t dspclk_gate;
  4943. I915_WRITE(RENCLK_GATE_D1, 0);
  4944. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  4945. GS_UNIT_CLOCK_GATE_DISABLE |
  4946. CL_UNIT_CLOCK_GATE_DISABLE);
  4947. I915_WRITE(RAMCLK_GATE_D, 0);
  4948. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  4949. OVRUNIT_CLOCK_GATE_DISABLE |
  4950. OVCUNIT_CLOCK_GATE_DISABLE;
  4951. if (IS_GM45(dev))
  4952. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  4953. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  4954. } else if (IS_I965GM(dev)) {
  4955. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  4956. I915_WRITE(RENCLK_GATE_D2, 0);
  4957. I915_WRITE(DSPCLK_GATE_D, 0);
  4958. I915_WRITE(RAMCLK_GATE_D, 0);
  4959. I915_WRITE16(DEUC, 0);
  4960. } else if (IS_I965G(dev)) {
  4961. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  4962. I965_RCC_CLOCK_GATE_DISABLE |
  4963. I965_RCPB_CLOCK_GATE_DISABLE |
  4964. I965_ISC_CLOCK_GATE_DISABLE |
  4965. I965_FBC_CLOCK_GATE_DISABLE);
  4966. I915_WRITE(RENCLK_GATE_D2, 0);
  4967. } else if (IS_I9XX(dev)) {
  4968. u32 dstate = I915_READ(D_STATE);
  4969. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  4970. DSTATE_DOT_CLOCK_GATING;
  4971. I915_WRITE(D_STATE, dstate);
  4972. } else if (IS_I85X(dev) || IS_I865G(dev)) {
  4973. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  4974. } else if (IS_I830(dev)) {
  4975. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  4976. }
  4977. /*
  4978. * GPU can automatically power down the render unit if given a page
  4979. * to save state.
  4980. */
  4981. if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
  4982. struct drm_i915_gem_object *obj_priv = NULL;
  4983. if (dev_priv->pwrctx) {
  4984. obj_priv = to_intel_bo(dev_priv->pwrctx);
  4985. } else {
  4986. struct drm_gem_object *pwrctx;
  4987. pwrctx = intel_alloc_power_context(dev);
  4988. if (pwrctx) {
  4989. dev_priv->pwrctx = pwrctx;
  4990. obj_priv = to_intel_bo(pwrctx);
  4991. }
  4992. }
  4993. if (obj_priv) {
  4994. I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
  4995. I915_WRITE(MCHBAR_RENDER_STANDBY,
  4996. I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
  4997. }
  4998. }
  4999. }
  5000. /* Set up chip specific display functions */
  5001. static void intel_init_display(struct drm_device *dev)
  5002. {
  5003. struct drm_i915_private *dev_priv = dev->dev_private;
  5004. /* We always want a DPMS function */
  5005. if (HAS_PCH_SPLIT(dev))
  5006. dev_priv->display.dpms = ironlake_crtc_dpms;
  5007. else
  5008. dev_priv->display.dpms = i9xx_crtc_dpms;
  5009. if (I915_HAS_FBC(dev)) {
  5010. if (IS_IRONLAKE_M(dev)) {
  5011. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  5012. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  5013. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  5014. } else if (IS_GM45(dev)) {
  5015. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  5016. dev_priv->display.enable_fbc = g4x_enable_fbc;
  5017. dev_priv->display.disable_fbc = g4x_disable_fbc;
  5018. } else if (IS_I965GM(dev)) {
  5019. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  5020. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  5021. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  5022. }
  5023. /* 855GM needs testing */
  5024. }
  5025. /* Returns the core display clock speed */
  5026. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  5027. dev_priv->display.get_display_clock_speed =
  5028. i945_get_display_clock_speed;
  5029. else if (IS_I915G(dev))
  5030. dev_priv->display.get_display_clock_speed =
  5031. i915_get_display_clock_speed;
  5032. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  5033. dev_priv->display.get_display_clock_speed =
  5034. i9xx_misc_get_display_clock_speed;
  5035. else if (IS_I915GM(dev))
  5036. dev_priv->display.get_display_clock_speed =
  5037. i915gm_get_display_clock_speed;
  5038. else if (IS_I865G(dev))
  5039. dev_priv->display.get_display_clock_speed =
  5040. i865_get_display_clock_speed;
  5041. else if (IS_I85X(dev))
  5042. dev_priv->display.get_display_clock_speed =
  5043. i855_get_display_clock_speed;
  5044. else /* 852, 830 */
  5045. dev_priv->display.get_display_clock_speed =
  5046. i830_get_display_clock_speed;
  5047. /* For FIFO watermark updates */
  5048. if (HAS_PCH_SPLIT(dev)) {
  5049. if (IS_IRONLAKE(dev)) {
  5050. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  5051. dev_priv->display.update_wm = ironlake_update_wm;
  5052. else {
  5053. DRM_DEBUG_KMS("Failed to get proper latency. "
  5054. "Disable CxSR\n");
  5055. dev_priv->display.update_wm = NULL;
  5056. }
  5057. } else
  5058. dev_priv->display.update_wm = NULL;
  5059. } else if (IS_PINEVIEW(dev)) {
  5060. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  5061. dev_priv->is_ddr3,
  5062. dev_priv->fsb_freq,
  5063. dev_priv->mem_freq)) {
  5064. DRM_INFO("failed to find known CxSR latency "
  5065. "(found ddr%s fsb freq %d, mem freq %d), "
  5066. "disabling CxSR\n",
  5067. (dev_priv->is_ddr3 == 1) ? "3": "2",
  5068. dev_priv->fsb_freq, dev_priv->mem_freq);
  5069. /* Disable CxSR and never update its watermark again */
  5070. pineview_disable_cxsr(dev);
  5071. dev_priv->display.update_wm = NULL;
  5072. } else
  5073. dev_priv->display.update_wm = pineview_update_wm;
  5074. } else if (IS_G4X(dev))
  5075. dev_priv->display.update_wm = g4x_update_wm;
  5076. else if (IS_I965G(dev))
  5077. dev_priv->display.update_wm = i965_update_wm;
  5078. else if (IS_I9XX(dev)) {
  5079. dev_priv->display.update_wm = i9xx_update_wm;
  5080. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  5081. } else if (IS_I85X(dev)) {
  5082. dev_priv->display.update_wm = i9xx_update_wm;
  5083. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  5084. } else {
  5085. dev_priv->display.update_wm = i830_update_wm;
  5086. if (IS_845G(dev))
  5087. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  5088. else
  5089. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  5090. }
  5091. }
  5092. /*
  5093. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  5094. * resume, or other times. This quirk makes sure that's the case for
  5095. * affected systems.
  5096. */
  5097. static void quirk_pipea_force (struct drm_device *dev)
  5098. {
  5099. struct drm_i915_private *dev_priv = dev->dev_private;
  5100. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  5101. DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
  5102. }
  5103. struct intel_quirk {
  5104. int device;
  5105. int subsystem_vendor;
  5106. int subsystem_device;
  5107. void (*hook)(struct drm_device *dev);
  5108. };
  5109. struct intel_quirk intel_quirks[] = {
  5110. /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
  5111. { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
  5112. /* HP Mini needs pipe A force quirk (LP: #322104) */
  5113. { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
  5114. /* Thinkpad R31 needs pipe A force quirk */
  5115. { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
  5116. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  5117. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  5118. /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
  5119. { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
  5120. /* ThinkPad X40 needs pipe A force quirk */
  5121. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  5122. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  5123. /* 855 & before need to leave pipe A & dpll A up */
  5124. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  5125. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  5126. };
  5127. static void intel_init_quirks(struct drm_device *dev)
  5128. {
  5129. struct pci_dev *d = dev->pdev;
  5130. int i;
  5131. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  5132. struct intel_quirk *q = &intel_quirks[i];
  5133. if (d->device == q->device &&
  5134. (d->subsystem_vendor == q->subsystem_vendor ||
  5135. q->subsystem_vendor == PCI_ANY_ID) &&
  5136. (d->subsystem_device == q->subsystem_device ||
  5137. q->subsystem_device == PCI_ANY_ID))
  5138. q->hook(dev);
  5139. }
  5140. }
  5141. void intel_modeset_init(struct drm_device *dev)
  5142. {
  5143. struct drm_i915_private *dev_priv = dev->dev_private;
  5144. int i;
  5145. drm_mode_config_init(dev);
  5146. dev->mode_config.min_width = 0;
  5147. dev->mode_config.min_height = 0;
  5148. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  5149. intel_init_quirks(dev);
  5150. intel_init_display(dev);
  5151. if (IS_I965G(dev)) {
  5152. dev->mode_config.max_width = 8192;
  5153. dev->mode_config.max_height = 8192;
  5154. } else if (IS_I9XX(dev)) {
  5155. dev->mode_config.max_width = 4096;
  5156. dev->mode_config.max_height = 4096;
  5157. } else {
  5158. dev->mode_config.max_width = 2048;
  5159. dev->mode_config.max_height = 2048;
  5160. }
  5161. /* set memory base */
  5162. if (IS_I9XX(dev))
  5163. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  5164. else
  5165. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  5166. if (IS_MOBILE(dev) || IS_I9XX(dev))
  5167. dev_priv->num_pipe = 2;
  5168. else
  5169. dev_priv->num_pipe = 1;
  5170. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  5171. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  5172. for (i = 0; i < dev_priv->num_pipe; i++) {
  5173. intel_crtc_init(dev, i);
  5174. }
  5175. intel_setup_outputs(dev);
  5176. intel_init_clock_gating(dev);
  5177. if (IS_IRONLAKE_M(dev)) {
  5178. ironlake_enable_drps(dev);
  5179. intel_init_emon(dev);
  5180. }
  5181. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  5182. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  5183. (unsigned long)dev);
  5184. intel_setup_overlay(dev);
  5185. }
  5186. void intel_modeset_cleanup(struct drm_device *dev)
  5187. {
  5188. struct drm_i915_private *dev_priv = dev->dev_private;
  5189. struct drm_crtc *crtc;
  5190. struct intel_crtc *intel_crtc;
  5191. mutex_lock(&dev->struct_mutex);
  5192. drm_kms_helper_poll_fini(dev);
  5193. intel_fbdev_fini(dev);
  5194. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5195. /* Skip inactive CRTCs */
  5196. if (!crtc->fb)
  5197. continue;
  5198. intel_crtc = to_intel_crtc(crtc);
  5199. intel_increase_pllclock(crtc, false);
  5200. del_timer_sync(&intel_crtc->idle_timer);
  5201. }
  5202. del_timer_sync(&dev_priv->idle_timer);
  5203. if (dev_priv->display.disable_fbc)
  5204. dev_priv->display.disable_fbc(dev);
  5205. if (dev_priv->pwrctx) {
  5206. struct drm_i915_gem_object *obj_priv;
  5207. obj_priv = to_intel_bo(dev_priv->pwrctx);
  5208. I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
  5209. I915_READ(PWRCTXA);
  5210. i915_gem_object_unpin(dev_priv->pwrctx);
  5211. drm_gem_object_unreference(dev_priv->pwrctx);
  5212. }
  5213. if (IS_IRONLAKE_M(dev))
  5214. ironlake_disable_drps(dev);
  5215. mutex_unlock(&dev->struct_mutex);
  5216. drm_mode_config_cleanup(dev);
  5217. }
  5218. /*
  5219. * Return which encoder is currently attached for connector.
  5220. */
  5221. struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
  5222. {
  5223. struct drm_mode_object *obj;
  5224. struct drm_encoder *encoder;
  5225. int i;
  5226. for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
  5227. if (connector->encoder_ids[i] == 0)
  5228. break;
  5229. obj = drm_mode_object_find(connector->dev,
  5230. connector->encoder_ids[i],
  5231. DRM_MODE_OBJECT_ENCODER);
  5232. if (!obj)
  5233. continue;
  5234. encoder = obj_to_encoder(obj);
  5235. return encoder;
  5236. }
  5237. return NULL;
  5238. }
  5239. /*
  5240. * set vga decode state - true == enable VGA decode
  5241. */
  5242. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  5243. {
  5244. struct drm_i915_private *dev_priv = dev->dev_private;
  5245. u16 gmch_ctrl;
  5246. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  5247. if (state)
  5248. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  5249. else
  5250. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  5251. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  5252. return 0;
  5253. }