i915_dma.c 62 KB

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  1. /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "drm_crtc_helper.h"
  31. #include "drm_fb_helper.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include <linux/pci.h>
  37. #include <linux/vgaarb.h>
  38. #include <linux/acpi.h>
  39. #include <linux/pnp.h>
  40. #include <linux/vga_switcheroo.h>
  41. #include <linux/slab.h>
  42. extern int intel_max_stolen; /* from AGP driver */
  43. /**
  44. * Sets up the hardware status page for devices that need a physical address
  45. * in the register.
  46. */
  47. static int i915_init_phys_hws(struct drm_device *dev)
  48. {
  49. drm_i915_private_t *dev_priv = dev->dev_private;
  50. /* Program Hardware Status Page */
  51. dev_priv->status_page_dmah =
  52. drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  53. if (!dev_priv->status_page_dmah) {
  54. DRM_ERROR("Can not allocate hardware status page\n");
  55. return -ENOMEM;
  56. }
  57. dev_priv->render_ring.status_page.page_addr
  58. = dev_priv->status_page_dmah->vaddr;
  59. dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  60. memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  61. if (IS_I965G(dev))
  62. dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  63. 0xf0;
  64. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  65. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  66. return 0;
  67. }
  68. /**
  69. * Frees the hardware status page, whether it's a physical address or a virtual
  70. * address set up by the X Server.
  71. */
  72. static void i915_free_hws(struct drm_device *dev)
  73. {
  74. drm_i915_private_t *dev_priv = dev->dev_private;
  75. if (dev_priv->status_page_dmah) {
  76. drm_pci_free(dev, dev_priv->status_page_dmah);
  77. dev_priv->status_page_dmah = NULL;
  78. }
  79. if (dev_priv->render_ring.status_page.gfx_addr) {
  80. dev_priv->render_ring.status_page.gfx_addr = 0;
  81. drm_core_ioremapfree(&dev_priv->hws_map, dev);
  82. }
  83. /* Need to rewrite hardware status page */
  84. I915_WRITE(HWS_PGA, 0x1ffff000);
  85. }
  86. void i915_kernel_lost_context(struct drm_device * dev)
  87. {
  88. drm_i915_private_t *dev_priv = dev->dev_private;
  89. struct drm_i915_master_private *master_priv;
  90. struct intel_ring_buffer *ring = &dev_priv->render_ring;
  91. /*
  92. * We should never lose context on the ring with modesetting
  93. * as we don't expose it to userspace
  94. */
  95. if (drm_core_check_feature(dev, DRIVER_MODESET))
  96. return;
  97. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  98. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  99. ring->space = ring->head - (ring->tail + 8);
  100. if (ring->space < 0)
  101. ring->space += ring->size;
  102. if (!dev->primary->master)
  103. return;
  104. master_priv = dev->primary->master->driver_priv;
  105. if (ring->head == ring->tail && master_priv->sarea_priv)
  106. master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  107. }
  108. static int i915_dma_cleanup(struct drm_device * dev)
  109. {
  110. drm_i915_private_t *dev_priv = dev->dev_private;
  111. /* Make sure interrupts are disabled here because the uninstall ioctl
  112. * may not have been called from userspace and after dev_private
  113. * is freed, it's too late.
  114. */
  115. if (dev->irq_enabled)
  116. drm_irq_uninstall(dev);
  117. mutex_lock(&dev->struct_mutex);
  118. intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
  119. if (HAS_BSD(dev))
  120. intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
  121. mutex_unlock(&dev->struct_mutex);
  122. /* Clear the HWS virtual address at teardown */
  123. if (I915_NEED_GFX_HWS(dev))
  124. i915_free_hws(dev);
  125. return 0;
  126. }
  127. static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
  128. {
  129. drm_i915_private_t *dev_priv = dev->dev_private;
  130. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  131. master_priv->sarea = drm_getsarea(dev);
  132. if (master_priv->sarea) {
  133. master_priv->sarea_priv = (drm_i915_sarea_t *)
  134. ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
  135. } else {
  136. DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
  137. }
  138. if (init->ring_size != 0) {
  139. if (dev_priv->render_ring.gem_object != NULL) {
  140. i915_dma_cleanup(dev);
  141. DRM_ERROR("Client tried to initialize ringbuffer in "
  142. "GEM mode\n");
  143. return -EINVAL;
  144. }
  145. dev_priv->render_ring.size = init->ring_size;
  146. dev_priv->render_ring.map.offset = init->ring_start;
  147. dev_priv->render_ring.map.size = init->ring_size;
  148. dev_priv->render_ring.map.type = 0;
  149. dev_priv->render_ring.map.flags = 0;
  150. dev_priv->render_ring.map.mtrr = 0;
  151. drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
  152. if (dev_priv->render_ring.map.handle == NULL) {
  153. i915_dma_cleanup(dev);
  154. DRM_ERROR("can not ioremap virtual address for"
  155. " ring buffer\n");
  156. return -ENOMEM;
  157. }
  158. }
  159. dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
  160. dev_priv->cpp = init->cpp;
  161. dev_priv->back_offset = init->back_offset;
  162. dev_priv->front_offset = init->front_offset;
  163. dev_priv->current_page = 0;
  164. if (master_priv->sarea_priv)
  165. master_priv->sarea_priv->pf_current_page = 0;
  166. /* Allow hardware batchbuffers unless told otherwise.
  167. */
  168. dev_priv->allow_batchbuffer = 1;
  169. return 0;
  170. }
  171. static int i915_dma_resume(struct drm_device * dev)
  172. {
  173. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  174. struct intel_ring_buffer *ring;
  175. DRM_DEBUG_DRIVER("%s\n", __func__);
  176. ring = &dev_priv->render_ring;
  177. if (ring->map.handle == NULL) {
  178. DRM_ERROR("can not ioremap virtual address for"
  179. " ring buffer\n");
  180. return -ENOMEM;
  181. }
  182. /* Program Hardware Status Page */
  183. if (!ring->status_page.page_addr) {
  184. DRM_ERROR("Can not find hardware status page\n");
  185. return -EINVAL;
  186. }
  187. DRM_DEBUG_DRIVER("hw status page @ %p\n",
  188. ring->status_page.page_addr);
  189. if (ring->status_page.gfx_addr != 0)
  190. ring->setup_status_page(dev, ring);
  191. else
  192. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  193. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  194. return 0;
  195. }
  196. static int i915_dma_init(struct drm_device *dev, void *data,
  197. struct drm_file *file_priv)
  198. {
  199. drm_i915_init_t *init = data;
  200. int retcode = 0;
  201. switch (init->func) {
  202. case I915_INIT_DMA:
  203. retcode = i915_initialize(dev, init);
  204. break;
  205. case I915_CLEANUP_DMA:
  206. retcode = i915_dma_cleanup(dev);
  207. break;
  208. case I915_RESUME_DMA:
  209. retcode = i915_dma_resume(dev);
  210. break;
  211. default:
  212. retcode = -EINVAL;
  213. break;
  214. }
  215. return retcode;
  216. }
  217. /* Implement basically the same security restrictions as hardware does
  218. * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
  219. *
  220. * Most of the calculations below involve calculating the size of a
  221. * particular instruction. It's important to get the size right as
  222. * that tells us where the next instruction to check is. Any illegal
  223. * instruction detected will be given a size of zero, which is a
  224. * signal to abort the rest of the buffer.
  225. */
  226. static int do_validate_cmd(int cmd)
  227. {
  228. switch (((cmd >> 29) & 0x7)) {
  229. case 0x0:
  230. switch ((cmd >> 23) & 0x3f) {
  231. case 0x0:
  232. return 1; /* MI_NOOP */
  233. case 0x4:
  234. return 1; /* MI_FLUSH */
  235. default:
  236. return 0; /* disallow everything else */
  237. }
  238. break;
  239. case 0x1:
  240. return 0; /* reserved */
  241. case 0x2:
  242. return (cmd & 0xff) + 2; /* 2d commands */
  243. case 0x3:
  244. if (((cmd >> 24) & 0x1f) <= 0x18)
  245. return 1;
  246. switch ((cmd >> 24) & 0x1f) {
  247. case 0x1c:
  248. return 1;
  249. case 0x1d:
  250. switch ((cmd >> 16) & 0xff) {
  251. case 0x3:
  252. return (cmd & 0x1f) + 2;
  253. case 0x4:
  254. return (cmd & 0xf) + 2;
  255. default:
  256. return (cmd & 0xffff) + 2;
  257. }
  258. case 0x1e:
  259. if (cmd & (1 << 23))
  260. return (cmd & 0xffff) + 1;
  261. else
  262. return 1;
  263. case 0x1f:
  264. if ((cmd & (1 << 23)) == 0) /* inline vertices */
  265. return (cmd & 0x1ffff) + 2;
  266. else if (cmd & (1 << 17)) /* indirect random */
  267. if ((cmd & 0xffff) == 0)
  268. return 0; /* unknown length, too hard */
  269. else
  270. return (((cmd & 0xffff) + 1) / 2) + 1;
  271. else
  272. return 2; /* indirect sequential */
  273. default:
  274. return 0;
  275. }
  276. default:
  277. return 0;
  278. }
  279. return 0;
  280. }
  281. static int validate_cmd(int cmd)
  282. {
  283. int ret = do_validate_cmd(cmd);
  284. /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
  285. return ret;
  286. }
  287. static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
  288. {
  289. drm_i915_private_t *dev_priv = dev->dev_private;
  290. int i;
  291. if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
  292. return -EINVAL;
  293. BEGIN_LP_RING((dwords+1)&~1);
  294. for (i = 0; i < dwords;) {
  295. int cmd, sz;
  296. cmd = buffer[i];
  297. if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
  298. return -EINVAL;
  299. OUT_RING(cmd);
  300. while (++i, --sz) {
  301. OUT_RING(buffer[i]);
  302. }
  303. }
  304. if (dwords & 1)
  305. OUT_RING(0);
  306. ADVANCE_LP_RING();
  307. return 0;
  308. }
  309. int
  310. i915_emit_box(struct drm_device *dev,
  311. struct drm_clip_rect *boxes,
  312. int i, int DR1, int DR4)
  313. {
  314. struct drm_clip_rect box = boxes[i];
  315. if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
  316. DRM_ERROR("Bad box %d,%d..%d,%d\n",
  317. box.x1, box.y1, box.x2, box.y2);
  318. return -EINVAL;
  319. }
  320. if (IS_I965G(dev)) {
  321. BEGIN_LP_RING(4);
  322. OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
  323. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  324. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  325. OUT_RING(DR4);
  326. ADVANCE_LP_RING();
  327. } else {
  328. BEGIN_LP_RING(6);
  329. OUT_RING(GFX_OP_DRAWRECT_INFO);
  330. OUT_RING(DR1);
  331. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  332. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  333. OUT_RING(DR4);
  334. OUT_RING(0);
  335. ADVANCE_LP_RING();
  336. }
  337. return 0;
  338. }
  339. /* XXX: Emitting the counter should really be moved to part of the IRQ
  340. * emit. For now, do it in both places:
  341. */
  342. static void i915_emit_breadcrumb(struct drm_device *dev)
  343. {
  344. drm_i915_private_t *dev_priv = dev->dev_private;
  345. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  346. dev_priv->counter++;
  347. if (dev_priv->counter > 0x7FFFFFFFUL)
  348. dev_priv->counter = 0;
  349. if (master_priv->sarea_priv)
  350. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  351. BEGIN_LP_RING(4);
  352. OUT_RING(MI_STORE_DWORD_INDEX);
  353. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  354. OUT_RING(dev_priv->counter);
  355. OUT_RING(0);
  356. ADVANCE_LP_RING();
  357. }
  358. static int i915_dispatch_cmdbuffer(struct drm_device * dev,
  359. drm_i915_cmdbuffer_t *cmd,
  360. struct drm_clip_rect *cliprects,
  361. void *cmdbuf)
  362. {
  363. int nbox = cmd->num_cliprects;
  364. int i = 0, count, ret;
  365. if (cmd->sz & 0x3) {
  366. DRM_ERROR("alignment");
  367. return -EINVAL;
  368. }
  369. i915_kernel_lost_context(dev);
  370. count = nbox ? nbox : 1;
  371. for (i = 0; i < count; i++) {
  372. if (i < nbox) {
  373. ret = i915_emit_box(dev, cliprects, i,
  374. cmd->DR1, cmd->DR4);
  375. if (ret)
  376. return ret;
  377. }
  378. ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
  379. if (ret)
  380. return ret;
  381. }
  382. i915_emit_breadcrumb(dev);
  383. return 0;
  384. }
  385. static int i915_dispatch_batchbuffer(struct drm_device * dev,
  386. drm_i915_batchbuffer_t * batch,
  387. struct drm_clip_rect *cliprects)
  388. {
  389. int nbox = batch->num_cliprects;
  390. int i = 0, count;
  391. if ((batch->start | batch->used) & 0x7) {
  392. DRM_ERROR("alignment");
  393. return -EINVAL;
  394. }
  395. i915_kernel_lost_context(dev);
  396. count = nbox ? nbox : 1;
  397. for (i = 0; i < count; i++) {
  398. if (i < nbox) {
  399. int ret = i915_emit_box(dev, cliprects, i,
  400. batch->DR1, batch->DR4);
  401. if (ret)
  402. return ret;
  403. }
  404. if (!IS_I830(dev) && !IS_845G(dev)) {
  405. BEGIN_LP_RING(2);
  406. if (IS_I965G(dev)) {
  407. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
  408. OUT_RING(batch->start);
  409. } else {
  410. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
  411. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  412. }
  413. ADVANCE_LP_RING();
  414. } else {
  415. BEGIN_LP_RING(4);
  416. OUT_RING(MI_BATCH_BUFFER);
  417. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  418. OUT_RING(batch->start + batch->used - 4);
  419. OUT_RING(0);
  420. ADVANCE_LP_RING();
  421. }
  422. }
  423. i915_emit_breadcrumb(dev);
  424. return 0;
  425. }
  426. static int i915_dispatch_flip(struct drm_device * dev)
  427. {
  428. drm_i915_private_t *dev_priv = dev->dev_private;
  429. struct drm_i915_master_private *master_priv =
  430. dev->primary->master->driver_priv;
  431. if (!master_priv->sarea_priv)
  432. return -EINVAL;
  433. DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
  434. __func__,
  435. dev_priv->current_page,
  436. master_priv->sarea_priv->pf_current_page);
  437. i915_kernel_lost_context(dev);
  438. BEGIN_LP_RING(2);
  439. OUT_RING(MI_FLUSH | MI_READ_FLUSH);
  440. OUT_RING(0);
  441. ADVANCE_LP_RING();
  442. BEGIN_LP_RING(6);
  443. OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
  444. OUT_RING(0);
  445. if (dev_priv->current_page == 0) {
  446. OUT_RING(dev_priv->back_offset);
  447. dev_priv->current_page = 1;
  448. } else {
  449. OUT_RING(dev_priv->front_offset);
  450. dev_priv->current_page = 0;
  451. }
  452. OUT_RING(0);
  453. ADVANCE_LP_RING();
  454. BEGIN_LP_RING(2);
  455. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
  456. OUT_RING(0);
  457. ADVANCE_LP_RING();
  458. master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
  459. BEGIN_LP_RING(4);
  460. OUT_RING(MI_STORE_DWORD_INDEX);
  461. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  462. OUT_RING(dev_priv->counter);
  463. OUT_RING(0);
  464. ADVANCE_LP_RING();
  465. master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  466. return 0;
  467. }
  468. static int i915_quiescent(struct drm_device * dev)
  469. {
  470. drm_i915_private_t *dev_priv = dev->dev_private;
  471. i915_kernel_lost_context(dev);
  472. return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
  473. dev_priv->render_ring.size - 8);
  474. }
  475. static int i915_flush_ioctl(struct drm_device *dev, void *data,
  476. struct drm_file *file_priv)
  477. {
  478. int ret;
  479. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  480. mutex_lock(&dev->struct_mutex);
  481. ret = i915_quiescent(dev);
  482. mutex_unlock(&dev->struct_mutex);
  483. return ret;
  484. }
  485. static int i915_batchbuffer(struct drm_device *dev, void *data,
  486. struct drm_file *file_priv)
  487. {
  488. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  489. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  490. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  491. master_priv->sarea_priv;
  492. drm_i915_batchbuffer_t *batch = data;
  493. int ret;
  494. struct drm_clip_rect *cliprects = NULL;
  495. if (!dev_priv->allow_batchbuffer) {
  496. DRM_ERROR("Batchbuffer ioctl disabled\n");
  497. return -EINVAL;
  498. }
  499. DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
  500. batch->start, batch->used, batch->num_cliprects);
  501. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  502. if (batch->num_cliprects < 0)
  503. return -EINVAL;
  504. if (batch->num_cliprects) {
  505. cliprects = kcalloc(batch->num_cliprects,
  506. sizeof(struct drm_clip_rect),
  507. GFP_KERNEL);
  508. if (cliprects == NULL)
  509. return -ENOMEM;
  510. ret = copy_from_user(cliprects, batch->cliprects,
  511. batch->num_cliprects *
  512. sizeof(struct drm_clip_rect));
  513. if (ret != 0)
  514. goto fail_free;
  515. }
  516. mutex_lock(&dev->struct_mutex);
  517. ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
  518. mutex_unlock(&dev->struct_mutex);
  519. if (sarea_priv)
  520. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  521. fail_free:
  522. kfree(cliprects);
  523. return ret;
  524. }
  525. static int i915_cmdbuffer(struct drm_device *dev, void *data,
  526. struct drm_file *file_priv)
  527. {
  528. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  529. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  530. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  531. master_priv->sarea_priv;
  532. drm_i915_cmdbuffer_t *cmdbuf = data;
  533. struct drm_clip_rect *cliprects = NULL;
  534. void *batch_data;
  535. int ret;
  536. DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
  537. cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
  538. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  539. if (cmdbuf->num_cliprects < 0)
  540. return -EINVAL;
  541. batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
  542. if (batch_data == NULL)
  543. return -ENOMEM;
  544. ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
  545. if (ret != 0)
  546. goto fail_batch_free;
  547. if (cmdbuf->num_cliprects) {
  548. cliprects = kcalloc(cmdbuf->num_cliprects,
  549. sizeof(struct drm_clip_rect), GFP_KERNEL);
  550. if (cliprects == NULL) {
  551. ret = -ENOMEM;
  552. goto fail_batch_free;
  553. }
  554. ret = copy_from_user(cliprects, cmdbuf->cliprects,
  555. cmdbuf->num_cliprects *
  556. sizeof(struct drm_clip_rect));
  557. if (ret != 0)
  558. goto fail_clip_free;
  559. }
  560. mutex_lock(&dev->struct_mutex);
  561. ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
  562. mutex_unlock(&dev->struct_mutex);
  563. if (ret) {
  564. DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
  565. goto fail_clip_free;
  566. }
  567. if (sarea_priv)
  568. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  569. fail_clip_free:
  570. kfree(cliprects);
  571. fail_batch_free:
  572. kfree(batch_data);
  573. return ret;
  574. }
  575. static int i915_flip_bufs(struct drm_device *dev, void *data,
  576. struct drm_file *file_priv)
  577. {
  578. int ret;
  579. DRM_DEBUG_DRIVER("%s\n", __func__);
  580. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  581. mutex_lock(&dev->struct_mutex);
  582. ret = i915_dispatch_flip(dev);
  583. mutex_unlock(&dev->struct_mutex);
  584. return ret;
  585. }
  586. static int i915_getparam(struct drm_device *dev, void *data,
  587. struct drm_file *file_priv)
  588. {
  589. drm_i915_private_t *dev_priv = dev->dev_private;
  590. drm_i915_getparam_t *param = data;
  591. int value;
  592. if (!dev_priv) {
  593. DRM_ERROR("called with no initialization\n");
  594. return -EINVAL;
  595. }
  596. switch (param->param) {
  597. case I915_PARAM_IRQ_ACTIVE:
  598. value = dev->pdev->irq ? 1 : 0;
  599. break;
  600. case I915_PARAM_ALLOW_BATCHBUFFER:
  601. value = dev_priv->allow_batchbuffer ? 1 : 0;
  602. break;
  603. case I915_PARAM_LAST_DISPATCH:
  604. value = READ_BREADCRUMB(dev_priv);
  605. break;
  606. case I915_PARAM_CHIPSET_ID:
  607. value = dev->pci_device;
  608. break;
  609. case I915_PARAM_HAS_GEM:
  610. value = dev_priv->has_gem;
  611. break;
  612. case I915_PARAM_NUM_FENCES_AVAIL:
  613. value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  614. break;
  615. case I915_PARAM_HAS_OVERLAY:
  616. value = dev_priv->overlay ? 1 : 0;
  617. break;
  618. case I915_PARAM_HAS_PAGEFLIPPING:
  619. value = 1;
  620. break;
  621. case I915_PARAM_HAS_EXECBUF2:
  622. /* depends on GEM */
  623. value = dev_priv->has_gem;
  624. break;
  625. case I915_PARAM_HAS_BSD:
  626. value = HAS_BSD(dev);
  627. break;
  628. default:
  629. DRM_DEBUG_DRIVER("Unknown parameter %d\n",
  630. param->param);
  631. return -EINVAL;
  632. }
  633. if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
  634. DRM_ERROR("DRM_COPY_TO_USER failed\n");
  635. return -EFAULT;
  636. }
  637. return 0;
  638. }
  639. static int i915_setparam(struct drm_device *dev, void *data,
  640. struct drm_file *file_priv)
  641. {
  642. drm_i915_private_t *dev_priv = dev->dev_private;
  643. drm_i915_setparam_t *param = data;
  644. if (!dev_priv) {
  645. DRM_ERROR("called with no initialization\n");
  646. return -EINVAL;
  647. }
  648. switch (param->param) {
  649. case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
  650. break;
  651. case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
  652. dev_priv->tex_lru_log_granularity = param->value;
  653. break;
  654. case I915_SETPARAM_ALLOW_BATCHBUFFER:
  655. dev_priv->allow_batchbuffer = param->value;
  656. break;
  657. case I915_SETPARAM_NUM_USED_FENCES:
  658. if (param->value > dev_priv->num_fence_regs ||
  659. param->value < 0)
  660. return -EINVAL;
  661. /* Userspace can use first N regs */
  662. dev_priv->fence_reg_start = param->value;
  663. break;
  664. default:
  665. DRM_DEBUG_DRIVER("unknown parameter %d\n",
  666. param->param);
  667. return -EINVAL;
  668. }
  669. return 0;
  670. }
  671. static int i915_set_status_page(struct drm_device *dev, void *data,
  672. struct drm_file *file_priv)
  673. {
  674. drm_i915_private_t *dev_priv = dev->dev_private;
  675. drm_i915_hws_addr_t *hws = data;
  676. struct intel_ring_buffer *ring = &dev_priv->render_ring;
  677. if (!I915_NEED_GFX_HWS(dev))
  678. return -EINVAL;
  679. if (!dev_priv) {
  680. DRM_ERROR("called with no initialization\n");
  681. return -EINVAL;
  682. }
  683. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  684. WARN(1, "tried to set status page when mode setting active\n");
  685. return 0;
  686. }
  687. DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
  688. ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
  689. dev_priv->hws_map.offset = dev->agp->base + hws->addr;
  690. dev_priv->hws_map.size = 4*1024;
  691. dev_priv->hws_map.type = 0;
  692. dev_priv->hws_map.flags = 0;
  693. dev_priv->hws_map.mtrr = 0;
  694. drm_core_ioremap_wc(&dev_priv->hws_map, dev);
  695. if (dev_priv->hws_map.handle == NULL) {
  696. i915_dma_cleanup(dev);
  697. ring->status_page.gfx_addr = 0;
  698. DRM_ERROR("can not ioremap virtual address for"
  699. " G33 hw status page\n");
  700. return -ENOMEM;
  701. }
  702. ring->status_page.page_addr = dev_priv->hws_map.handle;
  703. memset(ring->status_page.page_addr, 0, PAGE_SIZE);
  704. I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
  705. DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
  706. ring->status_page.gfx_addr);
  707. DRM_DEBUG_DRIVER("load hws at %p\n",
  708. ring->status_page.page_addr);
  709. return 0;
  710. }
  711. static int i915_get_bridge_dev(struct drm_device *dev)
  712. {
  713. struct drm_i915_private *dev_priv = dev->dev_private;
  714. dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
  715. if (!dev_priv->bridge_dev) {
  716. DRM_ERROR("bridge device not found\n");
  717. return -1;
  718. }
  719. return 0;
  720. }
  721. #define MCHBAR_I915 0x44
  722. #define MCHBAR_I965 0x48
  723. #define MCHBAR_SIZE (4*4096)
  724. #define DEVEN_REG 0x54
  725. #define DEVEN_MCHBAR_EN (1 << 28)
  726. /* Allocate space for the MCH regs if needed, return nonzero on error */
  727. static int
  728. intel_alloc_mchbar_resource(struct drm_device *dev)
  729. {
  730. drm_i915_private_t *dev_priv = dev->dev_private;
  731. int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
  732. u32 temp_lo, temp_hi = 0;
  733. u64 mchbar_addr;
  734. int ret = 0;
  735. if (IS_I965G(dev))
  736. pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
  737. pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
  738. mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
  739. /* If ACPI doesn't have it, assume we need to allocate it ourselves */
  740. #ifdef CONFIG_PNP
  741. if (mchbar_addr &&
  742. pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
  743. ret = 0;
  744. goto out;
  745. }
  746. #endif
  747. /* Get some space for it */
  748. ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
  749. MCHBAR_SIZE, MCHBAR_SIZE,
  750. PCIBIOS_MIN_MEM,
  751. 0, pcibios_align_resource,
  752. dev_priv->bridge_dev);
  753. if (ret) {
  754. DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
  755. dev_priv->mch_res.start = 0;
  756. goto out;
  757. }
  758. if (IS_I965G(dev))
  759. pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
  760. upper_32_bits(dev_priv->mch_res.start));
  761. pci_write_config_dword(dev_priv->bridge_dev, reg,
  762. lower_32_bits(dev_priv->mch_res.start));
  763. out:
  764. return ret;
  765. }
  766. /* Setup MCHBAR if possible, return true if we should disable it again */
  767. static void
  768. intel_setup_mchbar(struct drm_device *dev)
  769. {
  770. drm_i915_private_t *dev_priv = dev->dev_private;
  771. int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
  772. u32 temp;
  773. bool enabled;
  774. dev_priv->mchbar_need_disable = false;
  775. if (IS_I915G(dev) || IS_I915GM(dev)) {
  776. pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  777. enabled = !!(temp & DEVEN_MCHBAR_EN);
  778. } else {
  779. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  780. enabled = temp & 1;
  781. }
  782. /* If it's already enabled, don't have to do anything */
  783. if (enabled)
  784. return;
  785. if (intel_alloc_mchbar_resource(dev))
  786. return;
  787. dev_priv->mchbar_need_disable = true;
  788. /* Space is allocated or reserved, so enable it. */
  789. if (IS_I915G(dev) || IS_I915GM(dev)) {
  790. pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
  791. temp | DEVEN_MCHBAR_EN);
  792. } else {
  793. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  794. pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
  795. }
  796. }
  797. static void
  798. intel_teardown_mchbar(struct drm_device *dev)
  799. {
  800. drm_i915_private_t *dev_priv = dev->dev_private;
  801. int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
  802. u32 temp;
  803. if (dev_priv->mchbar_need_disable) {
  804. if (IS_I915G(dev) || IS_I915GM(dev)) {
  805. pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  806. temp &= ~DEVEN_MCHBAR_EN;
  807. pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
  808. } else {
  809. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  810. temp &= ~1;
  811. pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
  812. }
  813. }
  814. if (dev_priv->mch_res.start)
  815. release_resource(&dev_priv->mch_res);
  816. }
  817. /**
  818. * i915_probe_agp - get AGP bootup configuration
  819. * @pdev: PCI device
  820. * @aperture_size: returns AGP aperture configured size
  821. * @preallocated_size: returns size of BIOS preallocated AGP space
  822. *
  823. * Since Intel integrated graphics are UMA, the BIOS has to set aside
  824. * some RAM for the framebuffer at early boot. This code figures out
  825. * how much was set aside so we can use it for our own purposes.
  826. */
  827. static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
  828. uint32_t *preallocated_size,
  829. uint32_t *start)
  830. {
  831. struct drm_i915_private *dev_priv = dev->dev_private;
  832. u16 tmp = 0;
  833. unsigned long overhead;
  834. unsigned long stolen;
  835. /* Get the fb aperture size and "stolen" memory amount. */
  836. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
  837. *aperture_size = 1024 * 1024;
  838. *preallocated_size = 1024 * 1024;
  839. switch (dev->pdev->device) {
  840. case PCI_DEVICE_ID_INTEL_82830_CGC:
  841. case PCI_DEVICE_ID_INTEL_82845G_IG:
  842. case PCI_DEVICE_ID_INTEL_82855GM_IG:
  843. case PCI_DEVICE_ID_INTEL_82865_IG:
  844. if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  845. *aperture_size *= 64;
  846. else
  847. *aperture_size *= 128;
  848. break;
  849. default:
  850. /* 9xx supports large sizes, just look at the length */
  851. *aperture_size = pci_resource_len(dev->pdev, 2);
  852. break;
  853. }
  854. /*
  855. * Some of the preallocated space is taken by the GTT
  856. * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
  857. */
  858. if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
  859. overhead = 4096;
  860. else
  861. overhead = (*aperture_size / 1024) + 4096;
  862. if (IS_GEN6(dev)) {
  863. /* SNB has memory control reg at 0x50.w */
  864. pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
  865. switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
  866. case INTEL_855_GMCH_GMS_DISABLED:
  867. DRM_ERROR("video memory is disabled\n");
  868. return -1;
  869. case SNB_GMCH_GMS_STOLEN_32M:
  870. stolen = 32 * 1024 * 1024;
  871. break;
  872. case SNB_GMCH_GMS_STOLEN_64M:
  873. stolen = 64 * 1024 * 1024;
  874. break;
  875. case SNB_GMCH_GMS_STOLEN_96M:
  876. stolen = 96 * 1024 * 1024;
  877. break;
  878. case SNB_GMCH_GMS_STOLEN_128M:
  879. stolen = 128 * 1024 * 1024;
  880. break;
  881. case SNB_GMCH_GMS_STOLEN_160M:
  882. stolen = 160 * 1024 * 1024;
  883. break;
  884. case SNB_GMCH_GMS_STOLEN_192M:
  885. stolen = 192 * 1024 * 1024;
  886. break;
  887. case SNB_GMCH_GMS_STOLEN_224M:
  888. stolen = 224 * 1024 * 1024;
  889. break;
  890. case SNB_GMCH_GMS_STOLEN_256M:
  891. stolen = 256 * 1024 * 1024;
  892. break;
  893. case SNB_GMCH_GMS_STOLEN_288M:
  894. stolen = 288 * 1024 * 1024;
  895. break;
  896. case SNB_GMCH_GMS_STOLEN_320M:
  897. stolen = 320 * 1024 * 1024;
  898. break;
  899. case SNB_GMCH_GMS_STOLEN_352M:
  900. stolen = 352 * 1024 * 1024;
  901. break;
  902. case SNB_GMCH_GMS_STOLEN_384M:
  903. stolen = 384 * 1024 * 1024;
  904. break;
  905. case SNB_GMCH_GMS_STOLEN_416M:
  906. stolen = 416 * 1024 * 1024;
  907. break;
  908. case SNB_GMCH_GMS_STOLEN_448M:
  909. stolen = 448 * 1024 * 1024;
  910. break;
  911. case SNB_GMCH_GMS_STOLEN_480M:
  912. stolen = 480 * 1024 * 1024;
  913. break;
  914. case SNB_GMCH_GMS_STOLEN_512M:
  915. stolen = 512 * 1024 * 1024;
  916. break;
  917. default:
  918. DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  919. tmp & SNB_GMCH_GMS_STOLEN_MASK);
  920. return -1;
  921. }
  922. } else {
  923. switch (tmp & INTEL_GMCH_GMS_MASK) {
  924. case INTEL_855_GMCH_GMS_DISABLED:
  925. DRM_ERROR("video memory is disabled\n");
  926. return -1;
  927. case INTEL_855_GMCH_GMS_STOLEN_1M:
  928. stolen = 1 * 1024 * 1024;
  929. break;
  930. case INTEL_855_GMCH_GMS_STOLEN_4M:
  931. stolen = 4 * 1024 * 1024;
  932. break;
  933. case INTEL_855_GMCH_GMS_STOLEN_8M:
  934. stolen = 8 * 1024 * 1024;
  935. break;
  936. case INTEL_855_GMCH_GMS_STOLEN_16M:
  937. stolen = 16 * 1024 * 1024;
  938. break;
  939. case INTEL_855_GMCH_GMS_STOLEN_32M:
  940. stolen = 32 * 1024 * 1024;
  941. break;
  942. case INTEL_915G_GMCH_GMS_STOLEN_48M:
  943. stolen = 48 * 1024 * 1024;
  944. break;
  945. case INTEL_915G_GMCH_GMS_STOLEN_64M:
  946. stolen = 64 * 1024 * 1024;
  947. break;
  948. case INTEL_GMCH_GMS_STOLEN_128M:
  949. stolen = 128 * 1024 * 1024;
  950. break;
  951. case INTEL_GMCH_GMS_STOLEN_256M:
  952. stolen = 256 * 1024 * 1024;
  953. break;
  954. case INTEL_GMCH_GMS_STOLEN_96M:
  955. stolen = 96 * 1024 * 1024;
  956. break;
  957. case INTEL_GMCH_GMS_STOLEN_160M:
  958. stolen = 160 * 1024 * 1024;
  959. break;
  960. case INTEL_GMCH_GMS_STOLEN_224M:
  961. stolen = 224 * 1024 * 1024;
  962. break;
  963. case INTEL_GMCH_GMS_STOLEN_352M:
  964. stolen = 352 * 1024 * 1024;
  965. break;
  966. default:
  967. DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  968. tmp & INTEL_GMCH_GMS_MASK);
  969. return -1;
  970. }
  971. }
  972. *preallocated_size = stolen - overhead;
  973. *start = overhead;
  974. return 0;
  975. }
  976. #define PTE_ADDRESS_MASK 0xfffff000
  977. #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
  978. #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
  979. #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
  980. #define PTE_MAPPING_TYPE_CACHED (3 << 1)
  981. #define PTE_MAPPING_TYPE_MASK (3 << 1)
  982. #define PTE_VALID (1 << 0)
  983. /**
  984. * i915_gtt_to_phys - take a GTT address and turn it into a physical one
  985. * @dev: drm device
  986. * @gtt_addr: address to translate
  987. *
  988. * Some chip functions require allocations from stolen space but need the
  989. * physical address of the memory in question. We use this routine
  990. * to get a physical address suitable for register programming from a given
  991. * GTT address.
  992. */
  993. static unsigned long i915_gtt_to_phys(struct drm_device *dev,
  994. unsigned long gtt_addr)
  995. {
  996. unsigned long *gtt;
  997. unsigned long entry, phys;
  998. int gtt_bar = IS_I9XX(dev) ? 0 : 1;
  999. int gtt_offset, gtt_size;
  1000. if (IS_I965G(dev)) {
  1001. if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
  1002. gtt_offset = 2*1024*1024;
  1003. gtt_size = 2*1024*1024;
  1004. } else {
  1005. gtt_offset = 512*1024;
  1006. gtt_size = 512*1024;
  1007. }
  1008. } else {
  1009. gtt_bar = 3;
  1010. gtt_offset = 0;
  1011. gtt_size = pci_resource_len(dev->pdev, gtt_bar);
  1012. }
  1013. gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
  1014. gtt_size);
  1015. if (!gtt) {
  1016. DRM_ERROR("ioremap of GTT failed\n");
  1017. return 0;
  1018. }
  1019. entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
  1020. DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
  1021. /* Mask out these reserved bits on this hardware. */
  1022. if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
  1023. IS_I945G(dev) || IS_I945GM(dev)) {
  1024. entry &= ~PTE_ADDRESS_MASK_HIGH;
  1025. }
  1026. /* If it's not a mapping type we know, then bail. */
  1027. if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
  1028. (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
  1029. iounmap(gtt);
  1030. return 0;
  1031. }
  1032. if (!(entry & PTE_VALID)) {
  1033. DRM_ERROR("bad GTT entry in stolen space\n");
  1034. iounmap(gtt);
  1035. return 0;
  1036. }
  1037. iounmap(gtt);
  1038. phys =(entry & PTE_ADDRESS_MASK) |
  1039. ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
  1040. DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
  1041. return phys;
  1042. }
  1043. static void i915_warn_stolen(struct drm_device *dev)
  1044. {
  1045. DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
  1046. DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
  1047. }
  1048. static void i915_setup_compression(struct drm_device *dev, int size)
  1049. {
  1050. struct drm_i915_private *dev_priv = dev->dev_private;
  1051. struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
  1052. unsigned long cfb_base;
  1053. unsigned long ll_base = 0;
  1054. /* Leave 1M for line length buffer & misc. */
  1055. compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
  1056. if (!compressed_fb) {
  1057. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1058. i915_warn_stolen(dev);
  1059. return;
  1060. }
  1061. compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
  1062. if (!compressed_fb) {
  1063. i915_warn_stolen(dev);
  1064. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1065. return;
  1066. }
  1067. cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
  1068. if (!cfb_base) {
  1069. DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
  1070. drm_mm_put_block(compressed_fb);
  1071. }
  1072. if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
  1073. compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
  1074. 4096, 0);
  1075. if (!compressed_llb) {
  1076. i915_warn_stolen(dev);
  1077. return;
  1078. }
  1079. compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
  1080. if (!compressed_llb) {
  1081. i915_warn_stolen(dev);
  1082. return;
  1083. }
  1084. ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
  1085. if (!ll_base) {
  1086. DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
  1087. drm_mm_put_block(compressed_fb);
  1088. drm_mm_put_block(compressed_llb);
  1089. }
  1090. }
  1091. dev_priv->cfb_size = size;
  1092. intel_disable_fbc(dev);
  1093. dev_priv->compressed_fb = compressed_fb;
  1094. if (IS_IRONLAKE_M(dev))
  1095. I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
  1096. else if (IS_GM45(dev)) {
  1097. I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
  1098. } else {
  1099. I915_WRITE(FBC_CFB_BASE, cfb_base);
  1100. I915_WRITE(FBC_LL_BASE, ll_base);
  1101. dev_priv->compressed_llb = compressed_llb;
  1102. }
  1103. DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
  1104. ll_base, size >> 20);
  1105. }
  1106. static void i915_cleanup_compression(struct drm_device *dev)
  1107. {
  1108. struct drm_i915_private *dev_priv = dev->dev_private;
  1109. drm_mm_put_block(dev_priv->compressed_fb);
  1110. if (dev_priv->compressed_llb)
  1111. drm_mm_put_block(dev_priv->compressed_llb);
  1112. }
  1113. /* true = enable decode, false = disable decoder */
  1114. static unsigned int i915_vga_set_decode(void *cookie, bool state)
  1115. {
  1116. struct drm_device *dev = cookie;
  1117. intel_modeset_vga_set_state(dev, state);
  1118. if (state)
  1119. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  1120. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  1121. else
  1122. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  1123. }
  1124. static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
  1125. {
  1126. struct drm_device *dev = pci_get_drvdata(pdev);
  1127. pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
  1128. if (state == VGA_SWITCHEROO_ON) {
  1129. printk(KERN_INFO "i915: switched on\n");
  1130. /* i915 resume handler doesn't set to D0 */
  1131. pci_set_power_state(dev->pdev, PCI_D0);
  1132. i915_resume(dev);
  1133. drm_kms_helper_poll_enable(dev);
  1134. } else {
  1135. printk(KERN_ERR "i915: switched off\n");
  1136. drm_kms_helper_poll_disable(dev);
  1137. i915_suspend(dev, pmm);
  1138. }
  1139. }
  1140. static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
  1141. {
  1142. struct drm_device *dev = pci_get_drvdata(pdev);
  1143. bool can_switch;
  1144. spin_lock(&dev->count_lock);
  1145. can_switch = (dev->open_count == 0);
  1146. spin_unlock(&dev->count_lock);
  1147. return can_switch;
  1148. }
  1149. static int i915_load_modeset_init(struct drm_device *dev,
  1150. unsigned long prealloc_start,
  1151. unsigned long prealloc_size,
  1152. unsigned long agp_size)
  1153. {
  1154. struct drm_i915_private *dev_priv = dev->dev_private;
  1155. int fb_bar = IS_I9XX(dev) ? 2 : 0;
  1156. int ret = 0;
  1157. dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
  1158. 0xff000000;
  1159. /* Basic memrange allocator for stolen space (aka vram) */
  1160. drm_mm_init(&dev_priv->vram, 0, prealloc_size);
  1161. DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
  1162. /* We're off and running w/KMS */
  1163. dev_priv->mm.suspended = 0;
  1164. /* Let GEM Manage from end of prealloc space to end of aperture.
  1165. *
  1166. * However, leave one page at the end still bound to the scratch page.
  1167. * There are a number of places where the hardware apparently
  1168. * prefetches past the end of the object, and we've seen multiple
  1169. * hangs with the GPU head pointer stuck in a batchbuffer bound
  1170. * at the last page of the aperture. One page should be enough to
  1171. * keep any prefetching inside of the aperture.
  1172. */
  1173. i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
  1174. mutex_lock(&dev->struct_mutex);
  1175. ret = i915_gem_init_ringbuffer(dev);
  1176. mutex_unlock(&dev->struct_mutex);
  1177. if (ret)
  1178. goto out;
  1179. /* Try to set up FBC with a reasonable compressed buffer size */
  1180. if (I915_HAS_FBC(dev) && i915_powersave) {
  1181. int cfb_size;
  1182. /* Try to get an 8M buffer... */
  1183. if (prealloc_size > (9*1024*1024))
  1184. cfb_size = 8*1024*1024;
  1185. else /* fall back to 7/8 of the stolen space */
  1186. cfb_size = prealloc_size * 7 / 8;
  1187. i915_setup_compression(dev, cfb_size);
  1188. }
  1189. /* Allow hardware batchbuffers unless told otherwise.
  1190. */
  1191. dev_priv->allow_batchbuffer = 1;
  1192. ret = intel_init_bios(dev);
  1193. if (ret)
  1194. DRM_INFO("failed to find VBIOS tables\n");
  1195. /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  1196. ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
  1197. if (ret)
  1198. goto cleanup_ringbuffer;
  1199. ret = vga_switcheroo_register_client(dev->pdev,
  1200. i915_switcheroo_set_state,
  1201. i915_switcheroo_can_switch);
  1202. if (ret)
  1203. goto cleanup_vga_client;
  1204. /* IIR "flip pending" bit means done if this bit is set */
  1205. if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
  1206. dev_priv->flip_pending_is_done = true;
  1207. intel_modeset_init(dev);
  1208. ret = drm_irq_install(dev);
  1209. if (ret)
  1210. goto cleanup_vga_switcheroo;
  1211. /* Always safe in the mode setting case. */
  1212. /* FIXME: do pre/post-mode set stuff in core KMS code */
  1213. dev->vblank_disable_allowed = 1;
  1214. /*
  1215. * Initialize the hardware status page IRQ location.
  1216. */
  1217. I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
  1218. ret = intel_fbdev_init(dev);
  1219. if (ret)
  1220. goto cleanup_irq;
  1221. drm_kms_helper_poll_init(dev);
  1222. return 0;
  1223. cleanup_irq:
  1224. drm_irq_uninstall(dev);
  1225. cleanup_vga_switcheroo:
  1226. vga_switcheroo_unregister_client(dev->pdev);
  1227. cleanup_vga_client:
  1228. vga_client_register(dev->pdev, NULL, NULL, NULL);
  1229. cleanup_ringbuffer:
  1230. mutex_lock(&dev->struct_mutex);
  1231. i915_gem_cleanup_ringbuffer(dev);
  1232. mutex_unlock(&dev->struct_mutex);
  1233. out:
  1234. return ret;
  1235. }
  1236. int i915_master_create(struct drm_device *dev, struct drm_master *master)
  1237. {
  1238. struct drm_i915_master_private *master_priv;
  1239. master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
  1240. if (!master_priv)
  1241. return -ENOMEM;
  1242. master->driver_priv = master_priv;
  1243. return 0;
  1244. }
  1245. void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
  1246. {
  1247. struct drm_i915_master_private *master_priv = master->driver_priv;
  1248. if (!master_priv)
  1249. return;
  1250. kfree(master_priv);
  1251. master->driver_priv = NULL;
  1252. }
  1253. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  1254. {
  1255. drm_i915_private_t *dev_priv = dev->dev_private;
  1256. u32 tmp;
  1257. tmp = I915_READ(CLKCFG);
  1258. switch (tmp & CLKCFG_FSB_MASK) {
  1259. case CLKCFG_FSB_533:
  1260. dev_priv->fsb_freq = 533; /* 133*4 */
  1261. break;
  1262. case CLKCFG_FSB_800:
  1263. dev_priv->fsb_freq = 800; /* 200*4 */
  1264. break;
  1265. case CLKCFG_FSB_667:
  1266. dev_priv->fsb_freq = 667; /* 167*4 */
  1267. break;
  1268. case CLKCFG_FSB_400:
  1269. dev_priv->fsb_freq = 400; /* 100*4 */
  1270. break;
  1271. }
  1272. switch (tmp & CLKCFG_MEM_MASK) {
  1273. case CLKCFG_MEM_533:
  1274. dev_priv->mem_freq = 533;
  1275. break;
  1276. case CLKCFG_MEM_667:
  1277. dev_priv->mem_freq = 667;
  1278. break;
  1279. case CLKCFG_MEM_800:
  1280. dev_priv->mem_freq = 800;
  1281. break;
  1282. }
  1283. /* detect pineview DDR3 setting */
  1284. tmp = I915_READ(CSHRDDR3CTL);
  1285. dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  1286. }
  1287. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  1288. {
  1289. drm_i915_private_t *dev_priv = dev->dev_private;
  1290. u16 ddrpll, csipll;
  1291. ddrpll = I915_READ16(DDRMPLL1);
  1292. csipll = I915_READ16(CSIPLL0);
  1293. switch (ddrpll & 0xff) {
  1294. case 0xc:
  1295. dev_priv->mem_freq = 800;
  1296. break;
  1297. case 0x10:
  1298. dev_priv->mem_freq = 1066;
  1299. break;
  1300. case 0x14:
  1301. dev_priv->mem_freq = 1333;
  1302. break;
  1303. case 0x18:
  1304. dev_priv->mem_freq = 1600;
  1305. break;
  1306. default:
  1307. DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  1308. ddrpll & 0xff);
  1309. dev_priv->mem_freq = 0;
  1310. break;
  1311. }
  1312. dev_priv->r_t = dev_priv->mem_freq;
  1313. switch (csipll & 0x3ff) {
  1314. case 0x00c:
  1315. dev_priv->fsb_freq = 3200;
  1316. break;
  1317. case 0x00e:
  1318. dev_priv->fsb_freq = 3733;
  1319. break;
  1320. case 0x010:
  1321. dev_priv->fsb_freq = 4266;
  1322. break;
  1323. case 0x012:
  1324. dev_priv->fsb_freq = 4800;
  1325. break;
  1326. case 0x014:
  1327. dev_priv->fsb_freq = 5333;
  1328. break;
  1329. case 0x016:
  1330. dev_priv->fsb_freq = 5866;
  1331. break;
  1332. case 0x018:
  1333. dev_priv->fsb_freq = 6400;
  1334. break;
  1335. default:
  1336. DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  1337. csipll & 0x3ff);
  1338. dev_priv->fsb_freq = 0;
  1339. break;
  1340. }
  1341. if (dev_priv->fsb_freq == 3200) {
  1342. dev_priv->c_m = 0;
  1343. } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  1344. dev_priv->c_m = 1;
  1345. } else {
  1346. dev_priv->c_m = 2;
  1347. }
  1348. }
  1349. struct v_table {
  1350. u8 vid;
  1351. unsigned long vd; /* in .1 mil */
  1352. unsigned long vm; /* in .1 mil */
  1353. u8 pvid;
  1354. };
  1355. static struct v_table v_table[] = {
  1356. { 0, 16125, 15000, 0x7f, },
  1357. { 1, 16000, 14875, 0x7e, },
  1358. { 2, 15875, 14750, 0x7d, },
  1359. { 3, 15750, 14625, 0x7c, },
  1360. { 4, 15625, 14500, 0x7b, },
  1361. { 5, 15500, 14375, 0x7a, },
  1362. { 6, 15375, 14250, 0x79, },
  1363. { 7, 15250, 14125, 0x78, },
  1364. { 8, 15125, 14000, 0x77, },
  1365. { 9, 15000, 13875, 0x76, },
  1366. { 10, 14875, 13750, 0x75, },
  1367. { 11, 14750, 13625, 0x74, },
  1368. { 12, 14625, 13500, 0x73, },
  1369. { 13, 14500, 13375, 0x72, },
  1370. { 14, 14375, 13250, 0x71, },
  1371. { 15, 14250, 13125, 0x70, },
  1372. { 16, 14125, 13000, 0x6f, },
  1373. { 17, 14000, 12875, 0x6e, },
  1374. { 18, 13875, 12750, 0x6d, },
  1375. { 19, 13750, 12625, 0x6c, },
  1376. { 20, 13625, 12500, 0x6b, },
  1377. { 21, 13500, 12375, 0x6a, },
  1378. { 22, 13375, 12250, 0x69, },
  1379. { 23, 13250, 12125, 0x68, },
  1380. { 24, 13125, 12000, 0x67, },
  1381. { 25, 13000, 11875, 0x66, },
  1382. { 26, 12875, 11750, 0x65, },
  1383. { 27, 12750, 11625, 0x64, },
  1384. { 28, 12625, 11500, 0x63, },
  1385. { 29, 12500, 11375, 0x62, },
  1386. { 30, 12375, 11250, 0x61, },
  1387. { 31, 12250, 11125, 0x60, },
  1388. { 32, 12125, 11000, 0x5f, },
  1389. { 33, 12000, 10875, 0x5e, },
  1390. { 34, 11875, 10750, 0x5d, },
  1391. { 35, 11750, 10625, 0x5c, },
  1392. { 36, 11625, 10500, 0x5b, },
  1393. { 37, 11500, 10375, 0x5a, },
  1394. { 38, 11375, 10250, 0x59, },
  1395. { 39, 11250, 10125, 0x58, },
  1396. { 40, 11125, 10000, 0x57, },
  1397. { 41, 11000, 9875, 0x56, },
  1398. { 42, 10875, 9750, 0x55, },
  1399. { 43, 10750, 9625, 0x54, },
  1400. { 44, 10625, 9500, 0x53, },
  1401. { 45, 10500, 9375, 0x52, },
  1402. { 46, 10375, 9250, 0x51, },
  1403. { 47, 10250, 9125, 0x50, },
  1404. { 48, 10125, 9000, 0x4f, },
  1405. { 49, 10000, 8875, 0x4e, },
  1406. { 50, 9875, 8750, 0x4d, },
  1407. { 51, 9750, 8625, 0x4c, },
  1408. { 52, 9625, 8500, 0x4b, },
  1409. { 53, 9500, 8375, 0x4a, },
  1410. { 54, 9375, 8250, 0x49, },
  1411. { 55, 9250, 8125, 0x48, },
  1412. { 56, 9125, 8000, 0x47, },
  1413. { 57, 9000, 7875, 0x46, },
  1414. { 58, 8875, 7750, 0x45, },
  1415. { 59, 8750, 7625, 0x44, },
  1416. { 60, 8625, 7500, 0x43, },
  1417. { 61, 8500, 7375, 0x42, },
  1418. { 62, 8375, 7250, 0x41, },
  1419. { 63, 8250, 7125, 0x40, },
  1420. { 64, 8125, 7000, 0x3f, },
  1421. { 65, 8000, 6875, 0x3e, },
  1422. { 66, 7875, 6750, 0x3d, },
  1423. { 67, 7750, 6625, 0x3c, },
  1424. { 68, 7625, 6500, 0x3b, },
  1425. { 69, 7500, 6375, 0x3a, },
  1426. { 70, 7375, 6250, 0x39, },
  1427. { 71, 7250, 6125, 0x38, },
  1428. { 72, 7125, 6000, 0x37, },
  1429. { 73, 7000, 5875, 0x36, },
  1430. { 74, 6875, 5750, 0x35, },
  1431. { 75, 6750, 5625, 0x34, },
  1432. { 76, 6625, 5500, 0x33, },
  1433. { 77, 6500, 5375, 0x32, },
  1434. { 78, 6375, 5250, 0x31, },
  1435. { 79, 6250, 5125, 0x30, },
  1436. { 80, 6125, 5000, 0x2f, },
  1437. { 81, 6000, 4875, 0x2e, },
  1438. { 82, 5875, 4750, 0x2d, },
  1439. { 83, 5750, 4625, 0x2c, },
  1440. { 84, 5625, 4500, 0x2b, },
  1441. { 85, 5500, 4375, 0x2a, },
  1442. { 86, 5375, 4250, 0x29, },
  1443. { 87, 5250, 4125, 0x28, },
  1444. { 88, 5125, 4000, 0x27, },
  1445. { 89, 5000, 3875, 0x26, },
  1446. { 90, 4875, 3750, 0x25, },
  1447. { 91, 4750, 3625, 0x24, },
  1448. { 92, 4625, 3500, 0x23, },
  1449. { 93, 4500, 3375, 0x22, },
  1450. { 94, 4375, 3250, 0x21, },
  1451. { 95, 4250, 3125, 0x20, },
  1452. { 96, 4125, 3000, 0x1f, },
  1453. { 97, 4125, 3000, 0x1e, },
  1454. { 98, 4125, 3000, 0x1d, },
  1455. { 99, 4125, 3000, 0x1c, },
  1456. { 100, 4125, 3000, 0x1b, },
  1457. { 101, 4125, 3000, 0x1a, },
  1458. { 102, 4125, 3000, 0x19, },
  1459. { 103, 4125, 3000, 0x18, },
  1460. { 104, 4125, 3000, 0x17, },
  1461. { 105, 4125, 3000, 0x16, },
  1462. { 106, 4125, 3000, 0x15, },
  1463. { 107, 4125, 3000, 0x14, },
  1464. { 108, 4125, 3000, 0x13, },
  1465. { 109, 4125, 3000, 0x12, },
  1466. { 110, 4125, 3000, 0x11, },
  1467. { 111, 4125, 3000, 0x10, },
  1468. { 112, 4125, 3000, 0x0f, },
  1469. { 113, 4125, 3000, 0x0e, },
  1470. { 114, 4125, 3000, 0x0d, },
  1471. { 115, 4125, 3000, 0x0c, },
  1472. { 116, 4125, 3000, 0x0b, },
  1473. { 117, 4125, 3000, 0x0a, },
  1474. { 118, 4125, 3000, 0x09, },
  1475. { 119, 4125, 3000, 0x08, },
  1476. { 120, 1125, 0, 0x07, },
  1477. { 121, 1000, 0, 0x06, },
  1478. { 122, 875, 0, 0x05, },
  1479. { 123, 750, 0, 0x04, },
  1480. { 124, 625, 0, 0x03, },
  1481. { 125, 500, 0, 0x02, },
  1482. { 126, 375, 0, 0x01, },
  1483. { 127, 0, 0, 0x00, },
  1484. };
  1485. struct cparams {
  1486. int i;
  1487. int t;
  1488. int m;
  1489. int c;
  1490. };
  1491. static struct cparams cparams[] = {
  1492. { 1, 1333, 301, 28664 },
  1493. { 1, 1066, 294, 24460 },
  1494. { 1, 800, 294, 25192 },
  1495. { 0, 1333, 276, 27605 },
  1496. { 0, 1066, 276, 27605 },
  1497. { 0, 800, 231, 23784 },
  1498. };
  1499. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  1500. {
  1501. u64 total_count, diff, ret;
  1502. u32 count1, count2, count3, m = 0, c = 0;
  1503. unsigned long now = jiffies_to_msecs(jiffies), diff1;
  1504. int i;
  1505. diff1 = now - dev_priv->last_time1;
  1506. count1 = I915_READ(DMIEC);
  1507. count2 = I915_READ(DDREC);
  1508. count3 = I915_READ(CSIEC);
  1509. total_count = count1 + count2 + count3;
  1510. /* FIXME: handle per-counter overflow */
  1511. if (total_count < dev_priv->last_count1) {
  1512. diff = ~0UL - dev_priv->last_count1;
  1513. diff += total_count;
  1514. } else {
  1515. diff = total_count - dev_priv->last_count1;
  1516. }
  1517. for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  1518. if (cparams[i].i == dev_priv->c_m &&
  1519. cparams[i].t == dev_priv->r_t) {
  1520. m = cparams[i].m;
  1521. c = cparams[i].c;
  1522. break;
  1523. }
  1524. }
  1525. div_u64(diff, diff1);
  1526. ret = ((m * diff) + c);
  1527. div_u64(ret, 10);
  1528. dev_priv->last_count1 = total_count;
  1529. dev_priv->last_time1 = now;
  1530. return ret;
  1531. }
  1532. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  1533. {
  1534. unsigned long m, x, b;
  1535. u32 tsfs;
  1536. tsfs = I915_READ(TSFS);
  1537. m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  1538. x = I915_READ8(TR1);
  1539. b = tsfs & TSFS_INTR_MASK;
  1540. return ((m * x) / 127) - b;
  1541. }
  1542. static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  1543. {
  1544. unsigned long val = 0;
  1545. int i;
  1546. for (i = 0; i < ARRAY_SIZE(v_table); i++) {
  1547. if (v_table[i].pvid == pxvid) {
  1548. if (IS_MOBILE(dev_priv->dev))
  1549. val = v_table[i].vm;
  1550. else
  1551. val = v_table[i].vd;
  1552. }
  1553. }
  1554. return val;
  1555. }
  1556. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  1557. {
  1558. struct timespec now, diff1;
  1559. u64 diff;
  1560. unsigned long diffms;
  1561. u32 count;
  1562. getrawmonotonic(&now);
  1563. diff1 = timespec_sub(now, dev_priv->last_time2);
  1564. /* Don't divide by 0 */
  1565. diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  1566. if (!diffms)
  1567. return;
  1568. count = I915_READ(GFXEC);
  1569. if (count < dev_priv->last_count2) {
  1570. diff = ~0UL - dev_priv->last_count2;
  1571. diff += count;
  1572. } else {
  1573. diff = count - dev_priv->last_count2;
  1574. }
  1575. dev_priv->last_count2 = count;
  1576. dev_priv->last_time2 = now;
  1577. /* More magic constants... */
  1578. diff = diff * 1181;
  1579. div_u64(diff, diffms * 10);
  1580. dev_priv->gfx_power = diff;
  1581. }
  1582. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  1583. {
  1584. unsigned long t, corr, state1, corr2, state2;
  1585. u32 pxvid, ext_v;
  1586. pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
  1587. pxvid = (pxvid >> 24) & 0x7f;
  1588. ext_v = pvid_to_extvid(dev_priv, pxvid);
  1589. state1 = ext_v;
  1590. t = i915_mch_val(dev_priv);
  1591. /* Revel in the empirically derived constants */
  1592. /* Correction factor in 1/100000 units */
  1593. if (t > 80)
  1594. corr = ((t * 2349) + 135940);
  1595. else if (t >= 50)
  1596. corr = ((t * 964) + 29317);
  1597. else /* < 50 */
  1598. corr = ((t * 301) + 1004);
  1599. corr = corr * ((150142 * state1) / 10000 - 78642);
  1600. corr /= 100000;
  1601. corr2 = (corr * dev_priv->corr);
  1602. state2 = (corr2 * state1) / 10000;
  1603. state2 /= 100; /* convert to mW */
  1604. i915_update_gfx_val(dev_priv);
  1605. return dev_priv->gfx_power + state2;
  1606. }
  1607. /* Global for IPS driver to get at the current i915 device */
  1608. static struct drm_i915_private *i915_mch_dev;
  1609. /*
  1610. * Lock protecting IPS related data structures
  1611. * - i915_mch_dev
  1612. * - dev_priv->max_delay
  1613. * - dev_priv->min_delay
  1614. * - dev_priv->fmax
  1615. * - dev_priv->gpu_busy
  1616. */
  1617. DEFINE_SPINLOCK(mchdev_lock);
  1618. /**
  1619. * i915_read_mch_val - return value for IPS use
  1620. *
  1621. * Calculate and return a value for the IPS driver to use when deciding whether
  1622. * we have thermal and power headroom to increase CPU or GPU power budget.
  1623. */
  1624. unsigned long i915_read_mch_val(void)
  1625. {
  1626. struct drm_i915_private *dev_priv;
  1627. unsigned long chipset_val, graphics_val, ret = 0;
  1628. spin_lock(&mchdev_lock);
  1629. if (!i915_mch_dev)
  1630. goto out_unlock;
  1631. dev_priv = i915_mch_dev;
  1632. chipset_val = i915_chipset_val(dev_priv);
  1633. graphics_val = i915_gfx_val(dev_priv);
  1634. ret = chipset_val + graphics_val;
  1635. out_unlock:
  1636. spin_unlock(&mchdev_lock);
  1637. return ret;
  1638. }
  1639. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  1640. /**
  1641. * i915_gpu_raise - raise GPU frequency limit
  1642. *
  1643. * Raise the limit; IPS indicates we have thermal headroom.
  1644. */
  1645. bool i915_gpu_raise(void)
  1646. {
  1647. struct drm_i915_private *dev_priv;
  1648. bool ret = true;
  1649. spin_lock(&mchdev_lock);
  1650. if (!i915_mch_dev) {
  1651. ret = false;
  1652. goto out_unlock;
  1653. }
  1654. dev_priv = i915_mch_dev;
  1655. if (dev_priv->max_delay > dev_priv->fmax)
  1656. dev_priv->max_delay--;
  1657. out_unlock:
  1658. spin_unlock(&mchdev_lock);
  1659. return ret;
  1660. }
  1661. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  1662. /**
  1663. * i915_gpu_lower - lower GPU frequency limit
  1664. *
  1665. * IPS indicates we're close to a thermal limit, so throttle back the GPU
  1666. * frequency maximum.
  1667. */
  1668. bool i915_gpu_lower(void)
  1669. {
  1670. struct drm_i915_private *dev_priv;
  1671. bool ret = true;
  1672. spin_lock(&mchdev_lock);
  1673. if (!i915_mch_dev) {
  1674. ret = false;
  1675. goto out_unlock;
  1676. }
  1677. dev_priv = i915_mch_dev;
  1678. if (dev_priv->max_delay < dev_priv->min_delay)
  1679. dev_priv->max_delay++;
  1680. out_unlock:
  1681. spin_unlock(&mchdev_lock);
  1682. return ret;
  1683. }
  1684. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  1685. /**
  1686. * i915_gpu_busy - indicate GPU business to IPS
  1687. *
  1688. * Tell the IPS driver whether or not the GPU is busy.
  1689. */
  1690. bool i915_gpu_busy(void)
  1691. {
  1692. struct drm_i915_private *dev_priv;
  1693. bool ret = false;
  1694. spin_lock(&mchdev_lock);
  1695. if (!i915_mch_dev)
  1696. goto out_unlock;
  1697. dev_priv = i915_mch_dev;
  1698. ret = dev_priv->busy;
  1699. out_unlock:
  1700. spin_unlock(&mchdev_lock);
  1701. return ret;
  1702. }
  1703. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  1704. /**
  1705. * i915_gpu_turbo_disable - disable graphics turbo
  1706. *
  1707. * Disable graphics turbo by resetting the max frequency and setting the
  1708. * current frequency to the default.
  1709. */
  1710. bool i915_gpu_turbo_disable(void)
  1711. {
  1712. struct drm_i915_private *dev_priv;
  1713. bool ret = true;
  1714. spin_lock(&mchdev_lock);
  1715. if (!i915_mch_dev) {
  1716. ret = false;
  1717. goto out_unlock;
  1718. }
  1719. dev_priv = i915_mch_dev;
  1720. dev_priv->max_delay = dev_priv->fstart;
  1721. if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
  1722. ret = false;
  1723. out_unlock:
  1724. spin_unlock(&mchdev_lock);
  1725. return ret;
  1726. }
  1727. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  1728. /**
  1729. * i915_driver_load - setup chip and create an initial config
  1730. * @dev: DRM device
  1731. * @flags: startup flags
  1732. *
  1733. * The driver load routine has to do several things:
  1734. * - drive output discovery via intel_modeset_init()
  1735. * - initialize the memory manager
  1736. * - allocate initial config memory
  1737. * - setup the DRM framebuffer with the allocated memory
  1738. */
  1739. int i915_driver_load(struct drm_device *dev, unsigned long flags)
  1740. {
  1741. struct drm_i915_private *dev_priv;
  1742. resource_size_t base, size;
  1743. int ret = 0, mmio_bar;
  1744. uint32_t agp_size, prealloc_size, prealloc_start;
  1745. /* i915 has 4 more counters */
  1746. dev->counters += 4;
  1747. dev->types[6] = _DRM_STAT_IRQ;
  1748. dev->types[7] = _DRM_STAT_PRIMARY;
  1749. dev->types[8] = _DRM_STAT_SECONDARY;
  1750. dev->types[9] = _DRM_STAT_DMA;
  1751. dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
  1752. if (dev_priv == NULL)
  1753. return -ENOMEM;
  1754. dev->dev_private = (void *)dev_priv;
  1755. dev_priv->dev = dev;
  1756. dev_priv->info = (struct intel_device_info *) flags;
  1757. /* Add register map (needed for suspend/resume) */
  1758. mmio_bar = IS_I9XX(dev) ? 0 : 1;
  1759. base = pci_resource_start(dev->pdev, mmio_bar);
  1760. size = pci_resource_len(dev->pdev, mmio_bar);
  1761. if (i915_get_bridge_dev(dev)) {
  1762. ret = -EIO;
  1763. goto free_priv;
  1764. }
  1765. dev_priv->regs = ioremap(base, size);
  1766. if (!dev_priv->regs) {
  1767. DRM_ERROR("failed to map registers\n");
  1768. ret = -EIO;
  1769. goto put_bridge;
  1770. }
  1771. dev_priv->mm.gtt_mapping =
  1772. io_mapping_create_wc(dev->agp->base,
  1773. dev->agp->agp_info.aper_size * 1024*1024);
  1774. if (dev_priv->mm.gtt_mapping == NULL) {
  1775. ret = -EIO;
  1776. goto out_rmmap;
  1777. }
  1778. /* Set up a WC MTRR for non-PAT systems. This is more common than
  1779. * one would think, because the kernel disables PAT on first
  1780. * generation Core chips because WC PAT gets overridden by a UC
  1781. * MTRR if present. Even if a UC MTRR isn't present.
  1782. */
  1783. dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
  1784. dev->agp->agp_info.aper_size *
  1785. 1024 * 1024,
  1786. MTRR_TYPE_WRCOMB, 1);
  1787. if (dev_priv->mm.gtt_mtrr < 0) {
  1788. DRM_INFO("MTRR allocation failed. Graphics "
  1789. "performance may suffer.\n");
  1790. }
  1791. ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
  1792. if (ret)
  1793. goto out_iomapfree;
  1794. if (prealloc_size > intel_max_stolen) {
  1795. DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
  1796. prealloc_size >> 20, intel_max_stolen >> 20);
  1797. prealloc_size = intel_max_stolen;
  1798. }
  1799. dev_priv->wq = create_singlethread_workqueue("i915");
  1800. if (dev_priv->wq == NULL) {
  1801. DRM_ERROR("Failed to create our workqueue.\n");
  1802. ret = -ENOMEM;
  1803. goto out_iomapfree;
  1804. }
  1805. /* enable GEM by default */
  1806. dev_priv->has_gem = 1;
  1807. if (prealloc_size > agp_size * 3 / 4) {
  1808. DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
  1809. "memory stolen.\n",
  1810. prealloc_size / 1024, agp_size / 1024);
  1811. DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
  1812. "updating the BIOS to fix).\n");
  1813. dev_priv->has_gem = 0;
  1814. }
  1815. if (dev_priv->has_gem == 0 &&
  1816. drm_core_check_feature(dev, DRIVER_MODESET)) {
  1817. DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
  1818. ret = -ENODEV;
  1819. goto out_iomapfree;
  1820. }
  1821. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  1822. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  1823. if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
  1824. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  1825. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  1826. }
  1827. /* Try to make sure MCHBAR is enabled before poking at it */
  1828. intel_setup_mchbar(dev);
  1829. i915_gem_load(dev);
  1830. /* Init HWS */
  1831. if (!I915_NEED_GFX_HWS(dev)) {
  1832. ret = i915_init_phys_hws(dev);
  1833. if (ret != 0)
  1834. goto out_workqueue_free;
  1835. }
  1836. if (IS_PINEVIEW(dev))
  1837. i915_pineview_get_mem_freq(dev);
  1838. else if (IS_IRONLAKE(dev))
  1839. i915_ironlake_get_mem_freq(dev);
  1840. /* On the 945G/GM, the chipset reports the MSI capability on the
  1841. * integrated graphics even though the support isn't actually there
  1842. * according to the published specs. It doesn't appear to function
  1843. * correctly in testing on 945G.
  1844. * This may be a side effect of MSI having been made available for PEG
  1845. * and the registers being closely associated.
  1846. *
  1847. * According to chipset errata, on the 965GM, MSI interrupts may
  1848. * be lost or delayed, but we use them anyways to avoid
  1849. * stuck interrupts on some machines.
  1850. */
  1851. if (!IS_I945G(dev) && !IS_I945GM(dev))
  1852. pci_enable_msi(dev->pdev);
  1853. spin_lock_init(&dev_priv->user_irq_lock);
  1854. spin_lock_init(&dev_priv->error_lock);
  1855. dev_priv->trace_irq_seqno = 0;
  1856. ret = drm_vblank_init(dev, I915_NUM_PIPE);
  1857. if (ret) {
  1858. (void) i915_driver_unload(dev);
  1859. return ret;
  1860. }
  1861. /* Start out suspended */
  1862. dev_priv->mm.suspended = 1;
  1863. intel_detect_pch(dev);
  1864. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1865. ret = i915_load_modeset_init(dev, prealloc_start,
  1866. prealloc_size, agp_size);
  1867. if (ret < 0) {
  1868. DRM_ERROR("failed to init modeset\n");
  1869. goto out_workqueue_free;
  1870. }
  1871. }
  1872. /* Must be done after probing outputs */
  1873. intel_opregion_init(dev, 0);
  1874. setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
  1875. (unsigned long) dev);
  1876. spin_lock(&mchdev_lock);
  1877. i915_mch_dev = dev_priv;
  1878. dev_priv->mchdev_lock = &mchdev_lock;
  1879. spin_unlock(&mchdev_lock);
  1880. return 0;
  1881. out_workqueue_free:
  1882. destroy_workqueue(dev_priv->wq);
  1883. out_iomapfree:
  1884. io_mapping_free(dev_priv->mm.gtt_mapping);
  1885. out_rmmap:
  1886. iounmap(dev_priv->regs);
  1887. put_bridge:
  1888. pci_dev_put(dev_priv->bridge_dev);
  1889. free_priv:
  1890. kfree(dev_priv);
  1891. return ret;
  1892. }
  1893. int i915_driver_unload(struct drm_device *dev)
  1894. {
  1895. struct drm_i915_private *dev_priv = dev->dev_private;
  1896. i915_destroy_error_state(dev);
  1897. spin_lock(&mchdev_lock);
  1898. i915_mch_dev = NULL;
  1899. spin_unlock(&mchdev_lock);
  1900. destroy_workqueue(dev_priv->wq);
  1901. del_timer_sync(&dev_priv->hangcheck_timer);
  1902. io_mapping_free(dev_priv->mm.gtt_mapping);
  1903. if (dev_priv->mm.gtt_mtrr >= 0) {
  1904. mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
  1905. dev->agp->agp_info.aper_size * 1024 * 1024);
  1906. dev_priv->mm.gtt_mtrr = -1;
  1907. }
  1908. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1909. intel_modeset_cleanup(dev);
  1910. /*
  1911. * free the memory space allocated for the child device
  1912. * config parsed from VBT
  1913. */
  1914. if (dev_priv->child_dev && dev_priv->child_dev_num) {
  1915. kfree(dev_priv->child_dev);
  1916. dev_priv->child_dev = NULL;
  1917. dev_priv->child_dev_num = 0;
  1918. }
  1919. drm_irq_uninstall(dev);
  1920. vga_switcheroo_unregister_client(dev->pdev);
  1921. vga_client_register(dev->pdev, NULL, NULL, NULL);
  1922. }
  1923. if (dev->pdev->msi_enabled)
  1924. pci_disable_msi(dev->pdev);
  1925. if (dev_priv->regs != NULL)
  1926. iounmap(dev_priv->regs);
  1927. intel_opregion_free(dev, 0);
  1928. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1929. i915_gem_free_all_phys_object(dev);
  1930. mutex_lock(&dev->struct_mutex);
  1931. i915_gem_cleanup_ringbuffer(dev);
  1932. mutex_unlock(&dev->struct_mutex);
  1933. if (I915_HAS_FBC(dev) && i915_powersave)
  1934. i915_cleanup_compression(dev);
  1935. drm_mm_takedown(&dev_priv->vram);
  1936. i915_gem_lastclose(dev);
  1937. intel_cleanup_overlay(dev);
  1938. }
  1939. intel_teardown_mchbar(dev);
  1940. pci_dev_put(dev_priv->bridge_dev);
  1941. kfree(dev->dev_private);
  1942. return 0;
  1943. }
  1944. int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  1945. {
  1946. struct drm_i915_file_private *i915_file_priv;
  1947. DRM_DEBUG_DRIVER("\n");
  1948. i915_file_priv = (struct drm_i915_file_private *)
  1949. kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
  1950. if (!i915_file_priv)
  1951. return -ENOMEM;
  1952. file_priv->driver_priv = i915_file_priv;
  1953. INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
  1954. return 0;
  1955. }
  1956. /**
  1957. * i915_driver_lastclose - clean up after all DRM clients have exited
  1958. * @dev: DRM device
  1959. *
  1960. * Take care of cleaning up after all DRM clients have exited. In the
  1961. * mode setting case, we want to restore the kernel's initial mode (just
  1962. * in case the last client left us in a bad state).
  1963. *
  1964. * Additionally, in the non-mode setting case, we'll tear down the AGP
  1965. * and DMA structures, since the kernel won't be using them, and clea
  1966. * up any GEM state.
  1967. */
  1968. void i915_driver_lastclose(struct drm_device * dev)
  1969. {
  1970. drm_i915_private_t *dev_priv = dev->dev_private;
  1971. if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
  1972. drm_fb_helper_restore();
  1973. vga_switcheroo_process_delayed_switch();
  1974. return;
  1975. }
  1976. i915_gem_lastclose(dev);
  1977. if (dev_priv->agp_heap)
  1978. i915_mem_takedown(&(dev_priv->agp_heap));
  1979. i915_dma_cleanup(dev);
  1980. }
  1981. void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1982. {
  1983. drm_i915_private_t *dev_priv = dev->dev_private;
  1984. i915_gem_release(dev, file_priv);
  1985. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  1986. i915_mem_release(dev, file_priv, dev_priv->agp_heap);
  1987. }
  1988. void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
  1989. {
  1990. struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
  1991. kfree(i915_file_priv);
  1992. }
  1993. struct drm_ioctl_desc i915_ioctls[] = {
  1994. DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1995. DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
  1996. DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
  1997. DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
  1998. DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
  1999. DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
  2000. DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
  2001. DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  2002. DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
  2003. DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
  2004. DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  2005. DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
  2006. DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  2007. DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  2008. DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
  2009. DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
  2010. DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  2011. DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2012. DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
  2013. DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
  2014. DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2015. DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2016. DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
  2017. DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
  2018. DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2019. DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2020. DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
  2021. DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
  2022. DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
  2023. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
  2024. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
  2025. DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
  2026. DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
  2027. DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
  2028. DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
  2029. DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
  2030. DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
  2031. DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
  2032. DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  2033. DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  2034. };
  2035. int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
  2036. /**
  2037. * Determine if the device really is AGP or not.
  2038. *
  2039. * All Intel graphics chipsets are treated as AGP, even if they are really
  2040. * PCI-e.
  2041. *
  2042. * \param dev The device to be tested.
  2043. *
  2044. * \returns
  2045. * A value of 1 is always retured to indictate every i9x5 is AGP.
  2046. */
  2047. int i915_driver_device_is_agp(struct drm_device * dev)
  2048. {
  2049. return 1;
  2050. }