cm_bf548.c 27 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2008-2009 Bluetechnix
  4. * 2005 National ICT Australia (NICTA)
  5. * Aidan Williams <aidan@nicta.com.au>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/spi/flash.h>
  16. #include <linux/irq.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/usb/musb.h>
  19. #include <asm/bfin5xx_spi.h>
  20. #include <asm/dma.h>
  21. #include <asm/gpio.h>
  22. #include <asm/nand.h>
  23. #include <asm/portmux.h>
  24. #include <asm/bfin_sdh.h>
  25. #include <mach/bf54x_keys.h>
  26. #include <asm/dpmc.h>
  27. #include <linux/input.h>
  28. #include <linux/spi/ad7877.h>
  29. /*
  30. * Name the Board for the /proc/cpuinfo
  31. */
  32. const char bfin_board_name[] = "Bluetechnix CM-BF548";
  33. /*
  34. * Driver needs to know address, irq and flag pin.
  35. */
  36. #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
  37. #include <mach/bf54x-lq043.h>
  38. static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
  39. .width = 480,
  40. .height = 272,
  41. .xres = {480, 480, 480},
  42. .yres = {272, 272, 272},
  43. .bpp = {24, 24, 24},
  44. .disp = GPIO_PE3,
  45. };
  46. static struct resource bf54x_lq043_resources[] = {
  47. {
  48. .start = IRQ_EPPI0_ERR,
  49. .end = IRQ_EPPI0_ERR,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. };
  53. static struct platform_device bf54x_lq043_device = {
  54. .name = "bf54x-lq043",
  55. .id = -1,
  56. .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
  57. .resource = bf54x_lq043_resources,
  58. .dev = {
  59. .platform_data = &bf54x_lq043_data,
  60. },
  61. };
  62. #endif
  63. #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
  64. static unsigned int bf548_keymap[] = {
  65. KEYVAL(0, 0, KEY_ENTER),
  66. KEYVAL(0, 1, KEY_HELP),
  67. KEYVAL(0, 2, KEY_0),
  68. KEYVAL(0, 3, KEY_BACKSPACE),
  69. KEYVAL(1, 0, KEY_TAB),
  70. KEYVAL(1, 1, KEY_9),
  71. KEYVAL(1, 2, KEY_8),
  72. KEYVAL(1, 3, KEY_7),
  73. KEYVAL(2, 0, KEY_DOWN),
  74. KEYVAL(2, 1, KEY_6),
  75. KEYVAL(2, 2, KEY_5),
  76. KEYVAL(2, 3, KEY_4),
  77. KEYVAL(3, 0, KEY_UP),
  78. KEYVAL(3, 1, KEY_3),
  79. KEYVAL(3, 2, KEY_2),
  80. KEYVAL(3, 3, KEY_1),
  81. };
  82. static struct bfin_kpad_platform_data bf54x_kpad_data = {
  83. .rows = 4,
  84. .cols = 4,
  85. .keymap = bf548_keymap,
  86. .keymapsize = ARRAY_SIZE(bf548_keymap),
  87. .repeat = 0,
  88. .debounce_time = 5000, /* ns (5ms) */
  89. .coldrive_time = 1000, /* ns (1ms) */
  90. .keyup_test_interval = 50, /* ms (50ms) */
  91. };
  92. static struct resource bf54x_kpad_resources[] = {
  93. {
  94. .start = IRQ_KEY,
  95. .end = IRQ_KEY,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. static struct platform_device bf54x_kpad_device = {
  100. .name = "bf54x-keys",
  101. .id = -1,
  102. .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
  103. .resource = bf54x_kpad_resources,
  104. .dev = {
  105. .platform_data = &bf54x_kpad_data,
  106. },
  107. };
  108. #endif
  109. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  110. static struct platform_device rtc_device = {
  111. .name = "rtc-bfin",
  112. .id = -1,
  113. };
  114. #endif
  115. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  116. #ifdef CONFIG_SERIAL_BFIN_UART0
  117. static struct resource bfin_uart0_resources[] = {
  118. {
  119. .start = UART0_DLL,
  120. .end = UART0_RBR+2,
  121. .flags = IORESOURCE_MEM,
  122. },
  123. {
  124. .start = IRQ_UART0_RX,
  125. .end = IRQ_UART0_RX+1,
  126. .flags = IORESOURCE_IRQ,
  127. },
  128. {
  129. .start = IRQ_UART0_ERROR,
  130. .end = IRQ_UART0_ERROR,
  131. .flags = IORESOURCE_IRQ,
  132. },
  133. {
  134. .start = CH_UART0_TX,
  135. .end = CH_UART0_TX,
  136. .flags = IORESOURCE_DMA,
  137. },
  138. {
  139. .start = CH_UART0_RX,
  140. .end = CH_UART0_RX,
  141. .flags = IORESOURCE_DMA,
  142. },
  143. };
  144. unsigned short bfin_uart0_peripherals[] = {
  145. P_UART0_TX, P_UART0_RX, 0
  146. };
  147. static struct platform_device bfin_uart0_device = {
  148. .name = "bfin-uart",
  149. .id = 0,
  150. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  151. .resource = bfin_uart0_resources,
  152. .dev = {
  153. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  154. },
  155. };
  156. #endif
  157. #ifdef CONFIG_SERIAL_BFIN_UART1
  158. static struct resource bfin_uart1_resources[] = {
  159. {
  160. .start = UART1_DLL,
  161. .end = UART1_RBR+2,
  162. .flags = IORESOURCE_MEM,
  163. },
  164. {
  165. .start = IRQ_UART1_RX,
  166. .end = IRQ_UART1_RX+1,
  167. .flags = IORESOURCE_IRQ,
  168. },
  169. {
  170. .start = IRQ_UART1_ERROR,
  171. .end = IRQ_UART1_ERROR,
  172. .flags = IORESOURCE_IRQ,
  173. },
  174. {
  175. .start = CH_UART1_TX,
  176. .end = CH_UART1_TX,
  177. .flags = IORESOURCE_DMA,
  178. },
  179. {
  180. .start = CH_UART1_RX,
  181. .end = CH_UART1_RX,
  182. .flags = IORESOURCE_DMA,
  183. },
  184. #ifdef CONFIG_BFIN_UART1_CTSRTS
  185. { /* CTS pin -- 0 means not supported */
  186. .start = GPIO_PE10,
  187. .end = GPIO_PE10,
  188. .flags = IORESOURCE_IO,
  189. },
  190. { /* RTS pin -- 0 means not supported */
  191. .start = GPIO_PE9,
  192. .end = GPIO_PE9,
  193. .flags = IORESOURCE_IO,
  194. },
  195. #endif
  196. };
  197. unsigned short bfin_uart1_peripherals[] = {
  198. P_UART1_TX, P_UART1_RX,
  199. #ifdef CONFIG_BFIN_UART1_CTSRTS
  200. P_UART1_RTS, P_UART1_CTS,
  201. #endif
  202. 0
  203. };
  204. static struct platform_device bfin_uart1_device = {
  205. .name = "bfin-uart",
  206. .id = 1,
  207. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  208. .resource = bfin_uart1_resources,
  209. .dev = {
  210. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  211. },
  212. };
  213. #endif
  214. #ifdef CONFIG_SERIAL_BFIN_UART2
  215. static struct resource bfin_uart2_resources[] = {
  216. {
  217. .start = UART2_DLL,
  218. .end = UART2_RBR+2,
  219. .flags = IORESOURCE_MEM,
  220. },
  221. {
  222. .start = IRQ_UART2_RX,
  223. .end = IRQ_UART2_RX+1,
  224. .flags = IORESOURCE_IRQ,
  225. },
  226. {
  227. .start = IRQ_UART2_ERROR,
  228. .end = IRQ_UART2_ERROR,
  229. .flags = IORESOURCE_IRQ,
  230. },
  231. {
  232. .start = CH_UART2_TX,
  233. .end = CH_UART2_TX,
  234. .flags = IORESOURCE_DMA,
  235. },
  236. {
  237. .start = CH_UART2_RX,
  238. .end = CH_UART2_RX,
  239. .flags = IORESOURCE_DMA,
  240. },
  241. };
  242. unsigned short bfin_uart2_peripherals[] = {
  243. P_UART2_TX, P_UART2_RX, 0
  244. };
  245. static struct platform_device bfin_uart2_device = {
  246. .name = "bfin-uart",
  247. .id = 2,
  248. .num_resources = ARRAY_SIZE(bfin_uart2_resources),
  249. .resource = bfin_uart2_resources,
  250. .dev = {
  251. .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
  252. },
  253. };
  254. #endif
  255. #ifdef CONFIG_SERIAL_BFIN_UART3
  256. static struct resource bfin_uart3_resources[] = {
  257. {
  258. .start = UART3_DLL,
  259. .end = UART3_RBR+2,
  260. .flags = IORESOURCE_MEM,
  261. },
  262. {
  263. .start = IRQ_UART3_RX,
  264. .end = IRQ_UART3_RX+1,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. {
  268. .start = IRQ_UART3_ERROR,
  269. .end = IRQ_UART3_ERROR,
  270. .flags = IORESOURCE_IRQ,
  271. },
  272. {
  273. .start = CH_UART3_TX,
  274. .end = CH_UART3_TX,
  275. .flags = IORESOURCE_DMA,
  276. },
  277. {
  278. .start = CH_UART3_RX,
  279. .end = CH_UART3_RX,
  280. .flags = IORESOURCE_DMA,
  281. },
  282. #ifdef CONFIG_BFIN_UART3_CTSRTS
  283. { /* CTS pin -- 0 means not supported */
  284. .start = GPIO_PB3,
  285. .end = GPIO_PB3,
  286. .flags = IORESOURCE_IO,
  287. },
  288. { /* RTS pin -- 0 means not supported */
  289. .start = GPIO_PB2,
  290. .end = GPIO_PB2,
  291. .flags = IORESOURCE_IO,
  292. },
  293. #endif
  294. };
  295. unsigned short bfin_uart3_peripherals[] = {
  296. P_UART3_TX, P_UART3_RX,
  297. #ifdef CONFIG_BFIN_UART3_CTSRTS
  298. P_UART3_RTS, P_UART3_CTS,
  299. #endif
  300. 0
  301. };
  302. static struct platform_device bfin_uart3_device = {
  303. .name = "bfin-uart",
  304. .id = 3,
  305. .num_resources = ARRAY_SIZE(bfin_uart3_resources),
  306. .resource = bfin_uart3_resources,
  307. .dev = {
  308. .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
  309. },
  310. };
  311. #endif
  312. #endif
  313. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  314. #ifdef CONFIG_BFIN_SIR0
  315. static struct resource bfin_sir0_resources[] = {
  316. {
  317. .start = 0xFFC00400,
  318. .end = 0xFFC004FF,
  319. .flags = IORESOURCE_MEM,
  320. },
  321. {
  322. .start = IRQ_UART0_RX,
  323. .end = IRQ_UART0_RX+1,
  324. .flags = IORESOURCE_IRQ,
  325. },
  326. {
  327. .start = CH_UART0_RX,
  328. .end = CH_UART0_RX+1,
  329. .flags = IORESOURCE_DMA,
  330. },
  331. };
  332. static struct platform_device bfin_sir0_device = {
  333. .name = "bfin_sir",
  334. .id = 0,
  335. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  336. .resource = bfin_sir0_resources,
  337. };
  338. #endif
  339. #ifdef CONFIG_BFIN_SIR1
  340. static struct resource bfin_sir1_resources[] = {
  341. {
  342. .start = 0xFFC02000,
  343. .end = 0xFFC020FF,
  344. .flags = IORESOURCE_MEM,
  345. },
  346. {
  347. .start = IRQ_UART1_RX,
  348. .end = IRQ_UART1_RX+1,
  349. .flags = IORESOURCE_IRQ,
  350. },
  351. {
  352. .start = CH_UART1_RX,
  353. .end = CH_UART1_RX+1,
  354. .flags = IORESOURCE_DMA,
  355. },
  356. };
  357. static struct platform_device bfin_sir1_device = {
  358. .name = "bfin_sir",
  359. .id = 1,
  360. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  361. .resource = bfin_sir1_resources,
  362. };
  363. #endif
  364. #ifdef CONFIG_BFIN_SIR2
  365. static struct resource bfin_sir2_resources[] = {
  366. {
  367. .start = 0xFFC02100,
  368. .end = 0xFFC021FF,
  369. .flags = IORESOURCE_MEM,
  370. },
  371. {
  372. .start = IRQ_UART2_RX,
  373. .end = IRQ_UART2_RX+1,
  374. .flags = IORESOURCE_IRQ,
  375. },
  376. {
  377. .start = CH_UART2_RX,
  378. .end = CH_UART2_RX+1,
  379. .flags = IORESOURCE_DMA,
  380. },
  381. };
  382. static struct platform_device bfin_sir2_device = {
  383. .name = "bfin_sir",
  384. .id = 2,
  385. .num_resources = ARRAY_SIZE(bfin_sir2_resources),
  386. .resource = bfin_sir2_resources,
  387. };
  388. #endif
  389. #ifdef CONFIG_BFIN_SIR3
  390. static struct resource bfin_sir3_resources[] = {
  391. {
  392. .start = 0xFFC03100,
  393. .end = 0xFFC031FF,
  394. .flags = IORESOURCE_MEM,
  395. },
  396. {
  397. .start = IRQ_UART3_RX,
  398. .end = IRQ_UART3_RX+1,
  399. .flags = IORESOURCE_IRQ,
  400. },
  401. {
  402. .start = CH_UART3_RX,
  403. .end = CH_UART3_RX+1,
  404. .flags = IORESOURCE_DMA,
  405. },
  406. };
  407. static struct platform_device bfin_sir3_device = {
  408. .name = "bfin_sir",
  409. .id = 3,
  410. .num_resources = ARRAY_SIZE(bfin_sir3_resources),
  411. .resource = bfin_sir3_resources,
  412. };
  413. #endif
  414. #endif
  415. #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
  416. #include <linux/smsc911x.h>
  417. static struct resource smsc911x_resources[] = {
  418. {
  419. .name = "smsc911x-memory",
  420. .start = 0x24000000,
  421. .end = 0x24000000 + 0xFF,
  422. .flags = IORESOURCE_MEM,
  423. },
  424. {
  425. .start = IRQ_PE6,
  426. .end = IRQ_PE6,
  427. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
  428. },
  429. };
  430. static struct smsc911x_platform_config smsc911x_config = {
  431. .flags = SMSC911X_USE_16BIT,
  432. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  433. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  434. .phy_interface = PHY_INTERFACE_MODE_MII,
  435. };
  436. static struct platform_device smsc911x_device = {
  437. .name = "smsc911x",
  438. .id = 0,
  439. .num_resources = ARRAY_SIZE(smsc911x_resources),
  440. .resource = smsc911x_resources,
  441. .dev = {
  442. .platform_data = &smsc911x_config,
  443. },
  444. };
  445. #endif
  446. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  447. static struct resource musb_resources[] = {
  448. [0] = {
  449. .start = 0xFFC03C00,
  450. .end = 0xFFC040FF,
  451. .flags = IORESOURCE_MEM,
  452. },
  453. [1] = { /* general IRQ */
  454. .start = IRQ_USB_INT0,
  455. .end = IRQ_USB_INT0,
  456. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  457. },
  458. [2] = { /* DMA IRQ */
  459. .start = IRQ_USB_DMA,
  460. .end = IRQ_USB_DMA,
  461. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  462. },
  463. };
  464. static struct musb_hdrc_config musb_config = {
  465. .multipoint = 0,
  466. .dyn_fifo = 0,
  467. .soft_con = 1,
  468. .dma = 1,
  469. .num_eps = 8,
  470. .dma_channels = 8,
  471. .gpio_vrsel = GPIO_PH6,
  472. /* Some custom boards need to be active low, just set it to "0"
  473. * if it is the case.
  474. */
  475. .gpio_vrsel_active = 1,
  476. };
  477. static struct musb_hdrc_platform_data musb_plat = {
  478. #if defined(CONFIG_USB_MUSB_OTG)
  479. .mode = MUSB_OTG,
  480. #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
  481. .mode = MUSB_HOST,
  482. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  483. .mode = MUSB_PERIPHERAL,
  484. #endif
  485. .config = &musb_config,
  486. };
  487. static u64 musb_dmamask = ~(u32)0;
  488. static struct platform_device musb_device = {
  489. .name = "musb_hdrc",
  490. .id = 0,
  491. .dev = {
  492. .dma_mask = &musb_dmamask,
  493. .coherent_dma_mask = 0xffffffff,
  494. .platform_data = &musb_plat,
  495. },
  496. .num_resources = ARRAY_SIZE(musb_resources),
  497. .resource = musb_resources,
  498. };
  499. #endif
  500. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  501. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  502. static struct resource bfin_sport0_uart_resources[] = {
  503. {
  504. .start = SPORT0_TCR1,
  505. .end = SPORT0_MRCS3+4,
  506. .flags = IORESOURCE_MEM,
  507. },
  508. {
  509. .start = IRQ_SPORT0_RX,
  510. .end = IRQ_SPORT0_RX+1,
  511. .flags = IORESOURCE_IRQ,
  512. },
  513. {
  514. .start = IRQ_SPORT0_ERROR,
  515. .end = IRQ_SPORT0_ERROR,
  516. .flags = IORESOURCE_IRQ,
  517. },
  518. };
  519. unsigned short bfin_sport0_peripherals[] = {
  520. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  521. P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
  522. };
  523. static struct platform_device bfin_sport0_uart_device = {
  524. .name = "bfin-sport-uart",
  525. .id = 0,
  526. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  527. .resource = bfin_sport0_uart_resources,
  528. .dev = {
  529. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  530. },
  531. };
  532. #endif
  533. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  534. static struct resource bfin_sport1_uart_resources[] = {
  535. {
  536. .start = SPORT1_TCR1,
  537. .end = SPORT1_MRCS3+4,
  538. .flags = IORESOURCE_MEM,
  539. },
  540. {
  541. .start = IRQ_SPORT1_RX,
  542. .end = IRQ_SPORT1_RX+1,
  543. .flags = IORESOURCE_IRQ,
  544. },
  545. {
  546. .start = IRQ_SPORT1_ERROR,
  547. .end = IRQ_SPORT1_ERROR,
  548. .flags = IORESOURCE_IRQ,
  549. },
  550. };
  551. unsigned short bfin_sport1_peripherals[] = {
  552. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  553. P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
  554. };
  555. static struct platform_device bfin_sport1_uart_device = {
  556. .name = "bfin-sport-uart",
  557. .id = 1,
  558. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  559. .resource = bfin_sport1_uart_resources,
  560. .dev = {
  561. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  562. },
  563. };
  564. #endif
  565. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  566. static struct resource bfin_sport2_uart_resources[] = {
  567. {
  568. .start = SPORT2_TCR1,
  569. .end = SPORT2_MRCS3+4,
  570. .flags = IORESOURCE_MEM,
  571. },
  572. {
  573. .start = IRQ_SPORT2_RX,
  574. .end = IRQ_SPORT2_RX+1,
  575. .flags = IORESOURCE_IRQ,
  576. },
  577. {
  578. .start = IRQ_SPORT2_ERROR,
  579. .end = IRQ_SPORT2_ERROR,
  580. .flags = IORESOURCE_IRQ,
  581. },
  582. };
  583. unsigned short bfin_sport2_peripherals[] = {
  584. P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
  585. P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
  586. };
  587. static struct platform_device bfin_sport2_uart_device = {
  588. .name = "bfin-sport-uart",
  589. .id = 2,
  590. .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
  591. .resource = bfin_sport2_uart_resources,
  592. .dev = {
  593. .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
  594. },
  595. };
  596. #endif
  597. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  598. static struct resource bfin_sport3_uart_resources[] = {
  599. {
  600. .start = SPORT3_TCR1,
  601. .end = SPORT3_MRCS3+4,
  602. .flags = IORESOURCE_MEM,
  603. },
  604. {
  605. .start = IRQ_SPORT3_RX,
  606. .end = IRQ_SPORT3_RX+1,
  607. .flags = IORESOURCE_IRQ,
  608. },
  609. {
  610. .start = IRQ_SPORT3_ERROR,
  611. .end = IRQ_SPORT3_ERROR,
  612. .flags = IORESOURCE_IRQ,
  613. },
  614. };
  615. unsigned short bfin_sport3_peripherals[] = {
  616. P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
  617. P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
  618. };
  619. static struct platform_device bfin_sport3_uart_device = {
  620. .name = "bfin-sport-uart",
  621. .id = 3,
  622. .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
  623. .resource = bfin_sport3_uart_resources,
  624. .dev = {
  625. .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
  626. },
  627. };
  628. #endif
  629. #endif
  630. #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
  631. static struct resource bfin_atapi_resources[] = {
  632. {
  633. .start = 0xFFC03800,
  634. .end = 0xFFC0386F,
  635. .flags = IORESOURCE_MEM,
  636. },
  637. {
  638. .start = IRQ_ATAPI_ERR,
  639. .end = IRQ_ATAPI_ERR,
  640. .flags = IORESOURCE_IRQ,
  641. },
  642. };
  643. static struct platform_device bfin_atapi_device = {
  644. .name = "pata-bf54x",
  645. .id = -1,
  646. .num_resources = ARRAY_SIZE(bfin_atapi_resources),
  647. .resource = bfin_atapi_resources,
  648. };
  649. #endif
  650. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  651. static struct mtd_partition partition_info[] = {
  652. {
  653. .name = "linux kernel(nand)",
  654. .offset = 0,
  655. .size = 4 * 1024 * 1024,
  656. },
  657. {
  658. .name = "file system(nand)",
  659. .offset = 4 * 1024 * 1024,
  660. .size = (256 - 4) * 1024 * 1024,
  661. },
  662. };
  663. static struct bf5xx_nand_platform bf5xx_nand_platform = {
  664. .page_size = NFC_PG_SIZE_256,
  665. .data_width = NFC_NWIDTH_8,
  666. .partitions = partition_info,
  667. .nr_partitions = ARRAY_SIZE(partition_info),
  668. .rd_dly = 3,
  669. .wr_dly = 3,
  670. };
  671. static struct resource bf5xx_nand_resources[] = {
  672. {
  673. .start = 0xFFC03B00,
  674. .end = 0xFFC03B4F,
  675. .flags = IORESOURCE_MEM,
  676. },
  677. {
  678. .start = CH_NFC,
  679. .end = CH_NFC,
  680. .flags = IORESOURCE_IRQ,
  681. },
  682. };
  683. static struct platform_device bf5xx_nand_device = {
  684. .name = "bf5xx-nand",
  685. .id = 0,
  686. .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
  687. .resource = bf5xx_nand_resources,
  688. .dev = {
  689. .platform_data = &bf5xx_nand_platform,
  690. },
  691. };
  692. #endif
  693. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  694. static struct bfin_sd_host bfin_sdh_data = {
  695. .dma_chan = CH_SDH,
  696. .irq_int0 = IRQ_SDH_MASK0,
  697. .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
  698. };
  699. static struct platform_device bf54x_sdh_device = {
  700. .name = "bfin-sdh",
  701. .id = 0,
  702. .dev = {
  703. .platform_data = &bfin_sdh_data,
  704. },
  705. };
  706. #endif
  707. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  708. static struct mtd_partition para_partitions[] = {
  709. {
  710. .name = "bootloader(nor)",
  711. .size = 0x40000,
  712. .offset = 0,
  713. }, {
  714. .name = "linux kernel(nor)",
  715. .size = 0x100000,
  716. .offset = MTDPART_OFS_APPEND,
  717. }, {
  718. .name = "file system(nor)",
  719. .size = MTDPART_SIZ_FULL,
  720. .offset = MTDPART_OFS_APPEND,
  721. }
  722. };
  723. static struct physmap_flash_data para_flash_data = {
  724. .width = 2,
  725. .parts = para_partitions,
  726. .nr_parts = ARRAY_SIZE(para_partitions),
  727. };
  728. static struct resource para_flash_resource = {
  729. .start = 0x20000000,
  730. .end = 0x207fffff,
  731. .flags = IORESOURCE_MEM,
  732. };
  733. static struct platform_device para_flash_device = {
  734. .name = "physmap-flash",
  735. .id = 0,
  736. .dev = {
  737. .platform_data = &para_flash_data,
  738. },
  739. .num_resources = 1,
  740. .resource = &para_flash_resource,
  741. };
  742. #endif
  743. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  744. /* all SPI peripherals info goes here */
  745. #if defined(CONFIG_MTD_M25P80) \
  746. || defined(CONFIG_MTD_M25P80_MODULE)
  747. /* SPI flash chip (m25p16) */
  748. static struct mtd_partition bfin_spi_flash_partitions[] = {
  749. {
  750. .name = "bootloader(spi)",
  751. .size = 0x00040000,
  752. .offset = 0,
  753. .mask_flags = MTD_CAP_ROM
  754. }, {
  755. .name = "linux kernel(spi)",
  756. .size = 0x1c0000,
  757. .offset = 0x40000
  758. }
  759. };
  760. static struct flash_platform_data bfin_spi_flash_data = {
  761. .name = "m25p80",
  762. .parts = bfin_spi_flash_partitions,
  763. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  764. .type = "m25p16",
  765. };
  766. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  767. .enable_dma = 0, /* use dma transfer with this chip*/
  768. .bits_per_word = 8,
  769. };
  770. #endif
  771. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  772. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  773. .enable_dma = 0,
  774. .bits_per_word = 16,
  775. };
  776. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  777. .model = 7877,
  778. .vref_delay_usecs = 50, /* internal, no capacitor */
  779. .x_plate_ohms = 419,
  780. .y_plate_ohms = 486,
  781. .pressure_max = 1000,
  782. .pressure_min = 0,
  783. .stopacq_polarity = 1,
  784. .first_conversion_delay = 3,
  785. .acquisition_time = 1,
  786. .averaging = 1,
  787. .pen_down_acc_interval = 1,
  788. };
  789. #endif
  790. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  791. static struct bfin5xx_spi_chip spidev_chip_info = {
  792. .enable_dma = 0,
  793. .bits_per_word = 8,
  794. };
  795. #endif
  796. static struct spi_board_info bf54x_spi_board_info[] __initdata = {
  797. #if defined(CONFIG_MTD_M25P80) \
  798. || defined(CONFIG_MTD_M25P80_MODULE)
  799. {
  800. /* the modalias must be the same as spi device driver name */
  801. .modalias = "m25p80", /* Name of spi_driver for this device */
  802. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  803. .bus_num = 0, /* Framework bus number */
  804. .chip_select = 1, /* SPI_SSEL1*/
  805. .platform_data = &bfin_spi_flash_data,
  806. .controller_data = &spi_flash_chip_info,
  807. .mode = SPI_MODE_3,
  808. },
  809. #endif
  810. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  811. {
  812. .modalias = "ad7877",
  813. .platform_data = &bfin_ad7877_ts_info,
  814. .irq = IRQ_PJ11,
  815. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  816. .bus_num = 0,
  817. .chip_select = 2,
  818. .controller_data = &spi_ad7877_chip_info,
  819. },
  820. #endif
  821. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  822. {
  823. .modalias = "spidev",
  824. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  825. .bus_num = 0,
  826. .chip_select = 1,
  827. .controller_data = &spidev_chip_info,
  828. },
  829. #endif
  830. };
  831. /* SPI (0) */
  832. static struct resource bfin_spi0_resource[] = {
  833. [0] = {
  834. .start = SPI0_REGBASE,
  835. .end = SPI0_REGBASE + 0xFF,
  836. .flags = IORESOURCE_MEM,
  837. },
  838. [1] = {
  839. .start = CH_SPI0,
  840. .end = CH_SPI0,
  841. .flags = IORESOURCE_DMA,
  842. },
  843. [2] = {
  844. .start = IRQ_SPI0,
  845. .end = IRQ_SPI0,
  846. .flags = IORESOURCE_IRQ,
  847. }
  848. };
  849. /* SPI (1) */
  850. static struct resource bfin_spi1_resource[] = {
  851. [0] = {
  852. .start = SPI1_REGBASE,
  853. .end = SPI1_REGBASE + 0xFF,
  854. .flags = IORESOURCE_MEM,
  855. },
  856. [1] = {
  857. .start = CH_SPI1,
  858. .end = CH_SPI1,
  859. .flags = IORESOURCE_DMA,
  860. },
  861. [2] = {
  862. .start = IRQ_SPI1,
  863. .end = IRQ_SPI1,
  864. .flags = IORESOURCE_IRQ,
  865. }
  866. };
  867. /* SPI controller data */
  868. static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
  869. .num_chipselect = 3,
  870. .enable_dma = 1, /* master has the ability to do dma transfer */
  871. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  872. };
  873. static struct platform_device bf54x_spi_master0 = {
  874. .name = "bfin-spi",
  875. .id = 0, /* Bus number */
  876. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  877. .resource = bfin_spi0_resource,
  878. .dev = {
  879. .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
  880. },
  881. };
  882. static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
  883. .num_chipselect = 3,
  884. .enable_dma = 1, /* master has the ability to do dma transfer */
  885. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  886. };
  887. static struct platform_device bf54x_spi_master1 = {
  888. .name = "bfin-spi",
  889. .id = 1, /* Bus number */
  890. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  891. .resource = bfin_spi1_resource,
  892. .dev = {
  893. .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
  894. },
  895. };
  896. #endif /* spi master and devices */
  897. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  898. static struct resource bfin_twi0_resource[] = {
  899. [0] = {
  900. .start = TWI0_REGBASE,
  901. .end = TWI0_REGBASE + 0xFF,
  902. .flags = IORESOURCE_MEM,
  903. },
  904. [1] = {
  905. .start = IRQ_TWI0,
  906. .end = IRQ_TWI0,
  907. .flags = IORESOURCE_IRQ,
  908. },
  909. };
  910. static struct platform_device i2c_bfin_twi0_device = {
  911. .name = "i2c-bfin-twi",
  912. .id = 0,
  913. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  914. .resource = bfin_twi0_resource,
  915. };
  916. #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
  917. static struct resource bfin_twi1_resource[] = {
  918. [0] = {
  919. .start = TWI1_REGBASE,
  920. .end = TWI1_REGBASE + 0xFF,
  921. .flags = IORESOURCE_MEM,
  922. },
  923. [1] = {
  924. .start = IRQ_TWI1,
  925. .end = IRQ_TWI1,
  926. .flags = IORESOURCE_IRQ,
  927. },
  928. };
  929. static struct platform_device i2c_bfin_twi1_device = {
  930. .name = "i2c-bfin-twi",
  931. .id = 1,
  932. .num_resources = ARRAY_SIZE(bfin_twi1_resource),
  933. .resource = bfin_twi1_resource,
  934. };
  935. #endif
  936. #endif
  937. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  938. #include <linux/gpio_keys.h>
  939. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  940. {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
  941. };
  942. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  943. .buttons = bfin_gpio_keys_table,
  944. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  945. };
  946. static struct platform_device bfin_device_gpiokeys = {
  947. .name = "gpio-keys",
  948. .dev = {
  949. .platform_data = &bfin_gpio_keys_data,
  950. },
  951. };
  952. #endif
  953. static const unsigned int cclk_vlev_datasheet[] =
  954. {
  955. /*
  956. * Internal VLEV BF54XSBBC1533
  957. ****temporarily using these values until data sheet is updated
  958. */
  959. VRPAIR(VLEV_085, 150000000),
  960. VRPAIR(VLEV_090, 250000000),
  961. VRPAIR(VLEV_110, 276000000),
  962. VRPAIR(VLEV_115, 301000000),
  963. VRPAIR(VLEV_120, 525000000),
  964. VRPAIR(VLEV_125, 550000000),
  965. VRPAIR(VLEV_130, 600000000),
  966. };
  967. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  968. .tuple_tab = cclk_vlev_datasheet,
  969. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  970. .vr_settling_time = 25 /* us */,
  971. };
  972. static struct platform_device bfin_dpmc = {
  973. .name = "bfin dpmc",
  974. .dev = {
  975. .platform_data = &bfin_dmpc_vreg_data,
  976. },
  977. };
  978. static struct platform_device *cm_bf548_devices[] __initdata = {
  979. &bfin_dpmc,
  980. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  981. &rtc_device,
  982. #endif
  983. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  984. #ifdef CONFIG_SERIAL_BFIN_UART0
  985. &bfin_uart0_device,
  986. #endif
  987. #ifdef CONFIG_SERIAL_BFIN_UART1
  988. &bfin_uart1_device,
  989. #endif
  990. #ifdef CONFIG_SERIAL_BFIN_UART2
  991. &bfin_uart2_device,
  992. #endif
  993. #ifdef CONFIG_SERIAL_BFIN_UART3
  994. &bfin_uart3_device,
  995. #endif
  996. #endif
  997. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  998. #ifdef CONFIG_BFIN_SIR0
  999. &bfin_sir0_device,
  1000. #endif
  1001. #ifdef CONFIG_BFIN_SIR1
  1002. &bfin_sir1_device,
  1003. #endif
  1004. #ifdef CONFIG_BFIN_SIR2
  1005. &bfin_sir2_device,
  1006. #endif
  1007. #ifdef CONFIG_BFIN_SIR3
  1008. &bfin_sir3_device,
  1009. #endif
  1010. #endif
  1011. #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
  1012. &bf54x_lq043_device,
  1013. #endif
  1014. #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
  1015. &smsc911x_device,
  1016. #endif
  1017. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  1018. &musb_device,
  1019. #endif
  1020. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  1021. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  1022. &bfin_sport0_uart_device,
  1023. #endif
  1024. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  1025. &bfin_sport1_uart_device,
  1026. #endif
  1027. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  1028. &bfin_sport2_uart_device,
  1029. #endif
  1030. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  1031. &bfin_sport3_uart_device,
  1032. #endif
  1033. #endif
  1034. #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
  1035. &bfin_atapi_device,
  1036. #endif
  1037. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  1038. &bf5xx_nand_device,
  1039. #endif
  1040. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  1041. &bf54x_sdh_device,
  1042. #endif
  1043. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  1044. &bf54x_spi_master0,
  1045. &bf54x_spi_master1,
  1046. #endif
  1047. #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
  1048. &bf54x_kpad_device,
  1049. #endif
  1050. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  1051. &i2c_bfin_twi0_device,
  1052. #if !defined(CONFIG_BF542)
  1053. &i2c_bfin_twi1_device,
  1054. #endif
  1055. #endif
  1056. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  1057. &bfin_device_gpiokeys,
  1058. #endif
  1059. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  1060. &para_flash_device,
  1061. #endif
  1062. };
  1063. static int __init cm_bf548_init(void)
  1064. {
  1065. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  1066. platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
  1067. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  1068. spi_register_board_info(bf54x_spi_board_info,
  1069. ARRAY_SIZE(bf54x_spi_board_info));
  1070. #endif
  1071. return 0;
  1072. }
  1073. arch_initcall(cm_bf548_init);
  1074. static struct platform_device *cm_bf548_early_devices[] __initdata = {
  1075. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  1076. #ifdef CONFIG_SERIAL_BFIN_UART0
  1077. &bfin_uart0_device,
  1078. #endif
  1079. #ifdef CONFIG_SERIAL_BFIN_UART1
  1080. &bfin_uart1_device,
  1081. #endif
  1082. #ifdef CONFIG_SERIAL_BFIN_UART2
  1083. &bfin_uart2_device,
  1084. #endif
  1085. #ifdef CONFIG_SERIAL_BFIN_UART3
  1086. &bfin_uart3_device,
  1087. #endif
  1088. #endif
  1089. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  1090. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  1091. &bfin_sport0_uart_device,
  1092. #endif
  1093. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  1094. &bfin_sport1_uart_device,
  1095. #endif
  1096. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  1097. &bfin_sport2_uart_device,
  1098. #endif
  1099. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  1100. &bfin_sport3_uart_device,
  1101. #endif
  1102. #endif
  1103. };
  1104. void __init native_machine_early_platform_add_devices(void)
  1105. {
  1106. printk(KERN_INFO "register early platform devices\n");
  1107. early_platform_add_devices(cm_bf548_early_devices,
  1108. ARRAY_SIZE(cm_bf548_early_devices));
  1109. }