main.c 62 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. spin_unlock(&common->cc_lock);
  92. }
  93. unlock:
  94. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  95. }
  96. void ath9k_ps_restore(struct ath_softc *sc)
  97. {
  98. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  99. enum ath9k_power_mode mode;
  100. unsigned long flags;
  101. bool reset;
  102. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  103. if (--sc->ps_usecount != 0)
  104. goto unlock;
  105. if (sc->ps_idle) {
  106. ath9k_hw_setrxabort(sc->sc_ah, 1);
  107. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  108. mode = ATH9K_PM_FULL_SLEEP;
  109. } else if (sc->ps_enabled &&
  110. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  111. PS_WAIT_FOR_CAB |
  112. PS_WAIT_FOR_PSPOLL_DATA |
  113. PS_WAIT_FOR_TX_ACK))) {
  114. mode = ATH9K_PM_NETWORK_SLEEP;
  115. } else {
  116. goto unlock;
  117. }
  118. spin_lock(&common->cc_lock);
  119. ath_hw_cycle_counters_update(common);
  120. spin_unlock(&common->cc_lock);
  121. ath9k_hw_setpower(sc->sc_ah, mode);
  122. unlock:
  123. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  124. }
  125. void ath_start_ani(struct ath_common *common)
  126. {
  127. struct ath_hw *ah = common->ah;
  128. unsigned long timestamp = jiffies_to_msecs(jiffies);
  129. struct ath_softc *sc = (struct ath_softc *) common->priv;
  130. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  131. return;
  132. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  133. return;
  134. common->ani.longcal_timer = timestamp;
  135. common->ani.shortcal_timer = timestamp;
  136. common->ani.checkani_timer = timestamp;
  137. mod_timer(&common->ani.timer,
  138. jiffies +
  139. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  140. }
  141. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  142. {
  143. struct ath_hw *ah = sc->sc_ah;
  144. struct ath9k_channel *chan = &ah->channels[channel];
  145. struct survey_info *survey = &sc->survey[channel];
  146. if (chan->noisefloor) {
  147. survey->filled |= SURVEY_INFO_NOISE_DBM;
  148. survey->noise = ath9k_hw_getchan_noise(ah, chan);
  149. }
  150. }
  151. /*
  152. * Updates the survey statistics and returns the busy time since last
  153. * update in %, if the measurement duration was long enough for the
  154. * result to be useful, -1 otherwise.
  155. */
  156. static int ath_update_survey_stats(struct ath_softc *sc)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. struct ath_common *common = ath9k_hw_common(ah);
  160. int pos = ah->curchan - &ah->channels[0];
  161. struct survey_info *survey = &sc->survey[pos];
  162. struct ath_cycle_counters *cc = &common->cc_survey;
  163. unsigned int div = common->clockrate * 1000;
  164. int ret = 0;
  165. if (!ah->curchan)
  166. return -1;
  167. if (ah->power_mode == ATH9K_PM_AWAKE)
  168. ath_hw_cycle_counters_update(common);
  169. if (cc->cycles > 0) {
  170. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  171. SURVEY_INFO_CHANNEL_TIME_BUSY |
  172. SURVEY_INFO_CHANNEL_TIME_RX |
  173. SURVEY_INFO_CHANNEL_TIME_TX;
  174. survey->channel_time += cc->cycles / div;
  175. survey->channel_time_busy += cc->rx_busy / div;
  176. survey->channel_time_rx += cc->rx_frame / div;
  177. survey->channel_time_tx += cc->tx_frame / div;
  178. }
  179. if (cc->cycles < div)
  180. return -1;
  181. if (cc->cycles > 0)
  182. ret = cc->rx_busy * 100 / cc->cycles;
  183. memset(cc, 0, sizeof(*cc));
  184. ath_update_survey_nf(sc, pos);
  185. return ret;
  186. }
  187. static void __ath_cancel_work(struct ath_softc *sc)
  188. {
  189. cancel_work_sync(&sc->paprd_work);
  190. cancel_work_sync(&sc->hw_check_work);
  191. cancel_delayed_work_sync(&sc->tx_complete_work);
  192. cancel_delayed_work_sync(&sc->hw_pll_work);
  193. }
  194. static void ath_cancel_work(struct ath_softc *sc)
  195. {
  196. __ath_cancel_work(sc);
  197. cancel_work_sync(&sc->hw_reset_work);
  198. }
  199. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  200. {
  201. struct ath_hw *ah = sc->sc_ah;
  202. struct ath_common *common = ath9k_hw_common(ah);
  203. bool ret = true;
  204. ieee80211_stop_queues(sc->hw);
  205. sc->hw_busy_count = 0;
  206. del_timer_sync(&common->ani.timer);
  207. del_timer_sync(&sc->rx_poll_timer);
  208. ath9k_debug_samp_bb_mac(sc);
  209. ath9k_hw_disable_interrupts(ah);
  210. if (!ath_stoprecv(sc))
  211. ret = false;
  212. if (!ath_drain_all_txq(sc, retry_tx))
  213. ret = false;
  214. if (!flush) {
  215. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  216. ath_rx_tasklet(sc, 1, true);
  217. ath_rx_tasklet(sc, 1, false);
  218. } else {
  219. ath_flushrecv(sc);
  220. }
  221. return ret;
  222. }
  223. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  224. {
  225. struct ath_hw *ah = sc->sc_ah;
  226. struct ath_common *common = ath9k_hw_common(ah);
  227. if (ath_startrecv(sc) != 0) {
  228. ath_err(common, "Unable to restart recv logic\n");
  229. return false;
  230. }
  231. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  232. sc->config.txpowlimit, &sc->curtxpow);
  233. ath9k_hw_set_interrupts(ah);
  234. ath9k_hw_enable_interrupts(ah);
  235. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
  236. if (sc->sc_flags & SC_OP_BEACONS)
  237. ath_set_beacon(sc);
  238. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  239. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  240. ath_start_rx_poll(sc, 3);
  241. if (!common->disable_ani)
  242. ath_start_ani(common);
  243. }
  244. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
  245. struct ath_hw_antcomb_conf div_ant_conf;
  246. u8 lna_conf;
  247. ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
  248. if (sc->ant_rx == 1)
  249. lna_conf = ATH_ANT_DIV_COMB_LNA1;
  250. else
  251. lna_conf = ATH_ANT_DIV_COMB_LNA2;
  252. div_ant_conf.main_lna_conf = lna_conf;
  253. div_ant_conf.alt_lna_conf = lna_conf;
  254. ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
  255. }
  256. ieee80211_wake_queues(sc->hw);
  257. return true;
  258. }
  259. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  260. bool retry_tx)
  261. {
  262. struct ath_hw *ah = sc->sc_ah;
  263. struct ath_common *common = ath9k_hw_common(ah);
  264. struct ath9k_hw_cal_data *caldata = NULL;
  265. bool fastcc = true;
  266. bool flush = false;
  267. int r;
  268. __ath_cancel_work(sc);
  269. spin_lock_bh(&sc->sc_pcu_lock);
  270. if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
  271. fastcc = false;
  272. caldata = &sc->caldata;
  273. }
  274. if (!hchan) {
  275. fastcc = false;
  276. flush = true;
  277. hchan = ah->curchan;
  278. }
  279. if (!ath_prepare_reset(sc, retry_tx, flush))
  280. fastcc = false;
  281. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  282. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  283. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  284. if (r) {
  285. ath_err(common,
  286. "Unable to reset channel, reset status %d\n", r);
  287. goto out;
  288. }
  289. if (!ath_complete_reset(sc, true))
  290. r = -EIO;
  291. out:
  292. spin_unlock_bh(&sc->sc_pcu_lock);
  293. return r;
  294. }
  295. /*
  296. * Set/change channels. If the channel is really being changed, it's done
  297. * by reseting the chip. To accomplish this we must first cleanup any pending
  298. * DMA, then restart stuff.
  299. */
  300. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  301. struct ath9k_channel *hchan)
  302. {
  303. int r;
  304. if (sc->sc_flags & SC_OP_INVALID)
  305. return -EIO;
  306. r = ath_reset_internal(sc, hchan, false);
  307. return r;
  308. }
  309. static void ath_paprd_activate(struct ath_softc *sc)
  310. {
  311. struct ath_hw *ah = sc->sc_ah;
  312. struct ath9k_hw_cal_data *caldata = ah->caldata;
  313. int chain;
  314. if (!caldata || !caldata->paprd_done)
  315. return;
  316. ath9k_ps_wakeup(sc);
  317. ar9003_paprd_enable(ah, false);
  318. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  319. if (!(ah->txchainmask & BIT(chain)))
  320. continue;
  321. ar9003_paprd_populate_single_table(ah, caldata, chain);
  322. }
  323. ar9003_paprd_enable(ah, true);
  324. ath9k_ps_restore(sc);
  325. }
  326. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  327. {
  328. struct ieee80211_hw *hw = sc->hw;
  329. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  330. struct ath_hw *ah = sc->sc_ah;
  331. struct ath_common *common = ath9k_hw_common(ah);
  332. struct ath_tx_control txctl;
  333. int time_left;
  334. memset(&txctl, 0, sizeof(txctl));
  335. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  336. memset(tx_info, 0, sizeof(*tx_info));
  337. tx_info->band = hw->conf.channel->band;
  338. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  339. tx_info->control.rates[0].idx = 0;
  340. tx_info->control.rates[0].count = 1;
  341. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  342. tx_info->control.rates[1].idx = -1;
  343. init_completion(&sc->paprd_complete);
  344. txctl.paprd = BIT(chain);
  345. if (ath_tx_start(hw, skb, &txctl) != 0) {
  346. ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
  347. dev_kfree_skb_any(skb);
  348. return false;
  349. }
  350. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  351. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  352. if (!time_left)
  353. ath_dbg(common, CALIBRATE,
  354. "Timeout waiting for paprd training on TX chain %d\n",
  355. chain);
  356. return !!time_left;
  357. }
  358. void ath_paprd_calibrate(struct work_struct *work)
  359. {
  360. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  361. struct ieee80211_hw *hw = sc->hw;
  362. struct ath_hw *ah = sc->sc_ah;
  363. struct ieee80211_hdr *hdr;
  364. struct sk_buff *skb = NULL;
  365. struct ath9k_hw_cal_data *caldata = ah->caldata;
  366. struct ath_common *common = ath9k_hw_common(ah);
  367. int ftype;
  368. int chain_ok = 0;
  369. int chain;
  370. int len = 1800;
  371. if (!caldata)
  372. return;
  373. ath9k_ps_wakeup(sc);
  374. if (ar9003_paprd_init_table(ah) < 0)
  375. goto fail_paprd;
  376. skb = alloc_skb(len, GFP_KERNEL);
  377. if (!skb)
  378. goto fail_paprd;
  379. skb_put(skb, len);
  380. memset(skb->data, 0, len);
  381. hdr = (struct ieee80211_hdr *)skb->data;
  382. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  383. hdr->frame_control = cpu_to_le16(ftype);
  384. hdr->duration_id = cpu_to_le16(10);
  385. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  386. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  387. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  388. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  389. if (!(ah->txchainmask & BIT(chain)))
  390. continue;
  391. chain_ok = 0;
  392. ath_dbg(common, CALIBRATE,
  393. "Sending PAPRD frame for thermal measurement on chain %d\n",
  394. chain);
  395. if (!ath_paprd_send_frame(sc, skb, chain))
  396. goto fail_paprd;
  397. ar9003_paprd_setup_gain_table(ah, chain);
  398. ath_dbg(common, CALIBRATE,
  399. "Sending PAPRD training frame on chain %d\n", chain);
  400. if (!ath_paprd_send_frame(sc, skb, chain))
  401. goto fail_paprd;
  402. if (!ar9003_paprd_is_done(ah)) {
  403. ath_dbg(common, CALIBRATE,
  404. "PAPRD not yet done on chain %d\n", chain);
  405. break;
  406. }
  407. if (ar9003_paprd_create_curve(ah, caldata, chain)) {
  408. ath_dbg(common, CALIBRATE,
  409. "PAPRD create curve failed on chain %d\n",
  410. chain);
  411. break;
  412. }
  413. chain_ok = 1;
  414. }
  415. kfree_skb(skb);
  416. if (chain_ok) {
  417. caldata->paprd_done = true;
  418. ath_paprd_activate(sc);
  419. }
  420. fail_paprd:
  421. ath9k_ps_restore(sc);
  422. }
  423. /*
  424. * This routine performs the periodic noise floor calibration function
  425. * that is used to adjust and optimize the chip performance. This
  426. * takes environmental changes (location, temperature) into account.
  427. * When the task is complete, it reschedules itself depending on the
  428. * appropriate interval that was calculated.
  429. */
  430. void ath_ani_calibrate(unsigned long data)
  431. {
  432. struct ath_softc *sc = (struct ath_softc *)data;
  433. struct ath_hw *ah = sc->sc_ah;
  434. struct ath_common *common = ath9k_hw_common(ah);
  435. bool longcal = false;
  436. bool shortcal = false;
  437. bool aniflag = false;
  438. unsigned int timestamp = jiffies_to_msecs(jiffies);
  439. u32 cal_interval, short_cal_interval, long_cal_interval;
  440. unsigned long flags;
  441. if (ah->caldata && ah->caldata->nfcal_interference)
  442. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  443. else
  444. long_cal_interval = ATH_LONG_CALINTERVAL;
  445. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  446. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  447. /* Only calibrate if awake */
  448. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  449. goto set_timer;
  450. ath9k_ps_wakeup(sc);
  451. /* Long calibration runs independently of short calibration. */
  452. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  453. longcal = true;
  454. common->ani.longcal_timer = timestamp;
  455. }
  456. /* Short calibration applies only while caldone is false */
  457. if (!common->ani.caldone) {
  458. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  459. shortcal = true;
  460. common->ani.shortcal_timer = timestamp;
  461. common->ani.resetcal_timer = timestamp;
  462. }
  463. } else {
  464. if ((timestamp - common->ani.resetcal_timer) >=
  465. ATH_RESTART_CALINTERVAL) {
  466. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  467. if (common->ani.caldone)
  468. common->ani.resetcal_timer = timestamp;
  469. }
  470. }
  471. /* Verify whether we must check ANI */
  472. if (sc->sc_ah->config.enable_ani
  473. && (timestamp - common->ani.checkani_timer) >=
  474. ah->config.ani_poll_interval) {
  475. aniflag = true;
  476. common->ani.checkani_timer = timestamp;
  477. }
  478. /* Call ANI routine if necessary */
  479. if (aniflag) {
  480. spin_lock_irqsave(&common->cc_lock, flags);
  481. ath9k_hw_ani_monitor(ah, ah->curchan);
  482. ath_update_survey_stats(sc);
  483. spin_unlock_irqrestore(&common->cc_lock, flags);
  484. }
  485. /* Perform calibration if necessary */
  486. if (longcal || shortcal) {
  487. common->ani.caldone =
  488. ath9k_hw_calibrate(ah, ah->curchan,
  489. ah->rxchainmask, longcal);
  490. }
  491. ath_dbg(common, ANI,
  492. "Calibration @%lu finished: %s %s %s, caldone: %s\n",
  493. jiffies,
  494. longcal ? "long" : "", shortcal ? "short" : "",
  495. aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
  496. ath9k_ps_restore(sc);
  497. set_timer:
  498. /*
  499. * Set timer interval based on previous results.
  500. * The interval must be the shortest necessary to satisfy ANI,
  501. * short calibration and long calibration.
  502. */
  503. ath9k_debug_samp_bb_mac(sc);
  504. cal_interval = ATH_LONG_CALINTERVAL;
  505. if (sc->sc_ah->config.enable_ani)
  506. cal_interval = min(cal_interval,
  507. (u32)ah->config.ani_poll_interval);
  508. if (!common->ani.caldone)
  509. cal_interval = min(cal_interval, (u32)short_cal_interval);
  510. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  511. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  512. if (!ah->caldata->paprd_done)
  513. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  514. else if (!ah->paprd_table_write_done)
  515. ath_paprd_activate(sc);
  516. }
  517. }
  518. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  519. struct ieee80211_vif *vif)
  520. {
  521. struct ath_node *an;
  522. an = (struct ath_node *)sta->drv_priv;
  523. #ifdef CONFIG_ATH9K_DEBUGFS
  524. spin_lock(&sc->nodes_lock);
  525. list_add(&an->list, &sc->nodes);
  526. spin_unlock(&sc->nodes_lock);
  527. #endif
  528. an->sta = sta;
  529. an->vif = vif;
  530. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  531. ath_tx_node_init(sc, an);
  532. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  533. sta->ht_cap.ampdu_factor);
  534. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  535. }
  536. }
  537. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  538. {
  539. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  540. #ifdef CONFIG_ATH9K_DEBUGFS
  541. spin_lock(&sc->nodes_lock);
  542. list_del(&an->list);
  543. spin_unlock(&sc->nodes_lock);
  544. an->sta = NULL;
  545. #endif
  546. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  547. ath_tx_node_cleanup(sc, an);
  548. }
  549. void ath9k_tasklet(unsigned long data)
  550. {
  551. struct ath_softc *sc = (struct ath_softc *)data;
  552. struct ath_hw *ah = sc->sc_ah;
  553. struct ath_common *common = ath9k_hw_common(ah);
  554. u32 status = sc->intrstatus;
  555. u32 rxmask;
  556. ath9k_ps_wakeup(sc);
  557. spin_lock(&sc->sc_pcu_lock);
  558. if ((status & ATH9K_INT_FATAL) ||
  559. (status & ATH9K_INT_BB_WATCHDOG)) {
  560. #ifdef CONFIG_ATH9K_DEBUGFS
  561. enum ath_reset_type type;
  562. if (status & ATH9K_INT_FATAL)
  563. type = RESET_TYPE_FATAL_INT;
  564. else
  565. type = RESET_TYPE_BB_WATCHDOG;
  566. RESET_STAT_INC(sc, type);
  567. #endif
  568. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  569. goto out;
  570. }
  571. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  572. /*
  573. * TSF sync does not look correct; remain awake to sync with
  574. * the next Beacon.
  575. */
  576. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  577. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  578. }
  579. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  580. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  581. ATH9K_INT_RXORN);
  582. else
  583. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  584. if (status & rxmask) {
  585. /* Check for high priority Rx first */
  586. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  587. (status & ATH9K_INT_RXHP))
  588. ath_rx_tasklet(sc, 0, true);
  589. ath_rx_tasklet(sc, 0, false);
  590. }
  591. if (status & ATH9K_INT_TX) {
  592. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  593. ath_tx_edma_tasklet(sc);
  594. else
  595. ath_tx_tasklet(sc);
  596. }
  597. ath9k_btcoex_handle_interrupt(sc, status);
  598. out:
  599. /* re-enable hardware interrupt */
  600. ath9k_hw_enable_interrupts(ah);
  601. spin_unlock(&sc->sc_pcu_lock);
  602. ath9k_ps_restore(sc);
  603. }
  604. irqreturn_t ath_isr(int irq, void *dev)
  605. {
  606. #define SCHED_INTR ( \
  607. ATH9K_INT_FATAL | \
  608. ATH9K_INT_BB_WATCHDOG | \
  609. ATH9K_INT_RXORN | \
  610. ATH9K_INT_RXEOL | \
  611. ATH9K_INT_RX | \
  612. ATH9K_INT_RXLP | \
  613. ATH9K_INT_RXHP | \
  614. ATH9K_INT_TX | \
  615. ATH9K_INT_BMISS | \
  616. ATH9K_INT_CST | \
  617. ATH9K_INT_TSFOOR | \
  618. ATH9K_INT_GENTIMER | \
  619. ATH9K_INT_MCI)
  620. struct ath_softc *sc = dev;
  621. struct ath_hw *ah = sc->sc_ah;
  622. struct ath_common *common = ath9k_hw_common(ah);
  623. enum ath9k_int status;
  624. bool sched = false;
  625. /*
  626. * The hardware is not ready/present, don't
  627. * touch anything. Note this can happen early
  628. * on if the IRQ is shared.
  629. */
  630. if (sc->sc_flags & SC_OP_INVALID)
  631. return IRQ_NONE;
  632. /* shared irq, not for us */
  633. if (!ath9k_hw_intrpend(ah))
  634. return IRQ_NONE;
  635. /*
  636. * Figure out the reason(s) for the interrupt. Note
  637. * that the hal returns a pseudo-ISR that may include
  638. * bits we haven't explicitly enabled so we mask the
  639. * value to insure we only process bits we requested.
  640. */
  641. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  642. status &= ah->imask; /* discard unasked-for bits */
  643. /*
  644. * If there are no status bits set, then this interrupt was not
  645. * for me (should have been caught above).
  646. */
  647. if (!status)
  648. return IRQ_NONE;
  649. /* Cache the status */
  650. sc->intrstatus = status;
  651. if (status & SCHED_INTR)
  652. sched = true;
  653. /*
  654. * If a FATAL or RXORN interrupt is received, we have to reset the
  655. * chip immediately.
  656. */
  657. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  658. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  659. goto chip_reset;
  660. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  661. (status & ATH9K_INT_BB_WATCHDOG)) {
  662. spin_lock(&common->cc_lock);
  663. ath_hw_cycle_counters_update(common);
  664. ar9003_hw_bb_watchdog_dbg_info(ah);
  665. spin_unlock(&common->cc_lock);
  666. goto chip_reset;
  667. }
  668. if (status & ATH9K_INT_SWBA)
  669. tasklet_schedule(&sc->bcon_tasklet);
  670. if (status & ATH9K_INT_TXURN)
  671. ath9k_hw_updatetxtriglevel(ah, true);
  672. if (status & ATH9K_INT_RXEOL) {
  673. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  674. ath9k_hw_set_interrupts(ah);
  675. }
  676. if (status & ATH9K_INT_MIB) {
  677. /*
  678. * Disable interrupts until we service the MIB
  679. * interrupt; otherwise it will continue to
  680. * fire.
  681. */
  682. ath9k_hw_disable_interrupts(ah);
  683. /*
  684. * Let the hal handle the event. We assume
  685. * it will clear whatever condition caused
  686. * the interrupt.
  687. */
  688. spin_lock(&common->cc_lock);
  689. ath9k_hw_proc_mib_event(ah);
  690. spin_unlock(&common->cc_lock);
  691. ath9k_hw_enable_interrupts(ah);
  692. }
  693. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  694. if (status & ATH9K_INT_TIM_TIMER) {
  695. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  696. goto chip_reset;
  697. /* Clear RxAbort bit so that we can
  698. * receive frames */
  699. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  700. ath9k_hw_setrxabort(sc->sc_ah, 0);
  701. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  702. }
  703. chip_reset:
  704. ath_debug_stat_interrupt(sc, status);
  705. if (sched) {
  706. /* turn off every interrupt */
  707. ath9k_hw_disable_interrupts(ah);
  708. tasklet_schedule(&sc->intr_tq);
  709. }
  710. return IRQ_HANDLED;
  711. #undef SCHED_INTR
  712. }
  713. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  714. {
  715. int r;
  716. ath9k_ps_wakeup(sc);
  717. r = ath_reset_internal(sc, NULL, retry_tx);
  718. if (retry_tx) {
  719. int i;
  720. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  721. if (ATH_TXQ_SETUP(sc, i)) {
  722. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  723. ath_txq_schedule(sc, &sc->tx.txq[i]);
  724. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  725. }
  726. }
  727. }
  728. ath9k_ps_restore(sc);
  729. return r;
  730. }
  731. void ath_reset_work(struct work_struct *work)
  732. {
  733. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  734. ath_reset(sc, true);
  735. }
  736. void ath_hw_check(struct work_struct *work)
  737. {
  738. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  739. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  740. unsigned long flags;
  741. int busy;
  742. u8 is_alive, nbeacon = 1;
  743. ath9k_ps_wakeup(sc);
  744. is_alive = ath9k_hw_check_alive(sc->sc_ah);
  745. if (is_alive && !AR_SREV_9300(sc->sc_ah))
  746. goto out;
  747. else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
  748. ath_dbg(common, RESET,
  749. "DCU stuck is detected. Schedule chip reset\n");
  750. RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
  751. goto sched_reset;
  752. }
  753. spin_lock_irqsave(&common->cc_lock, flags);
  754. busy = ath_update_survey_stats(sc);
  755. spin_unlock_irqrestore(&common->cc_lock, flags);
  756. ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
  757. busy, sc->hw_busy_count + 1);
  758. if (busy >= 99) {
  759. if (++sc->hw_busy_count >= 3) {
  760. RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
  761. goto sched_reset;
  762. }
  763. } else if (busy >= 0) {
  764. sc->hw_busy_count = 0;
  765. nbeacon = 3;
  766. }
  767. ath_start_rx_poll(sc, nbeacon);
  768. goto out;
  769. sched_reset:
  770. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  771. out:
  772. ath9k_ps_restore(sc);
  773. }
  774. static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
  775. {
  776. static int count;
  777. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  778. if (pll_sqsum >= 0x40000) {
  779. count++;
  780. if (count == 3) {
  781. /* Rx is hung for more than 500ms. Reset it */
  782. ath_dbg(common, RESET, "Possible RX hang, resetting\n");
  783. RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
  784. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  785. count = 0;
  786. }
  787. } else
  788. count = 0;
  789. }
  790. void ath_hw_pll_work(struct work_struct *work)
  791. {
  792. struct ath_softc *sc = container_of(work, struct ath_softc,
  793. hw_pll_work.work);
  794. u32 pll_sqsum;
  795. if (AR_SREV_9485(sc->sc_ah)) {
  796. ath9k_ps_wakeup(sc);
  797. pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
  798. ath9k_ps_restore(sc);
  799. ath_hw_pll_rx_hang_check(sc, pll_sqsum);
  800. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
  801. }
  802. }
  803. /**********************/
  804. /* mac80211 callbacks */
  805. /**********************/
  806. static int ath9k_start(struct ieee80211_hw *hw)
  807. {
  808. struct ath_softc *sc = hw->priv;
  809. struct ath_hw *ah = sc->sc_ah;
  810. struct ath_common *common = ath9k_hw_common(ah);
  811. struct ieee80211_channel *curchan = hw->conf.channel;
  812. struct ath9k_channel *init_channel;
  813. int r;
  814. ath_dbg(common, CONFIG,
  815. "Starting driver with initial channel: %d MHz\n",
  816. curchan->center_freq);
  817. ath9k_ps_wakeup(sc);
  818. mutex_lock(&sc->mutex);
  819. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  820. /* Reset SERDES registers */
  821. ath9k_hw_configpcipowersave(ah, false);
  822. /*
  823. * The basic interface to setting the hardware in a good
  824. * state is ``reset''. On return the hardware is known to
  825. * be powered up and with interrupts disabled. This must
  826. * be followed by initialization of the appropriate bits
  827. * and then setup of the interrupt mask.
  828. */
  829. spin_lock_bh(&sc->sc_pcu_lock);
  830. atomic_set(&ah->intr_ref_cnt, -1);
  831. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  832. if (r) {
  833. ath_err(common,
  834. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  835. r, curchan->center_freq);
  836. spin_unlock_bh(&sc->sc_pcu_lock);
  837. goto mutex_unlock;
  838. }
  839. /* Setup our intr mask. */
  840. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  841. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  842. ATH9K_INT_GLOBAL;
  843. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  844. ah->imask |= ATH9K_INT_RXHP |
  845. ATH9K_INT_RXLP |
  846. ATH9K_INT_BB_WATCHDOG;
  847. else
  848. ah->imask |= ATH9K_INT_RX;
  849. ah->imask |= ATH9K_INT_GTT;
  850. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  851. ah->imask |= ATH9K_INT_CST;
  852. if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  853. ah->imask |= ATH9K_INT_MCI;
  854. sc->sc_flags &= ~SC_OP_INVALID;
  855. sc->sc_ah->is_monitoring = false;
  856. if (!ath_complete_reset(sc, false)) {
  857. r = -EIO;
  858. spin_unlock_bh(&sc->sc_pcu_lock);
  859. goto mutex_unlock;
  860. }
  861. if (ah->led_pin >= 0) {
  862. ath9k_hw_cfg_output(ah, ah->led_pin,
  863. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  864. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  865. }
  866. /*
  867. * Reset key cache to sane defaults (all entries cleared) instead of
  868. * semi-random values after suspend/resume.
  869. */
  870. ath9k_cmn_init_crypto(sc->sc_ah);
  871. spin_unlock_bh(&sc->sc_pcu_lock);
  872. ath9k_start_btcoex(sc);
  873. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  874. common->bus_ops->extn_synch_en(common);
  875. mutex_unlock:
  876. mutex_unlock(&sc->mutex);
  877. ath9k_ps_restore(sc);
  878. return r;
  879. }
  880. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  881. {
  882. struct ath_softc *sc = hw->priv;
  883. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  884. struct ath_tx_control txctl;
  885. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  886. if (sc->ps_enabled) {
  887. /*
  888. * mac80211 does not set PM field for normal data frames, so we
  889. * need to update that based on the current PS mode.
  890. */
  891. if (ieee80211_is_data(hdr->frame_control) &&
  892. !ieee80211_is_nullfunc(hdr->frame_control) &&
  893. !ieee80211_has_pm(hdr->frame_control)) {
  894. ath_dbg(common, PS,
  895. "Add PM=1 for a TX frame while in PS mode\n");
  896. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  897. }
  898. }
  899. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  900. /*
  901. * We are using PS-Poll and mac80211 can request TX while in
  902. * power save mode. Need to wake up hardware for the TX to be
  903. * completed and if needed, also for RX of buffered frames.
  904. */
  905. ath9k_ps_wakeup(sc);
  906. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  907. ath9k_hw_setrxabort(sc->sc_ah, 0);
  908. if (ieee80211_is_pspoll(hdr->frame_control)) {
  909. ath_dbg(common, PS,
  910. "Sending PS-Poll to pick a buffered frame\n");
  911. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  912. } else {
  913. ath_dbg(common, PS, "Wake up to complete TX\n");
  914. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  915. }
  916. /*
  917. * The actual restore operation will happen only after
  918. * the ps_flags bit is cleared. We are just dropping
  919. * the ps_usecount here.
  920. */
  921. ath9k_ps_restore(sc);
  922. }
  923. /*
  924. * Cannot tx while the hardware is in full sleep, it first needs a full
  925. * chip reset to recover from that
  926. */
  927. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  928. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  929. goto exit;
  930. }
  931. memset(&txctl, 0, sizeof(struct ath_tx_control));
  932. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  933. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  934. if (ath_tx_start(hw, skb, &txctl) != 0) {
  935. ath_dbg(common, XMIT, "TX failed\n");
  936. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  937. goto exit;
  938. }
  939. return;
  940. exit:
  941. dev_kfree_skb_any(skb);
  942. }
  943. static void ath9k_stop(struct ieee80211_hw *hw)
  944. {
  945. struct ath_softc *sc = hw->priv;
  946. struct ath_hw *ah = sc->sc_ah;
  947. struct ath_common *common = ath9k_hw_common(ah);
  948. bool prev_idle;
  949. mutex_lock(&sc->mutex);
  950. ath_cancel_work(sc);
  951. del_timer_sync(&sc->rx_poll_timer);
  952. if (sc->sc_flags & SC_OP_INVALID) {
  953. ath_dbg(common, ANY, "Device not present\n");
  954. mutex_unlock(&sc->mutex);
  955. return;
  956. }
  957. /* Ensure HW is awake when we try to shut it down. */
  958. ath9k_ps_wakeup(sc);
  959. ath9k_stop_btcoex(sc);
  960. spin_lock_bh(&sc->sc_pcu_lock);
  961. /* prevent tasklets to enable interrupts once we disable them */
  962. ah->imask &= ~ATH9K_INT_GLOBAL;
  963. /* make sure h/w will not generate any interrupt
  964. * before setting the invalid flag. */
  965. ath9k_hw_disable_interrupts(ah);
  966. spin_unlock_bh(&sc->sc_pcu_lock);
  967. /* we can now sync irq and kill any running tasklets, since we already
  968. * disabled interrupts and not holding a spin lock */
  969. synchronize_irq(sc->irq);
  970. tasklet_kill(&sc->intr_tq);
  971. tasklet_kill(&sc->bcon_tasklet);
  972. prev_idle = sc->ps_idle;
  973. sc->ps_idle = true;
  974. spin_lock_bh(&sc->sc_pcu_lock);
  975. if (ah->led_pin >= 0) {
  976. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  977. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  978. }
  979. ath_prepare_reset(sc, false, true);
  980. if (sc->rx.frag) {
  981. dev_kfree_skb_any(sc->rx.frag);
  982. sc->rx.frag = NULL;
  983. }
  984. if (!ah->curchan)
  985. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  986. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  987. ath9k_hw_phy_disable(ah);
  988. ath9k_hw_configpcipowersave(ah, true);
  989. spin_unlock_bh(&sc->sc_pcu_lock);
  990. ath9k_ps_restore(sc);
  991. sc->sc_flags |= SC_OP_INVALID;
  992. sc->ps_idle = prev_idle;
  993. mutex_unlock(&sc->mutex);
  994. ath_dbg(common, CONFIG, "Driver halt\n");
  995. }
  996. bool ath9k_uses_beacons(int type)
  997. {
  998. switch (type) {
  999. case NL80211_IFTYPE_AP:
  1000. case NL80211_IFTYPE_ADHOC:
  1001. case NL80211_IFTYPE_MESH_POINT:
  1002. return true;
  1003. default:
  1004. return false;
  1005. }
  1006. }
  1007. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1008. struct ieee80211_vif *vif)
  1009. {
  1010. struct ath_vif *avp = (void *)vif->drv_priv;
  1011. ath9k_set_beaconing_status(sc, false);
  1012. ath_beacon_return(sc, avp);
  1013. ath9k_set_beaconing_status(sc, true);
  1014. }
  1015. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1016. {
  1017. struct ath9k_vif_iter_data *iter_data = data;
  1018. int i;
  1019. if (iter_data->hw_macaddr)
  1020. for (i = 0; i < ETH_ALEN; i++)
  1021. iter_data->mask[i] &=
  1022. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1023. switch (vif->type) {
  1024. case NL80211_IFTYPE_AP:
  1025. iter_data->naps++;
  1026. break;
  1027. case NL80211_IFTYPE_STATION:
  1028. iter_data->nstations++;
  1029. break;
  1030. case NL80211_IFTYPE_ADHOC:
  1031. iter_data->nadhocs++;
  1032. break;
  1033. case NL80211_IFTYPE_MESH_POINT:
  1034. iter_data->nmeshes++;
  1035. break;
  1036. case NL80211_IFTYPE_WDS:
  1037. iter_data->nwds++;
  1038. break;
  1039. default:
  1040. break;
  1041. }
  1042. }
  1043. /* Called with sc->mutex held. */
  1044. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1045. struct ieee80211_vif *vif,
  1046. struct ath9k_vif_iter_data *iter_data)
  1047. {
  1048. struct ath_softc *sc = hw->priv;
  1049. struct ath_hw *ah = sc->sc_ah;
  1050. struct ath_common *common = ath9k_hw_common(ah);
  1051. /*
  1052. * Use the hardware MAC address as reference, the hardware uses it
  1053. * together with the BSSID mask when matching addresses.
  1054. */
  1055. memset(iter_data, 0, sizeof(*iter_data));
  1056. iter_data->hw_macaddr = common->macaddr;
  1057. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1058. if (vif)
  1059. ath9k_vif_iter(iter_data, vif->addr, vif);
  1060. /* Get list of all active MAC addresses */
  1061. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1062. iter_data);
  1063. }
  1064. /* Called with sc->mutex held. */
  1065. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1066. struct ieee80211_vif *vif)
  1067. {
  1068. struct ath_softc *sc = hw->priv;
  1069. struct ath_hw *ah = sc->sc_ah;
  1070. struct ath_common *common = ath9k_hw_common(ah);
  1071. struct ath9k_vif_iter_data iter_data;
  1072. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1073. /* Set BSSID mask. */
  1074. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1075. ath_hw_setbssidmask(common);
  1076. /* Set op-mode & TSF */
  1077. if (iter_data.naps > 0) {
  1078. ath9k_hw_set_tsfadjust(ah, 1);
  1079. sc->sc_flags |= SC_OP_TSF_RESET;
  1080. ah->opmode = NL80211_IFTYPE_AP;
  1081. } else {
  1082. ath9k_hw_set_tsfadjust(ah, 0);
  1083. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1084. if (iter_data.nmeshes)
  1085. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  1086. else if (iter_data.nwds)
  1087. ah->opmode = NL80211_IFTYPE_AP;
  1088. else if (iter_data.nadhocs)
  1089. ah->opmode = NL80211_IFTYPE_ADHOC;
  1090. else
  1091. ah->opmode = NL80211_IFTYPE_STATION;
  1092. }
  1093. /*
  1094. * Enable MIB interrupts when there are hardware phy counters.
  1095. */
  1096. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1097. if (ah->config.enable_ani)
  1098. ah->imask |= ATH9K_INT_MIB;
  1099. ah->imask |= ATH9K_INT_TSFOOR;
  1100. } else {
  1101. ah->imask &= ~ATH9K_INT_MIB;
  1102. ah->imask &= ~ATH9K_INT_TSFOOR;
  1103. }
  1104. ath9k_hw_set_interrupts(ah);
  1105. /* Set up ANI */
  1106. if (iter_data.naps > 0) {
  1107. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1108. if (!common->disable_ani) {
  1109. sc->sc_flags |= SC_OP_ANI_RUN;
  1110. ath_start_ani(common);
  1111. }
  1112. } else {
  1113. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1114. del_timer_sync(&common->ani.timer);
  1115. }
  1116. }
  1117. /* Called with sc->mutex held, vif counts set up properly. */
  1118. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1119. struct ieee80211_vif *vif)
  1120. {
  1121. struct ath_softc *sc = hw->priv;
  1122. ath9k_calculate_summary_state(hw, vif);
  1123. if (ath9k_uses_beacons(vif->type)) {
  1124. /* Reserve a beacon slot for the vif */
  1125. ath9k_set_beaconing_status(sc, false);
  1126. ath_beacon_alloc(sc, vif);
  1127. ath9k_set_beaconing_status(sc, true);
  1128. }
  1129. }
  1130. void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
  1131. {
  1132. if (!AR_SREV_9300(sc->sc_ah))
  1133. return;
  1134. if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
  1135. return;
  1136. mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
  1137. (nbeacon * sc->cur_beacon_conf.beacon_interval));
  1138. }
  1139. void ath_rx_poll(unsigned long data)
  1140. {
  1141. struct ath_softc *sc = (struct ath_softc *)data;
  1142. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  1143. }
  1144. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1145. struct ieee80211_vif *vif)
  1146. {
  1147. struct ath_softc *sc = hw->priv;
  1148. struct ath_hw *ah = sc->sc_ah;
  1149. struct ath_common *common = ath9k_hw_common(ah);
  1150. int ret = 0;
  1151. ath9k_ps_wakeup(sc);
  1152. mutex_lock(&sc->mutex);
  1153. switch (vif->type) {
  1154. case NL80211_IFTYPE_STATION:
  1155. case NL80211_IFTYPE_WDS:
  1156. case NL80211_IFTYPE_ADHOC:
  1157. case NL80211_IFTYPE_AP:
  1158. case NL80211_IFTYPE_MESH_POINT:
  1159. break;
  1160. default:
  1161. ath_err(common, "Interface type %d not yet supported\n",
  1162. vif->type);
  1163. ret = -EOPNOTSUPP;
  1164. goto out;
  1165. }
  1166. if (ath9k_uses_beacons(vif->type)) {
  1167. if (sc->nbcnvifs >= ATH_BCBUF) {
  1168. ath_err(common, "Not enough beacon buffers when adding"
  1169. " new interface of type: %i\n",
  1170. vif->type);
  1171. ret = -ENOBUFS;
  1172. goto out;
  1173. }
  1174. }
  1175. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1176. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1177. sc->nvifs > 0)) {
  1178. ath_err(common, "Cannot create ADHOC interface when other"
  1179. " interfaces already exist.\n");
  1180. ret = -EINVAL;
  1181. goto out;
  1182. }
  1183. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  1184. sc->nvifs++;
  1185. ath9k_do_vif_add_setup(hw, vif);
  1186. out:
  1187. mutex_unlock(&sc->mutex);
  1188. ath9k_ps_restore(sc);
  1189. return ret;
  1190. }
  1191. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1192. struct ieee80211_vif *vif,
  1193. enum nl80211_iftype new_type,
  1194. bool p2p)
  1195. {
  1196. struct ath_softc *sc = hw->priv;
  1197. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1198. int ret = 0;
  1199. ath_dbg(common, CONFIG, "Change Interface\n");
  1200. mutex_lock(&sc->mutex);
  1201. ath9k_ps_wakeup(sc);
  1202. /* See if new interface type is valid. */
  1203. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1204. (sc->nvifs > 1)) {
  1205. ath_err(common, "When using ADHOC, it must be the only"
  1206. " interface.\n");
  1207. ret = -EINVAL;
  1208. goto out;
  1209. }
  1210. if (ath9k_uses_beacons(new_type) &&
  1211. !ath9k_uses_beacons(vif->type)) {
  1212. if (sc->nbcnvifs >= ATH_BCBUF) {
  1213. ath_err(common, "No beacon slot available\n");
  1214. ret = -ENOBUFS;
  1215. goto out;
  1216. }
  1217. }
  1218. /* Clean up old vif stuff */
  1219. if (ath9k_uses_beacons(vif->type))
  1220. ath9k_reclaim_beacon(sc, vif);
  1221. /* Add new settings */
  1222. vif->type = new_type;
  1223. vif->p2p = p2p;
  1224. ath9k_do_vif_add_setup(hw, vif);
  1225. out:
  1226. ath9k_ps_restore(sc);
  1227. mutex_unlock(&sc->mutex);
  1228. return ret;
  1229. }
  1230. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1231. struct ieee80211_vif *vif)
  1232. {
  1233. struct ath_softc *sc = hw->priv;
  1234. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1235. ath_dbg(common, CONFIG, "Detach Interface\n");
  1236. ath9k_ps_wakeup(sc);
  1237. mutex_lock(&sc->mutex);
  1238. sc->nvifs--;
  1239. /* Reclaim beacon resources */
  1240. if (ath9k_uses_beacons(vif->type))
  1241. ath9k_reclaim_beacon(sc, vif);
  1242. ath9k_calculate_summary_state(hw, NULL);
  1243. mutex_unlock(&sc->mutex);
  1244. ath9k_ps_restore(sc);
  1245. }
  1246. static void ath9k_enable_ps(struct ath_softc *sc)
  1247. {
  1248. struct ath_hw *ah = sc->sc_ah;
  1249. struct ath_common *common = ath9k_hw_common(ah);
  1250. sc->ps_enabled = true;
  1251. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1252. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1253. ah->imask |= ATH9K_INT_TIM_TIMER;
  1254. ath9k_hw_set_interrupts(ah);
  1255. }
  1256. ath9k_hw_setrxabort(ah, 1);
  1257. }
  1258. ath_dbg(common, PS, "PowerSave enabled\n");
  1259. }
  1260. static void ath9k_disable_ps(struct ath_softc *sc)
  1261. {
  1262. struct ath_hw *ah = sc->sc_ah;
  1263. struct ath_common *common = ath9k_hw_common(ah);
  1264. sc->ps_enabled = false;
  1265. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1266. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1267. ath9k_hw_setrxabort(ah, 0);
  1268. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1269. PS_WAIT_FOR_CAB |
  1270. PS_WAIT_FOR_PSPOLL_DATA |
  1271. PS_WAIT_FOR_TX_ACK);
  1272. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1273. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1274. ath9k_hw_set_interrupts(ah);
  1275. }
  1276. }
  1277. ath_dbg(common, PS, "PowerSave disabled\n");
  1278. }
  1279. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1280. {
  1281. struct ath_softc *sc = hw->priv;
  1282. struct ath_hw *ah = sc->sc_ah;
  1283. struct ath_common *common = ath9k_hw_common(ah);
  1284. struct ieee80211_conf *conf = &hw->conf;
  1285. bool reset_channel = false;
  1286. ath9k_ps_wakeup(sc);
  1287. mutex_lock(&sc->mutex);
  1288. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1289. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1290. if (sc->ps_idle)
  1291. ath_cancel_work(sc);
  1292. else
  1293. /*
  1294. * The chip needs a reset to properly wake up from
  1295. * full sleep
  1296. */
  1297. reset_channel = ah->chip_fullsleep;
  1298. }
  1299. /*
  1300. * We just prepare to enable PS. We have to wait until our AP has
  1301. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1302. * those ACKs and end up retransmitting the same null data frames.
  1303. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1304. */
  1305. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1306. unsigned long flags;
  1307. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1308. if (conf->flags & IEEE80211_CONF_PS)
  1309. ath9k_enable_ps(sc);
  1310. else
  1311. ath9k_disable_ps(sc);
  1312. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1313. }
  1314. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1315. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1316. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1317. sc->sc_ah->is_monitoring = true;
  1318. } else {
  1319. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1320. sc->sc_ah->is_monitoring = false;
  1321. }
  1322. }
  1323. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  1324. struct ieee80211_channel *curchan = hw->conf.channel;
  1325. int pos = curchan->hw_value;
  1326. int old_pos = -1;
  1327. unsigned long flags;
  1328. if (ah->curchan)
  1329. old_pos = ah->curchan - &ah->channels[0];
  1330. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1331. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1332. else
  1333. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1334. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  1335. curchan->center_freq, conf->channel_type);
  1336. /* update survey stats for the old channel before switching */
  1337. spin_lock_irqsave(&common->cc_lock, flags);
  1338. ath_update_survey_stats(sc);
  1339. spin_unlock_irqrestore(&common->cc_lock, flags);
  1340. /*
  1341. * Preserve the current channel values, before updating
  1342. * the same channel
  1343. */
  1344. if (ah->curchan && (old_pos == pos))
  1345. ath9k_hw_getnf(ah, ah->curchan);
  1346. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1347. curchan, conf->channel_type);
  1348. /*
  1349. * If the operating channel changes, change the survey in-use flags
  1350. * along with it.
  1351. * Reset the survey data for the new channel, unless we're switching
  1352. * back to the operating channel from an off-channel operation.
  1353. */
  1354. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1355. sc->cur_survey != &sc->survey[pos]) {
  1356. if (sc->cur_survey)
  1357. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1358. sc->cur_survey = &sc->survey[pos];
  1359. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1360. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1361. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1362. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1363. }
  1364. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1365. ath_err(common, "Unable to set channel\n");
  1366. mutex_unlock(&sc->mutex);
  1367. return -EINVAL;
  1368. }
  1369. /*
  1370. * The most recent snapshot of channel->noisefloor for the old
  1371. * channel is only available after the hardware reset. Copy it to
  1372. * the survey stats now.
  1373. */
  1374. if (old_pos >= 0)
  1375. ath_update_survey_nf(sc, old_pos);
  1376. }
  1377. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1378. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1379. sc->config.txpowlimit = 2 * conf->power_level;
  1380. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1381. sc->config.txpowlimit, &sc->curtxpow);
  1382. }
  1383. mutex_unlock(&sc->mutex);
  1384. ath9k_ps_restore(sc);
  1385. return 0;
  1386. }
  1387. #define SUPPORTED_FILTERS \
  1388. (FIF_PROMISC_IN_BSS | \
  1389. FIF_ALLMULTI | \
  1390. FIF_CONTROL | \
  1391. FIF_PSPOLL | \
  1392. FIF_OTHER_BSS | \
  1393. FIF_BCN_PRBRESP_PROMISC | \
  1394. FIF_PROBE_REQ | \
  1395. FIF_FCSFAIL)
  1396. /* FIXME: sc->sc_full_reset ? */
  1397. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1398. unsigned int changed_flags,
  1399. unsigned int *total_flags,
  1400. u64 multicast)
  1401. {
  1402. struct ath_softc *sc = hw->priv;
  1403. u32 rfilt;
  1404. changed_flags &= SUPPORTED_FILTERS;
  1405. *total_flags &= SUPPORTED_FILTERS;
  1406. sc->rx.rxfilter = *total_flags;
  1407. ath9k_ps_wakeup(sc);
  1408. rfilt = ath_calcrxfilter(sc);
  1409. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1410. ath9k_ps_restore(sc);
  1411. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1412. rfilt);
  1413. }
  1414. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1415. struct ieee80211_vif *vif,
  1416. struct ieee80211_sta *sta)
  1417. {
  1418. struct ath_softc *sc = hw->priv;
  1419. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1420. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1421. struct ieee80211_key_conf ps_key = { };
  1422. ath_node_attach(sc, sta, vif);
  1423. if (vif->type != NL80211_IFTYPE_AP &&
  1424. vif->type != NL80211_IFTYPE_AP_VLAN)
  1425. return 0;
  1426. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1427. return 0;
  1428. }
  1429. static void ath9k_del_ps_key(struct ath_softc *sc,
  1430. struct ieee80211_vif *vif,
  1431. struct ieee80211_sta *sta)
  1432. {
  1433. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1434. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1435. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1436. if (!an->ps_key)
  1437. return;
  1438. ath_key_delete(common, &ps_key);
  1439. }
  1440. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1441. struct ieee80211_vif *vif,
  1442. struct ieee80211_sta *sta)
  1443. {
  1444. struct ath_softc *sc = hw->priv;
  1445. ath9k_del_ps_key(sc, vif, sta);
  1446. ath_node_detach(sc, sta);
  1447. return 0;
  1448. }
  1449. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1450. struct ieee80211_vif *vif,
  1451. enum sta_notify_cmd cmd,
  1452. struct ieee80211_sta *sta)
  1453. {
  1454. struct ath_softc *sc = hw->priv;
  1455. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1456. if (!sta->ht_cap.ht_supported)
  1457. return;
  1458. switch (cmd) {
  1459. case STA_NOTIFY_SLEEP:
  1460. an->sleeping = true;
  1461. ath_tx_aggr_sleep(sta, sc, an);
  1462. break;
  1463. case STA_NOTIFY_AWAKE:
  1464. an->sleeping = false;
  1465. ath_tx_aggr_wakeup(sc, an);
  1466. break;
  1467. }
  1468. }
  1469. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1470. struct ieee80211_vif *vif, u16 queue,
  1471. const struct ieee80211_tx_queue_params *params)
  1472. {
  1473. struct ath_softc *sc = hw->priv;
  1474. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1475. struct ath_txq *txq;
  1476. struct ath9k_tx_queue_info qi;
  1477. int ret = 0;
  1478. if (queue >= WME_NUM_AC)
  1479. return 0;
  1480. txq = sc->tx.txq_map[queue];
  1481. ath9k_ps_wakeup(sc);
  1482. mutex_lock(&sc->mutex);
  1483. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1484. qi.tqi_aifs = params->aifs;
  1485. qi.tqi_cwmin = params->cw_min;
  1486. qi.tqi_cwmax = params->cw_max;
  1487. qi.tqi_burstTime = params->txop;
  1488. ath_dbg(common, CONFIG,
  1489. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1490. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1491. params->cw_max, params->txop);
  1492. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1493. if (ret)
  1494. ath_err(common, "TXQ Update failed\n");
  1495. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1496. if (queue == WME_AC_BE && !ret)
  1497. ath_beaconq_config(sc);
  1498. mutex_unlock(&sc->mutex);
  1499. ath9k_ps_restore(sc);
  1500. return ret;
  1501. }
  1502. static int ath9k_set_key(struct ieee80211_hw *hw,
  1503. enum set_key_cmd cmd,
  1504. struct ieee80211_vif *vif,
  1505. struct ieee80211_sta *sta,
  1506. struct ieee80211_key_conf *key)
  1507. {
  1508. struct ath_softc *sc = hw->priv;
  1509. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1510. int ret = 0;
  1511. if (ath9k_modparam_nohwcrypt)
  1512. return -ENOSPC;
  1513. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1514. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1515. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1516. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1517. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1518. /*
  1519. * For now, disable hw crypto for the RSN IBSS group keys. This
  1520. * could be optimized in the future to use a modified key cache
  1521. * design to support per-STA RX GTK, but until that gets
  1522. * implemented, use of software crypto for group addressed
  1523. * frames is a acceptable to allow RSN IBSS to be used.
  1524. */
  1525. return -EOPNOTSUPP;
  1526. }
  1527. mutex_lock(&sc->mutex);
  1528. ath9k_ps_wakeup(sc);
  1529. ath_dbg(common, CONFIG, "Set HW Key\n");
  1530. switch (cmd) {
  1531. case SET_KEY:
  1532. if (sta)
  1533. ath9k_del_ps_key(sc, vif, sta);
  1534. ret = ath_key_config(common, vif, sta, key);
  1535. if (ret >= 0) {
  1536. key->hw_key_idx = ret;
  1537. /* push IV and Michael MIC generation to stack */
  1538. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1539. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1540. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1541. if (sc->sc_ah->sw_mgmt_crypto &&
  1542. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1543. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1544. ret = 0;
  1545. }
  1546. break;
  1547. case DISABLE_KEY:
  1548. ath_key_delete(common, key);
  1549. break;
  1550. default:
  1551. ret = -EINVAL;
  1552. }
  1553. ath9k_ps_restore(sc);
  1554. mutex_unlock(&sc->mutex);
  1555. return ret;
  1556. }
  1557. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1558. {
  1559. struct ath_softc *sc = data;
  1560. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1561. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1562. struct ath_vif *avp = (void *)vif->drv_priv;
  1563. /*
  1564. * Skip iteration if primary station vif's bss info
  1565. * was not changed
  1566. */
  1567. if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
  1568. return;
  1569. if (bss_conf->assoc) {
  1570. sc->sc_flags |= SC_OP_PRIM_STA_VIF;
  1571. avp->primary_sta_vif = true;
  1572. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1573. common->curaid = bss_conf->aid;
  1574. ath9k_hw_write_associd(sc->sc_ah);
  1575. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1576. bss_conf->aid, common->curbssid);
  1577. ath_beacon_config(sc, vif);
  1578. /*
  1579. * Request a re-configuration of Beacon related timers
  1580. * on the receipt of the first Beacon frame (i.e.,
  1581. * after time sync with the AP).
  1582. */
  1583. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1584. /* Reset rssi stats */
  1585. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1586. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1587. ath_start_rx_poll(sc, 3);
  1588. if (!common->disable_ani) {
  1589. sc->sc_flags |= SC_OP_ANI_RUN;
  1590. ath_start_ani(common);
  1591. }
  1592. }
  1593. }
  1594. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1595. {
  1596. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1597. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1598. struct ath_vif *avp = (void *)vif->drv_priv;
  1599. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1600. return;
  1601. /* Reconfigure bss info */
  1602. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1603. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1604. common->curaid, common->curbssid);
  1605. sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
  1606. avp->primary_sta_vif = false;
  1607. memset(common->curbssid, 0, ETH_ALEN);
  1608. common->curaid = 0;
  1609. }
  1610. ieee80211_iterate_active_interfaces_atomic(
  1611. sc->hw, ath9k_bss_iter, sc);
  1612. /*
  1613. * None of station vifs are associated.
  1614. * Clear bssid & aid
  1615. */
  1616. if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
  1617. ath9k_hw_write_associd(sc->sc_ah);
  1618. /* Stop ANI */
  1619. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1620. del_timer_sync(&common->ani.timer);
  1621. del_timer_sync(&sc->rx_poll_timer);
  1622. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1623. }
  1624. }
  1625. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1626. struct ieee80211_vif *vif,
  1627. struct ieee80211_bss_conf *bss_conf,
  1628. u32 changed)
  1629. {
  1630. struct ath_softc *sc = hw->priv;
  1631. struct ath_hw *ah = sc->sc_ah;
  1632. struct ath_common *common = ath9k_hw_common(ah);
  1633. struct ath_vif *avp = (void *)vif->drv_priv;
  1634. int slottime;
  1635. ath9k_ps_wakeup(sc);
  1636. mutex_lock(&sc->mutex);
  1637. if (changed & BSS_CHANGED_ASSOC) {
  1638. ath9k_config_bss(sc, vif);
  1639. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1640. common->curbssid, common->curaid);
  1641. }
  1642. if (changed & BSS_CHANGED_IBSS) {
  1643. /* There can be only one vif available */
  1644. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1645. common->curaid = bss_conf->aid;
  1646. ath9k_hw_write_associd(sc->sc_ah);
  1647. if (bss_conf->ibss_joined) {
  1648. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1649. if (!common->disable_ani) {
  1650. sc->sc_flags |= SC_OP_ANI_RUN;
  1651. ath_start_ani(common);
  1652. }
  1653. } else {
  1654. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1655. del_timer_sync(&common->ani.timer);
  1656. del_timer_sync(&sc->rx_poll_timer);
  1657. }
  1658. }
  1659. /*
  1660. * In case of AP mode, the HW TSF has to be reset
  1661. * when the beacon interval changes.
  1662. */
  1663. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1664. (vif->type == NL80211_IFTYPE_AP))
  1665. sc->sc_flags |= SC_OP_TSF_RESET;
  1666. /* Configure beaconing (AP, IBSS, MESH) */
  1667. if (ath9k_uses_beacons(vif->type) &&
  1668. ((changed & BSS_CHANGED_BEACON) ||
  1669. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1670. (changed & BSS_CHANGED_BEACON_INT))) {
  1671. ath9k_set_beaconing_status(sc, false);
  1672. if (bss_conf->enable_beacon)
  1673. ath_beacon_alloc(sc, vif);
  1674. else
  1675. avp->is_bslot_active = false;
  1676. ath_beacon_config(sc, vif);
  1677. ath9k_set_beaconing_status(sc, true);
  1678. }
  1679. if (changed & BSS_CHANGED_ERP_SLOT) {
  1680. if (bss_conf->use_short_slot)
  1681. slottime = 9;
  1682. else
  1683. slottime = 20;
  1684. if (vif->type == NL80211_IFTYPE_AP) {
  1685. /*
  1686. * Defer update, so that connected stations can adjust
  1687. * their settings at the same time.
  1688. * See beacon.c for more details
  1689. */
  1690. sc->beacon.slottime = slottime;
  1691. sc->beacon.updateslot = UPDATE;
  1692. } else {
  1693. ah->slottime = slottime;
  1694. ath9k_hw_init_global_settings(ah);
  1695. }
  1696. }
  1697. mutex_unlock(&sc->mutex);
  1698. ath9k_ps_restore(sc);
  1699. }
  1700. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1701. {
  1702. struct ath_softc *sc = hw->priv;
  1703. u64 tsf;
  1704. mutex_lock(&sc->mutex);
  1705. ath9k_ps_wakeup(sc);
  1706. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1707. ath9k_ps_restore(sc);
  1708. mutex_unlock(&sc->mutex);
  1709. return tsf;
  1710. }
  1711. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1712. struct ieee80211_vif *vif,
  1713. u64 tsf)
  1714. {
  1715. struct ath_softc *sc = hw->priv;
  1716. mutex_lock(&sc->mutex);
  1717. ath9k_ps_wakeup(sc);
  1718. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1719. ath9k_ps_restore(sc);
  1720. mutex_unlock(&sc->mutex);
  1721. }
  1722. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1723. {
  1724. struct ath_softc *sc = hw->priv;
  1725. mutex_lock(&sc->mutex);
  1726. ath9k_ps_wakeup(sc);
  1727. ath9k_hw_reset_tsf(sc->sc_ah);
  1728. ath9k_ps_restore(sc);
  1729. mutex_unlock(&sc->mutex);
  1730. }
  1731. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1732. struct ieee80211_vif *vif,
  1733. enum ieee80211_ampdu_mlme_action action,
  1734. struct ieee80211_sta *sta,
  1735. u16 tid, u16 *ssn, u8 buf_size)
  1736. {
  1737. struct ath_softc *sc = hw->priv;
  1738. int ret = 0;
  1739. local_bh_disable();
  1740. switch (action) {
  1741. case IEEE80211_AMPDU_RX_START:
  1742. break;
  1743. case IEEE80211_AMPDU_RX_STOP:
  1744. break;
  1745. case IEEE80211_AMPDU_TX_START:
  1746. ath9k_ps_wakeup(sc);
  1747. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1748. if (!ret)
  1749. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1750. ath9k_ps_restore(sc);
  1751. break;
  1752. case IEEE80211_AMPDU_TX_STOP:
  1753. ath9k_ps_wakeup(sc);
  1754. ath_tx_aggr_stop(sc, sta, tid);
  1755. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1756. ath9k_ps_restore(sc);
  1757. break;
  1758. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1759. ath9k_ps_wakeup(sc);
  1760. ath_tx_aggr_resume(sc, sta, tid);
  1761. ath9k_ps_restore(sc);
  1762. break;
  1763. default:
  1764. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1765. }
  1766. local_bh_enable();
  1767. return ret;
  1768. }
  1769. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1770. struct survey_info *survey)
  1771. {
  1772. struct ath_softc *sc = hw->priv;
  1773. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1774. struct ieee80211_supported_band *sband;
  1775. struct ieee80211_channel *chan;
  1776. unsigned long flags;
  1777. int pos;
  1778. spin_lock_irqsave(&common->cc_lock, flags);
  1779. if (idx == 0)
  1780. ath_update_survey_stats(sc);
  1781. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1782. if (sband && idx >= sband->n_channels) {
  1783. idx -= sband->n_channels;
  1784. sband = NULL;
  1785. }
  1786. if (!sband)
  1787. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1788. if (!sband || idx >= sband->n_channels) {
  1789. spin_unlock_irqrestore(&common->cc_lock, flags);
  1790. return -ENOENT;
  1791. }
  1792. chan = &sband->channels[idx];
  1793. pos = chan->hw_value;
  1794. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1795. survey->channel = chan;
  1796. spin_unlock_irqrestore(&common->cc_lock, flags);
  1797. return 0;
  1798. }
  1799. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1800. {
  1801. struct ath_softc *sc = hw->priv;
  1802. struct ath_hw *ah = sc->sc_ah;
  1803. mutex_lock(&sc->mutex);
  1804. ah->coverage_class = coverage_class;
  1805. ath9k_ps_wakeup(sc);
  1806. ath9k_hw_init_global_settings(ah);
  1807. ath9k_ps_restore(sc);
  1808. mutex_unlock(&sc->mutex);
  1809. }
  1810. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1811. {
  1812. struct ath_softc *sc = hw->priv;
  1813. struct ath_hw *ah = sc->sc_ah;
  1814. struct ath_common *common = ath9k_hw_common(ah);
  1815. int timeout = 200; /* ms */
  1816. int i, j;
  1817. bool drain_txq;
  1818. mutex_lock(&sc->mutex);
  1819. cancel_delayed_work_sync(&sc->tx_complete_work);
  1820. if (ah->ah_flags & AH_UNPLUGGED) {
  1821. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1822. mutex_unlock(&sc->mutex);
  1823. return;
  1824. }
  1825. if (sc->sc_flags & SC_OP_INVALID) {
  1826. ath_dbg(common, ANY, "Device not present\n");
  1827. mutex_unlock(&sc->mutex);
  1828. return;
  1829. }
  1830. for (j = 0; j < timeout; j++) {
  1831. bool npend = false;
  1832. if (j)
  1833. usleep_range(1000, 2000);
  1834. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1835. if (!ATH_TXQ_SETUP(sc, i))
  1836. continue;
  1837. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1838. if (npend)
  1839. break;
  1840. }
  1841. if (!npend)
  1842. break;
  1843. }
  1844. if (drop) {
  1845. ath9k_ps_wakeup(sc);
  1846. spin_lock_bh(&sc->sc_pcu_lock);
  1847. drain_txq = ath_drain_all_txq(sc, false);
  1848. spin_unlock_bh(&sc->sc_pcu_lock);
  1849. if (!drain_txq)
  1850. ath_reset(sc, false);
  1851. ath9k_ps_restore(sc);
  1852. ieee80211_wake_queues(hw);
  1853. }
  1854. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1855. mutex_unlock(&sc->mutex);
  1856. }
  1857. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1858. {
  1859. struct ath_softc *sc = hw->priv;
  1860. int i;
  1861. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1862. if (!ATH_TXQ_SETUP(sc, i))
  1863. continue;
  1864. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1865. return true;
  1866. }
  1867. return false;
  1868. }
  1869. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1870. {
  1871. struct ath_softc *sc = hw->priv;
  1872. struct ath_hw *ah = sc->sc_ah;
  1873. struct ieee80211_vif *vif;
  1874. struct ath_vif *avp;
  1875. struct ath_buf *bf;
  1876. struct ath_tx_status ts;
  1877. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1878. int status;
  1879. vif = sc->beacon.bslot[0];
  1880. if (!vif)
  1881. return 0;
  1882. avp = (void *)vif->drv_priv;
  1883. if (!avp->is_bslot_active)
  1884. return 0;
  1885. if (!sc->beacon.tx_processed && !edma) {
  1886. tasklet_disable(&sc->bcon_tasklet);
  1887. bf = avp->av_bcbuf;
  1888. if (!bf || !bf->bf_mpdu)
  1889. goto skip;
  1890. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1891. if (status == -EINPROGRESS)
  1892. goto skip;
  1893. sc->beacon.tx_processed = true;
  1894. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1895. skip:
  1896. tasklet_enable(&sc->bcon_tasklet);
  1897. }
  1898. return sc->beacon.tx_last;
  1899. }
  1900. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1901. struct ieee80211_low_level_stats *stats)
  1902. {
  1903. struct ath_softc *sc = hw->priv;
  1904. struct ath_hw *ah = sc->sc_ah;
  1905. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1906. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1907. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1908. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1909. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1910. return 0;
  1911. }
  1912. static u32 fill_chainmask(u32 cap, u32 new)
  1913. {
  1914. u32 filled = 0;
  1915. int i;
  1916. for (i = 0; cap && new; i++, cap >>= 1) {
  1917. if (!(cap & BIT(0)))
  1918. continue;
  1919. if (new & BIT(0))
  1920. filled |= BIT(i);
  1921. new >>= 1;
  1922. }
  1923. return filled;
  1924. }
  1925. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1926. {
  1927. struct ath_softc *sc = hw->priv;
  1928. struct ath_hw *ah = sc->sc_ah;
  1929. if (!rx_ant || !tx_ant)
  1930. return -EINVAL;
  1931. sc->ant_rx = rx_ant;
  1932. sc->ant_tx = tx_ant;
  1933. if (ah->caps.rx_chainmask == 1)
  1934. return 0;
  1935. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1936. if (AR_SREV_9100(ah))
  1937. ah->rxchainmask = 0x7;
  1938. else
  1939. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1940. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1941. ath9k_reload_chainmask_settings(sc);
  1942. return 0;
  1943. }
  1944. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1945. {
  1946. struct ath_softc *sc = hw->priv;
  1947. *tx_ant = sc->ant_tx;
  1948. *rx_ant = sc->ant_rx;
  1949. return 0;
  1950. }
  1951. #ifdef CONFIG_ATH9K_DEBUGFS
  1952. /* Ethtool support for get-stats */
  1953. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1954. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1955. "tx_pkts_nic",
  1956. "tx_bytes_nic",
  1957. "rx_pkts_nic",
  1958. "rx_bytes_nic",
  1959. AMKSTR(d_tx_pkts),
  1960. AMKSTR(d_tx_bytes),
  1961. AMKSTR(d_tx_mpdus_queued),
  1962. AMKSTR(d_tx_mpdus_completed),
  1963. AMKSTR(d_tx_mpdu_xretries),
  1964. AMKSTR(d_tx_aggregates),
  1965. AMKSTR(d_tx_ampdus_queued_hw),
  1966. AMKSTR(d_tx_ampdus_queued_sw),
  1967. AMKSTR(d_tx_ampdus_completed),
  1968. AMKSTR(d_tx_ampdu_retries),
  1969. AMKSTR(d_tx_ampdu_xretries),
  1970. AMKSTR(d_tx_fifo_underrun),
  1971. AMKSTR(d_tx_op_exceeded),
  1972. AMKSTR(d_tx_timer_expiry),
  1973. AMKSTR(d_tx_desc_cfg_err),
  1974. AMKSTR(d_tx_data_underrun),
  1975. AMKSTR(d_tx_delim_underrun),
  1976. "d_rx_decrypt_crc_err",
  1977. "d_rx_phy_err",
  1978. "d_rx_mic_err",
  1979. "d_rx_pre_delim_crc_err",
  1980. "d_rx_post_delim_crc_err",
  1981. "d_rx_decrypt_busy_err",
  1982. "d_rx_phyerr_radar",
  1983. "d_rx_phyerr_ofdm_timing",
  1984. "d_rx_phyerr_cck_timing",
  1985. };
  1986. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1987. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1988. struct ieee80211_vif *vif,
  1989. u32 sset, u8 *data)
  1990. {
  1991. if (sset == ETH_SS_STATS)
  1992. memcpy(data, *ath9k_gstrings_stats,
  1993. sizeof(ath9k_gstrings_stats));
  1994. }
  1995. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1996. struct ieee80211_vif *vif, int sset)
  1997. {
  1998. if (sset == ETH_SS_STATS)
  1999. return ATH9K_SSTATS_LEN;
  2000. return 0;
  2001. }
  2002. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  2003. #define AWDATA(elem) \
  2004. do { \
  2005. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  2006. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  2007. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  2008. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  2009. } while (0)
  2010. #define AWDATA_RX(elem) \
  2011. do { \
  2012. data[i++] = sc->debug.stats.rxstats.elem; \
  2013. } while (0)
  2014. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  2015. struct ieee80211_vif *vif,
  2016. struct ethtool_stats *stats, u64 *data)
  2017. {
  2018. struct ath_softc *sc = hw->priv;
  2019. int i = 0;
  2020. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  2021. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  2022. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  2023. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  2024. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  2025. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  2026. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  2027. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  2028. AWDATA_RX(rx_pkts_all);
  2029. AWDATA_RX(rx_bytes_all);
  2030. AWDATA(tx_pkts_all);
  2031. AWDATA(tx_bytes_all);
  2032. AWDATA(queued);
  2033. AWDATA(completed);
  2034. AWDATA(xretries);
  2035. AWDATA(a_aggr);
  2036. AWDATA(a_queued_hw);
  2037. AWDATA(a_queued_sw);
  2038. AWDATA(a_completed);
  2039. AWDATA(a_retries);
  2040. AWDATA(a_xretries);
  2041. AWDATA(fifo_underrun);
  2042. AWDATA(xtxop);
  2043. AWDATA(timer_exp);
  2044. AWDATA(desc_cfg_err);
  2045. AWDATA(data_underrun);
  2046. AWDATA(delim_underrun);
  2047. AWDATA_RX(decrypt_crc_err);
  2048. AWDATA_RX(phy_err);
  2049. AWDATA_RX(mic_err);
  2050. AWDATA_RX(pre_delim_crc_err);
  2051. AWDATA_RX(post_delim_crc_err);
  2052. AWDATA_RX(decrypt_busy_err);
  2053. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  2054. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  2055. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  2056. WARN_ON(i != ATH9K_SSTATS_LEN);
  2057. }
  2058. /* End of ethtool get-stats functions */
  2059. #endif
  2060. struct ieee80211_ops ath9k_ops = {
  2061. .tx = ath9k_tx,
  2062. .start = ath9k_start,
  2063. .stop = ath9k_stop,
  2064. .add_interface = ath9k_add_interface,
  2065. .change_interface = ath9k_change_interface,
  2066. .remove_interface = ath9k_remove_interface,
  2067. .config = ath9k_config,
  2068. .configure_filter = ath9k_configure_filter,
  2069. .sta_add = ath9k_sta_add,
  2070. .sta_remove = ath9k_sta_remove,
  2071. .sta_notify = ath9k_sta_notify,
  2072. .conf_tx = ath9k_conf_tx,
  2073. .bss_info_changed = ath9k_bss_info_changed,
  2074. .set_key = ath9k_set_key,
  2075. .get_tsf = ath9k_get_tsf,
  2076. .set_tsf = ath9k_set_tsf,
  2077. .reset_tsf = ath9k_reset_tsf,
  2078. .ampdu_action = ath9k_ampdu_action,
  2079. .get_survey = ath9k_get_survey,
  2080. .rfkill_poll = ath9k_rfkill_poll_state,
  2081. .set_coverage_class = ath9k_set_coverage_class,
  2082. .flush = ath9k_flush,
  2083. .tx_frames_pending = ath9k_tx_frames_pending,
  2084. .tx_last_beacon = ath9k_tx_last_beacon,
  2085. .get_stats = ath9k_get_stats,
  2086. .set_antenna = ath9k_set_antenna,
  2087. .get_antenna = ath9k_get_antenna,
  2088. #ifdef CONFIG_ATH9K_DEBUGFS
  2089. .get_et_sset_count = ath9k_get_et_sset_count,
  2090. .get_et_stats = ath9k_get_et_stats,
  2091. .get_et_strings = ath9k_get_et_strings,
  2092. #endif
  2093. };