patch_hdmi.c 70 KB

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  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. *
  10. * Authors:
  11. * Wu Fengguang <wfg@linux.intel.com>
  12. *
  13. * Maintained by:
  14. * Wu Fengguang <wfg@linux.intel.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the Free
  18. * Software Foundation; either version 2 of the License, or (at your option)
  19. * any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful, but
  22. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  23. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  24. * for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software Foundation,
  28. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29. */
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/slab.h>
  33. #include <linux/module.h>
  34. #include <sound/core.h>
  35. #include <sound/jack.h>
  36. #include <sound/asoundef.h>
  37. #include <sound/tlv.h>
  38. #include "hda_codec.h"
  39. #include "hda_local.h"
  40. #include "hda_jack.h"
  41. static bool static_hdmi_pcm;
  42. module_param(static_hdmi_pcm, bool, 0644);
  43. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  44. /*
  45. * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
  46. * could support N independent pipes, each of them can be connected to one or
  47. * more ports (DVI, HDMI or DisplayPort).
  48. *
  49. * The HDA correspondence of pipes/ports are converter/pin nodes.
  50. */
  51. #define MAX_HDMI_CVTS 8
  52. #define MAX_HDMI_PINS 8
  53. struct hdmi_spec_per_cvt {
  54. hda_nid_t cvt_nid;
  55. int assigned;
  56. unsigned int channels_min;
  57. unsigned int channels_max;
  58. u32 rates;
  59. u64 formats;
  60. unsigned int maxbps;
  61. };
  62. /* max. connections to a widget */
  63. #define HDA_MAX_CONNECTIONS 32
  64. struct hdmi_spec_per_pin {
  65. hda_nid_t pin_nid;
  66. int num_mux_nids;
  67. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  68. struct hda_codec *codec;
  69. struct hdmi_eld sink_eld;
  70. struct delayed_work work;
  71. int repoll_count;
  72. bool non_pcm;
  73. bool chmap_set; /* channel-map override by ALSA API? */
  74. unsigned char chmap[8]; /* ALSA API channel-map */
  75. };
  76. struct hdmi_spec {
  77. int num_cvts;
  78. struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
  79. hda_nid_t cvt_nids[MAX_HDMI_CVTS];
  80. int num_pins;
  81. struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
  82. struct hda_pcm pcm_rec[MAX_HDMI_PINS];
  83. unsigned int channels_max; /* max over all cvts */
  84. struct hdmi_eld temp_eld;
  85. /*
  86. * Non-generic ATI/NVIDIA specific
  87. */
  88. struct hda_multi_out multiout;
  89. struct hda_pcm_stream pcm_playback;
  90. };
  91. struct hdmi_audio_infoframe {
  92. u8 type; /* 0x84 */
  93. u8 ver; /* 0x01 */
  94. u8 len; /* 0x0a */
  95. u8 checksum;
  96. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  97. u8 SS01_SF24;
  98. u8 CXT04;
  99. u8 CA;
  100. u8 LFEPBL01_LSV36_DM_INH7;
  101. };
  102. struct dp_audio_infoframe {
  103. u8 type; /* 0x84 */
  104. u8 len; /* 0x1b */
  105. u8 ver; /* 0x11 << 2 */
  106. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  107. u8 SS01_SF24;
  108. u8 CXT04;
  109. u8 CA;
  110. u8 LFEPBL01_LSV36_DM_INH7;
  111. };
  112. union audio_infoframe {
  113. struct hdmi_audio_infoframe hdmi;
  114. struct dp_audio_infoframe dp;
  115. u8 bytes[0];
  116. };
  117. /*
  118. * CEA speaker placement:
  119. *
  120. * FLH FCH FRH
  121. * FLW FL FLC FC FRC FR FRW
  122. *
  123. * LFE
  124. * TC
  125. *
  126. * RL RLC RC RRC RR
  127. *
  128. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  129. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  130. */
  131. enum cea_speaker_placement {
  132. FL = (1 << 0), /* Front Left */
  133. FC = (1 << 1), /* Front Center */
  134. FR = (1 << 2), /* Front Right */
  135. FLC = (1 << 3), /* Front Left Center */
  136. FRC = (1 << 4), /* Front Right Center */
  137. RL = (1 << 5), /* Rear Left */
  138. RC = (1 << 6), /* Rear Center */
  139. RR = (1 << 7), /* Rear Right */
  140. RLC = (1 << 8), /* Rear Left Center */
  141. RRC = (1 << 9), /* Rear Right Center */
  142. LFE = (1 << 10), /* Low Frequency Effect */
  143. FLW = (1 << 11), /* Front Left Wide */
  144. FRW = (1 << 12), /* Front Right Wide */
  145. FLH = (1 << 13), /* Front Left High */
  146. FCH = (1 << 14), /* Front Center High */
  147. FRH = (1 << 15), /* Front Right High */
  148. TC = (1 << 16), /* Top Center */
  149. };
  150. /*
  151. * ELD SA bits in the CEA Speaker Allocation data block
  152. */
  153. static int eld_speaker_allocation_bits[] = {
  154. [0] = FL | FR,
  155. [1] = LFE,
  156. [2] = FC,
  157. [3] = RL | RR,
  158. [4] = RC,
  159. [5] = FLC | FRC,
  160. [6] = RLC | RRC,
  161. /* the following are not defined in ELD yet */
  162. [7] = FLW | FRW,
  163. [8] = FLH | FRH,
  164. [9] = TC,
  165. [10] = FCH,
  166. };
  167. struct cea_channel_speaker_allocation {
  168. int ca_index;
  169. int speakers[8];
  170. /* derived values, just for convenience */
  171. int channels;
  172. int spk_mask;
  173. };
  174. /*
  175. * ALSA sequence is:
  176. *
  177. * surround40 surround41 surround50 surround51 surround71
  178. * ch0 front left = = = =
  179. * ch1 front right = = = =
  180. * ch2 rear left = = = =
  181. * ch3 rear right = = = =
  182. * ch4 LFE center center center
  183. * ch5 LFE LFE
  184. * ch6 side left
  185. * ch7 side right
  186. *
  187. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  188. */
  189. static int hdmi_channel_mapping[0x32][8] = {
  190. /* stereo */
  191. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  192. /* 2.1 */
  193. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  194. /* Dolby Surround */
  195. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  196. /* surround40 */
  197. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  198. /* 4ch */
  199. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  200. /* surround41 */
  201. [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
  202. /* surround50 */
  203. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  204. /* surround51 */
  205. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  206. /* 7.1 */
  207. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  208. };
  209. /*
  210. * This is an ordered list!
  211. *
  212. * The preceding ones have better chances to be selected by
  213. * hdmi_channel_allocation().
  214. */
  215. static struct cea_channel_speaker_allocation channel_allocations[] = {
  216. /* channel: 7 6 5 4 3 2 1 0 */
  217. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  218. /* 2.1 */
  219. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  220. /* Dolby Surround */
  221. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  222. /* surround40 */
  223. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  224. /* surround41 */
  225. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  226. /* surround50 */
  227. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  228. /* surround51 */
  229. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  230. /* 6.1 */
  231. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  232. /* surround71 */
  233. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  234. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  235. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  236. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  237. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  238. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  239. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  240. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  241. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  242. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  243. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  244. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  245. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  246. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  247. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  248. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  249. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  250. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  251. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  252. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  253. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  254. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  255. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  256. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  257. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  258. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  259. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  260. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  261. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  262. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  263. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  264. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  265. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  266. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  267. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  268. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  269. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  270. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  271. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  272. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  273. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  274. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  275. };
  276. /*
  277. * HDMI routines
  278. */
  279. static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
  280. {
  281. int pin_idx;
  282. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  283. if (spec->pins[pin_idx].pin_nid == pin_nid)
  284. return pin_idx;
  285. snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
  286. return -EINVAL;
  287. }
  288. static int hinfo_to_pin_index(struct hdmi_spec *spec,
  289. struct hda_pcm_stream *hinfo)
  290. {
  291. int pin_idx;
  292. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  293. if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
  294. return pin_idx;
  295. snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
  296. return -EINVAL;
  297. }
  298. static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
  299. {
  300. int cvt_idx;
  301. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  302. if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
  303. return cvt_idx;
  304. snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
  305. return -EINVAL;
  306. }
  307. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  308. struct snd_ctl_elem_info *uinfo)
  309. {
  310. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  311. struct hdmi_spec *spec = codec->spec;
  312. struct hdmi_eld *eld;
  313. int pin_idx;
  314. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  315. pin_idx = kcontrol->private_value;
  316. eld = &spec->pins[pin_idx].sink_eld;
  317. mutex_lock(&eld->lock);
  318. uinfo->count = eld->eld_valid ? eld->eld_size : 0;
  319. mutex_unlock(&eld->lock);
  320. return 0;
  321. }
  322. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  323. struct snd_ctl_elem_value *ucontrol)
  324. {
  325. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  326. struct hdmi_spec *spec = codec->spec;
  327. struct hdmi_eld *eld;
  328. int pin_idx;
  329. pin_idx = kcontrol->private_value;
  330. eld = &spec->pins[pin_idx].sink_eld;
  331. mutex_lock(&eld->lock);
  332. if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
  333. mutex_unlock(&eld->lock);
  334. snd_BUG();
  335. return -EINVAL;
  336. }
  337. memset(ucontrol->value.bytes.data, 0,
  338. ARRAY_SIZE(ucontrol->value.bytes.data));
  339. if (eld->eld_valid)
  340. memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
  341. eld->eld_size);
  342. mutex_unlock(&eld->lock);
  343. return 0;
  344. }
  345. static struct snd_kcontrol_new eld_bytes_ctl = {
  346. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  347. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  348. .name = "ELD",
  349. .info = hdmi_eld_ctl_info,
  350. .get = hdmi_eld_ctl_get,
  351. };
  352. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
  353. int device)
  354. {
  355. struct snd_kcontrol *kctl;
  356. struct hdmi_spec *spec = codec->spec;
  357. int err;
  358. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  359. if (!kctl)
  360. return -ENOMEM;
  361. kctl->private_value = pin_idx;
  362. kctl->id.device = device;
  363. err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
  364. if (err < 0)
  365. return err;
  366. return 0;
  367. }
  368. #ifdef BE_PARANOID
  369. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  370. int *packet_index, int *byte_index)
  371. {
  372. int val;
  373. val = snd_hda_codec_read(codec, pin_nid, 0,
  374. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  375. *packet_index = val >> 5;
  376. *byte_index = val & 0x1f;
  377. }
  378. #endif
  379. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  380. int packet_index, int byte_index)
  381. {
  382. int val;
  383. val = (packet_index << 5) | (byte_index & 0x1f);
  384. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  385. }
  386. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  387. unsigned char val)
  388. {
  389. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  390. }
  391. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  392. {
  393. /* Unmute */
  394. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  395. snd_hda_codec_write(codec, pin_nid, 0,
  396. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  397. /* Enable pin out: some machines with GM965 gets broken output when
  398. * the pin is disabled or changed while using with HDMI
  399. */
  400. snd_hda_codec_write(codec, pin_nid, 0,
  401. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  402. }
  403. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
  404. {
  405. return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
  406. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  407. }
  408. static void hdmi_set_channel_count(struct hda_codec *codec,
  409. hda_nid_t cvt_nid, int chs)
  410. {
  411. if (chs != hdmi_get_channel_count(codec, cvt_nid))
  412. snd_hda_codec_write(codec, cvt_nid, 0,
  413. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  414. }
  415. /*
  416. * Channel mapping routines
  417. */
  418. /*
  419. * Compute derived values in channel_allocations[].
  420. */
  421. static void init_channel_allocations(void)
  422. {
  423. int i, j;
  424. struct cea_channel_speaker_allocation *p;
  425. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  426. p = channel_allocations + i;
  427. p->channels = 0;
  428. p->spk_mask = 0;
  429. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  430. if (p->speakers[j]) {
  431. p->channels++;
  432. p->spk_mask |= p->speakers[j];
  433. }
  434. }
  435. }
  436. static int get_channel_allocation_order(int ca)
  437. {
  438. int i;
  439. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  440. if (channel_allocations[i].ca_index == ca)
  441. break;
  442. }
  443. return i;
  444. }
  445. /*
  446. * The transformation takes two steps:
  447. *
  448. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  449. * spk_mask => (channel_allocations[]) => ai->CA
  450. *
  451. * TODO: it could select the wrong CA from multiple candidates.
  452. */
  453. static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
  454. {
  455. int i;
  456. int ca = 0;
  457. int spk_mask = 0;
  458. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  459. /*
  460. * CA defaults to 0 for basic stereo audio
  461. */
  462. if (channels <= 2)
  463. return 0;
  464. /*
  465. * expand ELD's speaker allocation mask
  466. *
  467. * ELD tells the speaker mask in a compact(paired) form,
  468. * expand ELD's notions to match the ones used by Audio InfoFrame.
  469. */
  470. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  471. if (eld->info.spk_alloc & (1 << i))
  472. spk_mask |= eld_speaker_allocation_bits[i];
  473. }
  474. /* search for the first working match in the CA table */
  475. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  476. if (channels == channel_allocations[i].channels &&
  477. (spk_mask & channel_allocations[i].spk_mask) ==
  478. channel_allocations[i].spk_mask) {
  479. ca = channel_allocations[i].ca_index;
  480. break;
  481. }
  482. }
  483. snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
  484. snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  485. ca, channels, buf);
  486. return ca;
  487. }
  488. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  489. hda_nid_t pin_nid)
  490. {
  491. #ifdef CONFIG_SND_DEBUG_VERBOSE
  492. int i;
  493. int slot;
  494. for (i = 0; i < 8; i++) {
  495. slot = snd_hda_codec_read(codec, pin_nid, 0,
  496. AC_VERB_GET_HDMI_CHAN_SLOT, i);
  497. printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
  498. slot >> 4, slot & 0xf);
  499. }
  500. #endif
  501. }
  502. static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
  503. hda_nid_t pin_nid,
  504. bool non_pcm,
  505. int ca)
  506. {
  507. int i;
  508. int err;
  509. int order;
  510. int non_pcm_mapping[8];
  511. order = get_channel_allocation_order(ca);
  512. if (hdmi_channel_mapping[ca][1] == 0) {
  513. for (i = 0; i < channel_allocations[order].channels; i++)
  514. hdmi_channel_mapping[ca][i] = i | (i << 4);
  515. for (; i < 8; i++)
  516. hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
  517. }
  518. if (non_pcm) {
  519. for (i = 0; i < channel_allocations[order].channels; i++)
  520. non_pcm_mapping[i] = i | (i << 4);
  521. for (; i < 8; i++)
  522. non_pcm_mapping[i] = 0xf | (i << 4);
  523. }
  524. for (i = 0; i < 8; i++) {
  525. err = snd_hda_codec_write(codec, pin_nid, 0,
  526. AC_VERB_SET_HDMI_CHAN_SLOT,
  527. non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
  528. if (err) {
  529. snd_printdd(KERN_NOTICE
  530. "HDMI: channel mapping failed\n");
  531. break;
  532. }
  533. }
  534. hdmi_debug_channel_mapping(codec, pin_nid);
  535. }
  536. struct channel_map_table {
  537. unsigned char map; /* ALSA API channel map position */
  538. unsigned char cea_slot; /* CEA slot value */
  539. int spk_mask; /* speaker position bit mask */
  540. };
  541. static struct channel_map_table map_tables[] = {
  542. { SNDRV_CHMAP_FL, 0x00, FL },
  543. { SNDRV_CHMAP_FR, 0x01, FR },
  544. { SNDRV_CHMAP_RL, 0x04, RL },
  545. { SNDRV_CHMAP_RR, 0x05, RR },
  546. { SNDRV_CHMAP_LFE, 0x02, LFE },
  547. { SNDRV_CHMAP_FC, 0x03, FC },
  548. { SNDRV_CHMAP_RLC, 0x06, RLC },
  549. { SNDRV_CHMAP_RRC, 0x07, RRC },
  550. {} /* terminator */
  551. };
  552. /* from ALSA API channel position to speaker bit mask */
  553. static int to_spk_mask(unsigned char c)
  554. {
  555. struct channel_map_table *t = map_tables;
  556. for (; t->map; t++) {
  557. if (t->map == c)
  558. return t->spk_mask;
  559. }
  560. return 0;
  561. }
  562. /* from ALSA API channel position to CEA slot */
  563. static int to_cea_slot(unsigned char c)
  564. {
  565. struct channel_map_table *t = map_tables;
  566. for (; t->map; t++) {
  567. if (t->map == c)
  568. return t->cea_slot;
  569. }
  570. return 0x0f;
  571. }
  572. /* from CEA slot to ALSA API channel position */
  573. static int from_cea_slot(unsigned char c)
  574. {
  575. struct channel_map_table *t = map_tables;
  576. for (; t->map; t++) {
  577. if (t->cea_slot == c)
  578. return t->map;
  579. }
  580. return 0;
  581. }
  582. /* from speaker bit mask to ALSA API channel position */
  583. static int spk_to_chmap(int spk)
  584. {
  585. struct channel_map_table *t = map_tables;
  586. for (; t->map; t++) {
  587. if (t->spk_mask == spk)
  588. return t->map;
  589. }
  590. return 0;
  591. }
  592. /* get the CA index corresponding to the given ALSA API channel map */
  593. static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
  594. {
  595. int i, spks = 0, spk_mask = 0;
  596. for (i = 0; i < chs; i++) {
  597. int mask = to_spk_mask(map[i]);
  598. if (mask) {
  599. spk_mask |= mask;
  600. spks++;
  601. }
  602. }
  603. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  604. if ((chs == channel_allocations[i].channels ||
  605. spks == channel_allocations[i].channels) &&
  606. (spk_mask & channel_allocations[i].spk_mask) ==
  607. channel_allocations[i].spk_mask)
  608. return channel_allocations[i].ca_index;
  609. }
  610. return -1;
  611. }
  612. /* set up the channel slots for the given ALSA API channel map */
  613. static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
  614. hda_nid_t pin_nid,
  615. int chs, unsigned char *map)
  616. {
  617. int i;
  618. for (i = 0; i < 8; i++) {
  619. int val, err;
  620. if (i < chs)
  621. val = to_cea_slot(map[i]);
  622. else
  623. val = 0xf;
  624. val |= (i << 4);
  625. err = snd_hda_codec_write(codec, pin_nid, 0,
  626. AC_VERB_SET_HDMI_CHAN_SLOT, val);
  627. if (err)
  628. return -EINVAL;
  629. }
  630. return 0;
  631. }
  632. /* store ALSA API channel map from the current default map */
  633. static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
  634. {
  635. int i;
  636. for (i = 0; i < 8; i++) {
  637. if (i < channel_allocations[ca].channels)
  638. map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
  639. else
  640. map[i] = 0;
  641. }
  642. }
  643. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  644. hda_nid_t pin_nid, bool non_pcm, int ca,
  645. int channels, unsigned char *map,
  646. bool chmap_set)
  647. {
  648. if (!non_pcm && chmap_set) {
  649. hdmi_manual_setup_channel_mapping(codec, pin_nid,
  650. channels, map);
  651. } else {
  652. hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
  653. hdmi_setup_fake_chmap(map, ca);
  654. }
  655. }
  656. /*
  657. * Audio InfoFrame routines
  658. */
  659. /*
  660. * Enable Audio InfoFrame Transmission
  661. */
  662. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  663. hda_nid_t pin_nid)
  664. {
  665. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  666. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  667. AC_DIPXMIT_BEST);
  668. }
  669. /*
  670. * Disable Audio InfoFrame Transmission
  671. */
  672. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  673. hda_nid_t pin_nid)
  674. {
  675. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  676. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  677. AC_DIPXMIT_DISABLE);
  678. }
  679. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  680. {
  681. #ifdef CONFIG_SND_DEBUG_VERBOSE
  682. int i;
  683. int size;
  684. size = snd_hdmi_get_eld_size(codec, pin_nid);
  685. printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
  686. for (i = 0; i < 8; i++) {
  687. size = snd_hda_codec_read(codec, pin_nid, 0,
  688. AC_VERB_GET_HDMI_DIP_SIZE, i);
  689. printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  690. }
  691. #endif
  692. }
  693. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  694. {
  695. #ifdef BE_PARANOID
  696. int i, j;
  697. int size;
  698. int pi, bi;
  699. for (i = 0; i < 8; i++) {
  700. size = snd_hda_codec_read(codec, pin_nid, 0,
  701. AC_VERB_GET_HDMI_DIP_SIZE, i);
  702. if (size == 0)
  703. continue;
  704. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  705. for (j = 1; j < 1000; j++) {
  706. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  707. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  708. if (pi != i)
  709. snd_printd(KERN_INFO "dip index %d: %d != %d\n",
  710. bi, pi, i);
  711. if (bi == 0) /* byte index wrapped around */
  712. break;
  713. }
  714. snd_printd(KERN_INFO
  715. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  716. i, size, j);
  717. }
  718. #endif
  719. }
  720. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  721. {
  722. u8 *bytes = (u8 *)hdmi_ai;
  723. u8 sum = 0;
  724. int i;
  725. hdmi_ai->checksum = 0;
  726. for (i = 0; i < sizeof(*hdmi_ai); i++)
  727. sum += bytes[i];
  728. hdmi_ai->checksum = -sum;
  729. }
  730. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  731. hda_nid_t pin_nid,
  732. u8 *dip, int size)
  733. {
  734. int i;
  735. hdmi_debug_dip_size(codec, pin_nid);
  736. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  737. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  738. for (i = 0; i < size; i++)
  739. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  740. }
  741. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  742. u8 *dip, int size)
  743. {
  744. u8 val;
  745. int i;
  746. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  747. != AC_DIPXMIT_BEST)
  748. return false;
  749. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  750. for (i = 0; i < size; i++) {
  751. val = snd_hda_codec_read(codec, pin_nid, 0,
  752. AC_VERB_GET_HDMI_DIP_DATA, 0);
  753. if (val != dip[i])
  754. return false;
  755. }
  756. return true;
  757. }
  758. static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
  759. bool non_pcm,
  760. struct snd_pcm_substream *substream)
  761. {
  762. struct hdmi_spec *spec = codec->spec;
  763. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  764. hda_nid_t pin_nid = per_pin->pin_nid;
  765. int channels = substream->runtime->channels;
  766. struct hdmi_eld *eld;
  767. int ca;
  768. union audio_infoframe ai;
  769. eld = &spec->pins[pin_idx].sink_eld;
  770. if (!eld->monitor_present)
  771. return;
  772. if (!non_pcm && per_pin->chmap_set)
  773. ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
  774. else
  775. ca = hdmi_channel_allocation(eld, channels);
  776. if (ca < 0)
  777. ca = 0;
  778. memset(&ai, 0, sizeof(ai));
  779. if (eld->info.conn_type == 0) { /* HDMI */
  780. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  781. hdmi_ai->type = 0x84;
  782. hdmi_ai->ver = 0x01;
  783. hdmi_ai->len = 0x0a;
  784. hdmi_ai->CC02_CT47 = channels - 1;
  785. hdmi_ai->CA = ca;
  786. hdmi_checksum_audio_infoframe(hdmi_ai);
  787. } else if (eld->info.conn_type == 1) { /* DisplayPort */
  788. struct dp_audio_infoframe *dp_ai = &ai.dp;
  789. dp_ai->type = 0x84;
  790. dp_ai->len = 0x1b;
  791. dp_ai->ver = 0x11 << 2;
  792. dp_ai->CC02_CT47 = channels - 1;
  793. dp_ai->CA = ca;
  794. } else {
  795. snd_printd("HDMI: unknown connection type at pin %d\n",
  796. pin_nid);
  797. return;
  798. }
  799. /*
  800. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  801. * sizeof(*dp_ai) to avoid partial match/update problems when
  802. * the user switches between HDMI/DP monitors.
  803. */
  804. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  805. sizeof(ai))) {
  806. snd_printdd("hdmi_setup_audio_infoframe: "
  807. "pin=%d channels=%d\n",
  808. pin_nid,
  809. channels);
  810. hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
  811. channels, per_pin->chmap,
  812. per_pin->chmap_set);
  813. hdmi_stop_infoframe_trans(codec, pin_nid);
  814. hdmi_fill_audio_infoframe(codec, pin_nid,
  815. ai.bytes, sizeof(ai));
  816. hdmi_start_infoframe_trans(codec, pin_nid);
  817. } else {
  818. /* For non-pcm audio switch, setup new channel mapping
  819. * accordingly */
  820. if (per_pin->non_pcm != non_pcm)
  821. hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
  822. channels, per_pin->chmap,
  823. per_pin->chmap_set);
  824. }
  825. per_pin->non_pcm = non_pcm;
  826. }
  827. /*
  828. * Unsolicited events
  829. */
  830. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
  831. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  832. {
  833. struct hdmi_spec *spec = codec->spec;
  834. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  835. int pin_nid;
  836. int pin_idx;
  837. struct hda_jack_tbl *jack;
  838. jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
  839. if (!jack)
  840. return;
  841. pin_nid = jack->nid;
  842. jack->jack_dirty = 1;
  843. _snd_printd(SND_PR_VERBOSE,
  844. "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  845. codec->addr, pin_nid,
  846. !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
  847. pin_idx = pin_nid_to_pin_index(spec, pin_nid);
  848. if (pin_idx < 0)
  849. return;
  850. hdmi_present_sense(&spec->pins[pin_idx], 1);
  851. snd_hda_jack_report_sync(codec);
  852. }
  853. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  854. {
  855. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  856. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  857. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  858. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  859. printk(KERN_INFO
  860. "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  861. codec->addr,
  862. tag,
  863. subtag,
  864. cp_state,
  865. cp_ready);
  866. /* TODO */
  867. if (cp_state)
  868. ;
  869. if (cp_ready)
  870. ;
  871. }
  872. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  873. {
  874. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  875. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  876. if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
  877. snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
  878. return;
  879. }
  880. if (subtag == 0)
  881. hdmi_intrinsic_event(codec, res);
  882. else
  883. hdmi_non_intrinsic_event(codec, res);
  884. }
  885. /*
  886. * Callbacks
  887. */
  888. /* HBR should be Non-PCM, 8 channels */
  889. #define is_hbr_format(format) \
  890. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  891. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  892. hda_nid_t pin_nid, u32 stream_tag, int format)
  893. {
  894. int pinctl;
  895. int new_pinctl = 0;
  896. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  897. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  898. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  899. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  900. if (is_hbr_format(format))
  901. new_pinctl |= AC_PINCTL_EPT_HBR;
  902. else
  903. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  904. snd_printdd("hdmi_setup_stream: "
  905. "NID=0x%x, %spinctl=0x%x\n",
  906. pin_nid,
  907. pinctl == new_pinctl ? "" : "new-",
  908. new_pinctl);
  909. if (pinctl != new_pinctl)
  910. snd_hda_codec_write(codec, pin_nid, 0,
  911. AC_VERB_SET_PIN_WIDGET_CONTROL,
  912. new_pinctl);
  913. }
  914. if (is_hbr_format(format) && !new_pinctl) {
  915. snd_printdd("hdmi_setup_stream: HBR is not supported\n");
  916. return -EINVAL;
  917. }
  918. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  919. return 0;
  920. }
  921. /*
  922. * HDA PCM callbacks
  923. */
  924. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  925. struct hda_codec *codec,
  926. struct snd_pcm_substream *substream)
  927. {
  928. struct hdmi_spec *spec = codec->spec;
  929. struct snd_pcm_runtime *runtime = substream->runtime;
  930. int pin_idx, cvt_idx, mux_idx = 0;
  931. struct hdmi_spec_per_pin *per_pin;
  932. struct hdmi_eld *eld;
  933. struct hdmi_spec_per_cvt *per_cvt = NULL;
  934. /* Validate hinfo */
  935. pin_idx = hinfo_to_pin_index(spec, hinfo);
  936. if (snd_BUG_ON(pin_idx < 0))
  937. return -EINVAL;
  938. per_pin = &spec->pins[pin_idx];
  939. eld = &per_pin->sink_eld;
  940. /* Dynamically assign converter to stream */
  941. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  942. per_cvt = &spec->cvts[cvt_idx];
  943. /* Must not already be assigned */
  944. if (per_cvt->assigned)
  945. continue;
  946. /* Must be in pin's mux's list of converters */
  947. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  948. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  949. break;
  950. /* Not in mux list */
  951. if (mux_idx == per_pin->num_mux_nids)
  952. continue;
  953. break;
  954. }
  955. /* No free converters */
  956. if (cvt_idx == spec->num_cvts)
  957. return -ENODEV;
  958. /* Claim converter */
  959. per_cvt->assigned = 1;
  960. hinfo->nid = per_cvt->cvt_nid;
  961. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  962. AC_VERB_SET_CONNECT_SEL,
  963. mux_idx);
  964. snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
  965. /* Initially set the converter's capabilities */
  966. hinfo->channels_min = per_cvt->channels_min;
  967. hinfo->channels_max = per_cvt->channels_max;
  968. hinfo->rates = per_cvt->rates;
  969. hinfo->formats = per_cvt->formats;
  970. hinfo->maxbps = per_cvt->maxbps;
  971. /* Restrict capabilities by ELD if this isn't disabled */
  972. if (!static_hdmi_pcm && eld->eld_valid) {
  973. snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
  974. if (hinfo->channels_min > hinfo->channels_max ||
  975. !hinfo->rates || !hinfo->formats) {
  976. per_cvt->assigned = 0;
  977. hinfo->nid = 0;
  978. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  979. return -ENODEV;
  980. }
  981. }
  982. /* Store the updated parameters */
  983. runtime->hw.channels_min = hinfo->channels_min;
  984. runtime->hw.channels_max = hinfo->channels_max;
  985. runtime->hw.formats = hinfo->formats;
  986. runtime->hw.rates = hinfo->rates;
  987. snd_pcm_hw_constraint_step(substream->runtime, 0,
  988. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  989. return 0;
  990. }
  991. /*
  992. * HDA/HDMI auto parsing
  993. */
  994. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  995. {
  996. struct hdmi_spec *spec = codec->spec;
  997. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  998. hda_nid_t pin_nid = per_pin->pin_nid;
  999. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  1000. snd_printk(KERN_WARNING
  1001. "HDMI: pin %d wcaps %#x "
  1002. "does not support connection list\n",
  1003. pin_nid, get_wcaps(codec, pin_nid));
  1004. return -EINVAL;
  1005. }
  1006. per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
  1007. per_pin->mux_nids,
  1008. HDA_MAX_CONNECTIONS);
  1009. return 0;
  1010. }
  1011. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
  1012. {
  1013. struct hda_codec *codec = per_pin->codec;
  1014. struct hdmi_spec *spec = codec->spec;
  1015. struct hdmi_eld *eld = &spec->temp_eld;
  1016. struct hdmi_eld *pin_eld = &per_pin->sink_eld;
  1017. hda_nid_t pin_nid = per_pin->pin_nid;
  1018. /*
  1019. * Always execute a GetPinSense verb here, even when called from
  1020. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  1021. * response's PD bit is not the real PD value, but indicates that
  1022. * the real PD value changed. An older version of the HD-audio
  1023. * specification worked this way. Hence, we just ignore the data in
  1024. * the unsolicited response to avoid custom WARs.
  1025. */
  1026. int present = snd_hda_pin_sense(codec, pin_nid);
  1027. bool update_eld = false;
  1028. bool eld_changed = false;
  1029. pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  1030. if (pin_eld->monitor_present)
  1031. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  1032. else
  1033. eld->eld_valid = false;
  1034. _snd_printd(SND_PR_VERBOSE,
  1035. "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  1036. codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
  1037. if (eld->eld_valid) {
  1038. if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
  1039. &eld->eld_size) < 0)
  1040. eld->eld_valid = false;
  1041. else {
  1042. memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
  1043. if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
  1044. eld->eld_size) < 0)
  1045. eld->eld_valid = false;
  1046. }
  1047. if (eld->eld_valid) {
  1048. snd_hdmi_show_eld(&eld->info);
  1049. update_eld = true;
  1050. }
  1051. else if (repoll) {
  1052. queue_delayed_work(codec->bus->workq,
  1053. &per_pin->work,
  1054. msecs_to_jiffies(300));
  1055. return;
  1056. }
  1057. }
  1058. mutex_lock(&pin_eld->lock);
  1059. if (pin_eld->eld_valid && !eld->eld_valid)
  1060. update_eld = true;
  1061. if (update_eld) {
  1062. pin_eld->eld_valid = eld->eld_valid;
  1063. eld_changed = memcmp(pin_eld->eld_buffer, eld->eld_buffer,
  1064. eld->eld_size) != 0;
  1065. if (eld_changed)
  1066. memcpy(pin_eld->eld_buffer, eld->eld_buffer,
  1067. eld->eld_size);
  1068. pin_eld->eld_size = eld->eld_size;
  1069. pin_eld->info = eld->info;
  1070. }
  1071. mutex_unlock(&pin_eld->lock);
  1072. }
  1073. static void hdmi_repoll_eld(struct work_struct *work)
  1074. {
  1075. struct hdmi_spec_per_pin *per_pin =
  1076. container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
  1077. if (per_pin->repoll_count++ > 6)
  1078. per_pin->repoll_count = 0;
  1079. hdmi_present_sense(per_pin, per_pin->repoll_count);
  1080. }
  1081. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1082. hda_nid_t nid);
  1083. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  1084. {
  1085. struct hdmi_spec *spec = codec->spec;
  1086. unsigned int caps, config;
  1087. int pin_idx;
  1088. struct hdmi_spec_per_pin *per_pin;
  1089. int err;
  1090. caps = snd_hda_query_pin_caps(codec, pin_nid);
  1091. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  1092. return 0;
  1093. config = snd_hda_codec_get_pincfg(codec, pin_nid);
  1094. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
  1095. return 0;
  1096. if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
  1097. return -E2BIG;
  1098. if (codec->vendor_id == 0x80862807)
  1099. intel_haswell_fixup_connect_list(codec, pin_nid);
  1100. pin_idx = spec->num_pins;
  1101. per_pin = &spec->pins[pin_idx];
  1102. per_pin->pin_nid = pin_nid;
  1103. per_pin->non_pcm = false;
  1104. err = hdmi_read_pin_conn(codec, pin_idx);
  1105. if (err < 0)
  1106. return err;
  1107. spec->num_pins++;
  1108. return 0;
  1109. }
  1110. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1111. {
  1112. struct hdmi_spec *spec = codec->spec;
  1113. int cvt_idx;
  1114. struct hdmi_spec_per_cvt *per_cvt;
  1115. unsigned int chans;
  1116. int err;
  1117. if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
  1118. return -E2BIG;
  1119. chans = get_wcaps(codec, cvt_nid);
  1120. chans = get_wcaps_channels(chans);
  1121. cvt_idx = spec->num_cvts;
  1122. per_cvt = &spec->cvts[cvt_idx];
  1123. per_cvt->cvt_nid = cvt_nid;
  1124. per_cvt->channels_min = 2;
  1125. if (chans <= 16) {
  1126. per_cvt->channels_max = chans;
  1127. if (chans > spec->channels_max)
  1128. spec->channels_max = chans;
  1129. }
  1130. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  1131. &per_cvt->rates,
  1132. &per_cvt->formats,
  1133. &per_cvt->maxbps);
  1134. if (err < 0)
  1135. return err;
  1136. spec->cvt_nids[spec->num_cvts++] = cvt_nid;
  1137. return 0;
  1138. }
  1139. static int hdmi_parse_codec(struct hda_codec *codec)
  1140. {
  1141. hda_nid_t nid;
  1142. int i, nodes;
  1143. nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
  1144. if (!nid || nodes < 0) {
  1145. snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
  1146. return -EINVAL;
  1147. }
  1148. for (i = 0; i < nodes; i++, nid++) {
  1149. unsigned int caps;
  1150. unsigned int type;
  1151. caps = get_wcaps(codec, nid);
  1152. type = get_wcaps_type(caps);
  1153. if (!(caps & AC_WCAP_DIGITAL))
  1154. continue;
  1155. switch (type) {
  1156. case AC_WID_AUD_OUT:
  1157. hdmi_add_cvt(codec, nid);
  1158. break;
  1159. case AC_WID_PIN:
  1160. hdmi_add_pin(codec, nid);
  1161. break;
  1162. }
  1163. }
  1164. #ifdef CONFIG_PM
  1165. /* We're seeing some problems with unsolicited hot plug events on
  1166. * PantherPoint after S3, if this is not enabled */
  1167. if (codec->vendor_id == 0x80862806)
  1168. codec->bus->power_keep_link_on = 1;
  1169. /*
  1170. * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
  1171. * can be lost and presence sense verb will become inaccurate if the
  1172. * HDA link is powered off at hot plug or hw initialization time.
  1173. */
  1174. else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
  1175. AC_PWRST_EPSS))
  1176. codec->bus->power_keep_link_on = 1;
  1177. #endif
  1178. return 0;
  1179. }
  1180. /*
  1181. */
  1182. static char *get_hdmi_pcm_name(int idx)
  1183. {
  1184. static char names[MAX_HDMI_PINS][8];
  1185. sprintf(&names[idx][0], "HDMI %d", idx);
  1186. return &names[idx][0];
  1187. }
  1188. static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1189. {
  1190. struct hda_spdif_out *spdif;
  1191. bool non_pcm;
  1192. mutex_lock(&codec->spdif_mutex);
  1193. spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
  1194. non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
  1195. mutex_unlock(&codec->spdif_mutex);
  1196. return non_pcm;
  1197. }
  1198. /*
  1199. * HDMI callbacks
  1200. */
  1201. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1202. struct hda_codec *codec,
  1203. unsigned int stream_tag,
  1204. unsigned int format,
  1205. struct snd_pcm_substream *substream)
  1206. {
  1207. hda_nid_t cvt_nid = hinfo->nid;
  1208. struct hdmi_spec *spec = codec->spec;
  1209. int pin_idx = hinfo_to_pin_index(spec, hinfo);
  1210. hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
  1211. bool non_pcm;
  1212. non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
  1213. hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
  1214. hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
  1215. return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  1216. }
  1217. static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  1218. struct hda_codec *codec,
  1219. struct snd_pcm_substream *substream)
  1220. {
  1221. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  1222. return 0;
  1223. }
  1224. static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
  1225. struct hda_codec *codec,
  1226. struct snd_pcm_substream *substream)
  1227. {
  1228. struct hdmi_spec *spec = codec->spec;
  1229. int cvt_idx, pin_idx;
  1230. struct hdmi_spec_per_cvt *per_cvt;
  1231. struct hdmi_spec_per_pin *per_pin;
  1232. if (hinfo->nid) {
  1233. cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
  1234. if (snd_BUG_ON(cvt_idx < 0))
  1235. return -EINVAL;
  1236. per_cvt = &spec->cvts[cvt_idx];
  1237. snd_BUG_ON(!per_cvt->assigned);
  1238. per_cvt->assigned = 0;
  1239. hinfo->nid = 0;
  1240. pin_idx = hinfo_to_pin_index(spec, hinfo);
  1241. if (snd_BUG_ON(pin_idx < 0))
  1242. return -EINVAL;
  1243. per_pin = &spec->pins[pin_idx];
  1244. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1245. per_pin->chmap_set = false;
  1246. memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
  1247. }
  1248. return 0;
  1249. }
  1250. static const struct hda_pcm_ops generic_ops = {
  1251. .open = hdmi_pcm_open,
  1252. .close = hdmi_pcm_close,
  1253. .prepare = generic_hdmi_playback_pcm_prepare,
  1254. .cleanup = generic_hdmi_playback_pcm_cleanup,
  1255. };
  1256. /*
  1257. * ALSA API channel-map control callbacks
  1258. */
  1259. static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
  1260. struct snd_ctl_elem_info *uinfo)
  1261. {
  1262. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1263. struct hda_codec *codec = info->private_data;
  1264. struct hdmi_spec *spec = codec->spec;
  1265. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1266. uinfo->count = spec->channels_max;
  1267. uinfo->value.integer.min = 0;
  1268. uinfo->value.integer.max = SNDRV_CHMAP_LAST;
  1269. return 0;
  1270. }
  1271. static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
  1272. unsigned int size, unsigned int __user *tlv)
  1273. {
  1274. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1275. struct hda_codec *codec = info->private_data;
  1276. struct hdmi_spec *spec = codec->spec;
  1277. const unsigned int valid_mask =
  1278. FL | FR | RL | RR | LFE | FC | RLC | RRC;
  1279. unsigned int __user *dst;
  1280. int chs, count = 0;
  1281. if (size < 8)
  1282. return -ENOMEM;
  1283. if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
  1284. return -EFAULT;
  1285. size -= 8;
  1286. dst = tlv + 2;
  1287. for (chs = 2; chs <= spec->channels_max; chs++) {
  1288. int i, c;
  1289. struct cea_channel_speaker_allocation *cap;
  1290. cap = channel_allocations;
  1291. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
  1292. int chs_bytes = chs * 4;
  1293. if (cap->channels != chs)
  1294. continue;
  1295. if (cap->spk_mask & ~valid_mask)
  1296. continue;
  1297. if (size < 8)
  1298. return -ENOMEM;
  1299. if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
  1300. put_user(chs_bytes, dst + 1))
  1301. return -EFAULT;
  1302. dst += 2;
  1303. size -= 8;
  1304. count += 8;
  1305. if (size < chs_bytes)
  1306. return -ENOMEM;
  1307. size -= chs_bytes;
  1308. count += chs_bytes;
  1309. for (c = 7; c >= 0; c--) {
  1310. int spk = cap->speakers[c];
  1311. if (!spk)
  1312. continue;
  1313. if (put_user(spk_to_chmap(spk), dst))
  1314. return -EFAULT;
  1315. dst++;
  1316. }
  1317. }
  1318. }
  1319. if (put_user(count, tlv + 1))
  1320. return -EFAULT;
  1321. return 0;
  1322. }
  1323. static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
  1324. struct snd_ctl_elem_value *ucontrol)
  1325. {
  1326. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1327. struct hda_codec *codec = info->private_data;
  1328. struct hdmi_spec *spec = codec->spec;
  1329. int pin_idx = kcontrol->private_value;
  1330. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1331. int i;
  1332. for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
  1333. ucontrol->value.integer.value[i] = per_pin->chmap[i];
  1334. return 0;
  1335. }
  1336. static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
  1337. struct snd_ctl_elem_value *ucontrol)
  1338. {
  1339. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1340. struct hda_codec *codec = info->private_data;
  1341. struct hdmi_spec *spec = codec->spec;
  1342. int pin_idx = kcontrol->private_value;
  1343. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1344. unsigned int ctl_idx;
  1345. struct snd_pcm_substream *substream;
  1346. unsigned char chmap[8];
  1347. int i, ca, prepared = 0;
  1348. ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1349. substream = snd_pcm_chmap_substream(info, ctl_idx);
  1350. if (!substream || !substream->runtime)
  1351. return 0; /* just for avoiding error from alsactl restore */
  1352. switch (substream->runtime->status->state) {
  1353. case SNDRV_PCM_STATE_OPEN:
  1354. case SNDRV_PCM_STATE_SETUP:
  1355. break;
  1356. case SNDRV_PCM_STATE_PREPARED:
  1357. prepared = 1;
  1358. break;
  1359. default:
  1360. return -EBUSY;
  1361. }
  1362. memset(chmap, 0, sizeof(chmap));
  1363. for (i = 0; i < ARRAY_SIZE(chmap); i++)
  1364. chmap[i] = ucontrol->value.integer.value[i];
  1365. if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
  1366. return 0;
  1367. ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
  1368. if (ca < 0)
  1369. return -EINVAL;
  1370. per_pin->chmap_set = true;
  1371. memcpy(per_pin->chmap, chmap, sizeof(chmap));
  1372. if (prepared)
  1373. hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
  1374. substream);
  1375. return 0;
  1376. }
  1377. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1378. {
  1379. struct hdmi_spec *spec = codec->spec;
  1380. int pin_idx;
  1381. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1382. struct hda_pcm *info;
  1383. struct hda_pcm_stream *pstr;
  1384. info = &spec->pcm_rec[pin_idx];
  1385. info->name = get_hdmi_pcm_name(pin_idx);
  1386. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1387. info->own_chmap = true;
  1388. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1389. pstr->substreams = 1;
  1390. pstr->ops = generic_ops;
  1391. /* other pstr fields are set in open */
  1392. }
  1393. codec->num_pcms = spec->num_pins;
  1394. codec->pcm_info = spec->pcm_rec;
  1395. return 0;
  1396. }
  1397. static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
  1398. {
  1399. char hdmi_str[32] = "HDMI/DP";
  1400. struct hdmi_spec *spec = codec->spec;
  1401. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1402. int pcmdev = spec->pcm_rec[pin_idx].device;
  1403. if (pcmdev > 0)
  1404. sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
  1405. return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
  1406. }
  1407. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1408. {
  1409. struct hdmi_spec *spec = codec->spec;
  1410. int err;
  1411. int pin_idx;
  1412. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1413. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1414. err = generic_hdmi_build_jack(codec, pin_idx);
  1415. if (err < 0)
  1416. return err;
  1417. err = snd_hda_create_dig_out_ctls(codec,
  1418. per_pin->pin_nid,
  1419. per_pin->mux_nids[0],
  1420. HDA_PCM_TYPE_HDMI);
  1421. if (err < 0)
  1422. return err;
  1423. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1424. /* add control for ELD Bytes */
  1425. err = hdmi_create_eld_ctl(codec,
  1426. pin_idx,
  1427. spec->pcm_rec[pin_idx].device);
  1428. if (err < 0)
  1429. return err;
  1430. hdmi_present_sense(per_pin, 0);
  1431. }
  1432. /* add channel maps */
  1433. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1434. struct snd_pcm_chmap *chmap;
  1435. struct snd_kcontrol *kctl;
  1436. int i;
  1437. err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
  1438. SNDRV_PCM_STREAM_PLAYBACK,
  1439. NULL, 0, pin_idx, &chmap);
  1440. if (err < 0)
  1441. return err;
  1442. /* override handlers */
  1443. chmap->private_data = codec;
  1444. kctl = chmap->kctl;
  1445. for (i = 0; i < kctl->count; i++)
  1446. kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
  1447. kctl->info = hdmi_chmap_ctl_info;
  1448. kctl->get = hdmi_chmap_ctl_get;
  1449. kctl->put = hdmi_chmap_ctl_put;
  1450. kctl->tlv.c = hdmi_chmap_ctl_tlv;
  1451. }
  1452. return 0;
  1453. }
  1454. static int generic_hdmi_init_per_pins(struct hda_codec *codec)
  1455. {
  1456. struct hdmi_spec *spec = codec->spec;
  1457. int pin_idx;
  1458. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1459. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1460. struct hdmi_eld *eld = &per_pin->sink_eld;
  1461. per_pin->codec = codec;
  1462. mutex_init(&eld->lock);
  1463. INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
  1464. snd_hda_eld_proc_new(codec, eld, pin_idx);
  1465. }
  1466. return 0;
  1467. }
  1468. static int generic_hdmi_init(struct hda_codec *codec)
  1469. {
  1470. struct hdmi_spec *spec = codec->spec;
  1471. int pin_idx;
  1472. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1473. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1474. hda_nid_t pin_nid = per_pin->pin_nid;
  1475. hdmi_init_pin(codec, pin_nid);
  1476. snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
  1477. }
  1478. return 0;
  1479. }
  1480. static void generic_hdmi_free(struct hda_codec *codec)
  1481. {
  1482. struct hdmi_spec *spec = codec->spec;
  1483. int pin_idx;
  1484. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1485. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1486. struct hdmi_eld *eld = &per_pin->sink_eld;
  1487. cancel_delayed_work(&per_pin->work);
  1488. snd_hda_eld_proc_free(codec, eld);
  1489. }
  1490. flush_workqueue(codec->bus->workq);
  1491. kfree(spec);
  1492. }
  1493. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  1494. .init = generic_hdmi_init,
  1495. .free = generic_hdmi_free,
  1496. .build_pcms = generic_hdmi_build_pcms,
  1497. .build_controls = generic_hdmi_build_controls,
  1498. .unsol_event = hdmi_unsol_event,
  1499. };
  1500. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1501. hda_nid_t nid)
  1502. {
  1503. struct hdmi_spec *spec = codec->spec;
  1504. hda_nid_t conns[4];
  1505. int nconns;
  1506. nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
  1507. if (nconns == spec->num_cvts &&
  1508. !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
  1509. return;
  1510. /* override pins connection list */
  1511. snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
  1512. snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
  1513. }
  1514. #define INTEL_VENDOR_NID 0x08
  1515. #define INTEL_GET_VENDOR_VERB 0xf81
  1516. #define INTEL_SET_VENDOR_VERB 0x781
  1517. #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
  1518. #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
  1519. static void intel_haswell_enable_all_pins(struct hda_codec *codec,
  1520. const struct hda_fixup *fix, int action)
  1521. {
  1522. unsigned int vendor_param;
  1523. if (action != HDA_FIXUP_ACT_PRE_PROBE)
  1524. return;
  1525. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1526. INTEL_GET_VENDOR_VERB, 0);
  1527. if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
  1528. return;
  1529. vendor_param |= INTEL_EN_ALL_PIN_CVTS;
  1530. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1531. INTEL_SET_VENDOR_VERB, vendor_param);
  1532. if (vendor_param == -1)
  1533. return;
  1534. snd_hda_codec_update_widgets(codec);
  1535. return;
  1536. }
  1537. static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
  1538. {
  1539. unsigned int vendor_param;
  1540. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1541. INTEL_GET_VENDOR_VERB, 0);
  1542. if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
  1543. return;
  1544. /* enable DP1.2 mode */
  1545. vendor_param |= INTEL_EN_DP12;
  1546. snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
  1547. INTEL_SET_VENDOR_VERB, vendor_param);
  1548. }
  1549. /* available models for fixup */
  1550. enum {
  1551. INTEL_HASWELL,
  1552. };
  1553. static const struct hda_model_fixup hdmi_models[] = {
  1554. {.id = INTEL_HASWELL, .name = "Haswell"},
  1555. {}
  1556. };
  1557. static const struct snd_pci_quirk hdmi_fixup_tbl[] = {
  1558. SND_PCI_QUIRK(0x8086, 0x2010, "Haswell", INTEL_HASWELL),
  1559. {} /* terminator */
  1560. };
  1561. static const struct hda_fixup hdmi_fixups[] = {
  1562. [INTEL_HASWELL] = {
  1563. .type = HDA_FIXUP_FUNC,
  1564. .v.func = intel_haswell_enable_all_pins,
  1565. },
  1566. };
  1567. static int patch_generic_hdmi(struct hda_codec *codec)
  1568. {
  1569. struct hdmi_spec *spec;
  1570. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1571. if (spec == NULL)
  1572. return -ENOMEM;
  1573. codec->spec = spec;
  1574. snd_hda_pick_fixup(codec, hdmi_models, hdmi_fixup_tbl, hdmi_fixups);
  1575. snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
  1576. if (codec->vendor_id == 0x80862807)
  1577. intel_haswell_fixup_enable_dp12(codec);
  1578. if (hdmi_parse_codec(codec) < 0) {
  1579. codec->spec = NULL;
  1580. kfree(spec);
  1581. return -EINVAL;
  1582. }
  1583. codec->patch_ops = generic_hdmi_patch_ops;
  1584. generic_hdmi_init_per_pins(codec);
  1585. init_channel_allocations();
  1586. return 0;
  1587. }
  1588. /*
  1589. * Shared non-generic implementations
  1590. */
  1591. static int simple_playback_build_pcms(struct hda_codec *codec)
  1592. {
  1593. struct hdmi_spec *spec = codec->spec;
  1594. struct hda_pcm *info = spec->pcm_rec;
  1595. unsigned int chans;
  1596. struct hda_pcm_stream *pstr;
  1597. codec->num_pcms = 1;
  1598. codec->pcm_info = info;
  1599. chans = get_wcaps(codec, spec->cvts[0].cvt_nid);
  1600. chans = get_wcaps_channels(chans);
  1601. info->name = get_hdmi_pcm_name(0);
  1602. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1603. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1604. *pstr = spec->pcm_playback;
  1605. pstr->nid = spec->cvts[0].cvt_nid;
  1606. if (pstr->channels_max <= 2 && chans && chans <= 16)
  1607. pstr->channels_max = chans;
  1608. return 0;
  1609. }
  1610. /* unsolicited event for jack sensing */
  1611. static void simple_hdmi_unsol_event(struct hda_codec *codec,
  1612. unsigned int res)
  1613. {
  1614. snd_hda_jack_set_dirty_all(codec);
  1615. snd_hda_jack_report_sync(codec);
  1616. }
  1617. /* generic_hdmi_build_jack can be used for simple_hdmi, too,
  1618. * as long as spec->pins[] is set correctly
  1619. */
  1620. #define simple_hdmi_build_jack generic_hdmi_build_jack
  1621. static int simple_playback_build_controls(struct hda_codec *codec)
  1622. {
  1623. struct hdmi_spec *spec = codec->spec;
  1624. int err;
  1625. err = snd_hda_create_spdif_out_ctls(codec,
  1626. spec->cvts[0].cvt_nid,
  1627. spec->cvts[0].cvt_nid);
  1628. if (err < 0)
  1629. return err;
  1630. return simple_hdmi_build_jack(codec, 0);
  1631. }
  1632. static int simple_playback_init(struct hda_codec *codec)
  1633. {
  1634. struct hdmi_spec *spec = codec->spec;
  1635. hda_nid_t pin = spec->pins[0].pin_nid;
  1636. snd_hda_codec_write(codec, pin, 0,
  1637. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  1638. /* some codecs require to unmute the pin */
  1639. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  1640. snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  1641. AMP_OUT_UNMUTE);
  1642. snd_hda_jack_detect_enable(codec, pin, pin);
  1643. return 0;
  1644. }
  1645. static void simple_playback_free(struct hda_codec *codec)
  1646. {
  1647. struct hdmi_spec *spec = codec->spec;
  1648. kfree(spec);
  1649. }
  1650. /*
  1651. * Nvidia specific implementations
  1652. */
  1653. #define Nv_VERB_SET_Channel_Allocation 0xF79
  1654. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  1655. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  1656. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  1657. #define nvhdmi_master_con_nid_7x 0x04
  1658. #define nvhdmi_master_pin_nid_7x 0x05
  1659. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  1660. /*front, rear, clfe, rear_surr */
  1661. 0x6, 0x8, 0xa, 0xc,
  1662. };
  1663. static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
  1664. /* set audio protect on */
  1665. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1666. /* enable digital output on pin widget */
  1667. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1668. {} /* terminator */
  1669. };
  1670. static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
  1671. /* set audio protect on */
  1672. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1673. /* enable digital output on pin widget */
  1674. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1675. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1676. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1677. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1678. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1679. {} /* terminator */
  1680. };
  1681. #ifdef LIMITED_RATE_FMT_SUPPORT
  1682. /* support only the safe format and rate */
  1683. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  1684. #define SUPPORTED_MAXBPS 16
  1685. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  1686. #else
  1687. /* support all rates and formats */
  1688. #define SUPPORTED_RATES \
  1689. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  1690. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  1691. SNDRV_PCM_RATE_192000)
  1692. #define SUPPORTED_MAXBPS 24
  1693. #define SUPPORTED_FORMATS \
  1694. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1695. #endif
  1696. static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
  1697. {
  1698. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
  1699. return 0;
  1700. }
  1701. static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
  1702. {
  1703. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
  1704. return 0;
  1705. }
  1706. static unsigned int channels_2_6_8[] = {
  1707. 2, 6, 8
  1708. };
  1709. static unsigned int channels_2_8[] = {
  1710. 2, 8
  1711. };
  1712. static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  1713. .count = ARRAY_SIZE(channels_2_6_8),
  1714. .list = channels_2_6_8,
  1715. .mask = 0,
  1716. };
  1717. static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  1718. .count = ARRAY_SIZE(channels_2_8),
  1719. .list = channels_2_8,
  1720. .mask = 0,
  1721. };
  1722. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  1723. struct hda_codec *codec,
  1724. struct snd_pcm_substream *substream)
  1725. {
  1726. struct hdmi_spec *spec = codec->spec;
  1727. struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  1728. switch (codec->preset->id) {
  1729. case 0x10de0002:
  1730. case 0x10de0003:
  1731. case 0x10de0005:
  1732. case 0x10de0006:
  1733. hw_constraints_channels = &hw_constraints_2_8_channels;
  1734. break;
  1735. case 0x10de0007:
  1736. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  1737. break;
  1738. default:
  1739. break;
  1740. }
  1741. if (hw_constraints_channels != NULL) {
  1742. snd_pcm_hw_constraint_list(substream->runtime, 0,
  1743. SNDRV_PCM_HW_PARAM_CHANNELS,
  1744. hw_constraints_channels);
  1745. } else {
  1746. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1747. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1748. }
  1749. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  1750. }
  1751. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  1752. struct hda_codec *codec,
  1753. struct snd_pcm_substream *substream)
  1754. {
  1755. struct hdmi_spec *spec = codec->spec;
  1756. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1757. }
  1758. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1759. struct hda_codec *codec,
  1760. unsigned int stream_tag,
  1761. unsigned int format,
  1762. struct snd_pcm_substream *substream)
  1763. {
  1764. struct hdmi_spec *spec = codec->spec;
  1765. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  1766. stream_tag, format, substream);
  1767. }
  1768. static const struct hda_pcm_stream simple_pcm_playback = {
  1769. .substreams = 1,
  1770. .channels_min = 2,
  1771. .channels_max = 2,
  1772. .ops = {
  1773. .open = simple_playback_pcm_open,
  1774. .close = simple_playback_pcm_close,
  1775. .prepare = simple_playback_pcm_prepare
  1776. },
  1777. };
  1778. static const struct hda_codec_ops simple_hdmi_patch_ops = {
  1779. .build_controls = simple_playback_build_controls,
  1780. .build_pcms = simple_playback_build_pcms,
  1781. .init = simple_playback_init,
  1782. .free = simple_playback_free,
  1783. .unsol_event = simple_hdmi_unsol_event,
  1784. };
  1785. static int patch_simple_hdmi(struct hda_codec *codec,
  1786. hda_nid_t cvt_nid, hda_nid_t pin_nid)
  1787. {
  1788. struct hdmi_spec *spec;
  1789. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1790. if (!spec)
  1791. return -ENOMEM;
  1792. codec->spec = spec;
  1793. spec->multiout.num_dacs = 0; /* no analog */
  1794. spec->multiout.max_channels = 2;
  1795. spec->multiout.dig_out_nid = cvt_nid;
  1796. spec->num_cvts = 1;
  1797. spec->num_pins = 1;
  1798. spec->cvts[0].cvt_nid = cvt_nid;
  1799. spec->pins[0].pin_nid = pin_nid;
  1800. spec->pcm_playback = simple_pcm_playback;
  1801. codec->patch_ops = simple_hdmi_patch_ops;
  1802. return 0;
  1803. }
  1804. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  1805. int channels)
  1806. {
  1807. unsigned int chanmask;
  1808. int chan = channels ? (channels - 1) : 1;
  1809. switch (channels) {
  1810. default:
  1811. case 0:
  1812. case 2:
  1813. chanmask = 0x00;
  1814. break;
  1815. case 4:
  1816. chanmask = 0x08;
  1817. break;
  1818. case 6:
  1819. chanmask = 0x0b;
  1820. break;
  1821. case 8:
  1822. chanmask = 0x13;
  1823. break;
  1824. }
  1825. /* Set the audio infoframe channel allocation and checksum fields. The
  1826. * channel count is computed implicitly by the hardware. */
  1827. snd_hda_codec_write(codec, 0x1, 0,
  1828. Nv_VERB_SET_Channel_Allocation, chanmask);
  1829. snd_hda_codec_write(codec, 0x1, 0,
  1830. Nv_VERB_SET_Info_Frame_Checksum,
  1831. (0x71 - chan - chanmask));
  1832. }
  1833. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  1834. struct hda_codec *codec,
  1835. struct snd_pcm_substream *substream)
  1836. {
  1837. struct hdmi_spec *spec = codec->spec;
  1838. int i;
  1839. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  1840. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  1841. for (i = 0; i < 4; i++) {
  1842. /* set the stream id */
  1843. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1844. AC_VERB_SET_CHANNEL_STREAMID, 0);
  1845. /* set the stream format */
  1846. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1847. AC_VERB_SET_STREAM_FORMAT, 0);
  1848. }
  1849. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  1850. * streams are disabled. */
  1851. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  1852. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1853. }
  1854. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  1855. struct hda_codec *codec,
  1856. unsigned int stream_tag,
  1857. unsigned int format,
  1858. struct snd_pcm_substream *substream)
  1859. {
  1860. int chs;
  1861. unsigned int dataDCC2, channel_id;
  1862. int i;
  1863. struct hdmi_spec *spec = codec->spec;
  1864. struct hda_spdif_out *spdif;
  1865. mutex_lock(&codec->spdif_mutex);
  1866. spdif = snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
  1867. chs = substream->runtime->channels;
  1868. dataDCC2 = 0x2;
  1869. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  1870. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  1871. snd_hda_codec_write(codec,
  1872. nvhdmi_master_con_nid_7x,
  1873. 0,
  1874. AC_VERB_SET_DIGI_CONVERT_1,
  1875. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  1876. /* set the stream id */
  1877. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1878. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  1879. /* set the stream format */
  1880. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1881. AC_VERB_SET_STREAM_FORMAT, format);
  1882. /* turn on again (if needed) */
  1883. /* enable and set the channel status audio/data flag */
  1884. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  1885. snd_hda_codec_write(codec,
  1886. nvhdmi_master_con_nid_7x,
  1887. 0,
  1888. AC_VERB_SET_DIGI_CONVERT_1,
  1889. spdif->ctls & 0xff);
  1890. snd_hda_codec_write(codec,
  1891. nvhdmi_master_con_nid_7x,
  1892. 0,
  1893. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1894. }
  1895. for (i = 0; i < 4; i++) {
  1896. if (chs == 2)
  1897. channel_id = 0;
  1898. else
  1899. channel_id = i * 2;
  1900. /* turn off SPDIF once;
  1901. *otherwise the IEC958 bits won't be updated
  1902. */
  1903. if (codec->spdif_status_reset &&
  1904. (spdif->ctls & AC_DIG1_ENABLE))
  1905. snd_hda_codec_write(codec,
  1906. nvhdmi_con_nids_7x[i],
  1907. 0,
  1908. AC_VERB_SET_DIGI_CONVERT_1,
  1909. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  1910. /* set the stream id */
  1911. snd_hda_codec_write(codec,
  1912. nvhdmi_con_nids_7x[i],
  1913. 0,
  1914. AC_VERB_SET_CHANNEL_STREAMID,
  1915. (stream_tag << 4) | channel_id);
  1916. /* set the stream format */
  1917. snd_hda_codec_write(codec,
  1918. nvhdmi_con_nids_7x[i],
  1919. 0,
  1920. AC_VERB_SET_STREAM_FORMAT,
  1921. format);
  1922. /* turn on again (if needed) */
  1923. /* enable and set the channel status audio/data flag */
  1924. if (codec->spdif_status_reset &&
  1925. (spdif->ctls & AC_DIG1_ENABLE)) {
  1926. snd_hda_codec_write(codec,
  1927. nvhdmi_con_nids_7x[i],
  1928. 0,
  1929. AC_VERB_SET_DIGI_CONVERT_1,
  1930. spdif->ctls & 0xff);
  1931. snd_hda_codec_write(codec,
  1932. nvhdmi_con_nids_7x[i],
  1933. 0,
  1934. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1935. }
  1936. }
  1937. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  1938. mutex_unlock(&codec->spdif_mutex);
  1939. return 0;
  1940. }
  1941. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  1942. .substreams = 1,
  1943. .channels_min = 2,
  1944. .channels_max = 8,
  1945. .nid = nvhdmi_master_con_nid_7x,
  1946. .rates = SUPPORTED_RATES,
  1947. .maxbps = SUPPORTED_MAXBPS,
  1948. .formats = SUPPORTED_FORMATS,
  1949. .ops = {
  1950. .open = simple_playback_pcm_open,
  1951. .close = nvhdmi_8ch_7x_pcm_close,
  1952. .prepare = nvhdmi_8ch_7x_pcm_prepare
  1953. },
  1954. };
  1955. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  1956. {
  1957. struct hdmi_spec *spec;
  1958. int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
  1959. nvhdmi_master_pin_nid_7x);
  1960. if (err < 0)
  1961. return err;
  1962. codec->patch_ops.init = nvhdmi_7x_init_2ch;
  1963. /* override the PCM rates, etc, as the codec doesn't give full list */
  1964. spec = codec->spec;
  1965. spec->pcm_playback.rates = SUPPORTED_RATES;
  1966. spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
  1967. spec->pcm_playback.formats = SUPPORTED_FORMATS;
  1968. return 0;
  1969. }
  1970. static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
  1971. {
  1972. struct hdmi_spec *spec = codec->spec;
  1973. int err = simple_playback_build_pcms(codec);
  1974. spec->pcm_rec[0].own_chmap = true;
  1975. return err;
  1976. }
  1977. static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
  1978. {
  1979. struct hdmi_spec *spec = codec->spec;
  1980. struct snd_pcm_chmap *chmap;
  1981. int err;
  1982. err = simple_playback_build_controls(codec);
  1983. if (err < 0)
  1984. return err;
  1985. /* add channel maps */
  1986. err = snd_pcm_add_chmap_ctls(spec->pcm_rec[0].pcm,
  1987. SNDRV_PCM_STREAM_PLAYBACK,
  1988. snd_pcm_alt_chmaps, 8, 0, &chmap);
  1989. if (err < 0)
  1990. return err;
  1991. switch (codec->preset->id) {
  1992. case 0x10de0002:
  1993. case 0x10de0003:
  1994. case 0x10de0005:
  1995. case 0x10de0006:
  1996. chmap->channel_mask = (1U << 2) | (1U << 8);
  1997. break;
  1998. case 0x10de0007:
  1999. chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
  2000. }
  2001. return 0;
  2002. }
  2003. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  2004. {
  2005. struct hdmi_spec *spec;
  2006. int err = patch_nvhdmi_2ch(codec);
  2007. if (err < 0)
  2008. return err;
  2009. spec = codec->spec;
  2010. spec->multiout.max_channels = 8;
  2011. spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
  2012. codec->patch_ops.init = nvhdmi_7x_init_8ch;
  2013. codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
  2014. codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
  2015. /* Initialize the audio infoframe channel mask and checksum to something
  2016. * valid */
  2017. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2018. return 0;
  2019. }
  2020. /*
  2021. * ATI-specific implementations
  2022. *
  2023. * FIXME: we may omit the whole this and use the generic code once after
  2024. * it's confirmed to work.
  2025. */
  2026. #define ATIHDMI_CVT_NID 0x02 /* audio converter */
  2027. #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
  2028. static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2029. struct hda_codec *codec,
  2030. unsigned int stream_tag,
  2031. unsigned int format,
  2032. struct snd_pcm_substream *substream)
  2033. {
  2034. struct hdmi_spec *spec = codec->spec;
  2035. int chans = substream->runtime->channels;
  2036. int i, err;
  2037. err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
  2038. substream);
  2039. if (err < 0)
  2040. return err;
  2041. snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
  2042. AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
  2043. /* FIXME: XXX */
  2044. for (i = 0; i < chans; i++) {
  2045. snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
  2046. AC_VERB_SET_HDMI_CHAN_SLOT,
  2047. (i << 4) | i);
  2048. }
  2049. return 0;
  2050. }
  2051. static int patch_atihdmi(struct hda_codec *codec)
  2052. {
  2053. struct hdmi_spec *spec;
  2054. int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
  2055. if (err < 0)
  2056. return err;
  2057. spec = codec->spec;
  2058. spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
  2059. return 0;
  2060. }
  2061. /* VIA HDMI Implementation */
  2062. #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
  2063. #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
  2064. static int patch_via_hdmi(struct hda_codec *codec)
  2065. {
  2066. return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
  2067. }
  2068. /*
  2069. * patch entries
  2070. */
  2071. static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
  2072. { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
  2073. { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
  2074. { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
  2075. { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
  2076. { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
  2077. { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
  2078. { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
  2079. { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2080. { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2081. { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2082. { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2083. { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
  2084. { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
  2085. { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
  2086. { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
  2087. { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
  2088. { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
  2089. { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
  2090. { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
  2091. { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
  2092. { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
  2093. { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
  2094. { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
  2095. /* 17 is known to be absent */
  2096. { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
  2097. { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
  2098. { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
  2099. { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
  2100. { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
  2101. { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
  2102. { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
  2103. { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
  2104. { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
  2105. { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
  2106. { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
  2107. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  2108. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  2109. { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  2110. { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  2111. { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  2112. { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  2113. { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  2114. { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
  2115. { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
  2116. { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
  2117. { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  2118. { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
  2119. { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
  2120. { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
  2121. { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
  2122. { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
  2123. {} /* terminator */
  2124. };
  2125. MODULE_ALIAS("snd-hda-codec-id:1002793c");
  2126. MODULE_ALIAS("snd-hda-codec-id:10027919");
  2127. MODULE_ALIAS("snd-hda-codec-id:1002791a");
  2128. MODULE_ALIAS("snd-hda-codec-id:1002aa01");
  2129. MODULE_ALIAS("snd-hda-codec-id:10951390");
  2130. MODULE_ALIAS("snd-hda-codec-id:10951392");
  2131. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  2132. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  2133. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  2134. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  2135. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  2136. MODULE_ALIAS("snd-hda-codec-id:10de000a");
  2137. MODULE_ALIAS("snd-hda-codec-id:10de000b");
  2138. MODULE_ALIAS("snd-hda-codec-id:10de000c");
  2139. MODULE_ALIAS("snd-hda-codec-id:10de000d");
  2140. MODULE_ALIAS("snd-hda-codec-id:10de0010");
  2141. MODULE_ALIAS("snd-hda-codec-id:10de0011");
  2142. MODULE_ALIAS("snd-hda-codec-id:10de0012");
  2143. MODULE_ALIAS("snd-hda-codec-id:10de0013");
  2144. MODULE_ALIAS("snd-hda-codec-id:10de0014");
  2145. MODULE_ALIAS("snd-hda-codec-id:10de0015");
  2146. MODULE_ALIAS("snd-hda-codec-id:10de0016");
  2147. MODULE_ALIAS("snd-hda-codec-id:10de0018");
  2148. MODULE_ALIAS("snd-hda-codec-id:10de0019");
  2149. MODULE_ALIAS("snd-hda-codec-id:10de001a");
  2150. MODULE_ALIAS("snd-hda-codec-id:10de001b");
  2151. MODULE_ALIAS("snd-hda-codec-id:10de001c");
  2152. MODULE_ALIAS("snd-hda-codec-id:10de0040");
  2153. MODULE_ALIAS("snd-hda-codec-id:10de0041");
  2154. MODULE_ALIAS("snd-hda-codec-id:10de0042");
  2155. MODULE_ALIAS("snd-hda-codec-id:10de0043");
  2156. MODULE_ALIAS("snd-hda-codec-id:10de0044");
  2157. MODULE_ALIAS("snd-hda-codec-id:10de0051");
  2158. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  2159. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  2160. MODULE_ALIAS("snd-hda-codec-id:11069f80");
  2161. MODULE_ALIAS("snd-hda-codec-id:11069f81");
  2162. MODULE_ALIAS("snd-hda-codec-id:11069f84");
  2163. MODULE_ALIAS("snd-hda-codec-id:11069f85");
  2164. MODULE_ALIAS("snd-hda-codec-id:17e80047");
  2165. MODULE_ALIAS("snd-hda-codec-id:80860054");
  2166. MODULE_ALIAS("snd-hda-codec-id:80862801");
  2167. MODULE_ALIAS("snd-hda-codec-id:80862802");
  2168. MODULE_ALIAS("snd-hda-codec-id:80862803");
  2169. MODULE_ALIAS("snd-hda-codec-id:80862804");
  2170. MODULE_ALIAS("snd-hda-codec-id:80862805");
  2171. MODULE_ALIAS("snd-hda-codec-id:80862806");
  2172. MODULE_ALIAS("snd-hda-codec-id:80862807");
  2173. MODULE_ALIAS("snd-hda-codec-id:80862880");
  2174. MODULE_ALIAS("snd-hda-codec-id:808629fb");
  2175. MODULE_LICENSE("GPL");
  2176. MODULE_DESCRIPTION("HDMI HD-audio codec");
  2177. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  2178. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  2179. MODULE_ALIAS("snd-hda-codec-atihdmi");
  2180. static struct hda_codec_preset_list intel_list = {
  2181. .preset = snd_hda_preset_hdmi,
  2182. .owner = THIS_MODULE,
  2183. };
  2184. static int __init patch_hdmi_init(void)
  2185. {
  2186. return snd_hda_add_codec_preset(&intel_list);
  2187. }
  2188. static void __exit patch_hdmi_exit(void)
  2189. {
  2190. snd_hda_delete_codec_preset(&intel_list);
  2191. }
  2192. module_init(patch_hdmi_init)
  2193. module_exit(patch_hdmi_exit)