qla_mbx.c 106 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/gfp.h>
  10. /*
  11. * qla2x00_mailbox_command
  12. * Issue mailbox command and waits for completion.
  13. *
  14. * Input:
  15. * ha = adapter block pointer.
  16. * mcp = driver internal mbx struct pointer.
  17. *
  18. * Output:
  19. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  20. *
  21. * Returns:
  22. * 0 : QLA_SUCCESS = cmd performed success
  23. * 1 : QLA_FUNCTION_FAILED (error encountered)
  24. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  25. *
  26. * Context:
  27. * Kernel context.
  28. */
  29. static int
  30. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  31. {
  32. int rval;
  33. unsigned long flags = 0;
  34. device_reg_t __iomem *reg;
  35. uint8_t abort_active;
  36. uint8_t io_lock_on;
  37. uint16_t command = 0;
  38. uint16_t *iptr;
  39. uint16_t __iomem *optr;
  40. uint32_t cnt;
  41. uint32_t mboxes;
  42. unsigned long wait_time;
  43. struct qla_hw_data *ha = vha->hw;
  44. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  45. ql_dbg(ql_dbg_mbx, base_vha, 0x1000, "Entered %s.\n", __func__);
  46. if (ha->pdev->error_state > pci_channel_io_frozen) {
  47. ql_log(ql_log_warn, base_vha, 0x1001,
  48. "error_state is greater than pci_channel_io_frozen, "
  49. "exiting.\n");
  50. return QLA_FUNCTION_TIMEOUT;
  51. }
  52. if (vha->device_flags & DFLG_DEV_FAILED) {
  53. ql_log(ql_log_warn, base_vha, 0x1002,
  54. "Device in failed state, exiting.\n");
  55. return QLA_FUNCTION_TIMEOUT;
  56. }
  57. reg = ha->iobase;
  58. io_lock_on = base_vha->flags.init_done;
  59. rval = QLA_SUCCESS;
  60. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  61. if (ha->flags.pci_channel_io_perm_failure) {
  62. ql_log(ql_log_warn, base_vha, 0x1003,
  63. "Perm failure on EEH timeout MBX, exiting.\n");
  64. return QLA_FUNCTION_TIMEOUT;
  65. }
  66. if (ha->flags.isp82xx_fw_hung) {
  67. /* Setting Link-Down error */
  68. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  69. ql_log(ql_log_warn, base_vha, 0x1004,
  70. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  71. return QLA_FUNCTION_TIMEOUT;
  72. }
  73. /*
  74. * Wait for active mailbox commands to finish by waiting at most tov
  75. * seconds. This is to serialize actual issuing of mailbox cmds during
  76. * non ISP abort time.
  77. */
  78. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  79. /* Timeout occurred. Return error. */
  80. ql_log(ql_log_warn, base_vha, 0x1005,
  81. "Cmd access timeout, Exiting.\n");
  82. return QLA_FUNCTION_TIMEOUT;
  83. }
  84. ha->flags.mbox_busy = 1;
  85. /* Save mailbox command for debug */
  86. ha->mcp = mcp;
  87. ql_dbg(ql_dbg_mbx, base_vha, 0x1006,
  88. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  89. spin_lock_irqsave(&ha->hardware_lock, flags);
  90. /* Load mailbox registers. */
  91. if (IS_QLA82XX(ha))
  92. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  93. else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
  94. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  95. else
  96. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  97. iptr = mcp->mb;
  98. command = mcp->mb[0];
  99. mboxes = mcp->out_mb;
  100. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  101. if (IS_QLA2200(ha) && cnt == 8)
  102. optr =
  103. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  104. if (mboxes & BIT_0)
  105. WRT_REG_WORD(optr, *iptr);
  106. mboxes >>= 1;
  107. optr++;
  108. iptr++;
  109. }
  110. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1111,
  111. "Loaded MBX registers (displayed in bytes) =.\n");
  112. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1112,
  113. (uint8_t *)mcp->mb, 16);
  114. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1113,
  115. ".\n");
  116. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1114,
  117. ((uint8_t *)mcp->mb + 0x10), 16);
  118. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1115,
  119. ".\n");
  120. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1116,
  121. ((uint8_t *)mcp->mb + 0x20), 8);
  122. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1117,
  123. "I/O Address = %p.\n", optr);
  124. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x100e);
  125. /* Issue set host interrupt command to send cmd out. */
  126. ha->flags.mbox_int = 0;
  127. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  128. /* Unlock mbx registers and wait for interrupt */
  129. ql_dbg(ql_dbg_mbx, base_vha, 0x100f,
  130. "Going to unlock irq & waiting for interrupts. "
  131. "jiffies=%lx.\n", jiffies);
  132. /* Wait for mbx cmd completion until timeout */
  133. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  134. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  135. if (IS_QLA82XX(ha)) {
  136. if (RD_REG_DWORD(&reg->isp82.hint) &
  137. HINT_MBX_INT_PENDING) {
  138. spin_unlock_irqrestore(&ha->hardware_lock,
  139. flags);
  140. ha->flags.mbox_busy = 0;
  141. ql_dbg(ql_dbg_mbx, base_vha, 0x1010,
  142. "Pending mailbox timeout, exiting.\n");
  143. rval = QLA_FUNCTION_TIMEOUT;
  144. goto premature_exit;
  145. }
  146. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  147. } else if (IS_FWI2_CAPABLE(ha))
  148. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  149. else
  150. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  151. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  152. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  153. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  154. } else {
  155. ql_dbg(ql_dbg_mbx, base_vha, 0x1011,
  156. "Cmd=%x Polling Mode.\n", command);
  157. if (IS_QLA82XX(ha)) {
  158. if (RD_REG_DWORD(&reg->isp82.hint) &
  159. HINT_MBX_INT_PENDING) {
  160. spin_unlock_irqrestore(&ha->hardware_lock,
  161. flags);
  162. ha->flags.mbox_busy = 0;
  163. ql_dbg(ql_dbg_mbx, base_vha, 0x1012,
  164. "Pending mailbox timeout, exiting.\n");
  165. rval = QLA_FUNCTION_TIMEOUT;
  166. goto premature_exit;
  167. }
  168. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  169. } else if (IS_FWI2_CAPABLE(ha))
  170. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  171. else
  172. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  173. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  174. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  175. while (!ha->flags.mbox_int) {
  176. if (time_after(jiffies, wait_time))
  177. break;
  178. /* Check for pending interrupts. */
  179. qla2x00_poll(ha->rsp_q_map[0]);
  180. if (!ha->flags.mbox_int &&
  181. !(IS_QLA2200(ha) &&
  182. command == MBC_LOAD_RISC_RAM_EXTENDED))
  183. msleep(10);
  184. } /* while */
  185. ql_dbg(ql_dbg_mbx, base_vha, 0x1013,
  186. "Waited %d sec.\n",
  187. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  188. }
  189. /* Check whether we timed out */
  190. if (ha->flags.mbox_int) {
  191. uint16_t *iptr2;
  192. ql_dbg(ql_dbg_mbx, base_vha, 0x1014,
  193. "Cmd=%x completed.\n", command);
  194. /* Got interrupt. Clear the flag. */
  195. ha->flags.mbox_int = 0;
  196. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  197. if (ha->flags.isp82xx_fw_hung) {
  198. ha->flags.mbox_busy = 0;
  199. /* Setting Link-Down error */
  200. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  201. ha->mcp = NULL;
  202. rval = QLA_FUNCTION_FAILED;
  203. ql_log(ql_log_warn, base_vha, 0x1015,
  204. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  205. goto premature_exit;
  206. }
  207. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  208. rval = QLA_FUNCTION_FAILED;
  209. /* Load return mailbox registers. */
  210. iptr2 = mcp->mb;
  211. iptr = (uint16_t *)&ha->mailbox_out[0];
  212. mboxes = mcp->in_mb;
  213. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  214. if (mboxes & BIT_0)
  215. *iptr2 = *iptr;
  216. mboxes >>= 1;
  217. iptr2++;
  218. iptr++;
  219. }
  220. } else {
  221. uint16_t mb0;
  222. uint32_t ictrl;
  223. if (IS_FWI2_CAPABLE(ha)) {
  224. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  225. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  226. } else {
  227. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  228. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  229. }
  230. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1119,
  231. "MBX Command timeout for cmd %x.\n", command);
  232. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111a,
  233. "iocontrol=%x jiffies=%lx.\n", ictrl, jiffies);
  234. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111b,
  235. "mb[0] = 0x%x.\n", mb0);
  236. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1019);
  237. rval = QLA_FUNCTION_TIMEOUT;
  238. }
  239. ha->flags.mbox_busy = 0;
  240. /* Clean up */
  241. ha->mcp = NULL;
  242. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  243. ql_dbg(ql_dbg_mbx, base_vha, 0x101a,
  244. "Checking for additional resp interrupt.\n");
  245. /* polling mode for non isp_abort commands. */
  246. qla2x00_poll(ha->rsp_q_map[0]);
  247. }
  248. if (rval == QLA_FUNCTION_TIMEOUT &&
  249. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  250. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  251. ha->flags.eeh_busy) {
  252. /* not in dpc. schedule it for dpc to take over. */
  253. ql_dbg(ql_dbg_mbx, base_vha, 0x101b,
  254. "Timeout, schedule isp_abort_needed.\n");
  255. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  256. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  257. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  258. if (IS_QLA82XX(ha)) {
  259. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  260. "disabling pause transmit on port "
  261. "0 & 1.\n");
  262. qla82xx_wr_32(ha,
  263. QLA82XX_CRB_NIU + 0x98,
  264. CRB_NIU_XG_PAUSE_CTL_P0|
  265. CRB_NIU_XG_PAUSE_CTL_P1);
  266. }
  267. ql_log(ql_log_info, base_vha, 0x101c,
  268. "Mailbox cmd timeout occured. "
  269. "Scheduling ISP abort eeh_busy=0x%x.\n",
  270. ha->flags.eeh_busy);
  271. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  272. qla2xxx_wake_dpc(vha);
  273. }
  274. } else if (!abort_active) {
  275. /* call abort directly since we are in the DPC thread */
  276. ql_dbg(ql_dbg_mbx, base_vha, 0x101d,
  277. "Timeout, calling abort_isp.\n");
  278. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  279. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  280. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  281. if (IS_QLA82XX(ha)) {
  282. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  283. "disabling pause transmit on port "
  284. "0 & 1.\n");
  285. qla82xx_wr_32(ha,
  286. QLA82XX_CRB_NIU + 0x98,
  287. CRB_NIU_XG_PAUSE_CTL_P0|
  288. CRB_NIU_XG_PAUSE_CTL_P1);
  289. }
  290. ql_log(ql_log_info, base_vha, 0x101e,
  291. "Mailbox cmd timeout occured. "
  292. "Scheduling ISP abort.\n");
  293. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  294. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  295. if (ha->isp_ops->abort_isp(vha)) {
  296. /* Failed. retry later. */
  297. set_bit(ISP_ABORT_NEEDED,
  298. &vha->dpc_flags);
  299. }
  300. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  301. ql_dbg(ql_dbg_mbx, base_vha, 0x101f,
  302. "Finished abort_isp.\n");
  303. }
  304. }
  305. }
  306. premature_exit:
  307. /* Allow next mbx cmd to come in. */
  308. complete(&ha->mbx_cmd_comp);
  309. if (rval) {
  310. ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
  311. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, cmd=%x ****.\n",
  312. mcp->mb[0], mcp->mb[1], mcp->mb[2], command);
  313. } else {
  314. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  315. }
  316. return rval;
  317. }
  318. int
  319. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  320. uint32_t risc_code_size)
  321. {
  322. int rval;
  323. struct qla_hw_data *ha = vha->hw;
  324. mbx_cmd_t mc;
  325. mbx_cmd_t *mcp = &mc;
  326. ql_dbg(ql_dbg_mbx, vha, 0x1022, "Entered %s.\n", __func__);
  327. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  328. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  329. mcp->mb[8] = MSW(risc_addr);
  330. mcp->out_mb = MBX_8|MBX_0;
  331. } else {
  332. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  333. mcp->out_mb = MBX_0;
  334. }
  335. mcp->mb[1] = LSW(risc_addr);
  336. mcp->mb[2] = MSW(req_dma);
  337. mcp->mb[3] = LSW(req_dma);
  338. mcp->mb[6] = MSW(MSD(req_dma));
  339. mcp->mb[7] = LSW(MSD(req_dma));
  340. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  341. if (IS_FWI2_CAPABLE(ha)) {
  342. mcp->mb[4] = MSW(risc_code_size);
  343. mcp->mb[5] = LSW(risc_code_size);
  344. mcp->out_mb |= MBX_5|MBX_4;
  345. } else {
  346. mcp->mb[4] = LSW(risc_code_size);
  347. mcp->out_mb |= MBX_4;
  348. }
  349. mcp->in_mb = MBX_0;
  350. mcp->tov = MBX_TOV_SECONDS;
  351. mcp->flags = 0;
  352. rval = qla2x00_mailbox_command(vha, mcp);
  353. if (rval != QLA_SUCCESS) {
  354. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  355. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  356. } else {
  357. ql_dbg(ql_dbg_mbx, vha, 0x1024, "Done %s.\n", __func__);
  358. }
  359. return rval;
  360. }
  361. #define EXTENDED_BB_CREDITS BIT_0
  362. /*
  363. * qla2x00_execute_fw
  364. * Start adapter firmware.
  365. *
  366. * Input:
  367. * ha = adapter block pointer.
  368. * TARGET_QUEUE_LOCK must be released.
  369. * ADAPTER_STATE_LOCK must be released.
  370. *
  371. * Returns:
  372. * qla2x00 local function return status code.
  373. *
  374. * Context:
  375. * Kernel context.
  376. */
  377. int
  378. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  379. {
  380. int rval;
  381. struct qla_hw_data *ha = vha->hw;
  382. mbx_cmd_t mc;
  383. mbx_cmd_t *mcp = &mc;
  384. ql_dbg(ql_dbg_mbx, vha, 0x1025, "Entered %s.\n", __func__);
  385. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  386. mcp->out_mb = MBX_0;
  387. mcp->in_mb = MBX_0;
  388. if (IS_FWI2_CAPABLE(ha)) {
  389. mcp->mb[1] = MSW(risc_addr);
  390. mcp->mb[2] = LSW(risc_addr);
  391. mcp->mb[3] = 0;
  392. if (IS_QLA81XX(ha)) {
  393. struct nvram_81xx *nv = ha->nvram;
  394. mcp->mb[4] = (nv->enhanced_features &
  395. EXTENDED_BB_CREDITS);
  396. } else
  397. mcp->mb[4] = 0;
  398. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  399. mcp->in_mb |= MBX_1;
  400. } else {
  401. mcp->mb[1] = LSW(risc_addr);
  402. mcp->out_mb |= MBX_1;
  403. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  404. mcp->mb[2] = 0;
  405. mcp->out_mb |= MBX_2;
  406. }
  407. }
  408. mcp->tov = MBX_TOV_SECONDS;
  409. mcp->flags = 0;
  410. rval = qla2x00_mailbox_command(vha, mcp);
  411. if (rval != QLA_SUCCESS) {
  412. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  413. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  414. } else {
  415. if (IS_FWI2_CAPABLE(ha)) {
  416. ql_dbg(ql_dbg_mbx, vha, 0x1027,
  417. "Done exchanges=%x.\n", mcp->mb[1]);
  418. } else {
  419. ql_dbg(ql_dbg_mbx, vha, 0x1028, "Done %s.\n", __func__);
  420. }
  421. }
  422. return rval;
  423. }
  424. /*
  425. * qla2x00_get_fw_version
  426. * Get firmware version.
  427. *
  428. * Input:
  429. * ha: adapter state pointer.
  430. * major: pointer for major number.
  431. * minor: pointer for minor number.
  432. * subminor: pointer for subminor number.
  433. *
  434. * Returns:
  435. * qla2x00 local function return status code.
  436. *
  437. * Context:
  438. * Kernel context.
  439. */
  440. int
  441. qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
  442. uint16_t *subminor, uint16_t *attributes, uint32_t *memory, uint8_t *mpi,
  443. uint32_t *mpi_caps, uint8_t *phy)
  444. {
  445. int rval;
  446. mbx_cmd_t mc;
  447. mbx_cmd_t *mcp = &mc;
  448. ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__);
  449. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  450. mcp->out_mb = MBX_0;
  451. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  452. if (IS_QLA81XX(vha->hw))
  453. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  454. mcp->flags = 0;
  455. mcp->tov = MBX_TOV_SECONDS;
  456. rval = qla2x00_mailbox_command(vha, mcp);
  457. if (rval != QLA_SUCCESS)
  458. goto failed;
  459. /* Return mailbox data. */
  460. *major = mcp->mb[1];
  461. *minor = mcp->mb[2];
  462. *subminor = mcp->mb[3];
  463. *attributes = mcp->mb[6];
  464. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  465. *memory = 0x1FFFF; /* Defaults to 128KB. */
  466. else
  467. *memory = (mcp->mb[5] << 16) | mcp->mb[4];
  468. if (IS_QLA81XX(vha->hw)) {
  469. mpi[0] = mcp->mb[10] & 0xff;
  470. mpi[1] = mcp->mb[11] >> 8;
  471. mpi[2] = mcp->mb[11] & 0xff;
  472. *mpi_caps = (mcp->mb[12] << 16) | mcp->mb[13];
  473. phy[0] = mcp->mb[8] & 0xff;
  474. phy[1] = mcp->mb[9] >> 8;
  475. phy[2] = mcp->mb[9] & 0xff;
  476. }
  477. failed:
  478. if (rval != QLA_SUCCESS) {
  479. /*EMPTY*/
  480. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  481. } else {
  482. /*EMPTY*/
  483. ql_dbg(ql_dbg_mbx, vha, 0x102b, "Done %s.\n", __func__);
  484. }
  485. return rval;
  486. }
  487. /*
  488. * qla2x00_get_fw_options
  489. * Set firmware options.
  490. *
  491. * Input:
  492. * ha = adapter block pointer.
  493. * fwopt = pointer for firmware options.
  494. *
  495. * Returns:
  496. * qla2x00 local function return status code.
  497. *
  498. * Context:
  499. * Kernel context.
  500. */
  501. int
  502. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  503. {
  504. int rval;
  505. mbx_cmd_t mc;
  506. mbx_cmd_t *mcp = &mc;
  507. ql_dbg(ql_dbg_mbx, vha, 0x102c, "Entered %s.\n", __func__);
  508. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  509. mcp->out_mb = MBX_0;
  510. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  511. mcp->tov = MBX_TOV_SECONDS;
  512. mcp->flags = 0;
  513. rval = qla2x00_mailbox_command(vha, mcp);
  514. if (rval != QLA_SUCCESS) {
  515. /*EMPTY*/
  516. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  517. } else {
  518. fwopts[0] = mcp->mb[0];
  519. fwopts[1] = mcp->mb[1];
  520. fwopts[2] = mcp->mb[2];
  521. fwopts[3] = mcp->mb[3];
  522. ql_dbg(ql_dbg_mbx, vha, 0x102e, "Done %s.\n", __func__);
  523. }
  524. return rval;
  525. }
  526. /*
  527. * qla2x00_set_fw_options
  528. * Set firmware options.
  529. *
  530. * Input:
  531. * ha = adapter block pointer.
  532. * fwopt = pointer for firmware options.
  533. *
  534. * Returns:
  535. * qla2x00 local function return status code.
  536. *
  537. * Context:
  538. * Kernel context.
  539. */
  540. int
  541. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  542. {
  543. int rval;
  544. mbx_cmd_t mc;
  545. mbx_cmd_t *mcp = &mc;
  546. ql_dbg(ql_dbg_mbx, vha, 0x102f, "Entered %s.\n", __func__);
  547. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  548. mcp->mb[1] = fwopts[1];
  549. mcp->mb[2] = fwopts[2];
  550. mcp->mb[3] = fwopts[3];
  551. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  552. mcp->in_mb = MBX_0;
  553. if (IS_FWI2_CAPABLE(vha->hw)) {
  554. mcp->in_mb |= MBX_1;
  555. } else {
  556. mcp->mb[10] = fwopts[10];
  557. mcp->mb[11] = fwopts[11];
  558. mcp->mb[12] = 0; /* Undocumented, but used */
  559. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  560. }
  561. mcp->tov = MBX_TOV_SECONDS;
  562. mcp->flags = 0;
  563. rval = qla2x00_mailbox_command(vha, mcp);
  564. fwopts[0] = mcp->mb[0];
  565. if (rval != QLA_SUCCESS) {
  566. /*EMPTY*/
  567. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  568. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  569. } else {
  570. /*EMPTY*/
  571. ql_dbg(ql_dbg_mbx, vha, 0x1031, "Done %s.\n", __func__);
  572. }
  573. return rval;
  574. }
  575. /*
  576. * qla2x00_mbx_reg_test
  577. * Mailbox register wrap test.
  578. *
  579. * Input:
  580. * ha = adapter block pointer.
  581. * TARGET_QUEUE_LOCK must be released.
  582. * ADAPTER_STATE_LOCK must be released.
  583. *
  584. * Returns:
  585. * qla2x00 local function return status code.
  586. *
  587. * Context:
  588. * Kernel context.
  589. */
  590. int
  591. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  592. {
  593. int rval;
  594. mbx_cmd_t mc;
  595. mbx_cmd_t *mcp = &mc;
  596. ql_dbg(ql_dbg_mbx, vha, 0x1032, "Entered %s.\n", __func__);
  597. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  598. mcp->mb[1] = 0xAAAA;
  599. mcp->mb[2] = 0x5555;
  600. mcp->mb[3] = 0xAA55;
  601. mcp->mb[4] = 0x55AA;
  602. mcp->mb[5] = 0xA5A5;
  603. mcp->mb[6] = 0x5A5A;
  604. mcp->mb[7] = 0x2525;
  605. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  606. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  607. mcp->tov = MBX_TOV_SECONDS;
  608. mcp->flags = 0;
  609. rval = qla2x00_mailbox_command(vha, mcp);
  610. if (rval == QLA_SUCCESS) {
  611. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  612. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  613. rval = QLA_FUNCTION_FAILED;
  614. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  615. mcp->mb[7] != 0x2525)
  616. rval = QLA_FUNCTION_FAILED;
  617. }
  618. if (rval != QLA_SUCCESS) {
  619. /*EMPTY*/
  620. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  621. } else {
  622. /*EMPTY*/
  623. ql_dbg(ql_dbg_mbx, vha, 0x1034, "Done %s.\n", __func__);
  624. }
  625. return rval;
  626. }
  627. /*
  628. * qla2x00_verify_checksum
  629. * Verify firmware checksum.
  630. *
  631. * Input:
  632. * ha = adapter block pointer.
  633. * TARGET_QUEUE_LOCK must be released.
  634. * ADAPTER_STATE_LOCK must be released.
  635. *
  636. * Returns:
  637. * qla2x00 local function return status code.
  638. *
  639. * Context:
  640. * Kernel context.
  641. */
  642. int
  643. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  644. {
  645. int rval;
  646. mbx_cmd_t mc;
  647. mbx_cmd_t *mcp = &mc;
  648. ql_dbg(ql_dbg_mbx, vha, 0x1035, "Entered %s.\n", __func__);
  649. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  650. mcp->out_mb = MBX_0;
  651. mcp->in_mb = MBX_0;
  652. if (IS_FWI2_CAPABLE(vha->hw)) {
  653. mcp->mb[1] = MSW(risc_addr);
  654. mcp->mb[2] = LSW(risc_addr);
  655. mcp->out_mb |= MBX_2|MBX_1;
  656. mcp->in_mb |= MBX_2|MBX_1;
  657. } else {
  658. mcp->mb[1] = LSW(risc_addr);
  659. mcp->out_mb |= MBX_1;
  660. mcp->in_mb |= MBX_1;
  661. }
  662. mcp->tov = MBX_TOV_SECONDS;
  663. mcp->flags = 0;
  664. rval = qla2x00_mailbox_command(vha, mcp);
  665. if (rval != QLA_SUCCESS) {
  666. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  667. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  668. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  669. } else {
  670. ql_dbg(ql_dbg_mbx, vha, 0x1037, "Done %s.\n", __func__);
  671. }
  672. return rval;
  673. }
  674. /*
  675. * qla2x00_issue_iocb
  676. * Issue IOCB using mailbox command
  677. *
  678. * Input:
  679. * ha = adapter state pointer.
  680. * buffer = buffer pointer.
  681. * phys_addr = physical address of buffer.
  682. * size = size of buffer.
  683. * TARGET_QUEUE_LOCK must be released.
  684. * ADAPTER_STATE_LOCK must be released.
  685. *
  686. * Returns:
  687. * qla2x00 local function return status code.
  688. *
  689. * Context:
  690. * Kernel context.
  691. */
  692. int
  693. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  694. dma_addr_t phys_addr, size_t size, uint32_t tov)
  695. {
  696. int rval;
  697. mbx_cmd_t mc;
  698. mbx_cmd_t *mcp = &mc;
  699. ql_dbg(ql_dbg_mbx, vha, 0x1038, "Entered %s.\n", __func__);
  700. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  701. mcp->mb[1] = 0;
  702. mcp->mb[2] = MSW(phys_addr);
  703. mcp->mb[3] = LSW(phys_addr);
  704. mcp->mb[6] = MSW(MSD(phys_addr));
  705. mcp->mb[7] = LSW(MSD(phys_addr));
  706. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  707. mcp->in_mb = MBX_2|MBX_0;
  708. mcp->tov = tov;
  709. mcp->flags = 0;
  710. rval = qla2x00_mailbox_command(vha, mcp);
  711. if (rval != QLA_SUCCESS) {
  712. /*EMPTY*/
  713. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  714. } else {
  715. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  716. /* Mask reserved bits. */
  717. sts_entry->entry_status &=
  718. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  719. ql_dbg(ql_dbg_mbx, vha, 0x103a, "Done %s.\n", __func__);
  720. }
  721. return rval;
  722. }
  723. int
  724. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  725. size_t size)
  726. {
  727. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  728. MBX_TOV_SECONDS);
  729. }
  730. /*
  731. * qla2x00_abort_command
  732. * Abort command aborts a specified IOCB.
  733. *
  734. * Input:
  735. * ha = adapter block pointer.
  736. * sp = SB structure pointer.
  737. *
  738. * Returns:
  739. * qla2x00 local function return status code.
  740. *
  741. * Context:
  742. * Kernel context.
  743. */
  744. int
  745. qla2x00_abort_command(srb_t *sp)
  746. {
  747. unsigned long flags = 0;
  748. int rval;
  749. uint32_t handle = 0;
  750. mbx_cmd_t mc;
  751. mbx_cmd_t *mcp = &mc;
  752. fc_port_t *fcport = sp->fcport;
  753. scsi_qla_host_t *vha = fcport->vha;
  754. struct qla_hw_data *ha = vha->hw;
  755. struct req_que *req = vha->req;
  756. ql_dbg(ql_dbg_mbx, vha, 0x103b, "Entered %s.\n", __func__);
  757. spin_lock_irqsave(&ha->hardware_lock, flags);
  758. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  759. if (req->outstanding_cmds[handle] == sp)
  760. break;
  761. }
  762. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  763. if (handle == MAX_OUTSTANDING_COMMANDS) {
  764. /* command not found */
  765. return QLA_FUNCTION_FAILED;
  766. }
  767. mcp->mb[0] = MBC_ABORT_COMMAND;
  768. if (HAS_EXTENDED_IDS(ha))
  769. mcp->mb[1] = fcport->loop_id;
  770. else
  771. mcp->mb[1] = fcport->loop_id << 8;
  772. mcp->mb[2] = (uint16_t)handle;
  773. mcp->mb[3] = (uint16_t)(handle >> 16);
  774. mcp->mb[6] = (uint16_t)sp->cmd->device->lun;
  775. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  776. mcp->in_mb = MBX_0;
  777. mcp->tov = MBX_TOV_SECONDS;
  778. mcp->flags = 0;
  779. rval = qla2x00_mailbox_command(vha, mcp);
  780. if (rval != QLA_SUCCESS) {
  781. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  782. } else {
  783. ql_dbg(ql_dbg_mbx, vha, 0x103d, "Done %s.\n", __func__);
  784. }
  785. return rval;
  786. }
  787. int
  788. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  789. {
  790. int rval, rval2;
  791. mbx_cmd_t mc;
  792. mbx_cmd_t *mcp = &mc;
  793. scsi_qla_host_t *vha;
  794. struct req_que *req;
  795. struct rsp_que *rsp;
  796. l = l;
  797. vha = fcport->vha;
  798. ql_dbg(ql_dbg_mbx, vha, 0x103e, "Entered %s.\n", __func__);
  799. req = vha->hw->req_q_map[0];
  800. rsp = req->rsp;
  801. mcp->mb[0] = MBC_ABORT_TARGET;
  802. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  803. if (HAS_EXTENDED_IDS(vha->hw)) {
  804. mcp->mb[1] = fcport->loop_id;
  805. mcp->mb[10] = 0;
  806. mcp->out_mb |= MBX_10;
  807. } else {
  808. mcp->mb[1] = fcport->loop_id << 8;
  809. }
  810. mcp->mb[2] = vha->hw->loop_reset_delay;
  811. mcp->mb[9] = vha->vp_idx;
  812. mcp->in_mb = MBX_0;
  813. mcp->tov = MBX_TOV_SECONDS;
  814. mcp->flags = 0;
  815. rval = qla2x00_mailbox_command(vha, mcp);
  816. if (rval != QLA_SUCCESS) {
  817. ql_dbg(ql_dbg_mbx, vha, 0x103f, "Failed=%x.\n", rval);
  818. }
  819. /* Issue marker IOCB. */
  820. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  821. MK_SYNC_ID);
  822. if (rval2 != QLA_SUCCESS) {
  823. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  824. "Failed to issue marker IOCB (%x).\n", rval2);
  825. } else {
  826. ql_dbg(ql_dbg_mbx, vha, 0x1041, "Done %s.\n", __func__);
  827. }
  828. return rval;
  829. }
  830. int
  831. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  832. {
  833. int rval, rval2;
  834. mbx_cmd_t mc;
  835. mbx_cmd_t *mcp = &mc;
  836. scsi_qla_host_t *vha;
  837. struct req_que *req;
  838. struct rsp_que *rsp;
  839. vha = fcport->vha;
  840. ql_dbg(ql_dbg_mbx, vha, 0x1042, "Entered %s.\n", __func__);
  841. req = vha->hw->req_q_map[0];
  842. rsp = req->rsp;
  843. mcp->mb[0] = MBC_LUN_RESET;
  844. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  845. if (HAS_EXTENDED_IDS(vha->hw))
  846. mcp->mb[1] = fcport->loop_id;
  847. else
  848. mcp->mb[1] = fcport->loop_id << 8;
  849. mcp->mb[2] = l;
  850. mcp->mb[3] = 0;
  851. mcp->mb[9] = vha->vp_idx;
  852. mcp->in_mb = MBX_0;
  853. mcp->tov = MBX_TOV_SECONDS;
  854. mcp->flags = 0;
  855. rval = qla2x00_mailbox_command(vha, mcp);
  856. if (rval != QLA_SUCCESS) {
  857. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  858. }
  859. /* Issue marker IOCB. */
  860. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  861. MK_SYNC_ID_LUN);
  862. if (rval2 != QLA_SUCCESS) {
  863. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  864. "Failed to issue marker IOCB (%x).\n", rval2);
  865. } else {
  866. ql_dbg(ql_dbg_mbx, vha, 0x1045, "Done %s.\n", __func__);
  867. }
  868. return rval;
  869. }
  870. /*
  871. * qla2x00_get_adapter_id
  872. * Get adapter ID and topology.
  873. *
  874. * Input:
  875. * ha = adapter block pointer.
  876. * id = pointer for loop ID.
  877. * al_pa = pointer for AL_PA.
  878. * area = pointer for area.
  879. * domain = pointer for domain.
  880. * top = pointer for topology.
  881. * TARGET_QUEUE_LOCK must be released.
  882. * ADAPTER_STATE_LOCK must be released.
  883. *
  884. * Returns:
  885. * qla2x00 local function return status code.
  886. *
  887. * Context:
  888. * Kernel context.
  889. */
  890. int
  891. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  892. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  893. {
  894. int rval;
  895. mbx_cmd_t mc;
  896. mbx_cmd_t *mcp = &mc;
  897. ql_dbg(ql_dbg_mbx, vha, 0x1046, "Entered %s.\n", __func__);
  898. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  899. mcp->mb[9] = vha->vp_idx;
  900. mcp->out_mb = MBX_9|MBX_0;
  901. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  902. if (IS_QLA8XXX_TYPE(vha->hw))
  903. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  904. mcp->tov = MBX_TOV_SECONDS;
  905. mcp->flags = 0;
  906. rval = qla2x00_mailbox_command(vha, mcp);
  907. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  908. rval = QLA_COMMAND_ERROR;
  909. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  910. rval = QLA_INVALID_COMMAND;
  911. /* Return data. */
  912. *id = mcp->mb[1];
  913. *al_pa = LSB(mcp->mb[2]);
  914. *area = MSB(mcp->mb[2]);
  915. *domain = LSB(mcp->mb[3]);
  916. *top = mcp->mb[6];
  917. *sw_cap = mcp->mb[7];
  918. if (rval != QLA_SUCCESS) {
  919. /*EMPTY*/
  920. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  921. } else {
  922. ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__);
  923. if (IS_QLA8XXX_TYPE(vha->hw)) {
  924. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  925. vha->fcoe_fcf_idx = mcp->mb[10];
  926. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  927. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  928. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  929. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  930. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  931. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  932. }
  933. }
  934. return rval;
  935. }
  936. /*
  937. * qla2x00_get_retry_cnt
  938. * Get current firmware login retry count and delay.
  939. *
  940. * Input:
  941. * ha = adapter block pointer.
  942. * retry_cnt = pointer to login retry count.
  943. * tov = pointer to login timeout value.
  944. *
  945. * Returns:
  946. * qla2x00 local function return status code.
  947. *
  948. * Context:
  949. * Kernel context.
  950. */
  951. int
  952. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  953. uint16_t *r_a_tov)
  954. {
  955. int rval;
  956. uint16_t ratov;
  957. mbx_cmd_t mc;
  958. mbx_cmd_t *mcp = &mc;
  959. ql_dbg(ql_dbg_mbx, vha, 0x1049, "Entered %s.\n", __func__);
  960. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  961. mcp->out_mb = MBX_0;
  962. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  963. mcp->tov = MBX_TOV_SECONDS;
  964. mcp->flags = 0;
  965. rval = qla2x00_mailbox_command(vha, mcp);
  966. if (rval != QLA_SUCCESS) {
  967. /*EMPTY*/
  968. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  969. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  970. } else {
  971. /* Convert returned data and check our values. */
  972. *r_a_tov = mcp->mb[3] / 2;
  973. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  974. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  975. /* Update to the larger values */
  976. *retry_cnt = (uint8_t)mcp->mb[1];
  977. *tov = ratov;
  978. }
  979. ql_dbg(ql_dbg_mbx, vha, 0x104b,
  980. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  981. }
  982. return rval;
  983. }
  984. /*
  985. * qla2x00_init_firmware
  986. * Initialize adapter firmware.
  987. *
  988. * Input:
  989. * ha = adapter block pointer.
  990. * dptr = Initialization control block pointer.
  991. * size = size of initialization control block.
  992. * TARGET_QUEUE_LOCK must be released.
  993. * ADAPTER_STATE_LOCK must be released.
  994. *
  995. * Returns:
  996. * qla2x00 local function return status code.
  997. *
  998. * Context:
  999. * Kernel context.
  1000. */
  1001. int
  1002. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1003. {
  1004. int rval;
  1005. mbx_cmd_t mc;
  1006. mbx_cmd_t *mcp = &mc;
  1007. struct qla_hw_data *ha = vha->hw;
  1008. ql_dbg(ql_dbg_mbx, vha, 0x104c, "Entered %s.\n", __func__);
  1009. if (IS_QLA82XX(ha) && ql2xdbwr)
  1010. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1011. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1012. if (ha->flags.npiv_supported)
  1013. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1014. else
  1015. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1016. mcp->mb[1] = 0;
  1017. mcp->mb[2] = MSW(ha->init_cb_dma);
  1018. mcp->mb[3] = LSW(ha->init_cb_dma);
  1019. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1020. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1021. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1022. if (IS_QLA81XX(ha) && ha->ex_init_cb->ex_version) {
  1023. mcp->mb[1] = BIT_0;
  1024. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1025. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1026. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1027. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1028. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1029. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1030. }
  1031. mcp->in_mb = MBX_0;
  1032. mcp->buf_size = size;
  1033. mcp->flags = MBX_DMA_OUT;
  1034. mcp->tov = MBX_TOV_SECONDS;
  1035. rval = qla2x00_mailbox_command(vha, mcp);
  1036. if (rval != QLA_SUCCESS) {
  1037. /*EMPTY*/
  1038. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1039. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1040. } else {
  1041. /*EMPTY*/
  1042. ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__);
  1043. }
  1044. return rval;
  1045. }
  1046. /*
  1047. * qla2x00_get_port_database
  1048. * Issue normal/enhanced get port database mailbox command
  1049. * and copy device name as necessary.
  1050. *
  1051. * Input:
  1052. * ha = adapter state pointer.
  1053. * dev = structure pointer.
  1054. * opt = enhanced cmd option byte.
  1055. *
  1056. * Returns:
  1057. * qla2x00 local function return status code.
  1058. *
  1059. * Context:
  1060. * Kernel context.
  1061. */
  1062. int
  1063. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1064. {
  1065. int rval;
  1066. mbx_cmd_t mc;
  1067. mbx_cmd_t *mcp = &mc;
  1068. port_database_t *pd;
  1069. struct port_database_24xx *pd24;
  1070. dma_addr_t pd_dma;
  1071. struct qla_hw_data *ha = vha->hw;
  1072. ql_dbg(ql_dbg_mbx, vha, 0x104f, "Entered %s.\n", __func__);
  1073. pd24 = NULL;
  1074. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1075. if (pd == NULL) {
  1076. ql_log(ql_log_warn, vha, 0x1050,
  1077. "Failed to allocate port database structure.\n");
  1078. return QLA_MEMORY_ALLOC_FAILED;
  1079. }
  1080. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1081. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1082. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1083. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1084. mcp->mb[2] = MSW(pd_dma);
  1085. mcp->mb[3] = LSW(pd_dma);
  1086. mcp->mb[6] = MSW(MSD(pd_dma));
  1087. mcp->mb[7] = LSW(MSD(pd_dma));
  1088. mcp->mb[9] = vha->vp_idx;
  1089. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1090. mcp->in_mb = MBX_0;
  1091. if (IS_FWI2_CAPABLE(ha)) {
  1092. mcp->mb[1] = fcport->loop_id;
  1093. mcp->mb[10] = opt;
  1094. mcp->out_mb |= MBX_10|MBX_1;
  1095. mcp->in_mb |= MBX_1;
  1096. } else if (HAS_EXTENDED_IDS(ha)) {
  1097. mcp->mb[1] = fcport->loop_id;
  1098. mcp->mb[10] = opt;
  1099. mcp->out_mb |= MBX_10|MBX_1;
  1100. } else {
  1101. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1102. mcp->out_mb |= MBX_1;
  1103. }
  1104. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1105. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1106. mcp->flags = MBX_DMA_IN;
  1107. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1108. rval = qla2x00_mailbox_command(vha, mcp);
  1109. if (rval != QLA_SUCCESS)
  1110. goto gpd_error_out;
  1111. if (IS_FWI2_CAPABLE(ha)) {
  1112. pd24 = (struct port_database_24xx *) pd;
  1113. /* Check for logged in state. */
  1114. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1115. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1116. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1117. "Unable to verify login-state (%x/%x) for "
  1118. "loop_id %x.\n", pd24->current_login_state,
  1119. pd24->last_login_state, fcport->loop_id);
  1120. rval = QLA_FUNCTION_FAILED;
  1121. goto gpd_error_out;
  1122. }
  1123. /* Names are little-endian. */
  1124. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1125. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1126. /* Get port_id of device. */
  1127. fcport->d_id.b.domain = pd24->port_id[0];
  1128. fcport->d_id.b.area = pd24->port_id[1];
  1129. fcport->d_id.b.al_pa = pd24->port_id[2];
  1130. fcport->d_id.b.rsvd_1 = 0;
  1131. /* If not target must be initiator or unknown type. */
  1132. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1133. fcport->port_type = FCT_INITIATOR;
  1134. else
  1135. fcport->port_type = FCT_TARGET;
  1136. } else {
  1137. /* Check for logged in state. */
  1138. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1139. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1140. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1141. "Unable to verify login-state (%x/%x) - "
  1142. "portid=%02x%02x%02x.\n", pd->master_state,
  1143. pd->slave_state, fcport->d_id.b.domain,
  1144. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1145. rval = QLA_FUNCTION_FAILED;
  1146. goto gpd_error_out;
  1147. }
  1148. /* Names are little-endian. */
  1149. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1150. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1151. /* Get port_id of device. */
  1152. fcport->d_id.b.domain = pd->port_id[0];
  1153. fcport->d_id.b.area = pd->port_id[3];
  1154. fcport->d_id.b.al_pa = pd->port_id[2];
  1155. fcport->d_id.b.rsvd_1 = 0;
  1156. /* If not target must be initiator or unknown type. */
  1157. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1158. fcport->port_type = FCT_INITIATOR;
  1159. else
  1160. fcport->port_type = FCT_TARGET;
  1161. /* Passback COS information. */
  1162. fcport->supported_classes = (pd->options & BIT_4) ?
  1163. FC_COS_CLASS2: FC_COS_CLASS3;
  1164. }
  1165. gpd_error_out:
  1166. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1167. if (rval != QLA_SUCCESS) {
  1168. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1169. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1170. mcp->mb[0], mcp->mb[1]);
  1171. } else {
  1172. ql_dbg(ql_dbg_mbx, vha, 0x1053, "Done %s.\n", __func__);
  1173. }
  1174. return rval;
  1175. }
  1176. /*
  1177. * qla2x00_get_firmware_state
  1178. * Get adapter firmware state.
  1179. *
  1180. * Input:
  1181. * ha = adapter block pointer.
  1182. * dptr = pointer for firmware state.
  1183. * TARGET_QUEUE_LOCK must be released.
  1184. * ADAPTER_STATE_LOCK must be released.
  1185. *
  1186. * Returns:
  1187. * qla2x00 local function return status code.
  1188. *
  1189. * Context:
  1190. * Kernel context.
  1191. */
  1192. int
  1193. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1194. {
  1195. int rval;
  1196. mbx_cmd_t mc;
  1197. mbx_cmd_t *mcp = &mc;
  1198. ql_dbg(ql_dbg_mbx, vha, 0x1054, "Entered %s.\n", __func__);
  1199. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1200. mcp->out_mb = MBX_0;
  1201. if (IS_FWI2_CAPABLE(vha->hw))
  1202. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1203. else
  1204. mcp->in_mb = MBX_1|MBX_0;
  1205. mcp->tov = MBX_TOV_SECONDS;
  1206. mcp->flags = 0;
  1207. rval = qla2x00_mailbox_command(vha, mcp);
  1208. /* Return firmware states. */
  1209. states[0] = mcp->mb[1];
  1210. if (IS_FWI2_CAPABLE(vha->hw)) {
  1211. states[1] = mcp->mb[2];
  1212. states[2] = mcp->mb[3];
  1213. states[3] = mcp->mb[4];
  1214. states[4] = mcp->mb[5];
  1215. }
  1216. if (rval != QLA_SUCCESS) {
  1217. /*EMPTY*/
  1218. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1219. } else {
  1220. /*EMPTY*/
  1221. ql_dbg(ql_dbg_mbx, vha, 0x1056, "Done %s.\n", __func__);
  1222. }
  1223. return rval;
  1224. }
  1225. /*
  1226. * qla2x00_get_port_name
  1227. * Issue get port name mailbox command.
  1228. * Returned name is in big endian format.
  1229. *
  1230. * Input:
  1231. * ha = adapter block pointer.
  1232. * loop_id = loop ID of device.
  1233. * name = pointer for name.
  1234. * TARGET_QUEUE_LOCK must be released.
  1235. * ADAPTER_STATE_LOCK must be released.
  1236. *
  1237. * Returns:
  1238. * qla2x00 local function return status code.
  1239. *
  1240. * Context:
  1241. * Kernel context.
  1242. */
  1243. int
  1244. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1245. uint8_t opt)
  1246. {
  1247. int rval;
  1248. mbx_cmd_t mc;
  1249. mbx_cmd_t *mcp = &mc;
  1250. ql_dbg(ql_dbg_mbx, vha, 0x1057, "Entered %s.\n", __func__);
  1251. mcp->mb[0] = MBC_GET_PORT_NAME;
  1252. mcp->mb[9] = vha->vp_idx;
  1253. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1254. if (HAS_EXTENDED_IDS(vha->hw)) {
  1255. mcp->mb[1] = loop_id;
  1256. mcp->mb[10] = opt;
  1257. mcp->out_mb |= MBX_10;
  1258. } else {
  1259. mcp->mb[1] = loop_id << 8 | opt;
  1260. }
  1261. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1262. mcp->tov = MBX_TOV_SECONDS;
  1263. mcp->flags = 0;
  1264. rval = qla2x00_mailbox_command(vha, mcp);
  1265. if (rval != QLA_SUCCESS) {
  1266. /*EMPTY*/
  1267. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1268. } else {
  1269. if (name != NULL) {
  1270. /* This function returns name in big endian. */
  1271. name[0] = MSB(mcp->mb[2]);
  1272. name[1] = LSB(mcp->mb[2]);
  1273. name[2] = MSB(mcp->mb[3]);
  1274. name[3] = LSB(mcp->mb[3]);
  1275. name[4] = MSB(mcp->mb[6]);
  1276. name[5] = LSB(mcp->mb[6]);
  1277. name[6] = MSB(mcp->mb[7]);
  1278. name[7] = LSB(mcp->mb[7]);
  1279. }
  1280. ql_dbg(ql_dbg_mbx, vha, 0x1059, "Done %s.\n", __func__);
  1281. }
  1282. return rval;
  1283. }
  1284. /*
  1285. * qla2x00_lip_reset
  1286. * Issue LIP reset mailbox command.
  1287. *
  1288. * Input:
  1289. * ha = adapter block pointer.
  1290. * TARGET_QUEUE_LOCK must be released.
  1291. * ADAPTER_STATE_LOCK must be released.
  1292. *
  1293. * Returns:
  1294. * qla2x00 local function return status code.
  1295. *
  1296. * Context:
  1297. * Kernel context.
  1298. */
  1299. int
  1300. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1301. {
  1302. int rval;
  1303. mbx_cmd_t mc;
  1304. mbx_cmd_t *mcp = &mc;
  1305. ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__);
  1306. if (IS_QLA8XXX_TYPE(vha->hw)) {
  1307. /* Logout across all FCFs. */
  1308. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1309. mcp->mb[1] = BIT_1;
  1310. mcp->mb[2] = 0;
  1311. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1312. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1313. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1314. mcp->mb[1] = BIT_6;
  1315. mcp->mb[2] = 0;
  1316. mcp->mb[3] = vha->hw->loop_reset_delay;
  1317. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1318. } else {
  1319. mcp->mb[0] = MBC_LIP_RESET;
  1320. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1321. if (HAS_EXTENDED_IDS(vha->hw)) {
  1322. mcp->mb[1] = 0x00ff;
  1323. mcp->mb[10] = 0;
  1324. mcp->out_mb |= MBX_10;
  1325. } else {
  1326. mcp->mb[1] = 0xff00;
  1327. }
  1328. mcp->mb[2] = vha->hw->loop_reset_delay;
  1329. mcp->mb[3] = 0;
  1330. }
  1331. mcp->in_mb = MBX_0;
  1332. mcp->tov = MBX_TOV_SECONDS;
  1333. mcp->flags = 0;
  1334. rval = qla2x00_mailbox_command(vha, mcp);
  1335. if (rval != QLA_SUCCESS) {
  1336. /*EMPTY*/
  1337. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1338. } else {
  1339. /*EMPTY*/
  1340. ql_dbg(ql_dbg_mbx, vha, 0x105c, "Done %s.\n", __func__);
  1341. }
  1342. return rval;
  1343. }
  1344. /*
  1345. * qla2x00_send_sns
  1346. * Send SNS command.
  1347. *
  1348. * Input:
  1349. * ha = adapter block pointer.
  1350. * sns = pointer for command.
  1351. * cmd_size = command size.
  1352. * buf_size = response/command size.
  1353. * TARGET_QUEUE_LOCK must be released.
  1354. * ADAPTER_STATE_LOCK must be released.
  1355. *
  1356. * Returns:
  1357. * qla2x00 local function return status code.
  1358. *
  1359. * Context:
  1360. * Kernel context.
  1361. */
  1362. int
  1363. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1364. uint16_t cmd_size, size_t buf_size)
  1365. {
  1366. int rval;
  1367. mbx_cmd_t mc;
  1368. mbx_cmd_t *mcp = &mc;
  1369. ql_dbg(ql_dbg_mbx, vha, 0x105d, "Entered %s.\n", __func__);
  1370. ql_dbg(ql_dbg_mbx, vha, 0x105e,
  1371. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1372. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1373. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1374. mcp->mb[1] = cmd_size;
  1375. mcp->mb[2] = MSW(sns_phys_address);
  1376. mcp->mb[3] = LSW(sns_phys_address);
  1377. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1378. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1379. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1380. mcp->in_mb = MBX_0|MBX_1;
  1381. mcp->buf_size = buf_size;
  1382. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1383. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1384. rval = qla2x00_mailbox_command(vha, mcp);
  1385. if (rval != QLA_SUCCESS) {
  1386. /*EMPTY*/
  1387. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1388. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1389. rval, mcp->mb[0], mcp->mb[1]);
  1390. } else {
  1391. /*EMPTY*/
  1392. ql_dbg(ql_dbg_mbx, vha, 0x1060, "Done %s.\n", __func__);
  1393. }
  1394. return rval;
  1395. }
  1396. int
  1397. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1398. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1399. {
  1400. int rval;
  1401. struct logio_entry_24xx *lg;
  1402. dma_addr_t lg_dma;
  1403. uint32_t iop[2];
  1404. struct qla_hw_data *ha = vha->hw;
  1405. struct req_que *req;
  1406. struct rsp_que *rsp;
  1407. ql_dbg(ql_dbg_mbx, vha, 0x1061, "Entered %s.\n", __func__);
  1408. if (ha->flags.cpu_affinity_enabled)
  1409. req = ha->req_q_map[0];
  1410. else
  1411. req = vha->req;
  1412. rsp = req->rsp;
  1413. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1414. if (lg == NULL) {
  1415. ql_log(ql_log_warn, vha, 0x1062,
  1416. "Failed to allocate login IOCB.\n");
  1417. return QLA_MEMORY_ALLOC_FAILED;
  1418. }
  1419. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1420. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1421. lg->entry_count = 1;
  1422. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1423. lg->nport_handle = cpu_to_le16(loop_id);
  1424. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1425. if (opt & BIT_0)
  1426. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1427. if (opt & BIT_1)
  1428. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1429. lg->port_id[0] = al_pa;
  1430. lg->port_id[1] = area;
  1431. lg->port_id[2] = domain;
  1432. lg->vp_index = vha->vp_idx;
  1433. rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
  1434. if (rval != QLA_SUCCESS) {
  1435. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1436. "Failed to issue login IOCB (%x).\n", rval);
  1437. } else if (lg->entry_status != 0) {
  1438. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1439. "Failed to complete IOCB -- error status (%x).\n",
  1440. lg->entry_status);
  1441. rval = QLA_FUNCTION_FAILED;
  1442. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1443. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1444. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1445. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1446. "Failed to complete IOCB -- completion status (%x) "
  1447. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1448. iop[0], iop[1]);
  1449. switch (iop[0]) {
  1450. case LSC_SCODE_PORTID_USED:
  1451. mb[0] = MBS_PORT_ID_USED;
  1452. mb[1] = LSW(iop[1]);
  1453. break;
  1454. case LSC_SCODE_NPORT_USED:
  1455. mb[0] = MBS_LOOP_ID_USED;
  1456. break;
  1457. case LSC_SCODE_NOLINK:
  1458. case LSC_SCODE_NOIOCB:
  1459. case LSC_SCODE_NOXCB:
  1460. case LSC_SCODE_CMD_FAILED:
  1461. case LSC_SCODE_NOFABRIC:
  1462. case LSC_SCODE_FW_NOT_READY:
  1463. case LSC_SCODE_NOT_LOGGED_IN:
  1464. case LSC_SCODE_NOPCB:
  1465. case LSC_SCODE_ELS_REJECT:
  1466. case LSC_SCODE_CMD_PARAM_ERR:
  1467. case LSC_SCODE_NONPORT:
  1468. case LSC_SCODE_LOGGED_IN:
  1469. case LSC_SCODE_NOFLOGI_ACC:
  1470. default:
  1471. mb[0] = MBS_COMMAND_ERROR;
  1472. break;
  1473. }
  1474. } else {
  1475. ql_dbg(ql_dbg_mbx, vha, 0x1066, "Done %s.\n", __func__);
  1476. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1477. mb[0] = MBS_COMMAND_COMPLETE;
  1478. mb[1] = 0;
  1479. if (iop[0] & BIT_4) {
  1480. if (iop[0] & BIT_8)
  1481. mb[1] |= BIT_1;
  1482. } else
  1483. mb[1] = BIT_0;
  1484. /* Passback COS information. */
  1485. mb[10] = 0;
  1486. if (lg->io_parameter[7] || lg->io_parameter[8])
  1487. mb[10] |= BIT_0; /* Class 2. */
  1488. if (lg->io_parameter[9] || lg->io_parameter[10])
  1489. mb[10] |= BIT_1; /* Class 3. */
  1490. }
  1491. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1492. return rval;
  1493. }
  1494. /*
  1495. * qla2x00_login_fabric
  1496. * Issue login fabric port mailbox command.
  1497. *
  1498. * Input:
  1499. * ha = adapter block pointer.
  1500. * loop_id = device loop ID.
  1501. * domain = device domain.
  1502. * area = device area.
  1503. * al_pa = device AL_PA.
  1504. * status = pointer for return status.
  1505. * opt = command options.
  1506. * TARGET_QUEUE_LOCK must be released.
  1507. * ADAPTER_STATE_LOCK must be released.
  1508. *
  1509. * Returns:
  1510. * qla2x00 local function return status code.
  1511. *
  1512. * Context:
  1513. * Kernel context.
  1514. */
  1515. int
  1516. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1517. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1518. {
  1519. int rval;
  1520. mbx_cmd_t mc;
  1521. mbx_cmd_t *mcp = &mc;
  1522. struct qla_hw_data *ha = vha->hw;
  1523. ql_dbg(ql_dbg_mbx, vha, 0x1067, "Entered %s.\n", __func__);
  1524. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1525. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1526. if (HAS_EXTENDED_IDS(ha)) {
  1527. mcp->mb[1] = loop_id;
  1528. mcp->mb[10] = opt;
  1529. mcp->out_mb |= MBX_10;
  1530. } else {
  1531. mcp->mb[1] = (loop_id << 8) | opt;
  1532. }
  1533. mcp->mb[2] = domain;
  1534. mcp->mb[3] = area << 8 | al_pa;
  1535. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1536. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1537. mcp->flags = 0;
  1538. rval = qla2x00_mailbox_command(vha, mcp);
  1539. /* Return mailbox statuses. */
  1540. if (mb != NULL) {
  1541. mb[0] = mcp->mb[0];
  1542. mb[1] = mcp->mb[1];
  1543. mb[2] = mcp->mb[2];
  1544. mb[6] = mcp->mb[6];
  1545. mb[7] = mcp->mb[7];
  1546. /* COS retrieved from Get-Port-Database mailbox command. */
  1547. mb[10] = 0;
  1548. }
  1549. if (rval != QLA_SUCCESS) {
  1550. /* RLU tmp code: need to change main mailbox_command function to
  1551. * return ok even when the mailbox completion value is not
  1552. * SUCCESS. The caller needs to be responsible to interpret
  1553. * the return values of this mailbox command if we're not
  1554. * to change too much of the existing code.
  1555. */
  1556. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1557. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1558. mcp->mb[0] == 0x4006)
  1559. rval = QLA_SUCCESS;
  1560. /*EMPTY*/
  1561. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1562. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1563. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1564. } else {
  1565. /*EMPTY*/
  1566. ql_dbg(ql_dbg_mbx, vha, 0x1069, "Done %s.\n", __func__);
  1567. }
  1568. return rval;
  1569. }
  1570. /*
  1571. * qla2x00_login_local_device
  1572. * Issue login loop port mailbox command.
  1573. *
  1574. * Input:
  1575. * ha = adapter block pointer.
  1576. * loop_id = device loop ID.
  1577. * opt = command options.
  1578. *
  1579. * Returns:
  1580. * Return status code.
  1581. *
  1582. * Context:
  1583. * Kernel context.
  1584. *
  1585. */
  1586. int
  1587. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1588. uint16_t *mb_ret, uint8_t opt)
  1589. {
  1590. int rval;
  1591. mbx_cmd_t mc;
  1592. mbx_cmd_t *mcp = &mc;
  1593. struct qla_hw_data *ha = vha->hw;
  1594. ql_dbg(ql_dbg_mbx, vha, 0x106a, "Entered %s.\n", __func__);
  1595. if (IS_FWI2_CAPABLE(ha))
  1596. return qla24xx_login_fabric(vha, fcport->loop_id,
  1597. fcport->d_id.b.domain, fcport->d_id.b.area,
  1598. fcport->d_id.b.al_pa, mb_ret, opt);
  1599. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1600. if (HAS_EXTENDED_IDS(ha))
  1601. mcp->mb[1] = fcport->loop_id;
  1602. else
  1603. mcp->mb[1] = fcport->loop_id << 8;
  1604. mcp->mb[2] = opt;
  1605. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1606. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1607. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1608. mcp->flags = 0;
  1609. rval = qla2x00_mailbox_command(vha, mcp);
  1610. /* Return mailbox statuses. */
  1611. if (mb_ret != NULL) {
  1612. mb_ret[0] = mcp->mb[0];
  1613. mb_ret[1] = mcp->mb[1];
  1614. mb_ret[6] = mcp->mb[6];
  1615. mb_ret[7] = mcp->mb[7];
  1616. }
  1617. if (rval != QLA_SUCCESS) {
  1618. /* AV tmp code: need to change main mailbox_command function to
  1619. * return ok even when the mailbox completion value is not
  1620. * SUCCESS. The caller needs to be responsible to interpret
  1621. * the return values of this mailbox command if we're not
  1622. * to change too much of the existing code.
  1623. */
  1624. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1625. rval = QLA_SUCCESS;
  1626. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1627. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1628. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1629. } else {
  1630. /*EMPTY*/
  1631. ql_dbg(ql_dbg_mbx, vha, 0x106c, "Done %s.\n", __func__);
  1632. }
  1633. return (rval);
  1634. }
  1635. int
  1636. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1637. uint8_t area, uint8_t al_pa)
  1638. {
  1639. int rval;
  1640. struct logio_entry_24xx *lg;
  1641. dma_addr_t lg_dma;
  1642. struct qla_hw_data *ha = vha->hw;
  1643. struct req_que *req;
  1644. struct rsp_que *rsp;
  1645. ql_dbg(ql_dbg_mbx, vha, 0x106d, "Entered %s.\n", __func__);
  1646. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1647. if (lg == NULL) {
  1648. ql_log(ql_log_warn, vha, 0x106e,
  1649. "Failed to allocate logout IOCB.\n");
  1650. return QLA_MEMORY_ALLOC_FAILED;
  1651. }
  1652. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1653. if (ql2xmaxqueues > 1)
  1654. req = ha->req_q_map[0];
  1655. else
  1656. req = vha->req;
  1657. rsp = req->rsp;
  1658. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1659. lg->entry_count = 1;
  1660. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1661. lg->nport_handle = cpu_to_le16(loop_id);
  1662. lg->control_flags =
  1663. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1664. LCF_FREE_NPORT);
  1665. lg->port_id[0] = al_pa;
  1666. lg->port_id[1] = area;
  1667. lg->port_id[2] = domain;
  1668. lg->vp_index = vha->vp_idx;
  1669. rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
  1670. if (rval != QLA_SUCCESS) {
  1671. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1672. "Failed to issue logout IOCB (%x).\n", rval);
  1673. } else if (lg->entry_status != 0) {
  1674. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1675. "Failed to complete IOCB -- error status (%x).\n",
  1676. lg->entry_status);
  1677. rval = QLA_FUNCTION_FAILED;
  1678. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1679. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1680. "Failed to complete IOCB -- completion status (%x) "
  1681. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1682. le32_to_cpu(lg->io_parameter[0]),
  1683. le32_to_cpu(lg->io_parameter[1]));
  1684. } else {
  1685. /*EMPTY*/
  1686. ql_dbg(ql_dbg_mbx, vha, 0x1072, "Done %s.\n", __func__);
  1687. }
  1688. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1689. return rval;
  1690. }
  1691. /*
  1692. * qla2x00_fabric_logout
  1693. * Issue logout fabric port mailbox command.
  1694. *
  1695. * Input:
  1696. * ha = adapter block pointer.
  1697. * loop_id = device loop ID.
  1698. * TARGET_QUEUE_LOCK must be released.
  1699. * ADAPTER_STATE_LOCK must be released.
  1700. *
  1701. * Returns:
  1702. * qla2x00 local function return status code.
  1703. *
  1704. * Context:
  1705. * Kernel context.
  1706. */
  1707. int
  1708. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1709. uint8_t area, uint8_t al_pa)
  1710. {
  1711. int rval;
  1712. mbx_cmd_t mc;
  1713. mbx_cmd_t *mcp = &mc;
  1714. ql_dbg(ql_dbg_mbx, vha, 0x1073, "Entered %s.\n", __func__);
  1715. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1716. mcp->out_mb = MBX_1|MBX_0;
  1717. if (HAS_EXTENDED_IDS(vha->hw)) {
  1718. mcp->mb[1] = loop_id;
  1719. mcp->mb[10] = 0;
  1720. mcp->out_mb |= MBX_10;
  1721. } else {
  1722. mcp->mb[1] = loop_id << 8;
  1723. }
  1724. mcp->in_mb = MBX_1|MBX_0;
  1725. mcp->tov = MBX_TOV_SECONDS;
  1726. mcp->flags = 0;
  1727. rval = qla2x00_mailbox_command(vha, mcp);
  1728. if (rval != QLA_SUCCESS) {
  1729. /*EMPTY*/
  1730. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1731. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1732. } else {
  1733. /*EMPTY*/
  1734. ql_dbg(ql_dbg_mbx, vha, 0x1075, "Done %s.\n", __func__);
  1735. }
  1736. return rval;
  1737. }
  1738. /*
  1739. * qla2x00_full_login_lip
  1740. * Issue full login LIP mailbox command.
  1741. *
  1742. * Input:
  1743. * ha = adapter block pointer.
  1744. * TARGET_QUEUE_LOCK must be released.
  1745. * ADAPTER_STATE_LOCK must be released.
  1746. *
  1747. * Returns:
  1748. * qla2x00 local function return status code.
  1749. *
  1750. * Context:
  1751. * Kernel context.
  1752. */
  1753. int
  1754. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1755. {
  1756. int rval;
  1757. mbx_cmd_t mc;
  1758. mbx_cmd_t *mcp = &mc;
  1759. ql_dbg(ql_dbg_mbx, vha, 0x1076, "Entered %s.\n", __func__);
  1760. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1761. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1762. mcp->mb[2] = 0;
  1763. mcp->mb[3] = 0;
  1764. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1765. mcp->in_mb = MBX_0;
  1766. mcp->tov = MBX_TOV_SECONDS;
  1767. mcp->flags = 0;
  1768. rval = qla2x00_mailbox_command(vha, mcp);
  1769. if (rval != QLA_SUCCESS) {
  1770. /*EMPTY*/
  1771. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  1772. } else {
  1773. /*EMPTY*/
  1774. ql_dbg(ql_dbg_mbx, vha, 0x1078, "Done %s.\n", __func__);
  1775. }
  1776. return rval;
  1777. }
  1778. /*
  1779. * qla2x00_get_id_list
  1780. *
  1781. * Input:
  1782. * ha = adapter block pointer.
  1783. *
  1784. * Returns:
  1785. * qla2x00 local function return status code.
  1786. *
  1787. * Context:
  1788. * Kernel context.
  1789. */
  1790. int
  1791. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  1792. uint16_t *entries)
  1793. {
  1794. int rval;
  1795. mbx_cmd_t mc;
  1796. mbx_cmd_t *mcp = &mc;
  1797. ql_dbg(ql_dbg_mbx, vha, 0x1079, "Entered %s.\n", __func__);
  1798. if (id_list == NULL)
  1799. return QLA_FUNCTION_FAILED;
  1800. mcp->mb[0] = MBC_GET_ID_LIST;
  1801. mcp->out_mb = MBX_0;
  1802. if (IS_FWI2_CAPABLE(vha->hw)) {
  1803. mcp->mb[2] = MSW(id_list_dma);
  1804. mcp->mb[3] = LSW(id_list_dma);
  1805. mcp->mb[6] = MSW(MSD(id_list_dma));
  1806. mcp->mb[7] = LSW(MSD(id_list_dma));
  1807. mcp->mb[8] = 0;
  1808. mcp->mb[9] = vha->vp_idx;
  1809. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  1810. } else {
  1811. mcp->mb[1] = MSW(id_list_dma);
  1812. mcp->mb[2] = LSW(id_list_dma);
  1813. mcp->mb[3] = MSW(MSD(id_list_dma));
  1814. mcp->mb[6] = LSW(MSD(id_list_dma));
  1815. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  1816. }
  1817. mcp->in_mb = MBX_1|MBX_0;
  1818. mcp->tov = MBX_TOV_SECONDS;
  1819. mcp->flags = 0;
  1820. rval = qla2x00_mailbox_command(vha, mcp);
  1821. if (rval != QLA_SUCCESS) {
  1822. /*EMPTY*/
  1823. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  1824. } else {
  1825. *entries = mcp->mb[1];
  1826. ql_dbg(ql_dbg_mbx, vha, 0x107b, "Done %s.\n", __func__);
  1827. }
  1828. return rval;
  1829. }
  1830. /*
  1831. * qla2x00_get_resource_cnts
  1832. * Get current firmware resource counts.
  1833. *
  1834. * Input:
  1835. * ha = adapter block pointer.
  1836. *
  1837. * Returns:
  1838. * qla2x00 local function return status code.
  1839. *
  1840. * Context:
  1841. * Kernel context.
  1842. */
  1843. int
  1844. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  1845. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  1846. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  1847. {
  1848. int rval;
  1849. mbx_cmd_t mc;
  1850. mbx_cmd_t *mcp = &mc;
  1851. ql_dbg(ql_dbg_mbx, vha, 0x107c, "Entered %s.\n", __func__);
  1852. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  1853. mcp->out_mb = MBX_0;
  1854. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1855. if (IS_QLA81XX(vha->hw))
  1856. mcp->in_mb |= MBX_12;
  1857. mcp->tov = MBX_TOV_SECONDS;
  1858. mcp->flags = 0;
  1859. rval = qla2x00_mailbox_command(vha, mcp);
  1860. if (rval != QLA_SUCCESS) {
  1861. /*EMPTY*/
  1862. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  1863. "Failed mb[0]=%x.\n", mcp->mb[0]);
  1864. } else {
  1865. ql_dbg(ql_dbg_mbx, vha, 0x107e,
  1866. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  1867. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  1868. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  1869. mcp->mb[11], mcp->mb[12]);
  1870. if (cur_xchg_cnt)
  1871. *cur_xchg_cnt = mcp->mb[3];
  1872. if (orig_xchg_cnt)
  1873. *orig_xchg_cnt = mcp->mb[6];
  1874. if (cur_iocb_cnt)
  1875. *cur_iocb_cnt = mcp->mb[7];
  1876. if (orig_iocb_cnt)
  1877. *orig_iocb_cnt = mcp->mb[10];
  1878. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  1879. *max_npiv_vports = mcp->mb[11];
  1880. if (IS_QLA81XX(vha->hw) && max_fcfs)
  1881. *max_fcfs = mcp->mb[12];
  1882. }
  1883. return (rval);
  1884. }
  1885. /*
  1886. * qla2x00_get_fcal_position_map
  1887. * Get FCAL (LILP) position map using mailbox command
  1888. *
  1889. * Input:
  1890. * ha = adapter state pointer.
  1891. * pos_map = buffer pointer (can be NULL).
  1892. *
  1893. * Returns:
  1894. * qla2x00 local function return status code.
  1895. *
  1896. * Context:
  1897. * Kernel context.
  1898. */
  1899. int
  1900. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  1901. {
  1902. int rval;
  1903. mbx_cmd_t mc;
  1904. mbx_cmd_t *mcp = &mc;
  1905. char *pmap;
  1906. dma_addr_t pmap_dma;
  1907. struct qla_hw_data *ha = vha->hw;
  1908. ql_dbg(ql_dbg_mbx, vha, 0x107f, "Entered %s.\n", __func__);
  1909. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  1910. if (pmap == NULL) {
  1911. ql_log(ql_log_warn, vha, 0x1080,
  1912. "Memory alloc failed.\n");
  1913. return QLA_MEMORY_ALLOC_FAILED;
  1914. }
  1915. memset(pmap, 0, FCAL_MAP_SIZE);
  1916. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  1917. mcp->mb[2] = MSW(pmap_dma);
  1918. mcp->mb[3] = LSW(pmap_dma);
  1919. mcp->mb[6] = MSW(MSD(pmap_dma));
  1920. mcp->mb[7] = LSW(MSD(pmap_dma));
  1921. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1922. mcp->in_mb = MBX_1|MBX_0;
  1923. mcp->buf_size = FCAL_MAP_SIZE;
  1924. mcp->flags = MBX_DMA_IN;
  1925. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1926. rval = qla2x00_mailbox_command(vha, mcp);
  1927. if (rval == QLA_SUCCESS) {
  1928. ql_dbg(ql_dbg_mbx, vha, 0x1081,
  1929. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  1930. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  1931. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  1932. pmap, pmap[0] + 1);
  1933. if (pos_map)
  1934. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  1935. }
  1936. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  1937. if (rval != QLA_SUCCESS) {
  1938. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  1939. } else {
  1940. ql_dbg(ql_dbg_mbx, vha, 0x1083, "Done %s.\n", __func__);
  1941. }
  1942. return rval;
  1943. }
  1944. /*
  1945. * qla2x00_get_link_status
  1946. *
  1947. * Input:
  1948. * ha = adapter block pointer.
  1949. * loop_id = device loop ID.
  1950. * ret_buf = pointer to link status return buffer.
  1951. *
  1952. * Returns:
  1953. * 0 = success.
  1954. * BIT_0 = mem alloc error.
  1955. * BIT_1 = mailbox error.
  1956. */
  1957. int
  1958. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  1959. struct link_statistics *stats, dma_addr_t stats_dma)
  1960. {
  1961. int rval;
  1962. mbx_cmd_t mc;
  1963. mbx_cmd_t *mcp = &mc;
  1964. uint32_t *siter, *diter, dwords;
  1965. struct qla_hw_data *ha = vha->hw;
  1966. ql_dbg(ql_dbg_mbx, vha, 0x1084, "Entered %s.\n", __func__);
  1967. mcp->mb[0] = MBC_GET_LINK_STATUS;
  1968. mcp->mb[2] = MSW(stats_dma);
  1969. mcp->mb[3] = LSW(stats_dma);
  1970. mcp->mb[6] = MSW(MSD(stats_dma));
  1971. mcp->mb[7] = LSW(MSD(stats_dma));
  1972. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1973. mcp->in_mb = MBX_0;
  1974. if (IS_FWI2_CAPABLE(ha)) {
  1975. mcp->mb[1] = loop_id;
  1976. mcp->mb[4] = 0;
  1977. mcp->mb[10] = 0;
  1978. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  1979. mcp->in_mb |= MBX_1;
  1980. } else if (HAS_EXTENDED_IDS(ha)) {
  1981. mcp->mb[1] = loop_id;
  1982. mcp->mb[10] = 0;
  1983. mcp->out_mb |= MBX_10|MBX_1;
  1984. } else {
  1985. mcp->mb[1] = loop_id << 8;
  1986. mcp->out_mb |= MBX_1;
  1987. }
  1988. mcp->tov = MBX_TOV_SECONDS;
  1989. mcp->flags = IOCTL_CMD;
  1990. rval = qla2x00_mailbox_command(vha, mcp);
  1991. if (rval == QLA_SUCCESS) {
  1992. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  1993. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  1994. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1995. rval = QLA_FUNCTION_FAILED;
  1996. } else {
  1997. /* Copy over data -- firmware data is LE. */
  1998. ql_dbg(ql_dbg_mbx, vha, 0x1086, "Done %s.\n", __func__);
  1999. dwords = offsetof(struct link_statistics, unused1) / 4;
  2000. siter = diter = &stats->link_fail_cnt;
  2001. while (dwords--)
  2002. *diter++ = le32_to_cpu(*siter++);
  2003. }
  2004. } else {
  2005. /* Failed. */
  2006. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2007. }
  2008. return rval;
  2009. }
  2010. int
  2011. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2012. dma_addr_t stats_dma)
  2013. {
  2014. int rval;
  2015. mbx_cmd_t mc;
  2016. mbx_cmd_t *mcp = &mc;
  2017. uint32_t *siter, *diter, dwords;
  2018. ql_dbg(ql_dbg_mbx, vha, 0x1088, "Entered %s.\n", __func__);
  2019. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2020. mcp->mb[2] = MSW(stats_dma);
  2021. mcp->mb[3] = LSW(stats_dma);
  2022. mcp->mb[6] = MSW(MSD(stats_dma));
  2023. mcp->mb[7] = LSW(MSD(stats_dma));
  2024. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2025. mcp->mb[9] = vha->vp_idx;
  2026. mcp->mb[10] = 0;
  2027. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2028. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2029. mcp->tov = MBX_TOV_SECONDS;
  2030. mcp->flags = IOCTL_CMD;
  2031. rval = qla2x00_mailbox_command(vha, mcp);
  2032. if (rval == QLA_SUCCESS) {
  2033. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2034. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2035. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2036. rval = QLA_FUNCTION_FAILED;
  2037. } else {
  2038. ql_dbg(ql_dbg_mbx, vha, 0x108a, "Done %s.\n", __func__);
  2039. /* Copy over data -- firmware data is LE. */
  2040. dwords = sizeof(struct link_statistics) / 4;
  2041. siter = diter = &stats->link_fail_cnt;
  2042. while (dwords--)
  2043. *diter++ = le32_to_cpu(*siter++);
  2044. }
  2045. } else {
  2046. /* Failed. */
  2047. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2048. }
  2049. return rval;
  2050. }
  2051. int
  2052. qla24xx_abort_command(srb_t *sp)
  2053. {
  2054. int rval;
  2055. unsigned long flags = 0;
  2056. struct abort_entry_24xx *abt;
  2057. dma_addr_t abt_dma;
  2058. uint32_t handle;
  2059. fc_port_t *fcport = sp->fcport;
  2060. struct scsi_qla_host *vha = fcport->vha;
  2061. struct qla_hw_data *ha = vha->hw;
  2062. struct req_que *req = vha->req;
  2063. ql_dbg(ql_dbg_mbx, vha, 0x108c, "Entered %s.\n", __func__);
  2064. spin_lock_irqsave(&ha->hardware_lock, flags);
  2065. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  2066. if (req->outstanding_cmds[handle] == sp)
  2067. break;
  2068. }
  2069. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2070. if (handle == MAX_OUTSTANDING_COMMANDS) {
  2071. /* Command not found. */
  2072. return QLA_FUNCTION_FAILED;
  2073. }
  2074. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2075. if (abt == NULL) {
  2076. ql_log(ql_log_warn, vha, 0x108d,
  2077. "Failed to allocate abort IOCB.\n");
  2078. return QLA_MEMORY_ALLOC_FAILED;
  2079. }
  2080. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2081. abt->entry_type = ABORT_IOCB_TYPE;
  2082. abt->entry_count = 1;
  2083. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2084. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2085. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2086. abt->port_id[0] = fcport->d_id.b.al_pa;
  2087. abt->port_id[1] = fcport->d_id.b.area;
  2088. abt->port_id[2] = fcport->d_id.b.domain;
  2089. abt->vp_index = fcport->vp_idx;
  2090. abt->req_que_no = cpu_to_le16(req->id);
  2091. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2092. if (rval != QLA_SUCCESS) {
  2093. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2094. "Failed to issue IOCB (%x).\n", rval);
  2095. } else if (abt->entry_status != 0) {
  2096. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2097. "Failed to complete IOCB -- error status (%x).\n",
  2098. abt->entry_status);
  2099. rval = QLA_FUNCTION_FAILED;
  2100. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2101. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2102. "Failed to complete IOCB -- completion status (%x).\n",
  2103. le16_to_cpu(abt->nport_handle));
  2104. rval = QLA_FUNCTION_FAILED;
  2105. } else {
  2106. ql_dbg(ql_dbg_mbx, vha, 0x1091, "Done %s.\n", __func__);
  2107. }
  2108. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2109. return rval;
  2110. }
  2111. struct tsk_mgmt_cmd {
  2112. union {
  2113. struct tsk_mgmt_entry tsk;
  2114. struct sts_entry_24xx sts;
  2115. } p;
  2116. };
  2117. static int
  2118. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2119. unsigned int l, int tag)
  2120. {
  2121. int rval, rval2;
  2122. struct tsk_mgmt_cmd *tsk;
  2123. struct sts_entry_24xx *sts;
  2124. dma_addr_t tsk_dma;
  2125. scsi_qla_host_t *vha;
  2126. struct qla_hw_data *ha;
  2127. struct req_que *req;
  2128. struct rsp_que *rsp;
  2129. vha = fcport->vha;
  2130. ha = vha->hw;
  2131. req = vha->req;
  2132. ql_dbg(ql_dbg_mbx, vha, 0x1092, "Entered %s.\n", __func__);
  2133. if (ha->flags.cpu_affinity_enabled)
  2134. rsp = ha->rsp_q_map[tag + 1];
  2135. else
  2136. rsp = req->rsp;
  2137. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2138. if (tsk == NULL) {
  2139. ql_log(ql_log_warn, vha, 0x1093,
  2140. "Failed to allocate task management IOCB.\n");
  2141. return QLA_MEMORY_ALLOC_FAILED;
  2142. }
  2143. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2144. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2145. tsk->p.tsk.entry_count = 1;
  2146. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2147. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2148. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2149. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2150. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2151. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2152. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2153. tsk->p.tsk.vp_index = fcport->vp_idx;
  2154. if (type == TCF_LUN_RESET) {
  2155. int_to_scsilun(l, &tsk->p.tsk.lun);
  2156. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2157. sizeof(tsk->p.tsk.lun));
  2158. }
  2159. sts = &tsk->p.sts;
  2160. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2161. if (rval != QLA_SUCCESS) {
  2162. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2163. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2164. } else if (sts->entry_status != 0) {
  2165. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2166. "Failed to complete IOCB -- error status (%x).\n",
  2167. sts->entry_status);
  2168. rval = QLA_FUNCTION_FAILED;
  2169. } else if (sts->comp_status !=
  2170. __constant_cpu_to_le16(CS_COMPLETE)) {
  2171. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2172. "Failed to complete IOCB -- completion status (%x).\n",
  2173. le16_to_cpu(sts->comp_status));
  2174. rval = QLA_FUNCTION_FAILED;
  2175. } else if (le16_to_cpu(sts->scsi_status) &
  2176. SS_RESPONSE_INFO_LEN_VALID) {
  2177. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2178. ql_dbg(ql_dbg_mbx, vha, 0x1097,
  2179. "Ignoring inconsistent data length -- not enough "
  2180. "response info (%d).\n",
  2181. le32_to_cpu(sts->rsp_data_len));
  2182. } else if (sts->data[3]) {
  2183. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2184. "Failed to complete IOCB -- response (%x).\n",
  2185. sts->data[3]);
  2186. rval = QLA_FUNCTION_FAILED;
  2187. }
  2188. }
  2189. /* Issue marker IOCB. */
  2190. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2191. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2192. if (rval2 != QLA_SUCCESS) {
  2193. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2194. "Failed to issue marker IOCB (%x).\n", rval2);
  2195. } else {
  2196. ql_dbg(ql_dbg_mbx, vha, 0x109a, "Done %s.\n", __func__);
  2197. }
  2198. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2199. return rval;
  2200. }
  2201. int
  2202. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2203. {
  2204. struct qla_hw_data *ha = fcport->vha->hw;
  2205. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2206. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2207. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2208. }
  2209. int
  2210. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2211. {
  2212. struct qla_hw_data *ha = fcport->vha->hw;
  2213. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2214. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2215. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2216. }
  2217. int
  2218. qla2x00_system_error(scsi_qla_host_t *vha)
  2219. {
  2220. int rval;
  2221. mbx_cmd_t mc;
  2222. mbx_cmd_t *mcp = &mc;
  2223. struct qla_hw_data *ha = vha->hw;
  2224. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2225. return QLA_FUNCTION_FAILED;
  2226. ql_dbg(ql_dbg_mbx, vha, 0x109b, "Entered %s.\n", __func__);
  2227. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2228. mcp->out_mb = MBX_0;
  2229. mcp->in_mb = MBX_0;
  2230. mcp->tov = 5;
  2231. mcp->flags = 0;
  2232. rval = qla2x00_mailbox_command(vha, mcp);
  2233. if (rval != QLA_SUCCESS) {
  2234. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2235. } else {
  2236. ql_dbg(ql_dbg_mbx, vha, 0x109d, "Done %s.\n", __func__);
  2237. }
  2238. return rval;
  2239. }
  2240. /**
  2241. * qla2x00_set_serdes_params() -
  2242. * @ha: HA context
  2243. *
  2244. * Returns
  2245. */
  2246. int
  2247. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2248. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2249. {
  2250. int rval;
  2251. mbx_cmd_t mc;
  2252. mbx_cmd_t *mcp = &mc;
  2253. ql_dbg(ql_dbg_mbx, vha, 0x109e, "Entered %s.\n", __func__);
  2254. mcp->mb[0] = MBC_SERDES_PARAMS;
  2255. mcp->mb[1] = BIT_0;
  2256. mcp->mb[2] = sw_em_1g | BIT_15;
  2257. mcp->mb[3] = sw_em_2g | BIT_15;
  2258. mcp->mb[4] = sw_em_4g | BIT_15;
  2259. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2260. mcp->in_mb = MBX_0;
  2261. mcp->tov = MBX_TOV_SECONDS;
  2262. mcp->flags = 0;
  2263. rval = qla2x00_mailbox_command(vha, mcp);
  2264. if (rval != QLA_SUCCESS) {
  2265. /*EMPTY*/
  2266. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2267. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2268. } else {
  2269. /*EMPTY*/
  2270. ql_dbg(ql_dbg_mbx, vha, 0x10a0, "Done %s.\n", __func__);
  2271. }
  2272. return rval;
  2273. }
  2274. int
  2275. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2276. {
  2277. int rval;
  2278. mbx_cmd_t mc;
  2279. mbx_cmd_t *mcp = &mc;
  2280. if (!IS_FWI2_CAPABLE(vha->hw))
  2281. return QLA_FUNCTION_FAILED;
  2282. ql_dbg(ql_dbg_mbx, vha, 0x10a1, "Entered %s.\n", __func__);
  2283. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2284. mcp->mb[1] = 0;
  2285. mcp->out_mb = MBX_1|MBX_0;
  2286. mcp->in_mb = MBX_0;
  2287. mcp->tov = 5;
  2288. mcp->flags = 0;
  2289. rval = qla2x00_mailbox_command(vha, mcp);
  2290. if (rval != QLA_SUCCESS) {
  2291. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2292. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2293. rval = QLA_INVALID_COMMAND;
  2294. } else {
  2295. ql_dbg(ql_dbg_mbx, vha, 0x10a3, "Done %s.\n", __func__);
  2296. }
  2297. return rval;
  2298. }
  2299. int
  2300. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2301. uint16_t buffers)
  2302. {
  2303. int rval;
  2304. mbx_cmd_t mc;
  2305. mbx_cmd_t *mcp = &mc;
  2306. ql_dbg(ql_dbg_mbx, vha, 0x10a4, "Entered %s.\n", __func__);
  2307. if (!IS_FWI2_CAPABLE(vha->hw))
  2308. return QLA_FUNCTION_FAILED;
  2309. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2310. return QLA_FUNCTION_FAILED;
  2311. mcp->mb[0] = MBC_TRACE_CONTROL;
  2312. mcp->mb[1] = TC_EFT_ENABLE;
  2313. mcp->mb[2] = LSW(eft_dma);
  2314. mcp->mb[3] = MSW(eft_dma);
  2315. mcp->mb[4] = LSW(MSD(eft_dma));
  2316. mcp->mb[5] = MSW(MSD(eft_dma));
  2317. mcp->mb[6] = buffers;
  2318. mcp->mb[7] = TC_AEN_DISABLE;
  2319. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2320. mcp->in_mb = MBX_1|MBX_0;
  2321. mcp->tov = MBX_TOV_SECONDS;
  2322. mcp->flags = 0;
  2323. rval = qla2x00_mailbox_command(vha, mcp);
  2324. if (rval != QLA_SUCCESS) {
  2325. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2326. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2327. rval, mcp->mb[0], mcp->mb[1]);
  2328. } else {
  2329. ql_dbg(ql_dbg_mbx, vha, 0x10a6, "Done %s.\n", __func__);
  2330. }
  2331. return rval;
  2332. }
  2333. int
  2334. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2335. {
  2336. int rval;
  2337. mbx_cmd_t mc;
  2338. mbx_cmd_t *mcp = &mc;
  2339. ql_dbg(ql_dbg_mbx, vha, 0x10a7, "Entered %s.\n", __func__);
  2340. if (!IS_FWI2_CAPABLE(vha->hw))
  2341. return QLA_FUNCTION_FAILED;
  2342. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2343. return QLA_FUNCTION_FAILED;
  2344. mcp->mb[0] = MBC_TRACE_CONTROL;
  2345. mcp->mb[1] = TC_EFT_DISABLE;
  2346. mcp->out_mb = MBX_1|MBX_0;
  2347. mcp->in_mb = MBX_1|MBX_0;
  2348. mcp->tov = MBX_TOV_SECONDS;
  2349. mcp->flags = 0;
  2350. rval = qla2x00_mailbox_command(vha, mcp);
  2351. if (rval != QLA_SUCCESS) {
  2352. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2353. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2354. rval, mcp->mb[0], mcp->mb[1]);
  2355. } else {
  2356. ql_dbg(ql_dbg_mbx, vha, 0x10a9, "Done %s.\n", __func__);
  2357. }
  2358. return rval;
  2359. }
  2360. int
  2361. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2362. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2363. {
  2364. int rval;
  2365. mbx_cmd_t mc;
  2366. mbx_cmd_t *mcp = &mc;
  2367. ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__);
  2368. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw))
  2369. return QLA_FUNCTION_FAILED;
  2370. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2371. return QLA_FUNCTION_FAILED;
  2372. mcp->mb[0] = MBC_TRACE_CONTROL;
  2373. mcp->mb[1] = TC_FCE_ENABLE;
  2374. mcp->mb[2] = LSW(fce_dma);
  2375. mcp->mb[3] = MSW(fce_dma);
  2376. mcp->mb[4] = LSW(MSD(fce_dma));
  2377. mcp->mb[5] = MSW(MSD(fce_dma));
  2378. mcp->mb[6] = buffers;
  2379. mcp->mb[7] = TC_AEN_DISABLE;
  2380. mcp->mb[8] = 0;
  2381. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2382. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2383. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2384. MBX_1|MBX_0;
  2385. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2386. mcp->tov = MBX_TOV_SECONDS;
  2387. mcp->flags = 0;
  2388. rval = qla2x00_mailbox_command(vha, mcp);
  2389. if (rval != QLA_SUCCESS) {
  2390. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2391. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2392. rval, mcp->mb[0], mcp->mb[1]);
  2393. } else {
  2394. ql_dbg(ql_dbg_mbx, vha, 0x10ac, "Done %s.\n", __func__);
  2395. if (mb)
  2396. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2397. if (dwords)
  2398. *dwords = buffers;
  2399. }
  2400. return rval;
  2401. }
  2402. int
  2403. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2404. {
  2405. int rval;
  2406. mbx_cmd_t mc;
  2407. mbx_cmd_t *mcp = &mc;
  2408. ql_dbg(ql_dbg_mbx, vha, 0x10ad, "Entered %s.\n", __func__);
  2409. if (!IS_FWI2_CAPABLE(vha->hw))
  2410. return QLA_FUNCTION_FAILED;
  2411. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2412. return QLA_FUNCTION_FAILED;
  2413. mcp->mb[0] = MBC_TRACE_CONTROL;
  2414. mcp->mb[1] = TC_FCE_DISABLE;
  2415. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2416. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2417. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2418. MBX_1|MBX_0;
  2419. mcp->tov = MBX_TOV_SECONDS;
  2420. mcp->flags = 0;
  2421. rval = qla2x00_mailbox_command(vha, mcp);
  2422. if (rval != QLA_SUCCESS) {
  2423. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2424. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2425. rval, mcp->mb[0], mcp->mb[1]);
  2426. } else {
  2427. ql_dbg(ql_dbg_mbx, vha, 0x10af, "Done %s.\n", __func__);
  2428. if (wr)
  2429. *wr = (uint64_t) mcp->mb[5] << 48 |
  2430. (uint64_t) mcp->mb[4] << 32 |
  2431. (uint64_t) mcp->mb[3] << 16 |
  2432. (uint64_t) mcp->mb[2];
  2433. if (rd)
  2434. *rd = (uint64_t) mcp->mb[9] << 48 |
  2435. (uint64_t) mcp->mb[8] << 32 |
  2436. (uint64_t) mcp->mb[7] << 16 |
  2437. (uint64_t) mcp->mb[6];
  2438. }
  2439. return rval;
  2440. }
  2441. int
  2442. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2443. uint16_t *port_speed, uint16_t *mb)
  2444. {
  2445. int rval;
  2446. mbx_cmd_t mc;
  2447. mbx_cmd_t *mcp = &mc;
  2448. ql_dbg(ql_dbg_mbx, vha, 0x10b0, "Entered %s.\n", __func__);
  2449. if (!IS_IIDMA_CAPABLE(vha->hw))
  2450. return QLA_FUNCTION_FAILED;
  2451. mcp->mb[0] = MBC_PORT_PARAMS;
  2452. mcp->mb[1] = loop_id;
  2453. mcp->mb[2] = mcp->mb[3] = 0;
  2454. mcp->mb[9] = vha->vp_idx;
  2455. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2456. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2457. mcp->tov = MBX_TOV_SECONDS;
  2458. mcp->flags = 0;
  2459. rval = qla2x00_mailbox_command(vha, mcp);
  2460. /* Return mailbox statuses. */
  2461. if (mb != NULL) {
  2462. mb[0] = mcp->mb[0];
  2463. mb[1] = mcp->mb[1];
  2464. mb[3] = mcp->mb[3];
  2465. }
  2466. if (rval != QLA_SUCCESS) {
  2467. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2468. } else {
  2469. ql_dbg(ql_dbg_mbx, vha, 0x10b2, "Done %s.\n", __func__);
  2470. if (port_speed)
  2471. *port_speed = mcp->mb[3];
  2472. }
  2473. return rval;
  2474. }
  2475. int
  2476. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2477. uint16_t port_speed, uint16_t *mb)
  2478. {
  2479. int rval;
  2480. mbx_cmd_t mc;
  2481. mbx_cmd_t *mcp = &mc;
  2482. ql_dbg(ql_dbg_mbx, vha, 0x10b3, "Entered %s.\n", __func__);
  2483. if (!IS_IIDMA_CAPABLE(vha->hw))
  2484. return QLA_FUNCTION_FAILED;
  2485. mcp->mb[0] = MBC_PORT_PARAMS;
  2486. mcp->mb[1] = loop_id;
  2487. mcp->mb[2] = BIT_0;
  2488. if (IS_QLA8XXX_TYPE(vha->hw))
  2489. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2490. else
  2491. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2492. mcp->mb[9] = vha->vp_idx;
  2493. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2494. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2495. mcp->tov = MBX_TOV_SECONDS;
  2496. mcp->flags = 0;
  2497. rval = qla2x00_mailbox_command(vha, mcp);
  2498. /* Return mailbox statuses. */
  2499. if (mb != NULL) {
  2500. mb[0] = mcp->mb[0];
  2501. mb[1] = mcp->mb[1];
  2502. mb[3] = mcp->mb[3];
  2503. }
  2504. if (rval != QLA_SUCCESS) {
  2505. ql_dbg(ql_dbg_mbx, vha, 0x10b4, "Failed=%x.\n", rval);
  2506. } else {
  2507. ql_dbg(ql_dbg_mbx, vha, 0x10b5, "Done %s.\n", __func__);
  2508. }
  2509. return rval;
  2510. }
  2511. void
  2512. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2513. struct vp_rpt_id_entry_24xx *rptid_entry)
  2514. {
  2515. uint8_t vp_idx;
  2516. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2517. struct qla_hw_data *ha = vha->hw;
  2518. scsi_qla_host_t *vp;
  2519. unsigned long flags;
  2520. ql_dbg(ql_dbg_mbx, vha, 0x10b6, "Entered %s.\n", __func__);
  2521. if (rptid_entry->entry_status != 0)
  2522. return;
  2523. if (rptid_entry->format == 0) {
  2524. ql_dbg(ql_dbg_mbx, vha, 0x10b7,
  2525. "Format 0 : Number of VPs setup %d, number of "
  2526. "VPs acquired %d.\n",
  2527. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2528. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2529. ql_dbg(ql_dbg_mbx, vha, 0x10b8,
  2530. "Primary port id %02x%02x%02x.\n",
  2531. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2532. rptid_entry->port_id[0]);
  2533. } else if (rptid_entry->format == 1) {
  2534. vp_idx = LSB(stat);
  2535. ql_dbg(ql_dbg_mbx, vha, 0x10b9,
  2536. "Format 1: VP[%d] enabled - status %d - with "
  2537. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2538. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2539. rptid_entry->port_id[0]);
  2540. vp = vha;
  2541. if (vp_idx == 0 && (MSB(stat) != 1))
  2542. goto reg_needed;
  2543. if (MSB(stat) != 0) {
  2544. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2545. "Could not acquire ID for VP[%d].\n", vp_idx);
  2546. return;
  2547. }
  2548. spin_lock_irqsave(&ha->vport_slock, flags);
  2549. list_for_each_entry(vp, &ha->vp_list, list)
  2550. if (vp_idx == vp->vp_idx)
  2551. break;
  2552. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2553. if (!vp)
  2554. return;
  2555. vp->d_id.b.domain = rptid_entry->port_id[2];
  2556. vp->d_id.b.area = rptid_entry->port_id[1];
  2557. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2558. /*
  2559. * Cannot configure here as we are still sitting on the
  2560. * response queue. Handle it in dpc context.
  2561. */
  2562. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2563. reg_needed:
  2564. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2565. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2566. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2567. qla2xxx_wake_dpc(vha);
  2568. }
  2569. }
  2570. /*
  2571. * qla24xx_modify_vp_config
  2572. * Change VP configuration for vha
  2573. *
  2574. * Input:
  2575. * vha = adapter block pointer.
  2576. *
  2577. * Returns:
  2578. * qla2xxx local function return status code.
  2579. *
  2580. * Context:
  2581. * Kernel context.
  2582. */
  2583. int
  2584. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2585. {
  2586. int rval;
  2587. struct vp_config_entry_24xx *vpmod;
  2588. dma_addr_t vpmod_dma;
  2589. struct qla_hw_data *ha = vha->hw;
  2590. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2591. /* This can be called by the parent */
  2592. ql_dbg(ql_dbg_mbx, vha, 0x10bb, "Entered %s.\n", __func__);
  2593. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2594. if (!vpmod) {
  2595. ql_log(ql_log_warn, vha, 0x10bc,
  2596. "Failed to allocate modify VP IOCB.\n");
  2597. return QLA_MEMORY_ALLOC_FAILED;
  2598. }
  2599. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2600. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2601. vpmod->entry_count = 1;
  2602. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2603. vpmod->vp_count = 1;
  2604. vpmod->vp_index1 = vha->vp_idx;
  2605. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2606. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2607. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2608. vpmod->entry_count = 1;
  2609. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2610. if (rval != QLA_SUCCESS) {
  2611. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2612. "Failed to issue VP config IOCB (%x).\n", rval);
  2613. } else if (vpmod->comp_status != 0) {
  2614. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2615. "Failed to complete IOCB -- error status (%x).\n",
  2616. vpmod->comp_status);
  2617. rval = QLA_FUNCTION_FAILED;
  2618. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2619. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2620. "Failed to complete IOCB -- completion status (%x).\n",
  2621. le16_to_cpu(vpmod->comp_status));
  2622. rval = QLA_FUNCTION_FAILED;
  2623. } else {
  2624. /* EMPTY */
  2625. ql_dbg(ql_dbg_mbx, vha, 0x10c0, "Done %s.\n", __func__);
  2626. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2627. }
  2628. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2629. return rval;
  2630. }
  2631. /*
  2632. * qla24xx_control_vp
  2633. * Enable a virtual port for given host
  2634. *
  2635. * Input:
  2636. * ha = adapter block pointer.
  2637. * vhba = virtual adapter (unused)
  2638. * index = index number for enabled VP
  2639. *
  2640. * Returns:
  2641. * qla2xxx local function return status code.
  2642. *
  2643. * Context:
  2644. * Kernel context.
  2645. */
  2646. int
  2647. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2648. {
  2649. int rval;
  2650. int map, pos;
  2651. struct vp_ctrl_entry_24xx *vce;
  2652. dma_addr_t vce_dma;
  2653. struct qla_hw_data *ha = vha->hw;
  2654. int vp_index = vha->vp_idx;
  2655. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2656. ql_dbg(ql_dbg_mbx, vha, 0x10c1,
  2657. "Entered %s enabling index %d.\n", __func__, vp_index);
  2658. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2659. return QLA_PARAMETER_ERROR;
  2660. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2661. if (!vce) {
  2662. ql_log(ql_log_warn, vha, 0x10c2,
  2663. "Failed to allocate VP control IOCB.\n");
  2664. return QLA_MEMORY_ALLOC_FAILED;
  2665. }
  2666. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2667. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2668. vce->entry_count = 1;
  2669. vce->command = cpu_to_le16(cmd);
  2670. vce->vp_count = __constant_cpu_to_le16(1);
  2671. /* index map in firmware starts with 1; decrement index
  2672. * this is ok as we never use index 0
  2673. */
  2674. map = (vp_index - 1) / 8;
  2675. pos = (vp_index - 1) & 7;
  2676. mutex_lock(&ha->vport_lock);
  2677. vce->vp_idx_map[map] |= 1 << pos;
  2678. mutex_unlock(&ha->vport_lock);
  2679. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2680. if (rval != QLA_SUCCESS) {
  2681. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2682. "Failed to issue VP control IOCB (%x).\n", rval);
  2683. } else if (vce->entry_status != 0) {
  2684. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2685. "Failed to complete IOCB -- error status (%x).\n",
  2686. vce->entry_status);
  2687. rval = QLA_FUNCTION_FAILED;
  2688. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2689. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2690. "Failed to complet IOCB -- completion status (%x).\n",
  2691. le16_to_cpu(vce->comp_status));
  2692. rval = QLA_FUNCTION_FAILED;
  2693. } else {
  2694. ql_dbg(ql_dbg_mbx, vha, 0x10c6, "Done %s.\n", __func__);
  2695. }
  2696. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2697. return rval;
  2698. }
  2699. /*
  2700. * qla2x00_send_change_request
  2701. * Receive or disable RSCN request from fabric controller
  2702. *
  2703. * Input:
  2704. * ha = adapter block pointer
  2705. * format = registration format:
  2706. * 0 - Reserved
  2707. * 1 - Fabric detected registration
  2708. * 2 - N_port detected registration
  2709. * 3 - Full registration
  2710. * FF - clear registration
  2711. * vp_idx = Virtual port index
  2712. *
  2713. * Returns:
  2714. * qla2x00 local function return status code.
  2715. *
  2716. * Context:
  2717. * Kernel Context
  2718. */
  2719. int
  2720. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2721. uint16_t vp_idx)
  2722. {
  2723. int rval;
  2724. mbx_cmd_t mc;
  2725. mbx_cmd_t *mcp = &mc;
  2726. ql_dbg(ql_dbg_mbx, vha, 0x10c7, "Entered %s.\n", __func__);
  2727. /*
  2728. * This command is implicitly executed by firmware during login for the
  2729. * physical hosts
  2730. */
  2731. if (vp_idx == 0)
  2732. return QLA_FUNCTION_FAILED;
  2733. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  2734. mcp->mb[1] = format;
  2735. mcp->mb[9] = vp_idx;
  2736. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  2737. mcp->in_mb = MBX_0|MBX_1;
  2738. mcp->tov = MBX_TOV_SECONDS;
  2739. mcp->flags = 0;
  2740. rval = qla2x00_mailbox_command(vha, mcp);
  2741. if (rval == QLA_SUCCESS) {
  2742. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2743. rval = BIT_1;
  2744. }
  2745. } else
  2746. rval = BIT_1;
  2747. return rval;
  2748. }
  2749. int
  2750. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  2751. uint32_t size)
  2752. {
  2753. int rval;
  2754. mbx_cmd_t mc;
  2755. mbx_cmd_t *mcp = &mc;
  2756. ql_dbg(ql_dbg_mbx, vha, 0x1009, "Entered %s.\n", __func__);
  2757. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  2758. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  2759. mcp->mb[8] = MSW(addr);
  2760. mcp->out_mb = MBX_8|MBX_0;
  2761. } else {
  2762. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  2763. mcp->out_mb = MBX_0;
  2764. }
  2765. mcp->mb[1] = LSW(addr);
  2766. mcp->mb[2] = MSW(req_dma);
  2767. mcp->mb[3] = LSW(req_dma);
  2768. mcp->mb[6] = MSW(MSD(req_dma));
  2769. mcp->mb[7] = LSW(MSD(req_dma));
  2770. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  2771. if (IS_FWI2_CAPABLE(vha->hw)) {
  2772. mcp->mb[4] = MSW(size);
  2773. mcp->mb[5] = LSW(size);
  2774. mcp->out_mb |= MBX_5|MBX_4;
  2775. } else {
  2776. mcp->mb[4] = LSW(size);
  2777. mcp->out_mb |= MBX_4;
  2778. }
  2779. mcp->in_mb = MBX_0;
  2780. mcp->tov = MBX_TOV_SECONDS;
  2781. mcp->flags = 0;
  2782. rval = qla2x00_mailbox_command(vha, mcp);
  2783. if (rval != QLA_SUCCESS) {
  2784. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  2785. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2786. } else {
  2787. ql_dbg(ql_dbg_mbx, vha, 0x1007, "Done %s.\n", __func__);
  2788. }
  2789. return rval;
  2790. }
  2791. /* 84XX Support **************************************************************/
  2792. struct cs84xx_mgmt_cmd {
  2793. union {
  2794. struct verify_chip_entry_84xx req;
  2795. struct verify_chip_rsp_84xx rsp;
  2796. } p;
  2797. };
  2798. int
  2799. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  2800. {
  2801. int rval, retry;
  2802. struct cs84xx_mgmt_cmd *mn;
  2803. dma_addr_t mn_dma;
  2804. uint16_t options;
  2805. unsigned long flags;
  2806. struct qla_hw_data *ha = vha->hw;
  2807. ql_dbg(ql_dbg_mbx, vha, 0x10c8, "Entered %s.\n", __func__);
  2808. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  2809. if (mn == NULL) {
  2810. return QLA_MEMORY_ALLOC_FAILED;
  2811. }
  2812. /* Force Update? */
  2813. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  2814. /* Diagnostic firmware? */
  2815. /* options |= MENLO_DIAG_FW; */
  2816. /* We update the firmware with only one data sequence. */
  2817. options |= VCO_END_OF_DATA;
  2818. do {
  2819. retry = 0;
  2820. memset(mn, 0, sizeof(*mn));
  2821. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  2822. mn->p.req.entry_count = 1;
  2823. mn->p.req.options = cpu_to_le16(options);
  2824. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  2825. "Dump of Verify Request.\n");
  2826. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  2827. (uint8_t *)mn, sizeof(*mn));
  2828. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  2829. if (rval != QLA_SUCCESS) {
  2830. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  2831. "Failed to issue verify IOCB (%x).\n", rval);
  2832. goto verify_done;
  2833. }
  2834. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  2835. "Dump of Verify Response.\n");
  2836. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  2837. (uint8_t *)mn, sizeof(*mn));
  2838. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  2839. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  2840. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  2841. ql_dbg(ql_dbg_mbx, vha, 0x10ce,
  2842. "cs=%x fc=%x.\n", status[0], status[1]);
  2843. if (status[0] != CS_COMPLETE) {
  2844. rval = QLA_FUNCTION_FAILED;
  2845. if (!(options & VCO_DONT_UPDATE_FW)) {
  2846. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  2847. "Firmware update failed. Retrying "
  2848. "without update firmware.\n");
  2849. options |= VCO_DONT_UPDATE_FW;
  2850. options &= ~VCO_FORCE_UPDATE;
  2851. retry = 1;
  2852. }
  2853. } else {
  2854. ql_dbg(ql_dbg_mbx, vha, 0x10d0,
  2855. "Firmware updated to %x.\n",
  2856. le32_to_cpu(mn->p.rsp.fw_ver));
  2857. /* NOTE: we only update OP firmware. */
  2858. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  2859. ha->cs84xx->op_fw_version =
  2860. le32_to_cpu(mn->p.rsp.fw_ver);
  2861. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  2862. flags);
  2863. }
  2864. } while (retry);
  2865. verify_done:
  2866. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  2867. if (rval != QLA_SUCCESS) {
  2868. ql_dbg(ql_dbg_mbx, vha, 0x10d1, "Failed=%x.\n", rval);
  2869. } else {
  2870. ql_dbg(ql_dbg_mbx, vha, 0x10d2, "Done %s.\n", __func__);
  2871. }
  2872. return rval;
  2873. }
  2874. int
  2875. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  2876. {
  2877. int rval;
  2878. unsigned long flags;
  2879. mbx_cmd_t mc;
  2880. mbx_cmd_t *mcp = &mc;
  2881. struct device_reg_25xxmq __iomem *reg;
  2882. struct qla_hw_data *ha = vha->hw;
  2883. ql_dbg(ql_dbg_mbx, vha, 0x10d3, "Entered %s.\n", __func__);
  2884. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  2885. mcp->mb[1] = req->options;
  2886. mcp->mb[2] = MSW(LSD(req->dma));
  2887. mcp->mb[3] = LSW(LSD(req->dma));
  2888. mcp->mb[6] = MSW(MSD(req->dma));
  2889. mcp->mb[7] = LSW(MSD(req->dma));
  2890. mcp->mb[5] = req->length;
  2891. if (req->rsp)
  2892. mcp->mb[10] = req->rsp->id;
  2893. mcp->mb[12] = req->qos;
  2894. mcp->mb[11] = req->vp_idx;
  2895. mcp->mb[13] = req->rid;
  2896. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  2897. QLA_QUE_PAGE * req->id);
  2898. mcp->mb[4] = req->id;
  2899. /* que in ptr index */
  2900. mcp->mb[8] = 0;
  2901. /* que out ptr index */
  2902. mcp->mb[9] = 0;
  2903. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  2904. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2905. mcp->in_mb = MBX_0;
  2906. mcp->flags = MBX_DMA_OUT;
  2907. mcp->tov = 60;
  2908. spin_lock_irqsave(&ha->hardware_lock, flags);
  2909. if (!(req->options & BIT_0)) {
  2910. WRT_REG_DWORD(&reg->req_q_in, 0);
  2911. WRT_REG_DWORD(&reg->req_q_out, 0);
  2912. }
  2913. req->req_q_in = &reg->req_q_in;
  2914. req->req_q_out = &reg->req_q_out;
  2915. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2916. rval = qla2x00_mailbox_command(vha, mcp);
  2917. if (rval != QLA_SUCCESS) {
  2918. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  2919. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2920. } else {
  2921. ql_dbg(ql_dbg_mbx, vha, 0x10d5, "Done %s.\n", __func__);
  2922. }
  2923. return rval;
  2924. }
  2925. int
  2926. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  2927. {
  2928. int rval;
  2929. unsigned long flags;
  2930. mbx_cmd_t mc;
  2931. mbx_cmd_t *mcp = &mc;
  2932. struct device_reg_25xxmq __iomem *reg;
  2933. struct qla_hw_data *ha = vha->hw;
  2934. ql_dbg(ql_dbg_mbx, vha, 0x10d6, "Entered %s.\n", __func__);
  2935. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  2936. mcp->mb[1] = rsp->options;
  2937. mcp->mb[2] = MSW(LSD(rsp->dma));
  2938. mcp->mb[3] = LSW(LSD(rsp->dma));
  2939. mcp->mb[6] = MSW(MSD(rsp->dma));
  2940. mcp->mb[7] = LSW(MSD(rsp->dma));
  2941. mcp->mb[5] = rsp->length;
  2942. mcp->mb[14] = rsp->msix->entry;
  2943. mcp->mb[13] = rsp->rid;
  2944. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  2945. QLA_QUE_PAGE * rsp->id);
  2946. mcp->mb[4] = rsp->id;
  2947. /* que in ptr index */
  2948. mcp->mb[8] = 0;
  2949. /* que out ptr index */
  2950. mcp->mb[9] = 0;
  2951. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  2952. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2953. mcp->in_mb = MBX_0;
  2954. mcp->flags = MBX_DMA_OUT;
  2955. mcp->tov = 60;
  2956. spin_lock_irqsave(&ha->hardware_lock, flags);
  2957. if (!(rsp->options & BIT_0)) {
  2958. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  2959. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  2960. }
  2961. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2962. rval = qla2x00_mailbox_command(vha, mcp);
  2963. if (rval != QLA_SUCCESS) {
  2964. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  2965. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2966. } else {
  2967. ql_dbg(ql_dbg_mbx, vha, 0x10d8, "Done %s.\n", __func__);
  2968. }
  2969. return rval;
  2970. }
  2971. int
  2972. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  2973. {
  2974. int rval;
  2975. mbx_cmd_t mc;
  2976. mbx_cmd_t *mcp = &mc;
  2977. ql_dbg(ql_dbg_mbx, vha, 0x10d9, "Entered %s.\n", __func__);
  2978. mcp->mb[0] = MBC_IDC_ACK;
  2979. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2980. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2981. mcp->in_mb = MBX_0;
  2982. mcp->tov = MBX_TOV_SECONDS;
  2983. mcp->flags = 0;
  2984. rval = qla2x00_mailbox_command(vha, mcp);
  2985. if (rval != QLA_SUCCESS) {
  2986. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  2987. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2988. } else {
  2989. ql_dbg(ql_dbg_mbx, vha, 0x10db, "Done %s.\n", __func__);
  2990. }
  2991. return rval;
  2992. }
  2993. int
  2994. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  2995. {
  2996. int rval;
  2997. mbx_cmd_t mc;
  2998. mbx_cmd_t *mcp = &mc;
  2999. ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__);
  3000. if (!IS_QLA81XX(vha->hw))
  3001. return QLA_FUNCTION_FAILED;
  3002. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3003. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3004. mcp->out_mb = MBX_1|MBX_0;
  3005. mcp->in_mb = MBX_1|MBX_0;
  3006. mcp->tov = MBX_TOV_SECONDS;
  3007. mcp->flags = 0;
  3008. rval = qla2x00_mailbox_command(vha, mcp);
  3009. if (rval != QLA_SUCCESS) {
  3010. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3011. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3012. rval, mcp->mb[0], mcp->mb[1]);
  3013. } else {
  3014. ql_dbg(ql_dbg_mbx, vha, 0x10de, "Done %s.\n", __func__);
  3015. *sector_size = mcp->mb[1];
  3016. }
  3017. return rval;
  3018. }
  3019. int
  3020. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3021. {
  3022. int rval;
  3023. mbx_cmd_t mc;
  3024. mbx_cmd_t *mcp = &mc;
  3025. if (!IS_QLA81XX(vha->hw))
  3026. return QLA_FUNCTION_FAILED;
  3027. ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__);
  3028. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3029. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3030. FAC_OPT_CMD_WRITE_PROTECT;
  3031. mcp->out_mb = MBX_1|MBX_0;
  3032. mcp->in_mb = MBX_1|MBX_0;
  3033. mcp->tov = MBX_TOV_SECONDS;
  3034. mcp->flags = 0;
  3035. rval = qla2x00_mailbox_command(vha, mcp);
  3036. if (rval != QLA_SUCCESS) {
  3037. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3038. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3039. rval, mcp->mb[0], mcp->mb[1]);
  3040. } else {
  3041. ql_dbg(ql_dbg_mbx, vha, 0x10e1, "Done %s.\n", __func__);
  3042. }
  3043. return rval;
  3044. }
  3045. int
  3046. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3047. {
  3048. int rval;
  3049. mbx_cmd_t mc;
  3050. mbx_cmd_t *mcp = &mc;
  3051. if (!IS_QLA81XX(vha->hw))
  3052. return QLA_FUNCTION_FAILED;
  3053. ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__);
  3054. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3055. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3056. mcp->mb[2] = LSW(start);
  3057. mcp->mb[3] = MSW(start);
  3058. mcp->mb[4] = LSW(finish);
  3059. mcp->mb[5] = MSW(finish);
  3060. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3061. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3062. mcp->tov = MBX_TOV_SECONDS;
  3063. mcp->flags = 0;
  3064. rval = qla2x00_mailbox_command(vha, mcp);
  3065. if (rval != QLA_SUCCESS) {
  3066. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3067. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3068. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3069. } else {
  3070. ql_dbg(ql_dbg_mbx, vha, 0x10e4, "Done %s.\n", __func__);
  3071. }
  3072. return rval;
  3073. }
  3074. int
  3075. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3076. {
  3077. int rval = 0;
  3078. mbx_cmd_t mc;
  3079. mbx_cmd_t *mcp = &mc;
  3080. ql_dbg(ql_dbg_mbx, vha, 0x10e5, "Entered %s.\n", __func__);
  3081. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3082. mcp->out_mb = MBX_0;
  3083. mcp->in_mb = MBX_0|MBX_1;
  3084. mcp->tov = MBX_TOV_SECONDS;
  3085. mcp->flags = 0;
  3086. rval = qla2x00_mailbox_command(vha, mcp);
  3087. if (rval != QLA_SUCCESS) {
  3088. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3089. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3090. rval, mcp->mb[0], mcp->mb[1]);
  3091. } else {
  3092. ql_dbg(ql_dbg_mbx, vha, 0x10e7, "Done %s.\n", __func__);
  3093. }
  3094. return rval;
  3095. }
  3096. int
  3097. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3098. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3099. {
  3100. int rval;
  3101. mbx_cmd_t mc;
  3102. mbx_cmd_t *mcp = &mc;
  3103. struct qla_hw_data *ha = vha->hw;
  3104. ql_dbg(ql_dbg_mbx, vha, 0x10e8, "Entered %s.\n", __func__);
  3105. if (!IS_FWI2_CAPABLE(ha))
  3106. return QLA_FUNCTION_FAILED;
  3107. if (len == 1)
  3108. opt |= BIT_0;
  3109. mcp->mb[0] = MBC_READ_SFP;
  3110. mcp->mb[1] = dev;
  3111. mcp->mb[2] = MSW(sfp_dma);
  3112. mcp->mb[3] = LSW(sfp_dma);
  3113. mcp->mb[6] = MSW(MSD(sfp_dma));
  3114. mcp->mb[7] = LSW(MSD(sfp_dma));
  3115. mcp->mb[8] = len;
  3116. mcp->mb[9] = off;
  3117. mcp->mb[10] = opt;
  3118. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3119. mcp->in_mb = MBX_1|MBX_0;
  3120. mcp->tov = MBX_TOV_SECONDS;
  3121. mcp->flags = 0;
  3122. rval = qla2x00_mailbox_command(vha, mcp);
  3123. if (opt & BIT_0)
  3124. *sfp = mcp->mb[1];
  3125. if (rval != QLA_SUCCESS) {
  3126. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3127. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3128. } else {
  3129. ql_dbg(ql_dbg_mbx, vha, 0x10ea, "Done %s.\n", __func__);
  3130. }
  3131. return rval;
  3132. }
  3133. int
  3134. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3135. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3136. {
  3137. int rval;
  3138. mbx_cmd_t mc;
  3139. mbx_cmd_t *mcp = &mc;
  3140. struct qla_hw_data *ha = vha->hw;
  3141. ql_dbg(ql_dbg_mbx, vha, 0x10eb, "Entered %s.\n", __func__);
  3142. if (!IS_FWI2_CAPABLE(ha))
  3143. return QLA_FUNCTION_FAILED;
  3144. if (len == 1)
  3145. opt |= BIT_0;
  3146. if (opt & BIT_0)
  3147. len = *sfp;
  3148. mcp->mb[0] = MBC_WRITE_SFP;
  3149. mcp->mb[1] = dev;
  3150. mcp->mb[2] = MSW(sfp_dma);
  3151. mcp->mb[3] = LSW(sfp_dma);
  3152. mcp->mb[6] = MSW(MSD(sfp_dma));
  3153. mcp->mb[7] = LSW(MSD(sfp_dma));
  3154. mcp->mb[8] = len;
  3155. mcp->mb[9] = off;
  3156. mcp->mb[10] = opt;
  3157. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3158. mcp->in_mb = MBX_1|MBX_0;
  3159. mcp->tov = MBX_TOV_SECONDS;
  3160. mcp->flags = 0;
  3161. rval = qla2x00_mailbox_command(vha, mcp);
  3162. if (rval != QLA_SUCCESS) {
  3163. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3164. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3165. } else {
  3166. ql_dbg(ql_dbg_mbx, vha, 0x10ed, "Done %s.\n", __func__);
  3167. }
  3168. return rval;
  3169. }
  3170. int
  3171. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3172. uint16_t size_in_bytes, uint16_t *actual_size)
  3173. {
  3174. int rval;
  3175. mbx_cmd_t mc;
  3176. mbx_cmd_t *mcp = &mc;
  3177. ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__);
  3178. if (!IS_QLA8XXX_TYPE(vha->hw))
  3179. return QLA_FUNCTION_FAILED;
  3180. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3181. mcp->mb[2] = MSW(stats_dma);
  3182. mcp->mb[3] = LSW(stats_dma);
  3183. mcp->mb[6] = MSW(MSD(stats_dma));
  3184. mcp->mb[7] = LSW(MSD(stats_dma));
  3185. mcp->mb[8] = size_in_bytes >> 2;
  3186. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3187. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3188. mcp->tov = MBX_TOV_SECONDS;
  3189. mcp->flags = 0;
  3190. rval = qla2x00_mailbox_command(vha, mcp);
  3191. if (rval != QLA_SUCCESS) {
  3192. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3193. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3194. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3195. } else {
  3196. ql_dbg(ql_dbg_mbx, vha, 0x10f0, "Done %s.\n", __func__);
  3197. *actual_size = mcp->mb[2] << 2;
  3198. }
  3199. return rval;
  3200. }
  3201. int
  3202. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3203. uint16_t size)
  3204. {
  3205. int rval;
  3206. mbx_cmd_t mc;
  3207. mbx_cmd_t *mcp = &mc;
  3208. ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__);
  3209. if (!IS_QLA8XXX_TYPE(vha->hw))
  3210. return QLA_FUNCTION_FAILED;
  3211. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3212. mcp->mb[1] = 0;
  3213. mcp->mb[2] = MSW(tlv_dma);
  3214. mcp->mb[3] = LSW(tlv_dma);
  3215. mcp->mb[6] = MSW(MSD(tlv_dma));
  3216. mcp->mb[7] = LSW(MSD(tlv_dma));
  3217. mcp->mb[8] = size;
  3218. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3219. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3220. mcp->tov = MBX_TOV_SECONDS;
  3221. mcp->flags = 0;
  3222. rval = qla2x00_mailbox_command(vha, mcp);
  3223. if (rval != QLA_SUCCESS) {
  3224. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3225. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3226. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3227. } else {
  3228. ql_dbg(ql_dbg_mbx, vha, 0x10f3, "Done %s.\n", __func__);
  3229. }
  3230. return rval;
  3231. }
  3232. int
  3233. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3234. {
  3235. int rval;
  3236. mbx_cmd_t mc;
  3237. mbx_cmd_t *mcp = &mc;
  3238. ql_dbg(ql_dbg_mbx, vha, 0x10f4, "Entered %s.\n", __func__);
  3239. if (!IS_FWI2_CAPABLE(vha->hw))
  3240. return QLA_FUNCTION_FAILED;
  3241. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3242. mcp->mb[1] = LSW(risc_addr);
  3243. mcp->mb[8] = MSW(risc_addr);
  3244. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3245. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3246. mcp->tov = 30;
  3247. mcp->flags = 0;
  3248. rval = qla2x00_mailbox_command(vha, mcp);
  3249. if (rval != QLA_SUCCESS) {
  3250. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3251. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3252. } else {
  3253. ql_dbg(ql_dbg_mbx, vha, 0x10f6, "Done %s.\n", __func__);
  3254. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3255. }
  3256. return rval;
  3257. }
  3258. int
  3259. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3260. uint16_t *mresp)
  3261. {
  3262. int rval;
  3263. mbx_cmd_t mc;
  3264. mbx_cmd_t *mcp = &mc;
  3265. uint32_t iter_cnt = 0x1;
  3266. ql_dbg(ql_dbg_mbx, vha, 0x10f7, "Entered %s.\n", __func__);
  3267. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3268. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3269. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3270. /* transfer count */
  3271. mcp->mb[10] = LSW(mreq->transfer_size);
  3272. mcp->mb[11] = MSW(mreq->transfer_size);
  3273. /* send data address */
  3274. mcp->mb[14] = LSW(mreq->send_dma);
  3275. mcp->mb[15] = MSW(mreq->send_dma);
  3276. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3277. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3278. /* receive data address */
  3279. mcp->mb[16] = LSW(mreq->rcv_dma);
  3280. mcp->mb[17] = MSW(mreq->rcv_dma);
  3281. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3282. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3283. /* Iteration count */
  3284. mcp->mb[18] = LSW(iter_cnt);
  3285. mcp->mb[19] = MSW(iter_cnt);
  3286. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3287. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3288. if (IS_QLA8XXX_TYPE(vha->hw))
  3289. mcp->out_mb |= MBX_2;
  3290. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3291. mcp->buf_size = mreq->transfer_size;
  3292. mcp->tov = MBX_TOV_SECONDS;
  3293. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3294. rval = qla2x00_mailbox_command(vha, mcp);
  3295. if (rval != QLA_SUCCESS) {
  3296. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3297. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3298. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3299. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3300. } else {
  3301. ql_dbg(ql_dbg_mbx, vha, 0x10f9, "Done %s.\n", __func__);
  3302. }
  3303. /* Copy mailbox information */
  3304. memcpy( mresp, mcp->mb, 64);
  3305. return rval;
  3306. }
  3307. int
  3308. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3309. uint16_t *mresp)
  3310. {
  3311. int rval;
  3312. mbx_cmd_t mc;
  3313. mbx_cmd_t *mcp = &mc;
  3314. struct qla_hw_data *ha = vha->hw;
  3315. ql_dbg(ql_dbg_mbx, vha, 0x10fa, "Entered %s.\n", __func__);
  3316. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3317. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3318. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3319. if (IS_QLA8XXX_TYPE(ha)) {
  3320. mcp->mb[1] |= BIT_15;
  3321. mcp->mb[2] = vha->fcoe_fcf_idx;
  3322. }
  3323. mcp->mb[16] = LSW(mreq->rcv_dma);
  3324. mcp->mb[17] = MSW(mreq->rcv_dma);
  3325. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3326. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3327. mcp->mb[10] = LSW(mreq->transfer_size);
  3328. mcp->mb[14] = LSW(mreq->send_dma);
  3329. mcp->mb[15] = MSW(mreq->send_dma);
  3330. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3331. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3332. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3333. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3334. if (IS_QLA8XXX_TYPE(ha))
  3335. mcp->out_mb |= MBX_2;
  3336. mcp->in_mb = MBX_0;
  3337. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha))
  3338. mcp->in_mb |= MBX_1;
  3339. if (IS_QLA8XXX_TYPE(ha))
  3340. mcp->in_mb |= MBX_3;
  3341. mcp->tov = MBX_TOV_SECONDS;
  3342. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3343. mcp->buf_size = mreq->transfer_size;
  3344. rval = qla2x00_mailbox_command(vha, mcp);
  3345. if (rval != QLA_SUCCESS) {
  3346. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3347. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3348. rval, mcp->mb[0], mcp->mb[1]);
  3349. } else {
  3350. ql_dbg(ql_dbg_mbx, vha, 0x10fc, "Done %s.\n", __func__);
  3351. }
  3352. /* Copy mailbox information */
  3353. memcpy(mresp, mcp->mb, 64);
  3354. return rval;
  3355. }
  3356. int
  3357. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3358. {
  3359. int rval;
  3360. mbx_cmd_t mc;
  3361. mbx_cmd_t *mcp = &mc;
  3362. ql_dbg(ql_dbg_mbx, vha, 0x10fd,
  3363. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3364. mcp->mb[0] = MBC_ISP84XX_RESET;
  3365. mcp->mb[1] = enable_diagnostic;
  3366. mcp->out_mb = MBX_1|MBX_0;
  3367. mcp->in_mb = MBX_1|MBX_0;
  3368. mcp->tov = MBX_TOV_SECONDS;
  3369. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3370. rval = qla2x00_mailbox_command(vha, mcp);
  3371. if (rval != QLA_SUCCESS)
  3372. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3373. else
  3374. ql_dbg(ql_dbg_mbx, vha, 0x10ff, "Done %s.\n", __func__);
  3375. return rval;
  3376. }
  3377. int
  3378. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3379. {
  3380. int rval;
  3381. mbx_cmd_t mc;
  3382. mbx_cmd_t *mcp = &mc;
  3383. ql_dbg(ql_dbg_mbx, vha, 0x1100, "Entered %s.\n", __func__);
  3384. if (!IS_FWI2_CAPABLE(vha->hw))
  3385. return QLA_FUNCTION_FAILED;
  3386. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3387. mcp->mb[1] = LSW(risc_addr);
  3388. mcp->mb[2] = LSW(data);
  3389. mcp->mb[3] = MSW(data);
  3390. mcp->mb[8] = MSW(risc_addr);
  3391. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3392. mcp->in_mb = MBX_0;
  3393. mcp->tov = 30;
  3394. mcp->flags = 0;
  3395. rval = qla2x00_mailbox_command(vha, mcp);
  3396. if (rval != QLA_SUCCESS) {
  3397. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3398. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3399. } else {
  3400. ql_dbg(ql_dbg_mbx, vha, 0x1102, "Done %s.\n", __func__);
  3401. }
  3402. return rval;
  3403. }
  3404. int
  3405. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3406. {
  3407. int rval;
  3408. uint32_t stat, timer;
  3409. uint16_t mb0 = 0;
  3410. struct qla_hw_data *ha = vha->hw;
  3411. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3412. rval = QLA_SUCCESS;
  3413. ql_dbg(ql_dbg_mbx, vha, 0x1103, "Entered %s.\n", __func__);
  3414. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3415. /* Write the MBC data to the registers */
  3416. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3417. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3418. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3419. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3420. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3421. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3422. /* Poll for MBC interrupt */
  3423. for (timer = 6000000; timer; timer--) {
  3424. /* Check for pending interrupts. */
  3425. stat = RD_REG_DWORD(&reg->host_status);
  3426. if (stat & HSRX_RISC_INT) {
  3427. stat &= 0xff;
  3428. if (stat == 0x1 || stat == 0x2 ||
  3429. stat == 0x10 || stat == 0x11) {
  3430. set_bit(MBX_INTERRUPT,
  3431. &ha->mbx_cmd_flags);
  3432. mb0 = RD_REG_WORD(&reg->mailbox0);
  3433. WRT_REG_DWORD(&reg->hccr,
  3434. HCCRX_CLR_RISC_INT);
  3435. RD_REG_DWORD(&reg->hccr);
  3436. break;
  3437. }
  3438. }
  3439. udelay(5);
  3440. }
  3441. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3442. rval = mb0 & MBS_MASK;
  3443. else
  3444. rval = QLA_FUNCTION_FAILED;
  3445. if (rval != QLA_SUCCESS) {
  3446. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3447. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3448. } else {
  3449. ql_dbg(ql_dbg_mbx, vha, 0x1105, "Done %s.\n", __func__);
  3450. }
  3451. return rval;
  3452. }
  3453. int
  3454. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3455. {
  3456. int rval;
  3457. mbx_cmd_t mc;
  3458. mbx_cmd_t *mcp = &mc;
  3459. struct qla_hw_data *ha = vha->hw;
  3460. ql_dbg(ql_dbg_mbx, vha, 0x1106, "Entered %s.\n", __func__);
  3461. if (!IS_FWI2_CAPABLE(ha))
  3462. return QLA_FUNCTION_FAILED;
  3463. mcp->mb[0] = MBC_DATA_RATE;
  3464. mcp->mb[1] = 0;
  3465. mcp->out_mb = MBX_1|MBX_0;
  3466. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3467. mcp->tov = MBX_TOV_SECONDS;
  3468. mcp->flags = 0;
  3469. rval = qla2x00_mailbox_command(vha, mcp);
  3470. if (rval != QLA_SUCCESS) {
  3471. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3472. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3473. } else {
  3474. ql_dbg(ql_dbg_mbx, vha, 0x1108, "Done %s.\n", __func__);
  3475. if (mcp->mb[1] != 0x7)
  3476. ha->link_data_rate = mcp->mb[1];
  3477. }
  3478. return rval;
  3479. }
  3480. int
  3481. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3482. {
  3483. int rval;
  3484. mbx_cmd_t mc;
  3485. mbx_cmd_t *mcp = &mc;
  3486. struct qla_hw_data *ha = vha->hw;
  3487. ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__);
  3488. if (!IS_QLA81XX(ha))
  3489. return QLA_FUNCTION_FAILED;
  3490. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3491. mcp->out_mb = MBX_0;
  3492. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3493. mcp->tov = MBX_TOV_SECONDS;
  3494. mcp->flags = 0;
  3495. rval = qla2x00_mailbox_command(vha, mcp);
  3496. if (rval != QLA_SUCCESS) {
  3497. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3498. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3499. } else {
  3500. /* Copy all bits to preserve original value */
  3501. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3502. ql_dbg(ql_dbg_mbx, vha, 0x110b, "Done %s.\n", __func__);
  3503. }
  3504. return rval;
  3505. }
  3506. int
  3507. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3508. {
  3509. int rval;
  3510. mbx_cmd_t mc;
  3511. mbx_cmd_t *mcp = &mc;
  3512. ql_dbg(ql_dbg_mbx, vha, 0x110c, "Entered %s.\n", __func__);
  3513. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3514. /* Copy all bits to preserve original setting */
  3515. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3516. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3517. mcp->in_mb = MBX_0;
  3518. mcp->tov = MBX_TOV_SECONDS;
  3519. mcp->flags = 0;
  3520. rval = qla2x00_mailbox_command(vha, mcp);
  3521. if (rval != QLA_SUCCESS) {
  3522. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3523. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3524. } else
  3525. ql_dbg(ql_dbg_mbx, vha, 0x110e, "Done %s.\n", __func__);
  3526. return rval;
  3527. }
  3528. int
  3529. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3530. uint16_t *mb)
  3531. {
  3532. int rval;
  3533. mbx_cmd_t mc;
  3534. mbx_cmd_t *mcp = &mc;
  3535. struct qla_hw_data *ha = vha->hw;
  3536. ql_dbg(ql_dbg_mbx, vha, 0x110f, "Entered %s.\n", __func__);
  3537. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3538. return QLA_FUNCTION_FAILED;
  3539. mcp->mb[0] = MBC_PORT_PARAMS;
  3540. mcp->mb[1] = loop_id;
  3541. if (ha->flags.fcp_prio_enabled)
  3542. mcp->mb[2] = BIT_1;
  3543. else
  3544. mcp->mb[2] = BIT_2;
  3545. mcp->mb[4] = priority & 0xf;
  3546. mcp->mb[9] = vha->vp_idx;
  3547. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3548. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3549. mcp->tov = 30;
  3550. mcp->flags = 0;
  3551. rval = qla2x00_mailbox_command(vha, mcp);
  3552. if (mb != NULL) {
  3553. mb[0] = mcp->mb[0];
  3554. mb[1] = mcp->mb[1];
  3555. mb[3] = mcp->mb[3];
  3556. mb[4] = mcp->mb[4];
  3557. }
  3558. if (rval != QLA_SUCCESS) {
  3559. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3560. } else {
  3561. ql_dbg(ql_dbg_mbx, vha, 0x10cc, "Done %s.\n", __func__);
  3562. }
  3563. return rval;
  3564. }
  3565. int
  3566. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
  3567. {
  3568. int rval;
  3569. uint8_t byte;
  3570. struct qla_hw_data *ha = vha->hw;
  3571. ql_dbg(ql_dbg_mbx, vha, 0x10ca, "Entered %s.\n", __func__);
  3572. /* Integer part */
  3573. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0);
  3574. if (rval != QLA_SUCCESS) {
  3575. ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
  3576. ha->flags.thermal_supported = 0;
  3577. goto fail;
  3578. }
  3579. *temp = byte;
  3580. /* Fraction part */
  3581. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0);
  3582. if (rval != QLA_SUCCESS) {
  3583. ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
  3584. ha->flags.thermal_supported = 0;
  3585. goto fail;
  3586. }
  3587. *frac = (byte >> 6) * 25;
  3588. ql_dbg(ql_dbg_mbx, vha, 0x1018, "Done %s.\n", __func__);
  3589. fail:
  3590. return rval;
  3591. }
  3592. int
  3593. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  3594. {
  3595. int rval;
  3596. struct qla_hw_data *ha = vha->hw;
  3597. mbx_cmd_t mc;
  3598. mbx_cmd_t *mcp = &mc;
  3599. ql_dbg(ql_dbg_mbx, vha, 0x1017, "Entered %s.\n", __func__);
  3600. if (!IS_FWI2_CAPABLE(ha))
  3601. return QLA_FUNCTION_FAILED;
  3602. memset(mcp, 0, sizeof(mbx_cmd_t));
  3603. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3604. mcp->mb[1] = 1;
  3605. mcp->out_mb = MBX_1|MBX_0;
  3606. mcp->in_mb = MBX_0;
  3607. mcp->tov = 30;
  3608. mcp->flags = 0;
  3609. rval = qla2x00_mailbox_command(vha, mcp);
  3610. if (rval != QLA_SUCCESS) {
  3611. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  3612. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3613. } else {
  3614. ql_dbg(ql_dbg_mbx, vha, 0x100e, "Done %s.\n", __func__);
  3615. }
  3616. return rval;
  3617. }
  3618. int
  3619. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  3620. {
  3621. int rval;
  3622. struct qla_hw_data *ha = vha->hw;
  3623. mbx_cmd_t mc;
  3624. mbx_cmd_t *mcp = &mc;
  3625. ql_dbg(ql_dbg_mbx, vha, 0x100d, "Entered %s.\n", __func__);
  3626. if (!IS_QLA82XX(ha))
  3627. return QLA_FUNCTION_FAILED;
  3628. memset(mcp, 0, sizeof(mbx_cmd_t));
  3629. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3630. mcp->mb[1] = 0;
  3631. mcp->out_mb = MBX_1|MBX_0;
  3632. mcp->in_mb = MBX_0;
  3633. mcp->tov = 30;
  3634. mcp->flags = 0;
  3635. rval = qla2x00_mailbox_command(vha, mcp);
  3636. if (rval != QLA_SUCCESS) {
  3637. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  3638. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3639. } else {
  3640. ql_dbg(ql_dbg_mbx, vha, 0x100b, "Done %s.\n", __func__);
  3641. }
  3642. return rval;
  3643. }
  3644. int
  3645. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  3646. {
  3647. struct qla_hw_data *ha = vha->hw;
  3648. mbx_cmd_t mc;
  3649. mbx_cmd_t *mcp = &mc;
  3650. int rval = QLA_FUNCTION_FAILED;
  3651. ql_dbg(ql_dbg_mbx, vha, 0x111f, "Entered %s.\n", __func__);
  3652. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3653. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3654. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3655. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  3656. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  3657. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3658. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  3659. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3660. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3661. mcp->tov = MBX_TOV_SECONDS;
  3662. rval = qla2x00_mailbox_command(vha, mcp);
  3663. /* Always copy back return mailbox values. */
  3664. if (rval != QLA_SUCCESS) {
  3665. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  3666. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3667. (mcp->mb[1] << 16) | mcp->mb[0],
  3668. (mcp->mb[3] << 16) | mcp->mb[2]);
  3669. } else {
  3670. ql_dbg(ql_dbg_mbx, vha, 0x1121, "Done %s.\n", __func__);
  3671. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  3672. if (!ha->md_template_size) {
  3673. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  3674. "Null template size obtained.\n");
  3675. rval = QLA_FUNCTION_FAILED;
  3676. }
  3677. }
  3678. return rval;
  3679. }
  3680. int
  3681. qla82xx_md_get_template(scsi_qla_host_t *vha)
  3682. {
  3683. struct qla_hw_data *ha = vha->hw;
  3684. mbx_cmd_t mc;
  3685. mbx_cmd_t *mcp = &mc;
  3686. int rval = QLA_FUNCTION_FAILED;
  3687. ql_dbg(ql_dbg_mbx, vha, 0x1123, "Entered %s.\n", __func__);
  3688. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  3689. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  3690. if (!ha->md_tmplt_hdr) {
  3691. ql_log(ql_log_warn, vha, 0x1124,
  3692. "Unable to allocate memory for Minidump template.\n");
  3693. return rval;
  3694. }
  3695. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3696. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3697. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3698. mcp->mb[2] = LSW(RQST_TMPLT);
  3699. mcp->mb[3] = MSW(RQST_TMPLT);
  3700. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  3701. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  3702. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  3703. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  3704. mcp->mb[8] = LSW(ha->md_template_size);
  3705. mcp->mb[9] = MSW(ha->md_template_size);
  3706. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3707. mcp->tov = MBX_TOV_SECONDS;
  3708. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  3709. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3710. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3711. rval = qla2x00_mailbox_command(vha, mcp);
  3712. if (rval != QLA_SUCCESS) {
  3713. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  3714. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3715. ((mcp->mb[1] << 16) | mcp->mb[0]),
  3716. ((mcp->mb[3] << 16) | mcp->mb[2]));
  3717. } else
  3718. ql_dbg(ql_dbg_mbx, vha, 0x1126, "Done %s.\n", __func__);
  3719. return rval;
  3720. }
  3721. int
  3722. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  3723. {
  3724. int rval;
  3725. struct qla_hw_data *ha = vha->hw;
  3726. mbx_cmd_t mc;
  3727. mbx_cmd_t *mcp = &mc;
  3728. if (!IS_QLA82XX(ha))
  3729. return QLA_FUNCTION_FAILED;
  3730. ql_dbg(ql_dbg_mbx, vha, 0x1127,
  3731. "Entered %s.\n", __func__);
  3732. memset(mcp, 0, sizeof(mbx_cmd_t));
  3733. mcp->mb[0] = MBC_SET_LED_CONFIG;
  3734. if (enable)
  3735. mcp->mb[7] = 0xE;
  3736. else
  3737. mcp->mb[7] = 0xD;
  3738. mcp->out_mb = MBX_7|MBX_0;
  3739. mcp->in_mb = MBX_0;
  3740. mcp->tov = 30;
  3741. mcp->flags = 0;
  3742. rval = qla2x00_mailbox_command(vha, mcp);
  3743. if (rval != QLA_SUCCESS) {
  3744. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  3745. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3746. } else {
  3747. ql_dbg(ql_dbg_mbx, vha, 0x1129,
  3748. "Done %s.\n", __func__);
  3749. }
  3750. return rval;
  3751. }