iwl-agn.c 105 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  67. #define VS "s"
  68. #else
  69. #define VS
  70. #endif
  71. #define DRV_VERSION IWLWIFI_VERSION VD VS
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. MODULE_ALIAS("iwl4965");
  77. /*************** STATION TABLE MANAGEMENT ****
  78. * mac80211 should be examined to determine if sta_info is duplicating
  79. * the functionality provided here
  80. */
  81. /**************************************************************/
  82. /**
  83. * iwl_commit_rxon - commit staging_rxon to hardware
  84. *
  85. * The RXON command in staging_rxon is committed to the hardware and
  86. * the active_rxon structure is updated with the new data. This
  87. * function correctly transitions out of the RXON_ASSOC_MSK state if
  88. * a HW tune is required based on the RXON structure changes.
  89. */
  90. int iwl_commit_rxon(struct iwl_priv *priv)
  91. {
  92. /* cast away the const for active_rxon in this function */
  93. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  94. int ret;
  95. bool new_assoc =
  96. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  97. if (!iwl_is_alive(priv))
  98. return -EBUSY;
  99. /* always get timestamp with Rx frame */
  100. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  101. ret = iwl_check_rxon_cmd(priv);
  102. if (ret) {
  103. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  104. return -EINVAL;
  105. }
  106. /*
  107. * receive commit_rxon request
  108. * abort any previous channel switch if still in process
  109. */
  110. if (priv->switch_rxon.switch_in_progress &&
  111. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  112. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  113. le16_to_cpu(priv->switch_rxon.channel));
  114. priv->switch_rxon.switch_in_progress = false;
  115. }
  116. /* If we don't need to send a full RXON, we can use
  117. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  118. * and other flags for the current radio configuration. */
  119. if (!iwl_full_rxon_required(priv)) {
  120. ret = iwl_send_rxon_assoc(priv);
  121. if (ret) {
  122. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  123. return ret;
  124. }
  125. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  126. iwl_print_rx_config_cmd(priv);
  127. return 0;
  128. }
  129. /* station table will be cleared */
  130. priv->assoc_station_added = 0;
  131. /* If we are currently associated and the new config requires
  132. * an RXON_ASSOC and the new config wants the associated mask enabled,
  133. * we must clear the associated from the active configuration
  134. * before we apply the new config */
  135. if (iwl_is_associated(priv) && new_assoc) {
  136. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  137. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  138. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  139. sizeof(struct iwl_rxon_cmd),
  140. &priv->active_rxon);
  141. /* If the mask clearing failed then we set
  142. * active_rxon back to what it was previously */
  143. if (ret) {
  144. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  145. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  146. return ret;
  147. }
  148. }
  149. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  150. "* with%s RXON_FILTER_ASSOC_MSK\n"
  151. "* channel = %d\n"
  152. "* bssid = %pM\n",
  153. (new_assoc ? "" : "out"),
  154. le16_to_cpu(priv->staging_rxon.channel),
  155. priv->staging_rxon.bssid_addr);
  156. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  157. /* Apply the new configuration
  158. * RXON unassoc clears the station table in uCode, send it before
  159. * we add the bcast station. If assoc bit is set, we will send RXON
  160. * after having added the bcast and bssid station.
  161. */
  162. if (!new_assoc) {
  163. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  164. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  165. if (ret) {
  166. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  167. return ret;
  168. }
  169. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  170. }
  171. iwl_clear_stations_table(priv);
  172. priv->start_calib = 0;
  173. /* Add the broadcast address so we can send broadcast frames */
  174. iwl_add_bcast_station(priv);
  175. /* If we have set the ASSOC_MSK and we are in BSS mode then
  176. * add the IWL_AP_ID to the station rate table */
  177. if (new_assoc) {
  178. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  179. ret = iwl_rxon_add_station(priv,
  180. priv->active_rxon.bssid_addr, 1);
  181. if (ret == IWL_INVALID_STATION) {
  182. IWL_ERR(priv,
  183. "Error adding AP address for TX.\n");
  184. return -EIO;
  185. }
  186. priv->assoc_station_added = 1;
  187. if (priv->default_wep_key &&
  188. iwl_send_static_wepkey_cmd(priv, 0))
  189. IWL_ERR(priv,
  190. "Could not send WEP static key.\n");
  191. }
  192. /*
  193. * allow CTS-to-self if possible for new association.
  194. * this is relevant only for 5000 series and up,
  195. * but will not damage 4965
  196. */
  197. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  198. /* Apply the new configuration
  199. * RXON assoc doesn't clear the station table in uCode,
  200. */
  201. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  202. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  203. if (ret) {
  204. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  205. return ret;
  206. }
  207. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  208. }
  209. iwl_print_rx_config_cmd(priv);
  210. iwl_init_sensitivity(priv);
  211. /* If we issue a new RXON command which required a tune then we must
  212. * send a new TXPOWER command or we won't be able to Tx any frames */
  213. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  214. if (ret) {
  215. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  216. return ret;
  217. }
  218. return 0;
  219. }
  220. void iwl_update_chain_flags(struct iwl_priv *priv)
  221. {
  222. if (priv->cfg->ops->hcmd->set_rxon_chain)
  223. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  224. iwlcore_commit_rxon(priv);
  225. }
  226. static void iwl_clear_free_frames(struct iwl_priv *priv)
  227. {
  228. struct list_head *element;
  229. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  230. priv->frames_count);
  231. while (!list_empty(&priv->free_frames)) {
  232. element = priv->free_frames.next;
  233. list_del(element);
  234. kfree(list_entry(element, struct iwl_frame, list));
  235. priv->frames_count--;
  236. }
  237. if (priv->frames_count) {
  238. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  239. priv->frames_count);
  240. priv->frames_count = 0;
  241. }
  242. }
  243. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  244. {
  245. struct iwl_frame *frame;
  246. struct list_head *element;
  247. if (list_empty(&priv->free_frames)) {
  248. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  249. if (!frame) {
  250. IWL_ERR(priv, "Could not allocate frame!\n");
  251. return NULL;
  252. }
  253. priv->frames_count++;
  254. return frame;
  255. }
  256. element = priv->free_frames.next;
  257. list_del(element);
  258. return list_entry(element, struct iwl_frame, list);
  259. }
  260. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  261. {
  262. memset(frame, 0, sizeof(*frame));
  263. list_add(&frame->list, &priv->free_frames);
  264. }
  265. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  266. struct ieee80211_hdr *hdr,
  267. int left)
  268. {
  269. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  270. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  271. (priv->iw_mode != NL80211_IFTYPE_AP)))
  272. return 0;
  273. if (priv->ibss_beacon->len > left)
  274. return 0;
  275. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  276. return priv->ibss_beacon->len;
  277. }
  278. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  279. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  280. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  281. u8 *beacon, u32 frame_size)
  282. {
  283. u16 tim_idx;
  284. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  285. /*
  286. * The index is relative to frame start but we start looking at the
  287. * variable-length part of the beacon.
  288. */
  289. tim_idx = mgmt->u.beacon.variable - beacon;
  290. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  291. while ((tim_idx < (frame_size - 2)) &&
  292. (beacon[tim_idx] != WLAN_EID_TIM))
  293. tim_idx += beacon[tim_idx+1] + 2;
  294. /* If TIM field was found, set variables */
  295. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  296. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  297. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  298. } else
  299. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  300. }
  301. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  302. struct iwl_frame *frame)
  303. {
  304. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  305. u32 frame_size;
  306. u32 rate_flags;
  307. u32 rate;
  308. /*
  309. * We have to set up the TX command, the TX Beacon command, and the
  310. * beacon contents.
  311. */
  312. /* Initialize memory */
  313. tx_beacon_cmd = &frame->u.beacon;
  314. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  315. /* Set up TX beacon contents */
  316. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  317. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  318. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  319. return 0;
  320. /* Set up TX command fields */
  321. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  322. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  323. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  324. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  325. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  326. /* Set up TX beacon command fields */
  327. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  328. frame_size);
  329. /* Set up packet rate and flags */
  330. rate = iwl_rate_get_lowest_plcp(priv);
  331. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  332. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  333. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  334. rate_flags |= RATE_MCS_CCK_MSK;
  335. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  336. rate_flags);
  337. return sizeof(*tx_beacon_cmd) + frame_size;
  338. }
  339. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  340. {
  341. struct iwl_frame *frame;
  342. unsigned int frame_size;
  343. int rc;
  344. frame = iwl_get_free_frame(priv);
  345. if (!frame) {
  346. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  347. "command.\n");
  348. return -ENOMEM;
  349. }
  350. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  351. if (!frame_size) {
  352. IWL_ERR(priv, "Error configuring the beacon command\n");
  353. iwl_free_frame(priv, frame);
  354. return -EINVAL;
  355. }
  356. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  357. &frame->u.cmd[0]);
  358. iwl_free_frame(priv, frame);
  359. return rc;
  360. }
  361. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  362. {
  363. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  364. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  365. if (sizeof(dma_addr_t) > sizeof(u32))
  366. addr |=
  367. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  368. return addr;
  369. }
  370. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  371. {
  372. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  373. return le16_to_cpu(tb->hi_n_len) >> 4;
  374. }
  375. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  376. dma_addr_t addr, u16 len)
  377. {
  378. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  379. u16 hi_n_len = len << 4;
  380. put_unaligned_le32(addr, &tb->lo);
  381. if (sizeof(dma_addr_t) > sizeof(u32))
  382. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  383. tb->hi_n_len = cpu_to_le16(hi_n_len);
  384. tfd->num_tbs = idx + 1;
  385. }
  386. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  387. {
  388. return tfd->num_tbs & 0x1f;
  389. }
  390. /**
  391. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  392. * @priv - driver private data
  393. * @txq - tx queue
  394. *
  395. * Does NOT advance any TFD circular buffer read/write indexes
  396. * Does NOT free the TFD itself (which is within circular buffer)
  397. */
  398. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  399. {
  400. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  401. struct iwl_tfd *tfd;
  402. struct pci_dev *dev = priv->pci_dev;
  403. int index = txq->q.read_ptr;
  404. int i;
  405. int num_tbs;
  406. tfd = &tfd_tmp[index];
  407. /* Sanity check on number of chunks */
  408. num_tbs = iwl_tfd_get_num_tbs(tfd);
  409. if (num_tbs >= IWL_NUM_OF_TBS) {
  410. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  411. /* @todo issue fatal error, it is quite serious situation */
  412. return;
  413. }
  414. /* Unmap tx_cmd */
  415. if (num_tbs)
  416. pci_unmap_single(dev,
  417. pci_unmap_addr(&txq->meta[index], mapping),
  418. pci_unmap_len(&txq->meta[index], len),
  419. PCI_DMA_BIDIRECTIONAL);
  420. /* Unmap chunks, if any. */
  421. for (i = 1; i < num_tbs; i++) {
  422. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  423. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  424. if (txq->txb) {
  425. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  426. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  427. }
  428. }
  429. }
  430. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  431. struct iwl_tx_queue *txq,
  432. dma_addr_t addr, u16 len,
  433. u8 reset, u8 pad)
  434. {
  435. struct iwl_queue *q;
  436. struct iwl_tfd *tfd, *tfd_tmp;
  437. u32 num_tbs;
  438. q = &txq->q;
  439. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  440. tfd = &tfd_tmp[q->write_ptr];
  441. if (reset)
  442. memset(tfd, 0, sizeof(*tfd));
  443. num_tbs = iwl_tfd_get_num_tbs(tfd);
  444. /* Each TFD can point to a maximum 20 Tx buffers */
  445. if (num_tbs >= IWL_NUM_OF_TBS) {
  446. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  447. IWL_NUM_OF_TBS);
  448. return -EINVAL;
  449. }
  450. BUG_ON(addr & ~DMA_BIT_MASK(36));
  451. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  452. IWL_ERR(priv, "Unaligned address = %llx\n",
  453. (unsigned long long)addr);
  454. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  455. return 0;
  456. }
  457. /*
  458. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  459. * given Tx queue, and enable the DMA channel used for that queue.
  460. *
  461. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  462. * channels supported in hardware.
  463. */
  464. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  465. struct iwl_tx_queue *txq)
  466. {
  467. int txq_id = txq->q.id;
  468. /* Circular buffer (TFD queue in DRAM) physical base address */
  469. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  470. txq->q.dma_addr >> 8);
  471. return 0;
  472. }
  473. /******************************************************************************
  474. *
  475. * Generic RX handler implementations
  476. *
  477. ******************************************************************************/
  478. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  479. struct iwl_rx_mem_buffer *rxb)
  480. {
  481. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  482. struct iwl_alive_resp *palive;
  483. struct delayed_work *pwork;
  484. palive = &pkt->u.alive_frame;
  485. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  486. "0x%01X 0x%01X\n",
  487. palive->is_valid, palive->ver_type,
  488. palive->ver_subtype);
  489. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  490. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  491. memcpy(&priv->card_alive_init,
  492. &pkt->u.alive_frame,
  493. sizeof(struct iwl_init_alive_resp));
  494. pwork = &priv->init_alive_start;
  495. } else {
  496. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  497. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  498. sizeof(struct iwl_alive_resp));
  499. pwork = &priv->alive_start;
  500. }
  501. /* We delay the ALIVE response by 5ms to
  502. * give the HW RF Kill time to activate... */
  503. if (palive->is_valid == UCODE_VALID_OK)
  504. queue_delayed_work(priv->workqueue, pwork,
  505. msecs_to_jiffies(5));
  506. else
  507. IWL_WARN(priv, "uCode did not respond OK.\n");
  508. }
  509. static void iwl_bg_beacon_update(struct work_struct *work)
  510. {
  511. struct iwl_priv *priv =
  512. container_of(work, struct iwl_priv, beacon_update);
  513. struct sk_buff *beacon;
  514. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  515. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  516. if (!beacon) {
  517. IWL_ERR(priv, "update beacon failed\n");
  518. return;
  519. }
  520. mutex_lock(&priv->mutex);
  521. /* new beacon skb is allocated every time; dispose previous.*/
  522. if (priv->ibss_beacon)
  523. dev_kfree_skb(priv->ibss_beacon);
  524. priv->ibss_beacon = beacon;
  525. mutex_unlock(&priv->mutex);
  526. iwl_send_beacon_cmd(priv);
  527. }
  528. /**
  529. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  530. *
  531. * This callback is provided in order to send a statistics request.
  532. *
  533. * This timer function is continually reset to execute within
  534. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  535. * was received. We need to ensure we receive the statistics in order
  536. * to update the temperature used for calibrating the TXPOWER.
  537. */
  538. static void iwl_bg_statistics_periodic(unsigned long data)
  539. {
  540. struct iwl_priv *priv = (struct iwl_priv *)data;
  541. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  542. return;
  543. /* dont send host command if rf-kill is on */
  544. if (!iwl_is_ready_rf(priv))
  545. return;
  546. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  547. }
  548. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  549. struct iwl_rx_mem_buffer *rxb)
  550. {
  551. #ifdef CONFIG_IWLWIFI_DEBUG
  552. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  553. struct iwl4965_beacon_notif *beacon =
  554. (struct iwl4965_beacon_notif *)pkt->u.raw;
  555. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  556. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  557. "tsf %d %d rate %d\n",
  558. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  559. beacon->beacon_notify_hdr.failure_frame,
  560. le32_to_cpu(beacon->ibss_mgr_status),
  561. le32_to_cpu(beacon->high_tsf),
  562. le32_to_cpu(beacon->low_tsf), rate);
  563. #endif
  564. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  565. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  566. queue_work(priv->workqueue, &priv->beacon_update);
  567. }
  568. /* Handle notification from uCode that card's power state is changing
  569. * due to software, hardware, or critical temperature RFKILL */
  570. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  571. struct iwl_rx_mem_buffer *rxb)
  572. {
  573. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  574. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  575. unsigned long status = priv->status;
  576. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  577. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  578. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  579. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  580. RF_CARD_DISABLED)) {
  581. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  582. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  583. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  584. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  585. if (!(flags & RXON_CARD_DISABLED)) {
  586. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  587. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  588. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  589. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  590. }
  591. if (flags & RF_CARD_DISABLED)
  592. iwl_tt_enter_ct_kill(priv);
  593. }
  594. if (!(flags & RF_CARD_DISABLED))
  595. iwl_tt_exit_ct_kill(priv);
  596. if (flags & HW_CARD_DISABLED)
  597. set_bit(STATUS_RF_KILL_HW, &priv->status);
  598. else
  599. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  600. if (!(flags & RXON_CARD_DISABLED))
  601. iwl_scan_cancel(priv);
  602. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  603. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  604. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  605. test_bit(STATUS_RF_KILL_HW, &priv->status));
  606. else
  607. wake_up_interruptible(&priv->wait_command_queue);
  608. }
  609. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  610. {
  611. if (src == IWL_PWR_SRC_VAUX) {
  612. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  613. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  614. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  615. ~APMG_PS_CTRL_MSK_PWR_SRC);
  616. } else {
  617. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  618. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  619. ~APMG_PS_CTRL_MSK_PWR_SRC);
  620. }
  621. return 0;
  622. }
  623. /**
  624. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  625. *
  626. * Setup the RX handlers for each of the reply types sent from the uCode
  627. * to the host.
  628. *
  629. * This function chains into the hardware specific files for them to setup
  630. * any hardware specific handlers as well.
  631. */
  632. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  633. {
  634. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  635. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  636. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  637. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  638. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  639. iwl_rx_pm_debug_statistics_notif;
  640. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  641. /*
  642. * The same handler is used for both the REPLY to a discrete
  643. * statistics request from the host as well as for the periodic
  644. * statistics notifications (after received beacons) from the uCode.
  645. */
  646. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  647. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  648. iwl_setup_spectrum_handlers(priv);
  649. iwl_setup_rx_scan_handlers(priv);
  650. /* status change handler */
  651. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  652. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  653. iwl_rx_missed_beacon_notif;
  654. /* Rx handlers */
  655. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  656. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  657. /* block ack */
  658. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  659. /* Set up hardware specific Rx handlers */
  660. priv->cfg->ops->lib->rx_handler_setup(priv);
  661. }
  662. /**
  663. * iwl_rx_handle - Main entry function for receiving responses from uCode
  664. *
  665. * Uses the priv->rx_handlers callback function array to invoke
  666. * the appropriate handlers, including command responses,
  667. * frame-received notifications, and other notifications.
  668. */
  669. void iwl_rx_handle(struct iwl_priv *priv)
  670. {
  671. struct iwl_rx_mem_buffer *rxb;
  672. struct iwl_rx_packet *pkt;
  673. struct iwl_rx_queue *rxq = &priv->rxq;
  674. u32 r, i;
  675. int reclaim;
  676. unsigned long flags;
  677. u8 fill_rx = 0;
  678. u32 count = 8;
  679. int total_empty;
  680. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  681. * buffer that the driver may process (last buffer filled by ucode). */
  682. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  683. i = rxq->read;
  684. /* Rx interrupt, but nothing sent from uCode */
  685. if (i == r)
  686. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  687. /* calculate total frames need to be restock after handling RX */
  688. total_empty = r - rxq->write_actual;
  689. if (total_empty < 0)
  690. total_empty += RX_QUEUE_SIZE;
  691. if (total_empty > (RX_QUEUE_SIZE / 2))
  692. fill_rx = 1;
  693. while (i != r) {
  694. rxb = rxq->queue[i];
  695. /* If an RXB doesn't have a Rx queue slot associated with it,
  696. * then a bug has been introduced in the queue refilling
  697. * routines -- catch it here */
  698. BUG_ON(rxb == NULL);
  699. rxq->queue[i] = NULL;
  700. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  701. PAGE_SIZE << priv->hw_params.rx_page_order,
  702. PCI_DMA_FROMDEVICE);
  703. pkt = rxb_addr(rxb);
  704. trace_iwlwifi_dev_rx(priv, pkt,
  705. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  706. /* Reclaim a command buffer only if this packet is a response
  707. * to a (driver-originated) command.
  708. * If the packet (e.g. Rx frame) originated from uCode,
  709. * there is no command buffer to reclaim.
  710. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  711. * but apparently a few don't get set; catch them here. */
  712. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  713. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  714. (pkt->hdr.cmd != REPLY_RX) &&
  715. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  716. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  717. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  718. (pkt->hdr.cmd != REPLY_TX);
  719. /* Based on type of command response or notification,
  720. * handle those that need handling via function in
  721. * rx_handlers table. See iwl_setup_rx_handlers() */
  722. if (priv->rx_handlers[pkt->hdr.cmd]) {
  723. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  724. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  725. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  726. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  727. } else {
  728. /* No handling needed */
  729. IWL_DEBUG_RX(priv,
  730. "r %d i %d No handler needed for %s, 0x%02x\n",
  731. r, i, get_cmd_string(pkt->hdr.cmd),
  732. pkt->hdr.cmd);
  733. }
  734. /*
  735. * XXX: After here, we should always check rxb->page
  736. * against NULL before touching it or its virtual
  737. * memory (pkt). Because some rx_handler might have
  738. * already taken or freed the pages.
  739. */
  740. if (reclaim) {
  741. /* Invoke any callbacks, transfer the buffer to caller,
  742. * and fire off the (possibly) blocking iwl_send_cmd()
  743. * as we reclaim the driver command queue */
  744. if (rxb->page)
  745. iwl_tx_cmd_complete(priv, rxb);
  746. else
  747. IWL_WARN(priv, "Claim null rxb?\n");
  748. }
  749. /* Reuse the page if possible. For notification packets and
  750. * SKBs that fail to Rx correctly, add them back into the
  751. * rx_free list for reuse later. */
  752. spin_lock_irqsave(&rxq->lock, flags);
  753. if (rxb->page != NULL) {
  754. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  755. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  756. PCI_DMA_FROMDEVICE);
  757. list_add_tail(&rxb->list, &rxq->rx_free);
  758. rxq->free_count++;
  759. } else
  760. list_add_tail(&rxb->list, &rxq->rx_used);
  761. spin_unlock_irqrestore(&rxq->lock, flags);
  762. i = (i + 1) & RX_QUEUE_MASK;
  763. /* If there are a lot of unused frames,
  764. * restock the Rx queue so ucode wont assert. */
  765. if (fill_rx) {
  766. count++;
  767. if (count >= 8) {
  768. rxq->read = i;
  769. iwl_rx_replenish_now(priv);
  770. count = 0;
  771. }
  772. }
  773. }
  774. /* Backtrack one entry */
  775. rxq->read = i;
  776. if (fill_rx)
  777. iwl_rx_replenish_now(priv);
  778. else
  779. iwl_rx_queue_restock(priv);
  780. }
  781. /* call this function to flush any scheduled tasklet */
  782. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  783. {
  784. /* wait to make sure we flush pending tasklet*/
  785. synchronize_irq(priv->pci_dev->irq);
  786. tasklet_kill(&priv->irq_tasklet);
  787. }
  788. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  789. {
  790. u32 inta, handled = 0;
  791. u32 inta_fh;
  792. unsigned long flags;
  793. u32 i;
  794. #ifdef CONFIG_IWLWIFI_DEBUG
  795. u32 inta_mask;
  796. #endif
  797. spin_lock_irqsave(&priv->lock, flags);
  798. /* Ack/clear/reset pending uCode interrupts.
  799. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  800. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  801. inta = iwl_read32(priv, CSR_INT);
  802. iwl_write32(priv, CSR_INT, inta);
  803. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  804. * Any new interrupts that happen after this, either while we're
  805. * in this tasklet, or later, will show up in next ISR/tasklet. */
  806. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  807. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  808. #ifdef CONFIG_IWLWIFI_DEBUG
  809. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  810. /* just for debug */
  811. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  812. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  813. inta, inta_mask, inta_fh);
  814. }
  815. #endif
  816. spin_unlock_irqrestore(&priv->lock, flags);
  817. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  818. * atomic, make sure that inta covers all the interrupts that
  819. * we've discovered, even if FH interrupt came in just after
  820. * reading CSR_INT. */
  821. if (inta_fh & CSR49_FH_INT_RX_MASK)
  822. inta |= CSR_INT_BIT_FH_RX;
  823. if (inta_fh & CSR49_FH_INT_TX_MASK)
  824. inta |= CSR_INT_BIT_FH_TX;
  825. /* Now service all interrupt bits discovered above. */
  826. if (inta & CSR_INT_BIT_HW_ERR) {
  827. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  828. /* Tell the device to stop sending interrupts */
  829. iwl_disable_interrupts(priv);
  830. priv->isr_stats.hw++;
  831. iwl_irq_handle_error(priv);
  832. handled |= CSR_INT_BIT_HW_ERR;
  833. return;
  834. }
  835. #ifdef CONFIG_IWLWIFI_DEBUG
  836. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  837. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  838. if (inta & CSR_INT_BIT_SCD) {
  839. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  840. "the frame/frames.\n");
  841. priv->isr_stats.sch++;
  842. }
  843. /* Alive notification via Rx interrupt will do the real work */
  844. if (inta & CSR_INT_BIT_ALIVE) {
  845. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  846. priv->isr_stats.alive++;
  847. }
  848. }
  849. #endif
  850. /* Safely ignore these bits for debug checks below */
  851. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  852. /* HW RF KILL switch toggled */
  853. if (inta & CSR_INT_BIT_RF_KILL) {
  854. int hw_rf_kill = 0;
  855. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  856. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  857. hw_rf_kill = 1;
  858. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  859. hw_rf_kill ? "disable radio" : "enable radio");
  860. priv->isr_stats.rfkill++;
  861. /* driver only loads ucode once setting the interface up.
  862. * the driver allows loading the ucode even if the radio
  863. * is killed. Hence update the killswitch state here. The
  864. * rfkill handler will care about restarting if needed.
  865. */
  866. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  867. if (hw_rf_kill)
  868. set_bit(STATUS_RF_KILL_HW, &priv->status);
  869. else
  870. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  871. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  872. }
  873. handled |= CSR_INT_BIT_RF_KILL;
  874. }
  875. /* Chip got too hot and stopped itself */
  876. if (inta & CSR_INT_BIT_CT_KILL) {
  877. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  878. priv->isr_stats.ctkill++;
  879. handled |= CSR_INT_BIT_CT_KILL;
  880. }
  881. /* Error detected by uCode */
  882. if (inta & CSR_INT_BIT_SW_ERR) {
  883. IWL_ERR(priv, "Microcode SW error detected. "
  884. " Restarting 0x%X.\n", inta);
  885. priv->isr_stats.sw++;
  886. priv->isr_stats.sw_err = inta;
  887. iwl_irq_handle_error(priv);
  888. handled |= CSR_INT_BIT_SW_ERR;
  889. }
  890. /*
  891. * uCode wakes up after power-down sleep.
  892. * Tell device about any new tx or host commands enqueued,
  893. * and about any Rx buffers made available while asleep.
  894. */
  895. if (inta & CSR_INT_BIT_WAKEUP) {
  896. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  897. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  898. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  899. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  900. priv->isr_stats.wakeup++;
  901. handled |= CSR_INT_BIT_WAKEUP;
  902. }
  903. /* All uCode command responses, including Tx command responses,
  904. * Rx "responses" (frame-received notification), and other
  905. * notifications from uCode come through here*/
  906. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  907. iwl_rx_handle(priv);
  908. priv->isr_stats.rx++;
  909. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  910. }
  911. /* This "Tx" DMA channel is used only for loading uCode */
  912. if (inta & CSR_INT_BIT_FH_TX) {
  913. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  914. priv->isr_stats.tx++;
  915. handled |= CSR_INT_BIT_FH_TX;
  916. /* Wake up uCode load routine, now that load is complete */
  917. priv->ucode_write_complete = 1;
  918. wake_up_interruptible(&priv->wait_command_queue);
  919. }
  920. if (inta & ~handled) {
  921. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  922. priv->isr_stats.unhandled++;
  923. }
  924. if (inta & ~(priv->inta_mask)) {
  925. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  926. inta & ~priv->inta_mask);
  927. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  928. }
  929. /* Re-enable all interrupts */
  930. /* only Re-enable if diabled by irq */
  931. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  932. iwl_enable_interrupts(priv);
  933. #ifdef CONFIG_IWLWIFI_DEBUG
  934. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  935. inta = iwl_read32(priv, CSR_INT);
  936. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  937. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  938. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  939. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  940. }
  941. #endif
  942. }
  943. /* tasklet for iwlagn interrupt */
  944. static void iwl_irq_tasklet(struct iwl_priv *priv)
  945. {
  946. u32 inta = 0;
  947. u32 handled = 0;
  948. unsigned long flags;
  949. u32 i;
  950. #ifdef CONFIG_IWLWIFI_DEBUG
  951. u32 inta_mask;
  952. #endif
  953. spin_lock_irqsave(&priv->lock, flags);
  954. /* Ack/clear/reset pending uCode interrupts.
  955. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  956. */
  957. iwl_write32(priv, CSR_INT, priv->inta);
  958. inta = priv->inta;
  959. #ifdef CONFIG_IWLWIFI_DEBUG
  960. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  961. /* just for debug */
  962. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  963. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  964. inta, inta_mask);
  965. }
  966. #endif
  967. spin_unlock_irqrestore(&priv->lock, flags);
  968. /* saved interrupt in inta variable now we can reset priv->inta */
  969. priv->inta = 0;
  970. /* Now service all interrupt bits discovered above. */
  971. if (inta & CSR_INT_BIT_HW_ERR) {
  972. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  973. /* Tell the device to stop sending interrupts */
  974. iwl_disable_interrupts(priv);
  975. priv->isr_stats.hw++;
  976. iwl_irq_handle_error(priv);
  977. handled |= CSR_INT_BIT_HW_ERR;
  978. return;
  979. }
  980. #ifdef CONFIG_IWLWIFI_DEBUG
  981. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  982. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  983. if (inta & CSR_INT_BIT_SCD) {
  984. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  985. "the frame/frames.\n");
  986. priv->isr_stats.sch++;
  987. }
  988. /* Alive notification via Rx interrupt will do the real work */
  989. if (inta & CSR_INT_BIT_ALIVE) {
  990. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  991. priv->isr_stats.alive++;
  992. }
  993. }
  994. #endif
  995. /* Safely ignore these bits for debug checks below */
  996. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  997. /* HW RF KILL switch toggled */
  998. if (inta & CSR_INT_BIT_RF_KILL) {
  999. int hw_rf_kill = 0;
  1000. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1001. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1002. hw_rf_kill = 1;
  1003. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1004. hw_rf_kill ? "disable radio" : "enable radio");
  1005. priv->isr_stats.rfkill++;
  1006. /* driver only loads ucode once setting the interface up.
  1007. * the driver allows loading the ucode even if the radio
  1008. * is killed. Hence update the killswitch state here. The
  1009. * rfkill handler will care about restarting if needed.
  1010. */
  1011. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1012. if (hw_rf_kill)
  1013. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1014. else
  1015. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1016. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1017. }
  1018. handled |= CSR_INT_BIT_RF_KILL;
  1019. }
  1020. /* Chip got too hot and stopped itself */
  1021. if (inta & CSR_INT_BIT_CT_KILL) {
  1022. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1023. priv->isr_stats.ctkill++;
  1024. handled |= CSR_INT_BIT_CT_KILL;
  1025. }
  1026. /* Error detected by uCode */
  1027. if (inta & CSR_INT_BIT_SW_ERR) {
  1028. IWL_ERR(priv, "Microcode SW error detected. "
  1029. " Restarting 0x%X.\n", inta);
  1030. priv->isr_stats.sw++;
  1031. priv->isr_stats.sw_err = inta;
  1032. iwl_irq_handle_error(priv);
  1033. handled |= CSR_INT_BIT_SW_ERR;
  1034. }
  1035. /* uCode wakes up after power-down sleep */
  1036. if (inta & CSR_INT_BIT_WAKEUP) {
  1037. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1038. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1039. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1040. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1041. priv->isr_stats.wakeup++;
  1042. handled |= CSR_INT_BIT_WAKEUP;
  1043. }
  1044. /* All uCode command responses, including Tx command responses,
  1045. * Rx "responses" (frame-received notification), and other
  1046. * notifications from uCode come through here*/
  1047. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1048. CSR_INT_BIT_RX_PERIODIC)) {
  1049. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1050. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1051. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1052. iwl_write32(priv, CSR_FH_INT_STATUS,
  1053. CSR49_FH_INT_RX_MASK);
  1054. }
  1055. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1056. handled |= CSR_INT_BIT_RX_PERIODIC;
  1057. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1058. }
  1059. /* Sending RX interrupt require many steps to be done in the
  1060. * the device:
  1061. * 1- write interrupt to current index in ICT table.
  1062. * 2- dma RX frame.
  1063. * 3- update RX shared data to indicate last write index.
  1064. * 4- send interrupt.
  1065. * This could lead to RX race, driver could receive RX interrupt
  1066. * but the shared data changes does not reflect this;
  1067. * periodic interrupt will detect any dangling Rx activity.
  1068. */
  1069. /* Disable periodic interrupt; we use it as just a one-shot. */
  1070. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1071. CSR_INT_PERIODIC_DIS);
  1072. iwl_rx_handle(priv);
  1073. /*
  1074. * Enable periodic interrupt in 8 msec only if we received
  1075. * real RX interrupt (instead of just periodic int), to catch
  1076. * any dangling Rx interrupt. If it was just the periodic
  1077. * interrupt, there was no dangling Rx activity, and no need
  1078. * to extend the periodic interrupt; one-shot is enough.
  1079. */
  1080. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1081. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1082. CSR_INT_PERIODIC_ENA);
  1083. priv->isr_stats.rx++;
  1084. }
  1085. /* This "Tx" DMA channel is used only for loading uCode */
  1086. if (inta & CSR_INT_BIT_FH_TX) {
  1087. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1088. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1089. priv->isr_stats.tx++;
  1090. handled |= CSR_INT_BIT_FH_TX;
  1091. /* Wake up uCode load routine, now that load is complete */
  1092. priv->ucode_write_complete = 1;
  1093. wake_up_interruptible(&priv->wait_command_queue);
  1094. }
  1095. if (inta & ~handled) {
  1096. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1097. priv->isr_stats.unhandled++;
  1098. }
  1099. if (inta & ~(priv->inta_mask)) {
  1100. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1101. inta & ~priv->inta_mask);
  1102. }
  1103. /* Re-enable all interrupts */
  1104. /* only Re-enable if diabled by irq */
  1105. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1106. iwl_enable_interrupts(priv);
  1107. }
  1108. /******************************************************************************
  1109. *
  1110. * uCode download functions
  1111. *
  1112. ******************************************************************************/
  1113. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1114. {
  1115. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1116. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1117. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1118. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1119. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1120. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1121. }
  1122. static void iwl_nic_start(struct iwl_priv *priv)
  1123. {
  1124. /* Remove all resets to allow NIC to operate */
  1125. iwl_write32(priv, CSR_RESET, 0);
  1126. }
  1127. /**
  1128. * iwl_read_ucode - Read uCode images from disk file.
  1129. *
  1130. * Copy into buffers for card to fetch via bus-mastering
  1131. */
  1132. static int iwl_read_ucode(struct iwl_priv *priv)
  1133. {
  1134. struct iwl_ucode_header *ucode;
  1135. int ret = -EINVAL, index;
  1136. const struct firmware *ucode_raw;
  1137. const char *name_pre = priv->cfg->fw_name_pre;
  1138. const unsigned int api_max = priv->cfg->ucode_api_max;
  1139. const unsigned int api_min = priv->cfg->ucode_api_min;
  1140. char buf[25];
  1141. u8 *src;
  1142. size_t len;
  1143. u32 api_ver, build;
  1144. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1145. u16 eeprom_ver;
  1146. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1147. * request_firmware() is synchronous, file is in memory on return. */
  1148. for (index = api_max; index >= api_min; index--) {
  1149. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1150. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1151. if (ret < 0) {
  1152. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1153. buf, ret);
  1154. if (ret == -ENOENT)
  1155. continue;
  1156. else
  1157. goto error;
  1158. } else {
  1159. if (index < api_max)
  1160. IWL_ERR(priv, "Loaded firmware %s, "
  1161. "which is deprecated. "
  1162. "Please use API v%u instead.\n",
  1163. buf, api_max);
  1164. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1165. buf, ucode_raw->size);
  1166. break;
  1167. }
  1168. }
  1169. if (ret < 0)
  1170. goto error;
  1171. /* Make sure that we got at least the v1 header! */
  1172. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1173. IWL_ERR(priv, "File size way too small!\n");
  1174. ret = -EINVAL;
  1175. goto err_release;
  1176. }
  1177. /* Data from ucode file: header followed by uCode images */
  1178. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1179. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1180. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1181. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1182. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1183. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1184. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1185. init_data_size =
  1186. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1187. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1188. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1189. /* api_ver should match the api version forming part of the
  1190. * firmware filename ... but we don't check for that and only rely
  1191. * on the API version read from firmware header from here on forward */
  1192. if (api_ver < api_min || api_ver > api_max) {
  1193. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1194. "Driver supports v%u, firmware is v%u.\n",
  1195. api_max, api_ver);
  1196. priv->ucode_ver = 0;
  1197. ret = -EINVAL;
  1198. goto err_release;
  1199. }
  1200. if (api_ver != api_max)
  1201. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1202. "got v%u. New firmware can be obtained "
  1203. "from http://www.intellinuxwireless.org.\n",
  1204. api_max, api_ver);
  1205. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1206. IWL_UCODE_MAJOR(priv->ucode_ver),
  1207. IWL_UCODE_MINOR(priv->ucode_ver),
  1208. IWL_UCODE_API(priv->ucode_ver),
  1209. IWL_UCODE_SERIAL(priv->ucode_ver));
  1210. snprintf(priv->hw->wiphy->fw_version,
  1211. sizeof(priv->hw->wiphy->fw_version),
  1212. "%u.%u.%u.%u",
  1213. IWL_UCODE_MAJOR(priv->ucode_ver),
  1214. IWL_UCODE_MINOR(priv->ucode_ver),
  1215. IWL_UCODE_API(priv->ucode_ver),
  1216. IWL_UCODE_SERIAL(priv->ucode_ver));
  1217. if (build)
  1218. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1219. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1220. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1221. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1222. ? "OTP" : "EEPROM", eeprom_ver);
  1223. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1224. priv->ucode_ver);
  1225. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1226. inst_size);
  1227. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1228. data_size);
  1229. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1230. init_size);
  1231. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1232. init_data_size);
  1233. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1234. boot_size);
  1235. /* Verify size of file vs. image size info in file's header */
  1236. if (ucode_raw->size !=
  1237. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1238. inst_size + data_size + init_size +
  1239. init_data_size + boot_size) {
  1240. IWL_DEBUG_INFO(priv,
  1241. "uCode file size %d does not match expected size\n",
  1242. (int)ucode_raw->size);
  1243. ret = -EINVAL;
  1244. goto err_release;
  1245. }
  1246. /* Verify that uCode images will fit in card's SRAM */
  1247. if (inst_size > priv->hw_params.max_inst_size) {
  1248. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1249. inst_size);
  1250. ret = -EINVAL;
  1251. goto err_release;
  1252. }
  1253. if (data_size > priv->hw_params.max_data_size) {
  1254. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1255. data_size);
  1256. ret = -EINVAL;
  1257. goto err_release;
  1258. }
  1259. if (init_size > priv->hw_params.max_inst_size) {
  1260. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1261. init_size);
  1262. ret = -EINVAL;
  1263. goto err_release;
  1264. }
  1265. if (init_data_size > priv->hw_params.max_data_size) {
  1266. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1267. init_data_size);
  1268. ret = -EINVAL;
  1269. goto err_release;
  1270. }
  1271. if (boot_size > priv->hw_params.max_bsm_size) {
  1272. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1273. boot_size);
  1274. ret = -EINVAL;
  1275. goto err_release;
  1276. }
  1277. /* Allocate ucode buffers for card's bus-master loading ... */
  1278. /* Runtime instructions and 2 copies of data:
  1279. * 1) unmodified from disk
  1280. * 2) backup cache for save/restore during power-downs */
  1281. priv->ucode_code.len = inst_size;
  1282. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1283. priv->ucode_data.len = data_size;
  1284. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1285. priv->ucode_data_backup.len = data_size;
  1286. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1287. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1288. !priv->ucode_data_backup.v_addr)
  1289. goto err_pci_alloc;
  1290. /* Initialization instructions and data */
  1291. if (init_size && init_data_size) {
  1292. priv->ucode_init.len = init_size;
  1293. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1294. priv->ucode_init_data.len = init_data_size;
  1295. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1296. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1297. goto err_pci_alloc;
  1298. }
  1299. /* Bootstrap (instructions only, no data) */
  1300. if (boot_size) {
  1301. priv->ucode_boot.len = boot_size;
  1302. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1303. if (!priv->ucode_boot.v_addr)
  1304. goto err_pci_alloc;
  1305. }
  1306. /* Copy images into buffers for card's bus-master reads ... */
  1307. /* Runtime instructions (first block of data in file) */
  1308. len = inst_size;
  1309. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1310. memcpy(priv->ucode_code.v_addr, src, len);
  1311. src += len;
  1312. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1313. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1314. /* Runtime data (2nd block)
  1315. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1316. len = data_size;
  1317. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1318. memcpy(priv->ucode_data.v_addr, src, len);
  1319. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1320. src += len;
  1321. /* Initialization instructions (3rd block) */
  1322. if (init_size) {
  1323. len = init_size;
  1324. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1325. len);
  1326. memcpy(priv->ucode_init.v_addr, src, len);
  1327. src += len;
  1328. }
  1329. /* Initialization data (4th block) */
  1330. if (init_data_size) {
  1331. len = init_data_size;
  1332. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1333. len);
  1334. memcpy(priv->ucode_init_data.v_addr, src, len);
  1335. src += len;
  1336. }
  1337. /* Bootstrap instructions (5th block) */
  1338. len = boot_size;
  1339. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1340. memcpy(priv->ucode_boot.v_addr, src, len);
  1341. /* We have our copies now, allow OS release its copies */
  1342. release_firmware(ucode_raw);
  1343. return 0;
  1344. err_pci_alloc:
  1345. IWL_ERR(priv, "failed to allocate pci memory\n");
  1346. ret = -ENOMEM;
  1347. iwl_dealloc_ucode_pci(priv);
  1348. err_release:
  1349. release_firmware(ucode_raw);
  1350. error:
  1351. return ret;
  1352. }
  1353. static const char *desc_lookup_text[] = {
  1354. "OK",
  1355. "FAIL",
  1356. "BAD_PARAM",
  1357. "BAD_CHECKSUM",
  1358. "NMI_INTERRUPT_WDG",
  1359. "SYSASSERT",
  1360. "FATAL_ERROR",
  1361. "BAD_COMMAND",
  1362. "HW_ERROR_TUNE_LOCK",
  1363. "HW_ERROR_TEMPERATURE",
  1364. "ILLEGAL_CHAN_FREQ",
  1365. "VCC_NOT_STABLE",
  1366. "FH_ERROR",
  1367. "NMI_INTERRUPT_HOST",
  1368. "NMI_INTERRUPT_ACTION_PT",
  1369. "NMI_INTERRUPT_UNKNOWN",
  1370. "UCODE_VERSION_MISMATCH",
  1371. "HW_ERROR_ABS_LOCK",
  1372. "HW_ERROR_CAL_LOCK_FAIL",
  1373. "NMI_INTERRUPT_INST_ACTION_PT",
  1374. "NMI_INTERRUPT_DATA_ACTION_PT",
  1375. "NMI_TRM_HW_ER",
  1376. "NMI_INTERRUPT_TRM",
  1377. "NMI_INTERRUPT_BREAK_POINT"
  1378. "DEBUG_0",
  1379. "DEBUG_1",
  1380. "DEBUG_2",
  1381. "DEBUG_3",
  1382. "UNKNOWN"
  1383. };
  1384. static const char *desc_lookup(int i)
  1385. {
  1386. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1387. if (i < 0 || i > max)
  1388. i = max;
  1389. return desc_lookup_text[i];
  1390. }
  1391. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1392. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1393. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1394. {
  1395. u32 data2, line;
  1396. u32 desc, time, count, base, data1;
  1397. u32 blink1, blink2, ilink1, ilink2;
  1398. if (priv->ucode_type == UCODE_INIT)
  1399. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1400. else
  1401. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1402. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1403. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1404. return;
  1405. }
  1406. count = iwl_read_targ_mem(priv, base);
  1407. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1408. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1409. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1410. priv->status, count);
  1411. }
  1412. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1413. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1414. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1415. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1416. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1417. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1418. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1419. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1420. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1421. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1422. blink1, blink2, ilink1, ilink2);
  1423. IWL_ERR(priv, "Desc Time "
  1424. "data1 data2 line\n");
  1425. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1426. desc_lookup(desc), desc, time, data1, data2, line);
  1427. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1428. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1429. ilink1, ilink2);
  1430. }
  1431. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1432. /**
  1433. * iwl_print_event_log - Dump error event log to syslog
  1434. *
  1435. */
  1436. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1437. u32 num_events, u32 mode)
  1438. {
  1439. u32 i;
  1440. u32 base; /* SRAM byte address of event log header */
  1441. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1442. u32 ptr; /* SRAM byte address of log data */
  1443. u32 ev, time, data; /* event log data */
  1444. unsigned long reg_flags;
  1445. if (num_events == 0)
  1446. return;
  1447. if (priv->ucode_type == UCODE_INIT)
  1448. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1449. else
  1450. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1451. if (mode == 0)
  1452. event_size = 2 * sizeof(u32);
  1453. else
  1454. event_size = 3 * sizeof(u32);
  1455. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1456. /* Make sure device is powered up for SRAM reads */
  1457. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1458. iwl_grab_nic_access(priv);
  1459. /* Set starting address; reads will auto-increment */
  1460. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1461. rmb();
  1462. /* "time" is actually "data" for mode 0 (no timestamp).
  1463. * place event id # at far right for easier visual parsing. */
  1464. for (i = 0; i < num_events; i++) {
  1465. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1466. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1467. if (mode == 0) {
  1468. /* data, ev */
  1469. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1470. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1471. } else {
  1472. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1473. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1474. time, data, ev);
  1475. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1476. }
  1477. }
  1478. /* Allow device to power down */
  1479. iwl_release_nic_access(priv);
  1480. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1481. }
  1482. /**
  1483. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1484. */
  1485. static void iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1486. u32 num_wraps, u32 next_entry,
  1487. u32 size, u32 mode)
  1488. {
  1489. /*
  1490. * display the newest DEFAULT_LOG_ENTRIES entries
  1491. * i.e the entries just before the next ont that uCode would fill.
  1492. */
  1493. if (num_wraps) {
  1494. if (next_entry < size) {
  1495. iwl_print_event_log(priv,
  1496. capacity - (size - next_entry),
  1497. size - next_entry, mode);
  1498. iwl_print_event_log(priv, 0,
  1499. next_entry, mode);
  1500. } else
  1501. iwl_print_event_log(priv, next_entry - size,
  1502. size, mode);
  1503. } else {
  1504. if (next_entry < size)
  1505. iwl_print_event_log(priv, 0, next_entry, mode);
  1506. else
  1507. iwl_print_event_log(priv, next_entry - size,
  1508. size, mode);
  1509. }
  1510. }
  1511. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1512. #define MAX_EVENT_LOG_SIZE (512)
  1513. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1514. void iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log)
  1515. {
  1516. u32 base; /* SRAM byte address of event log header */
  1517. u32 capacity; /* event log capacity in # entries */
  1518. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1519. u32 num_wraps; /* # times uCode wrapped to top of log */
  1520. u32 next_entry; /* index of next entry to be written by uCode */
  1521. u32 size; /* # entries that we'll print */
  1522. if (priv->ucode_type == UCODE_INIT)
  1523. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1524. else
  1525. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1526. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1527. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1528. return;
  1529. }
  1530. /* event log header */
  1531. capacity = iwl_read_targ_mem(priv, base);
  1532. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1533. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1534. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1535. if (capacity > MAX_EVENT_LOG_SIZE) {
  1536. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1537. capacity, MAX_EVENT_LOG_SIZE);
  1538. capacity = MAX_EVENT_LOG_SIZE;
  1539. }
  1540. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1541. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1542. next_entry, MAX_EVENT_LOG_SIZE);
  1543. next_entry = MAX_EVENT_LOG_SIZE;
  1544. }
  1545. size = num_wraps ? capacity : next_entry;
  1546. /* bail out if nothing in log */
  1547. if (size == 0) {
  1548. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1549. return;
  1550. }
  1551. #ifdef CONFIG_IWLWIFI_DEBUG
  1552. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS))
  1553. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1554. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1555. #else
  1556. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1557. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1558. #endif
  1559. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1560. size);
  1561. #ifdef CONFIG_IWLWIFI_DEBUG
  1562. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1563. /*
  1564. * if uCode has wrapped back to top of log,
  1565. * start at the oldest entry,
  1566. * i.e the next one that uCode would fill.
  1567. */
  1568. if (num_wraps)
  1569. iwl_print_event_log(priv, next_entry,
  1570. capacity - next_entry, mode);
  1571. /* (then/else) start at top of log */
  1572. iwl_print_event_log(priv, 0, next_entry, mode);
  1573. } else
  1574. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1575. next_entry, size, mode);
  1576. #else
  1577. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1578. next_entry, size, mode);
  1579. #endif
  1580. }
  1581. /**
  1582. * iwl_alive_start - called after REPLY_ALIVE notification received
  1583. * from protocol/runtime uCode (initialization uCode's
  1584. * Alive gets handled by iwl_init_alive_start()).
  1585. */
  1586. static void iwl_alive_start(struct iwl_priv *priv)
  1587. {
  1588. int ret = 0;
  1589. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1590. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1591. /* We had an error bringing up the hardware, so take it
  1592. * all the way back down so we can try again */
  1593. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1594. goto restart;
  1595. }
  1596. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1597. * This is a paranoid check, because we would not have gotten the
  1598. * "runtime" alive if code weren't properly loaded. */
  1599. if (iwl_verify_ucode(priv)) {
  1600. /* Runtime instruction load was bad;
  1601. * take it all the way back down so we can try again */
  1602. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1603. goto restart;
  1604. }
  1605. iwl_clear_stations_table(priv);
  1606. ret = priv->cfg->ops->lib->alive_notify(priv);
  1607. if (ret) {
  1608. IWL_WARN(priv,
  1609. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1610. goto restart;
  1611. }
  1612. /* After the ALIVE response, we can send host commands to the uCode */
  1613. set_bit(STATUS_ALIVE, &priv->status);
  1614. if (iwl_is_rfkill(priv))
  1615. return;
  1616. ieee80211_wake_queues(priv->hw);
  1617. priv->active_rate = priv->rates_mask;
  1618. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1619. /* Configure Tx antenna selection based on H/W config */
  1620. if (priv->cfg->ops->hcmd->set_tx_ant)
  1621. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1622. if (iwl_is_associated(priv)) {
  1623. struct iwl_rxon_cmd *active_rxon =
  1624. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1625. /* apply any changes in staging */
  1626. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1627. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1628. } else {
  1629. /* Initialize our rx_config data */
  1630. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1631. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1632. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1633. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1634. }
  1635. /* Configure Bluetooth device coexistence support */
  1636. iwl_send_bt_config(priv);
  1637. iwl_reset_run_time_calib(priv);
  1638. /* Configure the adapter for unassociated operation */
  1639. iwlcore_commit_rxon(priv);
  1640. /* At this point, the NIC is initialized and operational */
  1641. iwl_rf_kill_ct_config(priv);
  1642. iwl_leds_init(priv);
  1643. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1644. set_bit(STATUS_READY, &priv->status);
  1645. wake_up_interruptible(&priv->wait_command_queue);
  1646. iwl_power_update_mode(priv, true);
  1647. /* reassociate for ADHOC mode */
  1648. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1649. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1650. priv->vif);
  1651. if (beacon)
  1652. iwl_mac_beacon_update(priv->hw, beacon);
  1653. }
  1654. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1655. iwl_set_mode(priv, priv->iw_mode);
  1656. return;
  1657. restart:
  1658. queue_work(priv->workqueue, &priv->restart);
  1659. }
  1660. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1661. static void __iwl_down(struct iwl_priv *priv)
  1662. {
  1663. unsigned long flags;
  1664. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1665. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1666. if (!exit_pending)
  1667. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1668. iwl_clear_stations_table(priv);
  1669. /* Unblock any waiting calls */
  1670. wake_up_interruptible_all(&priv->wait_command_queue);
  1671. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1672. * exiting the module */
  1673. if (!exit_pending)
  1674. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1675. /* stop and reset the on-board processor */
  1676. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1677. /* tell the device to stop sending interrupts */
  1678. spin_lock_irqsave(&priv->lock, flags);
  1679. iwl_disable_interrupts(priv);
  1680. spin_unlock_irqrestore(&priv->lock, flags);
  1681. iwl_synchronize_irq(priv);
  1682. if (priv->mac80211_registered)
  1683. ieee80211_stop_queues(priv->hw);
  1684. /* If we have not previously called iwl_init() then
  1685. * clear all bits but the RF Kill bit and return */
  1686. if (!iwl_is_init(priv)) {
  1687. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1688. STATUS_RF_KILL_HW |
  1689. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1690. STATUS_GEO_CONFIGURED |
  1691. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1692. STATUS_EXIT_PENDING;
  1693. goto exit;
  1694. }
  1695. /* ...otherwise clear out all the status bits but the RF Kill
  1696. * bit and continue taking the NIC down. */
  1697. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1698. STATUS_RF_KILL_HW |
  1699. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1700. STATUS_GEO_CONFIGURED |
  1701. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1702. STATUS_FW_ERROR |
  1703. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1704. STATUS_EXIT_PENDING;
  1705. /* device going down, Stop using ICT table */
  1706. iwl_disable_ict(priv);
  1707. iwl_txq_ctx_stop(priv);
  1708. iwl_rxq_stop(priv);
  1709. /* Power-down device's busmaster DMA clocks */
  1710. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1711. udelay(5);
  1712. /* Make sure (redundant) we've released our request to stay awake */
  1713. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1714. /* Stop the device, and put it in low power state */
  1715. priv->cfg->ops->lib->apm_ops.stop(priv);
  1716. exit:
  1717. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1718. if (priv->ibss_beacon)
  1719. dev_kfree_skb(priv->ibss_beacon);
  1720. priv->ibss_beacon = NULL;
  1721. /* clear out any free frames */
  1722. iwl_clear_free_frames(priv);
  1723. }
  1724. static void iwl_down(struct iwl_priv *priv)
  1725. {
  1726. mutex_lock(&priv->mutex);
  1727. __iwl_down(priv);
  1728. mutex_unlock(&priv->mutex);
  1729. iwl_cancel_deferred_work(priv);
  1730. }
  1731. #define HW_READY_TIMEOUT (50)
  1732. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1733. {
  1734. int ret = 0;
  1735. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1736. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1737. /* See if we got it */
  1738. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1739. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1740. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1741. HW_READY_TIMEOUT);
  1742. if (ret != -ETIMEDOUT)
  1743. priv->hw_ready = true;
  1744. else
  1745. priv->hw_ready = false;
  1746. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1747. (priv->hw_ready == 1) ? "ready" : "not ready");
  1748. return ret;
  1749. }
  1750. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1751. {
  1752. int ret = 0;
  1753. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1754. ret = iwl_set_hw_ready(priv);
  1755. if (priv->hw_ready)
  1756. return ret;
  1757. /* If HW is not ready, prepare the conditions to check again */
  1758. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1759. CSR_HW_IF_CONFIG_REG_PREPARE);
  1760. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1761. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1762. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1763. /* HW should be ready by now, check again. */
  1764. if (ret != -ETIMEDOUT)
  1765. iwl_set_hw_ready(priv);
  1766. return ret;
  1767. }
  1768. #define MAX_HW_RESTARTS 5
  1769. static int __iwl_up(struct iwl_priv *priv)
  1770. {
  1771. int i;
  1772. int ret;
  1773. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1774. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1775. return -EIO;
  1776. }
  1777. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1778. IWL_ERR(priv, "ucode not available for device bringup\n");
  1779. return -EIO;
  1780. }
  1781. iwl_prepare_card_hw(priv);
  1782. if (!priv->hw_ready) {
  1783. IWL_WARN(priv, "Exit HW not ready\n");
  1784. return -EIO;
  1785. }
  1786. /* If platform's RF_KILL switch is NOT set to KILL */
  1787. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1788. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1789. else
  1790. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1791. if (iwl_is_rfkill(priv)) {
  1792. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1793. iwl_enable_interrupts(priv);
  1794. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1795. return 0;
  1796. }
  1797. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1798. ret = iwl_hw_nic_init(priv);
  1799. if (ret) {
  1800. IWL_ERR(priv, "Unable to init nic\n");
  1801. return ret;
  1802. }
  1803. /* make sure rfkill handshake bits are cleared */
  1804. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1805. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1806. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1807. /* clear (again), then enable host interrupts */
  1808. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1809. iwl_enable_interrupts(priv);
  1810. /* really make sure rfkill handshake bits are cleared */
  1811. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1812. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1813. /* Copy original ucode data image from disk into backup cache.
  1814. * This will be used to initialize the on-board processor's
  1815. * data SRAM for a clean start when the runtime program first loads. */
  1816. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1817. priv->ucode_data.len);
  1818. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1819. iwl_clear_stations_table(priv);
  1820. /* load bootstrap state machine,
  1821. * load bootstrap program into processor's memory,
  1822. * prepare to load the "initialize" uCode */
  1823. ret = priv->cfg->ops->lib->load_ucode(priv);
  1824. if (ret) {
  1825. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1826. ret);
  1827. continue;
  1828. }
  1829. /* start card; "initialize" will load runtime ucode */
  1830. iwl_nic_start(priv);
  1831. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1832. return 0;
  1833. }
  1834. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1835. __iwl_down(priv);
  1836. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1837. /* tried to restart and config the device for as long as our
  1838. * patience could withstand */
  1839. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1840. return -EIO;
  1841. }
  1842. /*****************************************************************************
  1843. *
  1844. * Workqueue callbacks
  1845. *
  1846. *****************************************************************************/
  1847. static void iwl_bg_init_alive_start(struct work_struct *data)
  1848. {
  1849. struct iwl_priv *priv =
  1850. container_of(data, struct iwl_priv, init_alive_start.work);
  1851. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1852. return;
  1853. mutex_lock(&priv->mutex);
  1854. priv->cfg->ops->lib->init_alive_start(priv);
  1855. mutex_unlock(&priv->mutex);
  1856. }
  1857. static void iwl_bg_alive_start(struct work_struct *data)
  1858. {
  1859. struct iwl_priv *priv =
  1860. container_of(data, struct iwl_priv, alive_start.work);
  1861. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1862. return;
  1863. /* enable dram interrupt */
  1864. iwl_reset_ict(priv);
  1865. mutex_lock(&priv->mutex);
  1866. iwl_alive_start(priv);
  1867. mutex_unlock(&priv->mutex);
  1868. }
  1869. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1870. {
  1871. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1872. run_time_calib_work);
  1873. mutex_lock(&priv->mutex);
  1874. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1875. test_bit(STATUS_SCANNING, &priv->status)) {
  1876. mutex_unlock(&priv->mutex);
  1877. return;
  1878. }
  1879. if (priv->start_calib) {
  1880. iwl_chain_noise_calibration(priv, &priv->statistics);
  1881. iwl_sensitivity_calibration(priv, &priv->statistics);
  1882. }
  1883. mutex_unlock(&priv->mutex);
  1884. return;
  1885. }
  1886. static void iwl_bg_up(struct work_struct *data)
  1887. {
  1888. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1889. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1890. return;
  1891. mutex_lock(&priv->mutex);
  1892. __iwl_up(priv);
  1893. mutex_unlock(&priv->mutex);
  1894. }
  1895. static void iwl_bg_restart(struct work_struct *data)
  1896. {
  1897. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1898. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1899. return;
  1900. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1901. mutex_lock(&priv->mutex);
  1902. priv->vif = NULL;
  1903. priv->is_open = 0;
  1904. mutex_unlock(&priv->mutex);
  1905. iwl_down(priv);
  1906. ieee80211_restart_hw(priv->hw);
  1907. } else {
  1908. iwl_down(priv);
  1909. queue_work(priv->workqueue, &priv->up);
  1910. }
  1911. }
  1912. static void iwl_bg_rx_replenish(struct work_struct *data)
  1913. {
  1914. struct iwl_priv *priv =
  1915. container_of(data, struct iwl_priv, rx_replenish);
  1916. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1917. return;
  1918. mutex_lock(&priv->mutex);
  1919. iwl_rx_replenish(priv);
  1920. mutex_unlock(&priv->mutex);
  1921. }
  1922. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1923. void iwl_post_associate(struct iwl_priv *priv)
  1924. {
  1925. struct ieee80211_conf *conf = NULL;
  1926. int ret = 0;
  1927. unsigned long flags;
  1928. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1929. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1930. return;
  1931. }
  1932. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1933. priv->assoc_id, priv->active_rxon.bssid_addr);
  1934. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1935. return;
  1936. if (!priv->vif || !priv->is_open)
  1937. return;
  1938. iwl_scan_cancel_timeout(priv, 200);
  1939. conf = ieee80211_get_hw_conf(priv->hw);
  1940. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1941. iwlcore_commit_rxon(priv);
  1942. iwl_setup_rxon_timing(priv);
  1943. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1944. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1945. if (ret)
  1946. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1947. "Attempting to continue.\n");
  1948. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1949. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1950. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1951. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1952. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1953. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1954. priv->assoc_id, priv->beacon_int);
  1955. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1956. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1957. else
  1958. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1959. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1960. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1961. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1962. else
  1963. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1964. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1965. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1966. }
  1967. iwlcore_commit_rxon(priv);
  1968. switch (priv->iw_mode) {
  1969. case NL80211_IFTYPE_STATION:
  1970. break;
  1971. case NL80211_IFTYPE_ADHOC:
  1972. /* assume default assoc id */
  1973. priv->assoc_id = 1;
  1974. iwl_rxon_add_station(priv, priv->bssid, 0);
  1975. iwl_send_beacon_cmd(priv);
  1976. break;
  1977. default:
  1978. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1979. __func__, priv->iw_mode);
  1980. break;
  1981. }
  1982. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1983. priv->assoc_station_added = 1;
  1984. spin_lock_irqsave(&priv->lock, flags);
  1985. iwl_activate_qos(priv, 0);
  1986. spin_unlock_irqrestore(&priv->lock, flags);
  1987. /* the chain noise calibration will enabled PM upon completion
  1988. * If chain noise has already been run, then we need to enable
  1989. * power management here */
  1990. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1991. iwl_power_update_mode(priv, false);
  1992. /* Enable Rx differential gain and sensitivity calibrations */
  1993. iwl_chain_noise_reset(priv);
  1994. priv->start_calib = 1;
  1995. }
  1996. /*****************************************************************************
  1997. *
  1998. * mac80211 entry point functions
  1999. *
  2000. *****************************************************************************/
  2001. #define UCODE_READY_TIMEOUT (4 * HZ)
  2002. /*
  2003. * Not a mac80211 entry point function, but it fits in with all the
  2004. * other mac80211 functions grouped here.
  2005. */
  2006. static int iwl_setup_mac(struct iwl_priv *priv)
  2007. {
  2008. int ret;
  2009. struct ieee80211_hw *hw = priv->hw;
  2010. hw->rate_control_algorithm = "iwl-agn-rs";
  2011. /* Tell mac80211 our characteristics */
  2012. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2013. IEEE80211_HW_NOISE_DBM |
  2014. IEEE80211_HW_AMPDU_AGGREGATION |
  2015. IEEE80211_HW_SPECTRUM_MGMT;
  2016. if (!priv->cfg->broken_powersave)
  2017. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2018. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2019. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2020. hw->wiphy->interface_modes =
  2021. BIT(NL80211_IFTYPE_STATION) |
  2022. BIT(NL80211_IFTYPE_ADHOC);
  2023. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2024. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2025. /*
  2026. * For now, disable PS by default because it affects
  2027. * RX performance significantly.
  2028. */
  2029. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2030. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2031. /* we create the 802.11 header and a zero-length SSID element */
  2032. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2033. /* Default value; 4 EDCA QOS priorities */
  2034. hw->queues = 4;
  2035. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2036. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2037. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2038. &priv->bands[IEEE80211_BAND_2GHZ];
  2039. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2040. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2041. &priv->bands[IEEE80211_BAND_5GHZ];
  2042. ret = ieee80211_register_hw(priv->hw);
  2043. if (ret) {
  2044. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2045. return ret;
  2046. }
  2047. priv->mac80211_registered = 1;
  2048. return 0;
  2049. }
  2050. static int iwl_mac_start(struct ieee80211_hw *hw)
  2051. {
  2052. struct iwl_priv *priv = hw->priv;
  2053. int ret;
  2054. IWL_DEBUG_MAC80211(priv, "enter\n");
  2055. /* we should be verifying the device is ready to be opened */
  2056. mutex_lock(&priv->mutex);
  2057. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2058. * ucode filename and max sizes are card-specific. */
  2059. if (!priv->ucode_code.len) {
  2060. ret = iwl_read_ucode(priv);
  2061. if (ret) {
  2062. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2063. mutex_unlock(&priv->mutex);
  2064. return ret;
  2065. }
  2066. }
  2067. ret = __iwl_up(priv);
  2068. mutex_unlock(&priv->mutex);
  2069. if (ret)
  2070. return ret;
  2071. if (iwl_is_rfkill(priv))
  2072. goto out;
  2073. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2074. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2075. * mac80211 will not be run successfully. */
  2076. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2077. test_bit(STATUS_READY, &priv->status),
  2078. UCODE_READY_TIMEOUT);
  2079. if (!ret) {
  2080. if (!test_bit(STATUS_READY, &priv->status)) {
  2081. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2082. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2083. return -ETIMEDOUT;
  2084. }
  2085. }
  2086. iwl_led_start(priv);
  2087. out:
  2088. priv->is_open = 1;
  2089. IWL_DEBUG_MAC80211(priv, "leave\n");
  2090. return 0;
  2091. }
  2092. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2093. {
  2094. struct iwl_priv *priv = hw->priv;
  2095. IWL_DEBUG_MAC80211(priv, "enter\n");
  2096. if (!priv->is_open)
  2097. return;
  2098. priv->is_open = 0;
  2099. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2100. /* stop mac, cancel any scan request and clear
  2101. * RXON_FILTER_ASSOC_MSK BIT
  2102. */
  2103. mutex_lock(&priv->mutex);
  2104. iwl_scan_cancel_timeout(priv, 100);
  2105. mutex_unlock(&priv->mutex);
  2106. }
  2107. iwl_down(priv);
  2108. flush_workqueue(priv->workqueue);
  2109. /* enable interrupts again in order to receive rfkill changes */
  2110. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2111. iwl_enable_interrupts(priv);
  2112. IWL_DEBUG_MAC80211(priv, "leave\n");
  2113. }
  2114. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2115. {
  2116. struct iwl_priv *priv = hw->priv;
  2117. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2118. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2119. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2120. if (iwl_tx_skb(priv, skb))
  2121. dev_kfree_skb_any(skb);
  2122. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2123. return NETDEV_TX_OK;
  2124. }
  2125. void iwl_config_ap(struct iwl_priv *priv)
  2126. {
  2127. int ret = 0;
  2128. unsigned long flags;
  2129. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2130. return;
  2131. /* The following should be done only at AP bring up */
  2132. if (!iwl_is_associated(priv)) {
  2133. /* RXON - unassoc (to set timing command) */
  2134. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2135. iwlcore_commit_rxon(priv);
  2136. /* RXON Timing */
  2137. iwl_setup_rxon_timing(priv);
  2138. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2139. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2140. if (ret)
  2141. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2142. "Attempting to continue.\n");
  2143. /* AP has all antennas */
  2144. priv->chain_noise_data.active_chains =
  2145. priv->hw_params.valid_rx_ant;
  2146. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2147. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2148. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2149. /* FIXME: what should be the assoc_id for AP? */
  2150. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2151. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2152. priv->staging_rxon.flags |=
  2153. RXON_FLG_SHORT_PREAMBLE_MSK;
  2154. else
  2155. priv->staging_rxon.flags &=
  2156. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2157. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2158. if (priv->assoc_capability &
  2159. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2160. priv->staging_rxon.flags |=
  2161. RXON_FLG_SHORT_SLOT_MSK;
  2162. else
  2163. priv->staging_rxon.flags &=
  2164. ~RXON_FLG_SHORT_SLOT_MSK;
  2165. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2166. priv->staging_rxon.flags &=
  2167. ~RXON_FLG_SHORT_SLOT_MSK;
  2168. }
  2169. /* restore RXON assoc */
  2170. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2171. iwlcore_commit_rxon(priv);
  2172. iwl_reset_qos(priv);
  2173. spin_lock_irqsave(&priv->lock, flags);
  2174. iwl_activate_qos(priv, 1);
  2175. spin_unlock_irqrestore(&priv->lock, flags);
  2176. iwl_add_bcast_station(priv);
  2177. }
  2178. iwl_send_beacon_cmd(priv);
  2179. /* FIXME - we need to add code here to detect a totally new
  2180. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2181. * clear sta table, add BCAST sta... */
  2182. }
  2183. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2184. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2185. u32 iv32, u16 *phase1key)
  2186. {
  2187. struct iwl_priv *priv = hw->priv;
  2188. IWL_DEBUG_MAC80211(priv, "enter\n");
  2189. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2190. IWL_DEBUG_MAC80211(priv, "leave\n");
  2191. }
  2192. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2193. struct ieee80211_vif *vif,
  2194. struct ieee80211_sta *sta,
  2195. struct ieee80211_key_conf *key)
  2196. {
  2197. struct iwl_priv *priv = hw->priv;
  2198. const u8 *addr;
  2199. int ret;
  2200. u8 sta_id;
  2201. bool is_default_wep_key = false;
  2202. IWL_DEBUG_MAC80211(priv, "enter\n");
  2203. if (priv->cfg->mod_params->sw_crypto) {
  2204. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2205. return -EOPNOTSUPP;
  2206. }
  2207. addr = sta ? sta->addr : iwl_bcast_addr;
  2208. sta_id = iwl_find_station(priv, addr);
  2209. if (sta_id == IWL_INVALID_STATION) {
  2210. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2211. addr);
  2212. return -EINVAL;
  2213. }
  2214. mutex_lock(&priv->mutex);
  2215. iwl_scan_cancel_timeout(priv, 100);
  2216. mutex_unlock(&priv->mutex);
  2217. /* If we are getting WEP group key and we didn't receive any key mapping
  2218. * so far, we are in legacy wep mode (group key only), otherwise we are
  2219. * in 1X mode.
  2220. * In legacy wep mode, we use another host command to the uCode */
  2221. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2222. priv->iw_mode != NL80211_IFTYPE_AP) {
  2223. if (cmd == SET_KEY)
  2224. is_default_wep_key = !priv->key_mapping_key;
  2225. else
  2226. is_default_wep_key =
  2227. (key->hw_key_idx == HW_KEY_DEFAULT);
  2228. }
  2229. switch (cmd) {
  2230. case SET_KEY:
  2231. if (is_default_wep_key)
  2232. ret = iwl_set_default_wep_key(priv, key);
  2233. else
  2234. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2235. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2236. break;
  2237. case DISABLE_KEY:
  2238. if (is_default_wep_key)
  2239. ret = iwl_remove_default_wep_key(priv, key);
  2240. else
  2241. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2242. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2243. break;
  2244. default:
  2245. ret = -EINVAL;
  2246. }
  2247. IWL_DEBUG_MAC80211(priv, "leave\n");
  2248. return ret;
  2249. }
  2250. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2251. struct ieee80211_vif *vif,
  2252. enum ieee80211_ampdu_mlme_action action,
  2253. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2254. {
  2255. struct iwl_priv *priv = hw->priv;
  2256. int ret;
  2257. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2258. sta->addr, tid);
  2259. if (!(priv->cfg->sku & IWL_SKU_N))
  2260. return -EACCES;
  2261. switch (action) {
  2262. case IEEE80211_AMPDU_RX_START:
  2263. IWL_DEBUG_HT(priv, "start Rx\n");
  2264. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2265. case IEEE80211_AMPDU_RX_STOP:
  2266. IWL_DEBUG_HT(priv, "stop Rx\n");
  2267. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2268. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2269. return 0;
  2270. else
  2271. return ret;
  2272. case IEEE80211_AMPDU_TX_START:
  2273. IWL_DEBUG_HT(priv, "start Tx\n");
  2274. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2275. case IEEE80211_AMPDU_TX_STOP:
  2276. IWL_DEBUG_HT(priv, "stop Tx\n");
  2277. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2278. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2279. return 0;
  2280. else
  2281. return ret;
  2282. default:
  2283. IWL_DEBUG_HT(priv, "unknown\n");
  2284. return -EINVAL;
  2285. break;
  2286. }
  2287. return 0;
  2288. }
  2289. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2290. struct ieee80211_low_level_stats *stats)
  2291. {
  2292. struct iwl_priv *priv = hw->priv;
  2293. priv = hw->priv;
  2294. IWL_DEBUG_MAC80211(priv, "enter\n");
  2295. IWL_DEBUG_MAC80211(priv, "leave\n");
  2296. return 0;
  2297. }
  2298. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2299. struct ieee80211_vif *vif,
  2300. enum sta_notify_cmd cmd,
  2301. struct ieee80211_sta *sta)
  2302. {
  2303. struct iwl_priv *priv = hw->priv;
  2304. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2305. int sta_id;
  2306. /*
  2307. * TODO: We really should use this callback to
  2308. * actually maintain the station table in
  2309. * the device.
  2310. */
  2311. switch (cmd) {
  2312. case STA_NOTIFY_ADD:
  2313. atomic_set(&sta_priv->pending_frames, 0);
  2314. if (vif->type == NL80211_IFTYPE_AP)
  2315. sta_priv->client = true;
  2316. break;
  2317. case STA_NOTIFY_SLEEP:
  2318. WARN_ON(!sta_priv->client);
  2319. sta_priv->asleep = true;
  2320. if (atomic_read(&sta_priv->pending_frames) > 0)
  2321. ieee80211_sta_block_awake(hw, sta, true);
  2322. break;
  2323. case STA_NOTIFY_AWAKE:
  2324. WARN_ON(!sta_priv->client);
  2325. sta_priv->asleep = false;
  2326. sta_id = iwl_find_station(priv, sta->addr);
  2327. if (sta_id != IWL_INVALID_STATION)
  2328. iwl_sta_modify_ps_wake(priv, sta_id);
  2329. break;
  2330. default:
  2331. break;
  2332. }
  2333. }
  2334. /*****************************************************************************
  2335. *
  2336. * sysfs attributes
  2337. *
  2338. *****************************************************************************/
  2339. #ifdef CONFIG_IWLWIFI_DEBUG
  2340. /*
  2341. * The following adds a new attribute to the sysfs representation
  2342. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2343. * used for controlling the debug level.
  2344. *
  2345. * See the level definitions in iwl for details.
  2346. *
  2347. * The debug_level being managed using sysfs below is a per device debug
  2348. * level that is used instead of the global debug level if it (the per
  2349. * device debug level) is set.
  2350. */
  2351. static ssize_t show_debug_level(struct device *d,
  2352. struct device_attribute *attr, char *buf)
  2353. {
  2354. struct iwl_priv *priv = dev_get_drvdata(d);
  2355. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2356. }
  2357. static ssize_t store_debug_level(struct device *d,
  2358. struct device_attribute *attr,
  2359. const char *buf, size_t count)
  2360. {
  2361. struct iwl_priv *priv = dev_get_drvdata(d);
  2362. unsigned long val;
  2363. int ret;
  2364. ret = strict_strtoul(buf, 0, &val);
  2365. if (ret)
  2366. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2367. else {
  2368. priv->debug_level = val;
  2369. if (iwl_alloc_traffic_mem(priv))
  2370. IWL_ERR(priv,
  2371. "Not enough memory to generate traffic log\n");
  2372. }
  2373. return strnlen(buf, count);
  2374. }
  2375. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2376. show_debug_level, store_debug_level);
  2377. #endif /* CONFIG_IWLWIFI_DEBUG */
  2378. static ssize_t show_temperature(struct device *d,
  2379. struct device_attribute *attr, char *buf)
  2380. {
  2381. struct iwl_priv *priv = dev_get_drvdata(d);
  2382. if (!iwl_is_alive(priv))
  2383. return -EAGAIN;
  2384. return sprintf(buf, "%d\n", priv->temperature);
  2385. }
  2386. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2387. static ssize_t show_tx_power(struct device *d,
  2388. struct device_attribute *attr, char *buf)
  2389. {
  2390. struct iwl_priv *priv = dev_get_drvdata(d);
  2391. if (!iwl_is_ready_rf(priv))
  2392. return sprintf(buf, "off\n");
  2393. else
  2394. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2395. }
  2396. static ssize_t store_tx_power(struct device *d,
  2397. struct device_attribute *attr,
  2398. const char *buf, size_t count)
  2399. {
  2400. struct iwl_priv *priv = dev_get_drvdata(d);
  2401. unsigned long val;
  2402. int ret;
  2403. ret = strict_strtoul(buf, 10, &val);
  2404. if (ret)
  2405. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2406. else {
  2407. ret = iwl_set_tx_power(priv, val, false);
  2408. if (ret)
  2409. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2410. ret);
  2411. else
  2412. ret = count;
  2413. }
  2414. return ret;
  2415. }
  2416. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2417. static ssize_t show_flags(struct device *d,
  2418. struct device_attribute *attr, char *buf)
  2419. {
  2420. struct iwl_priv *priv = dev_get_drvdata(d);
  2421. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2422. }
  2423. static ssize_t store_flags(struct device *d,
  2424. struct device_attribute *attr,
  2425. const char *buf, size_t count)
  2426. {
  2427. struct iwl_priv *priv = dev_get_drvdata(d);
  2428. unsigned long val;
  2429. u32 flags;
  2430. int ret = strict_strtoul(buf, 0, &val);
  2431. if (ret)
  2432. return ret;
  2433. flags = (u32)val;
  2434. mutex_lock(&priv->mutex);
  2435. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2436. /* Cancel any currently running scans... */
  2437. if (iwl_scan_cancel_timeout(priv, 100))
  2438. IWL_WARN(priv, "Could not cancel scan.\n");
  2439. else {
  2440. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2441. priv->staging_rxon.flags = cpu_to_le32(flags);
  2442. iwlcore_commit_rxon(priv);
  2443. }
  2444. }
  2445. mutex_unlock(&priv->mutex);
  2446. return count;
  2447. }
  2448. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2449. static ssize_t show_filter_flags(struct device *d,
  2450. struct device_attribute *attr, char *buf)
  2451. {
  2452. struct iwl_priv *priv = dev_get_drvdata(d);
  2453. return sprintf(buf, "0x%04X\n",
  2454. le32_to_cpu(priv->active_rxon.filter_flags));
  2455. }
  2456. static ssize_t store_filter_flags(struct device *d,
  2457. struct device_attribute *attr,
  2458. const char *buf, size_t count)
  2459. {
  2460. struct iwl_priv *priv = dev_get_drvdata(d);
  2461. unsigned long val;
  2462. u32 filter_flags;
  2463. int ret = strict_strtoul(buf, 0, &val);
  2464. if (ret)
  2465. return ret;
  2466. filter_flags = (u32)val;
  2467. mutex_lock(&priv->mutex);
  2468. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2469. /* Cancel any currently running scans... */
  2470. if (iwl_scan_cancel_timeout(priv, 100))
  2471. IWL_WARN(priv, "Could not cancel scan.\n");
  2472. else {
  2473. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2474. "0x%04X\n", filter_flags);
  2475. priv->staging_rxon.filter_flags =
  2476. cpu_to_le32(filter_flags);
  2477. iwlcore_commit_rxon(priv);
  2478. }
  2479. }
  2480. mutex_unlock(&priv->mutex);
  2481. return count;
  2482. }
  2483. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2484. store_filter_flags);
  2485. static ssize_t show_statistics(struct device *d,
  2486. struct device_attribute *attr, char *buf)
  2487. {
  2488. struct iwl_priv *priv = dev_get_drvdata(d);
  2489. u32 size = sizeof(struct iwl_notif_statistics);
  2490. u32 len = 0, ofs = 0;
  2491. u8 *data = (u8 *)&priv->statistics;
  2492. int rc = 0;
  2493. if (!iwl_is_alive(priv))
  2494. return -EAGAIN;
  2495. mutex_lock(&priv->mutex);
  2496. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2497. mutex_unlock(&priv->mutex);
  2498. if (rc) {
  2499. len = sprintf(buf,
  2500. "Error sending statistics request: 0x%08X\n", rc);
  2501. return len;
  2502. }
  2503. while (size && (PAGE_SIZE - len)) {
  2504. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2505. PAGE_SIZE - len, 1);
  2506. len = strlen(buf);
  2507. if (PAGE_SIZE - len)
  2508. buf[len++] = '\n';
  2509. ofs += 16;
  2510. size -= min(size, 16U);
  2511. }
  2512. return len;
  2513. }
  2514. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2515. static ssize_t show_rts_ht_protection(struct device *d,
  2516. struct device_attribute *attr, char *buf)
  2517. {
  2518. struct iwl_priv *priv = dev_get_drvdata(d);
  2519. return sprintf(buf, "%s\n",
  2520. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2521. }
  2522. static ssize_t store_rts_ht_protection(struct device *d,
  2523. struct device_attribute *attr,
  2524. const char *buf, size_t count)
  2525. {
  2526. struct iwl_priv *priv = dev_get_drvdata(d);
  2527. unsigned long val;
  2528. int ret;
  2529. ret = strict_strtoul(buf, 10, &val);
  2530. if (ret)
  2531. IWL_INFO(priv, "Input is not in decimal form.\n");
  2532. else {
  2533. if (!iwl_is_associated(priv))
  2534. priv->cfg->use_rts_for_ht = val ? true : false;
  2535. else
  2536. IWL_ERR(priv, "Sta associated with AP - "
  2537. "Change protection mechanism is not allowed\n");
  2538. ret = count;
  2539. }
  2540. return ret;
  2541. }
  2542. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2543. show_rts_ht_protection, store_rts_ht_protection);
  2544. /*****************************************************************************
  2545. *
  2546. * driver setup and teardown
  2547. *
  2548. *****************************************************************************/
  2549. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2550. {
  2551. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2552. init_waitqueue_head(&priv->wait_command_queue);
  2553. INIT_WORK(&priv->up, iwl_bg_up);
  2554. INIT_WORK(&priv->restart, iwl_bg_restart);
  2555. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2556. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2557. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2558. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2559. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2560. iwl_setup_scan_deferred_work(priv);
  2561. if (priv->cfg->ops->lib->setup_deferred_work)
  2562. priv->cfg->ops->lib->setup_deferred_work(priv);
  2563. init_timer(&priv->statistics_periodic);
  2564. priv->statistics_periodic.data = (unsigned long)priv;
  2565. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2566. if (!priv->cfg->use_isr_legacy)
  2567. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2568. iwl_irq_tasklet, (unsigned long)priv);
  2569. else
  2570. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2571. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2572. }
  2573. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2574. {
  2575. if (priv->cfg->ops->lib->cancel_deferred_work)
  2576. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2577. cancel_delayed_work_sync(&priv->init_alive_start);
  2578. cancel_delayed_work(&priv->scan_check);
  2579. cancel_delayed_work(&priv->alive_start);
  2580. cancel_work_sync(&priv->beacon_update);
  2581. del_timer_sync(&priv->statistics_periodic);
  2582. }
  2583. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2584. struct ieee80211_rate *rates)
  2585. {
  2586. int i;
  2587. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2588. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2589. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2590. rates[i].hw_value_short = i;
  2591. rates[i].flags = 0;
  2592. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2593. /*
  2594. * If CCK != 1M then set short preamble rate flag.
  2595. */
  2596. rates[i].flags |=
  2597. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2598. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2599. }
  2600. }
  2601. }
  2602. static int iwl_init_drv(struct iwl_priv *priv)
  2603. {
  2604. int ret;
  2605. priv->ibss_beacon = NULL;
  2606. spin_lock_init(&priv->lock);
  2607. spin_lock_init(&priv->sta_lock);
  2608. spin_lock_init(&priv->hcmd_lock);
  2609. INIT_LIST_HEAD(&priv->free_frames);
  2610. mutex_init(&priv->mutex);
  2611. /* Clear the driver's (not device's) station table */
  2612. iwl_clear_stations_table(priv);
  2613. priv->ieee_channels = NULL;
  2614. priv->ieee_rates = NULL;
  2615. priv->band = IEEE80211_BAND_2GHZ;
  2616. priv->iw_mode = NL80211_IFTYPE_STATION;
  2617. /* Choose which receivers/antennas to use */
  2618. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2619. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2620. iwl_init_scan_params(priv);
  2621. iwl_reset_qos(priv);
  2622. priv->qos_data.qos_active = 0;
  2623. priv->qos_data.qos_cap.val = 0;
  2624. priv->rates_mask = IWL_RATES_MASK;
  2625. /* Set the tx_power_user_lmt to the lowest power level
  2626. * this value will get overwritten by channel max power avg
  2627. * from eeprom */
  2628. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2629. ret = iwl_init_channel_map(priv);
  2630. if (ret) {
  2631. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2632. goto err;
  2633. }
  2634. ret = iwlcore_init_geos(priv);
  2635. if (ret) {
  2636. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2637. goto err_free_channel_map;
  2638. }
  2639. iwl_init_hw_rates(priv, priv->ieee_rates);
  2640. return 0;
  2641. err_free_channel_map:
  2642. iwl_free_channel_map(priv);
  2643. err:
  2644. return ret;
  2645. }
  2646. static void iwl_uninit_drv(struct iwl_priv *priv)
  2647. {
  2648. iwl_calib_free_results(priv);
  2649. iwlcore_free_geos(priv);
  2650. iwl_free_channel_map(priv);
  2651. kfree(priv->scan);
  2652. }
  2653. static struct attribute *iwl_sysfs_entries[] = {
  2654. &dev_attr_flags.attr,
  2655. &dev_attr_filter_flags.attr,
  2656. &dev_attr_statistics.attr,
  2657. &dev_attr_temperature.attr,
  2658. &dev_attr_tx_power.attr,
  2659. &dev_attr_rts_ht_protection.attr,
  2660. #ifdef CONFIG_IWLWIFI_DEBUG
  2661. &dev_attr_debug_level.attr,
  2662. #endif
  2663. NULL
  2664. };
  2665. static struct attribute_group iwl_attribute_group = {
  2666. .name = NULL, /* put in device directory */
  2667. .attrs = iwl_sysfs_entries,
  2668. };
  2669. static struct ieee80211_ops iwl_hw_ops = {
  2670. .tx = iwl_mac_tx,
  2671. .start = iwl_mac_start,
  2672. .stop = iwl_mac_stop,
  2673. .add_interface = iwl_mac_add_interface,
  2674. .remove_interface = iwl_mac_remove_interface,
  2675. .config = iwl_mac_config,
  2676. .configure_filter = iwl_configure_filter,
  2677. .set_key = iwl_mac_set_key,
  2678. .update_tkip_key = iwl_mac_update_tkip_key,
  2679. .get_stats = iwl_mac_get_stats,
  2680. .get_tx_stats = iwl_mac_get_tx_stats,
  2681. .conf_tx = iwl_mac_conf_tx,
  2682. .reset_tsf = iwl_mac_reset_tsf,
  2683. .bss_info_changed = iwl_bss_info_changed,
  2684. .ampdu_action = iwl_mac_ampdu_action,
  2685. .hw_scan = iwl_mac_hw_scan,
  2686. .sta_notify = iwl_mac_sta_notify,
  2687. };
  2688. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2689. {
  2690. int err = 0;
  2691. struct iwl_priv *priv;
  2692. struct ieee80211_hw *hw;
  2693. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2694. unsigned long flags;
  2695. u16 pci_cmd;
  2696. /************************
  2697. * 1. Allocating HW data
  2698. ************************/
  2699. /* Disabling hardware scan means that mac80211 will perform scans
  2700. * "the hard way", rather than using device's scan. */
  2701. if (cfg->mod_params->disable_hw_scan) {
  2702. if (iwl_debug_level & IWL_DL_INFO)
  2703. dev_printk(KERN_DEBUG, &(pdev->dev),
  2704. "Disabling hw_scan\n");
  2705. iwl_hw_ops.hw_scan = NULL;
  2706. }
  2707. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2708. if (!hw) {
  2709. err = -ENOMEM;
  2710. goto out;
  2711. }
  2712. priv = hw->priv;
  2713. /* At this point both hw and priv are allocated. */
  2714. SET_IEEE80211_DEV(hw, &pdev->dev);
  2715. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2716. priv->cfg = cfg;
  2717. priv->pci_dev = pdev;
  2718. priv->inta_mask = CSR_INI_SET_MASK;
  2719. #ifdef CONFIG_IWLWIFI_DEBUG
  2720. atomic_set(&priv->restrict_refcnt, 0);
  2721. #endif
  2722. if (iwl_alloc_traffic_mem(priv))
  2723. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2724. /**************************
  2725. * 2. Initializing PCI bus
  2726. **************************/
  2727. if (pci_enable_device(pdev)) {
  2728. err = -ENODEV;
  2729. goto out_ieee80211_free_hw;
  2730. }
  2731. pci_set_master(pdev);
  2732. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2733. if (!err)
  2734. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2735. if (err) {
  2736. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2737. if (!err)
  2738. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2739. /* both attempts failed: */
  2740. if (err) {
  2741. IWL_WARN(priv, "No suitable DMA available.\n");
  2742. goto out_pci_disable_device;
  2743. }
  2744. }
  2745. err = pci_request_regions(pdev, DRV_NAME);
  2746. if (err)
  2747. goto out_pci_disable_device;
  2748. pci_set_drvdata(pdev, priv);
  2749. /***********************
  2750. * 3. Read REV register
  2751. ***********************/
  2752. priv->hw_base = pci_iomap(pdev, 0, 0);
  2753. if (!priv->hw_base) {
  2754. err = -ENODEV;
  2755. goto out_pci_release_regions;
  2756. }
  2757. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2758. (unsigned long long) pci_resource_len(pdev, 0));
  2759. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2760. /* this spin lock will be used in apm_ops.init and EEPROM access
  2761. * we should init now
  2762. */
  2763. spin_lock_init(&priv->reg_lock);
  2764. iwl_hw_detect(priv);
  2765. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2766. priv->cfg->name, priv->hw_rev);
  2767. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2768. * PCI Tx retries from interfering with C3 CPU state */
  2769. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2770. iwl_prepare_card_hw(priv);
  2771. if (!priv->hw_ready) {
  2772. IWL_WARN(priv, "Failed, HW not ready\n");
  2773. goto out_iounmap;
  2774. }
  2775. /*****************
  2776. * 4. Read EEPROM
  2777. *****************/
  2778. /* Read the EEPROM */
  2779. err = iwl_eeprom_init(priv);
  2780. if (err) {
  2781. IWL_ERR(priv, "Unable to init EEPROM\n");
  2782. goto out_iounmap;
  2783. }
  2784. err = iwl_eeprom_check_version(priv);
  2785. if (err)
  2786. goto out_free_eeprom;
  2787. /* extract MAC Address */
  2788. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2789. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2790. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2791. /************************
  2792. * 5. Setup HW constants
  2793. ************************/
  2794. if (iwl_set_hw_params(priv)) {
  2795. IWL_ERR(priv, "failed to set hw parameters\n");
  2796. goto out_free_eeprom;
  2797. }
  2798. /*******************
  2799. * 6. Setup priv
  2800. *******************/
  2801. err = iwl_init_drv(priv);
  2802. if (err)
  2803. goto out_free_eeprom;
  2804. /* At this point both hw and priv are initialized. */
  2805. /********************
  2806. * 7. Setup services
  2807. ********************/
  2808. spin_lock_irqsave(&priv->lock, flags);
  2809. iwl_disable_interrupts(priv);
  2810. spin_unlock_irqrestore(&priv->lock, flags);
  2811. pci_enable_msi(priv->pci_dev);
  2812. iwl_alloc_isr_ict(priv);
  2813. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2814. IRQF_SHARED, DRV_NAME, priv);
  2815. if (err) {
  2816. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2817. goto out_disable_msi;
  2818. }
  2819. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2820. if (err) {
  2821. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2822. goto out_free_irq;
  2823. }
  2824. iwl_setup_deferred_work(priv);
  2825. iwl_setup_rx_handlers(priv);
  2826. /**********************************
  2827. * 8. Setup and register mac80211
  2828. **********************************/
  2829. /* enable interrupts if needed: hw bug w/a */
  2830. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2831. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2832. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2833. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2834. }
  2835. iwl_enable_interrupts(priv);
  2836. err = iwl_setup_mac(priv);
  2837. if (err)
  2838. goto out_remove_sysfs;
  2839. err = iwl_dbgfs_register(priv, DRV_NAME);
  2840. if (err)
  2841. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2842. /* If platform's RF_KILL switch is NOT set to KILL */
  2843. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2844. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2845. else
  2846. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2847. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2848. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2849. iwl_power_initialize(priv);
  2850. iwl_tt_initialize(priv);
  2851. return 0;
  2852. out_remove_sysfs:
  2853. destroy_workqueue(priv->workqueue);
  2854. priv->workqueue = NULL;
  2855. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2856. out_free_irq:
  2857. free_irq(priv->pci_dev->irq, priv);
  2858. iwl_free_isr_ict(priv);
  2859. out_disable_msi:
  2860. pci_disable_msi(priv->pci_dev);
  2861. iwl_uninit_drv(priv);
  2862. out_free_eeprom:
  2863. iwl_eeprom_free(priv);
  2864. out_iounmap:
  2865. pci_iounmap(pdev, priv->hw_base);
  2866. out_pci_release_regions:
  2867. pci_set_drvdata(pdev, NULL);
  2868. pci_release_regions(pdev);
  2869. out_pci_disable_device:
  2870. pci_disable_device(pdev);
  2871. out_ieee80211_free_hw:
  2872. iwl_free_traffic_mem(priv);
  2873. ieee80211_free_hw(priv->hw);
  2874. out:
  2875. return err;
  2876. }
  2877. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2878. {
  2879. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2880. unsigned long flags;
  2881. if (!priv)
  2882. return;
  2883. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2884. iwl_dbgfs_unregister(priv);
  2885. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2886. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2887. * to be called and iwl_down since we are removing the device
  2888. * we need to set STATUS_EXIT_PENDING bit.
  2889. */
  2890. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2891. if (priv->mac80211_registered) {
  2892. ieee80211_unregister_hw(priv->hw);
  2893. priv->mac80211_registered = 0;
  2894. } else {
  2895. iwl_down(priv);
  2896. }
  2897. /*
  2898. * Make sure device is reset to low power before unloading driver.
  2899. * This may be redundant with iwl_down(), but there are paths to
  2900. * run iwl_down() without calling apm_ops.stop(), and there are
  2901. * paths to avoid running iwl_down() at all before leaving driver.
  2902. * This (inexpensive) call *makes sure* device is reset.
  2903. */
  2904. priv->cfg->ops->lib->apm_ops.stop(priv);
  2905. iwl_tt_exit(priv);
  2906. /* make sure we flush any pending irq or
  2907. * tasklet for the driver
  2908. */
  2909. spin_lock_irqsave(&priv->lock, flags);
  2910. iwl_disable_interrupts(priv);
  2911. spin_unlock_irqrestore(&priv->lock, flags);
  2912. iwl_synchronize_irq(priv);
  2913. iwl_dealloc_ucode_pci(priv);
  2914. if (priv->rxq.bd)
  2915. iwl_rx_queue_free(priv, &priv->rxq);
  2916. iwl_hw_txq_ctx_free(priv);
  2917. iwl_clear_stations_table(priv);
  2918. iwl_eeprom_free(priv);
  2919. /*netif_stop_queue(dev); */
  2920. flush_workqueue(priv->workqueue);
  2921. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2922. * priv->workqueue... so we can't take down the workqueue
  2923. * until now... */
  2924. destroy_workqueue(priv->workqueue);
  2925. priv->workqueue = NULL;
  2926. iwl_free_traffic_mem(priv);
  2927. free_irq(priv->pci_dev->irq, priv);
  2928. pci_disable_msi(priv->pci_dev);
  2929. pci_iounmap(pdev, priv->hw_base);
  2930. pci_release_regions(pdev);
  2931. pci_disable_device(pdev);
  2932. pci_set_drvdata(pdev, NULL);
  2933. iwl_uninit_drv(priv);
  2934. iwl_free_isr_ict(priv);
  2935. if (priv->ibss_beacon)
  2936. dev_kfree_skb(priv->ibss_beacon);
  2937. ieee80211_free_hw(priv->hw);
  2938. }
  2939. /*****************************************************************************
  2940. *
  2941. * driver and module entry point
  2942. *
  2943. *****************************************************************************/
  2944. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2945. static struct pci_device_id iwl_hw_card_ids[] = {
  2946. #ifdef CONFIG_IWL4965
  2947. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2948. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2949. #endif /* CONFIG_IWL4965 */
  2950. #ifdef CONFIG_IWL5000
  2951. /* 5100 Series WiFi */
  2952. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  2953. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  2954. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  2955. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  2956. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  2957. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2958. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  2959. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  2960. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  2961. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  2962. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  2963. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  2964. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  2965. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2966. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  2967. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  2968. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  2969. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  2970. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  2971. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  2972. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  2973. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2974. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  2975. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  2976. /* 5300 Series WiFi */
  2977. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  2978. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  2979. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  2980. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  2981. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  2982. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  2983. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  2984. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  2985. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  2986. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  2987. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  2988. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  2989. /* 5350 Series WiFi/WiMax */
  2990. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  2991. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  2992. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  2993. /* 5150 Series Wifi/WiMax */
  2994. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  2995. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  2996. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  2997. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  2998. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  2999. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3000. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3001. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3002. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3003. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3004. /* 6x00 Series */
  3005. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3006. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3007. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3008. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3009. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3010. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3011. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3012. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3013. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3014. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3015. /* 6x50 WiFi/WiMax Series */
  3016. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3017. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3018. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3019. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3020. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3021. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3022. /* 1000 Series WiFi */
  3023. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3024. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3025. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3026. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3027. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3028. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3029. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3030. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3031. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3032. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3033. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3034. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3035. #endif /* CONFIG_IWL5000 */
  3036. {0}
  3037. };
  3038. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3039. static struct pci_driver iwl_driver = {
  3040. .name = DRV_NAME,
  3041. .id_table = iwl_hw_card_ids,
  3042. .probe = iwl_pci_probe,
  3043. .remove = __devexit_p(iwl_pci_remove),
  3044. #ifdef CONFIG_PM
  3045. .suspend = iwl_pci_suspend,
  3046. .resume = iwl_pci_resume,
  3047. #endif
  3048. };
  3049. static int __init iwl_init(void)
  3050. {
  3051. int ret;
  3052. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3053. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3054. ret = iwlagn_rate_control_register();
  3055. if (ret) {
  3056. printk(KERN_ERR DRV_NAME
  3057. "Unable to register rate control algorithm: %d\n", ret);
  3058. return ret;
  3059. }
  3060. ret = pci_register_driver(&iwl_driver);
  3061. if (ret) {
  3062. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3063. goto error_register;
  3064. }
  3065. return ret;
  3066. error_register:
  3067. iwlagn_rate_control_unregister();
  3068. return ret;
  3069. }
  3070. static void __exit iwl_exit(void)
  3071. {
  3072. pci_unregister_driver(&iwl_driver);
  3073. iwlagn_rate_control_unregister();
  3074. }
  3075. module_exit(iwl_exit);
  3076. module_init(iwl_init);
  3077. #ifdef CONFIG_IWLWIFI_DEBUG
  3078. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3079. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3080. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3081. MODULE_PARM_DESC(debug, "debug output mask");
  3082. #endif