core.h 26 KB

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  1. /*
  2. * core.h -- Core Driver for Wolfson WM8350 PMIC
  3. *
  4. * Copyright 2007 Wolfson Microelectronics PLC
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #ifndef __LINUX_MFD_WM8350_CORE_H_
  13. #define __LINUX_MFD_WM8350_CORE_H_
  14. #include <linux/kernel.h>
  15. #include <linux/mutex.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/completion.h>
  18. #include <linux/mfd/wm8350/audio.h>
  19. #include <linux/mfd/wm8350/gpio.h>
  20. #include <linux/mfd/wm8350/pmic.h>
  21. #include <linux/mfd/wm8350/rtc.h>
  22. #include <linux/mfd/wm8350/supply.h>
  23. #include <linux/mfd/wm8350/wdt.h>
  24. /*
  25. * Register values.
  26. */
  27. #define WM8350_RESET_ID 0x00
  28. #define WM8350_ID 0x01
  29. #define WM8350_REVISION 0x02
  30. #define WM8350_SYSTEM_CONTROL_1 0x03
  31. #define WM8350_SYSTEM_CONTROL_2 0x04
  32. #define WM8350_SYSTEM_HIBERNATE 0x05
  33. #define WM8350_INTERFACE_CONTROL 0x06
  34. #define WM8350_POWER_MGMT_1 0x08
  35. #define WM8350_POWER_MGMT_2 0x09
  36. #define WM8350_POWER_MGMT_3 0x0A
  37. #define WM8350_POWER_MGMT_4 0x0B
  38. #define WM8350_POWER_MGMT_5 0x0C
  39. #define WM8350_POWER_MGMT_6 0x0D
  40. #define WM8350_POWER_MGMT_7 0x0E
  41. #define WM8350_SYSTEM_INTERRUPTS 0x18
  42. #define WM8350_INT_STATUS_1 0x19
  43. #define WM8350_INT_STATUS_2 0x1A
  44. #define WM8350_POWER_UP_INT_STATUS 0x1B
  45. #define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C
  46. #define WM8350_OVER_CURRENT_INT_STATUS 0x1D
  47. #define WM8350_GPIO_INT_STATUS 0x1E
  48. #define WM8350_COMPARATOR_INT_STATUS 0x1F
  49. #define WM8350_SYSTEM_INTERRUPTS_MASK 0x20
  50. #define WM8350_INT_STATUS_1_MASK 0x21
  51. #define WM8350_INT_STATUS_2_MASK 0x22
  52. #define WM8350_POWER_UP_INT_STATUS_MASK 0x23
  53. #define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24
  54. #define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25
  55. #define WM8350_GPIO_INT_STATUS_MASK 0x26
  56. #define WM8350_COMPARATOR_INT_STATUS_MASK 0x27
  57. #define WM8350_CHARGER_OVERRIDES 0xE2
  58. #define WM8350_MISC_OVERRIDES 0xE3
  59. #define WM8350_COMPARATOR_OVERRIDES 0xE7
  60. #define WM8350_STATE_MACHINE_STATUS 0xE9
  61. #define WM8350_MAX_REGISTER 0xFF
  62. /*
  63. * Field Definitions.
  64. */
  65. /*
  66. * R0 (0x00) - Reset/ID
  67. */
  68. #define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF
  69. /*
  70. * R1 (0x01) - ID
  71. */
  72. #define WM8350_CHIP_REV_MASK 0x7000
  73. #define WM8350_CONF_STS_MASK 0x0C00
  74. #define WM8350_CUST_ID_MASK 0x00FF
  75. /*
  76. * R2 (0x02) - Revision
  77. */
  78. #define WM8350_MASK_REV_MASK 0x00FF
  79. /*
  80. * R3 (0x03) - System Control 1
  81. */
  82. #define WM8350_CHIP_ON 0x8000
  83. #define WM8350_POWERCYCLE 0x2000
  84. #define WM8350_VCC_FAULT_OV 0x1000
  85. #define WM8350_REG_RSTB_TIME_MASK 0x0C00
  86. #define WM8350_BG_SLEEP 0x0200
  87. #define WM8350_MEM_VALID 0x0020
  88. #define WM8350_CHIP_SET_UP 0x0010
  89. #define WM8350_ON_DEB_T 0x0008
  90. #define WM8350_ON_POL 0x0002
  91. #define WM8350_IRQ_POL 0x0001
  92. /*
  93. * R4 (0x04) - System Control 2
  94. */
  95. #define WM8350_USB_SUSPEND_8MA 0x8000
  96. #define WM8350_USB_SUSPEND 0x4000
  97. #define WM8350_USB_MSTR 0x2000
  98. #define WM8350_USB_MSTR_SRC 0x1000
  99. #define WM8350_USB_500MA 0x0800
  100. #define WM8350_USB_NOLIM 0x0400
  101. /*
  102. * R5 (0x05) - System Hibernate
  103. */
  104. #define WM8350_HIBERNATE 0x8000
  105. #define WM8350_WDOG_HIB_MODE 0x0080
  106. #define WM8350_REG_HIB_STARTUP_SEQ 0x0040
  107. #define WM8350_REG_RESET_HIB_MODE 0x0020
  108. #define WM8350_RST_HIB_MODE 0x0010
  109. #define WM8350_IRQ_HIB_MODE 0x0008
  110. #define WM8350_MEMRST_HIB_MODE 0x0004
  111. #define WM8350_PCCOMP_HIB_MODE 0x0002
  112. #define WM8350_TEMPMON_HIB_MODE 0x0001
  113. /*
  114. * R6 (0x06) - Interface Control
  115. */
  116. #define WM8350_USE_DEV_PINS 0x8000
  117. #define WM8350_USE_DEV_PINS_MASK 0x8000
  118. #define WM8350_USE_DEV_PINS_SHIFT 15
  119. #define WM8350_DEV_ADDR_MASK 0x6000
  120. #define WM8350_DEV_ADDR_SHIFT 13
  121. #define WM8350_CONFIG_DONE 0x1000
  122. #define WM8350_CONFIG_DONE_MASK 0x1000
  123. #define WM8350_CONFIG_DONE_SHIFT 12
  124. #define WM8350_RECONFIG_AT_ON 0x0800
  125. #define WM8350_RECONFIG_AT_ON_MASK 0x0800
  126. #define WM8350_RECONFIG_AT_ON_SHIFT 11
  127. #define WM8350_AUTOINC 0x0200
  128. #define WM8350_AUTOINC_MASK 0x0200
  129. #define WM8350_AUTOINC_SHIFT 9
  130. #define WM8350_ARA 0x0100
  131. #define WM8350_ARA_MASK 0x0100
  132. #define WM8350_ARA_SHIFT 8
  133. #define WM8350_SPI_CFG 0x0008
  134. #define WM8350_SPI_CFG_MASK 0x0008
  135. #define WM8350_SPI_CFG_SHIFT 3
  136. #define WM8350_SPI_4WIRE 0x0004
  137. #define WM8350_SPI_4WIRE_MASK 0x0004
  138. #define WM8350_SPI_4WIRE_SHIFT 2
  139. #define WM8350_SPI_3WIRE 0x0002
  140. #define WM8350_SPI_3WIRE_MASK 0x0002
  141. #define WM8350_SPI_3WIRE_SHIFT 1
  142. /* Bit values for R06 (0x06) */
  143. #define WM8350_USE_DEV_PINS_PRIMARY 0
  144. #define WM8350_USE_DEV_PINS_DEV 1
  145. #define WM8350_DEV_ADDR_34 0
  146. #define WM8350_DEV_ADDR_36 1
  147. #define WM8350_DEV_ADDR_3C 2
  148. #define WM8350_DEV_ADDR_3E 3
  149. #define WM8350_CONFIG_DONE_OFF 0
  150. #define WM8350_CONFIG_DONE_DONE 1
  151. #define WM8350_RECONFIG_AT_ON_OFF 0
  152. #define WM8350_RECONFIG_AT_ON_ON 1
  153. #define WM8350_AUTOINC_OFF 0
  154. #define WM8350_AUTOINC_ON 1
  155. #define WM8350_ARA_OFF 0
  156. #define WM8350_ARA_ON 1
  157. #define WM8350_SPI_CFG_CMOS 0
  158. #define WM8350_SPI_CFG_OD 1
  159. #define WM8350_SPI_4WIRE_3WIRE 0
  160. #define WM8350_SPI_4WIRE_4WIRE 1
  161. #define WM8350_SPI_3WIRE_I2C 0
  162. #define WM8350_SPI_3WIRE_SPI 1
  163. /*
  164. * R8 (0x08) - Power mgmt (1)
  165. */
  166. #define WM8350_CODEC_ISEL_MASK 0xC000
  167. #define WM8350_VBUFEN 0x2000
  168. #define WM8350_OUTPUT_DRAIN_EN 0x0400
  169. #define WM8350_MIC_DET_ENA 0x0100
  170. #define WM8350_BIASEN 0x0020
  171. #define WM8350_MICBEN 0x0010
  172. #define WM8350_VMIDEN 0x0004
  173. #define WM8350_VMID_MASK 0x0003
  174. #define WM8350_VMID_SHIFT 0
  175. /*
  176. * R9 (0x09) - Power mgmt (2)
  177. */
  178. #define WM8350_IN3R_ENA 0x0800
  179. #define WM8350_IN3L_ENA 0x0400
  180. #define WM8350_INR_ENA 0x0200
  181. #define WM8350_INL_ENA 0x0100
  182. #define WM8350_MIXINR_ENA 0x0080
  183. #define WM8350_MIXINL_ENA 0x0040
  184. #define WM8350_OUT4_ENA 0x0020
  185. #define WM8350_OUT3_ENA 0x0010
  186. #define WM8350_MIXOUTR_ENA 0x0002
  187. #define WM8350_MIXOUTL_ENA 0x0001
  188. /*
  189. * R10 (0x0A) - Power mgmt (3)
  190. */
  191. #define WM8350_IN3R_TO_OUT2R 0x0080
  192. #define WM8350_OUT2R_ENA 0x0008
  193. #define WM8350_OUT2L_ENA 0x0004
  194. #define WM8350_OUT1R_ENA 0x0002
  195. #define WM8350_OUT1L_ENA 0x0001
  196. /*
  197. * R11 (0x0B) - Power mgmt (4)
  198. */
  199. #define WM8350_SYSCLK_ENA 0x4000
  200. #define WM8350_ADC_HPF_ENA 0x2000
  201. #define WM8350_FLL_ENA 0x0800
  202. #define WM8350_FLL_OSC_ENA 0x0400
  203. #define WM8350_TOCLK_ENA 0x0100
  204. #define WM8350_DACR_ENA 0x0020
  205. #define WM8350_DACL_ENA 0x0010
  206. #define WM8350_ADCR_ENA 0x0008
  207. #define WM8350_ADCL_ENA 0x0004
  208. /*
  209. * R12 (0x0C) - Power mgmt (5)
  210. */
  211. #define WM8350_CODEC_ENA 0x1000
  212. #define WM8350_RTC_TICK_ENA 0x0800
  213. #define WM8350_OSC32K_ENA 0x0400
  214. #define WM8350_CHG_ENA 0x0200
  215. #define WM8350_ACC_DET_ENA 0x0100
  216. #define WM8350_AUXADC_ENA 0x0080
  217. #define WM8350_DCMP4_ENA 0x0008
  218. #define WM8350_DCMP3_ENA 0x0004
  219. #define WM8350_DCMP2_ENA 0x0002
  220. #define WM8350_DCMP1_ENA 0x0001
  221. /*
  222. * R13 (0x0D) - Power mgmt (6)
  223. */
  224. #define WM8350_LS_ENA 0x8000
  225. #define WM8350_LDO4_ENA 0x0800
  226. #define WM8350_LDO3_ENA 0x0400
  227. #define WM8350_LDO2_ENA 0x0200
  228. #define WM8350_LDO1_ENA 0x0100
  229. #define WM8350_DC6_ENA 0x0020
  230. #define WM8350_DC5_ENA 0x0010
  231. #define WM8350_DC4_ENA 0x0008
  232. #define WM8350_DC3_ENA 0x0004
  233. #define WM8350_DC2_ENA 0x0002
  234. #define WM8350_DC1_ENA 0x0001
  235. /*
  236. * R14 (0x0E) - Power mgmt (7)
  237. */
  238. #define WM8350_CS2_ENA 0x0002
  239. #define WM8350_CS1_ENA 0x0001
  240. /*
  241. * R24 (0x18) - System Interrupts
  242. */
  243. #define WM8350_OC_INT 0x2000
  244. #define WM8350_UV_INT 0x1000
  245. #define WM8350_PUTO_INT 0x0800
  246. #define WM8350_CS_INT 0x0200
  247. #define WM8350_EXT_INT 0x0100
  248. #define WM8350_CODEC_INT 0x0080
  249. #define WM8350_GP_INT 0x0040
  250. #define WM8350_AUXADC_INT 0x0020
  251. #define WM8350_RTC_INT 0x0010
  252. #define WM8350_SYS_INT 0x0008
  253. #define WM8350_CHG_INT 0x0004
  254. #define WM8350_USB_INT 0x0002
  255. #define WM8350_WKUP_INT 0x0001
  256. /*
  257. * R25 (0x19) - Interrupt Status 1
  258. */
  259. #define WM8350_CHG_BAT_HOT_EINT 0x8000
  260. #define WM8350_CHG_BAT_COLD_EINT 0x4000
  261. #define WM8350_CHG_BAT_FAIL_EINT 0x2000
  262. #define WM8350_CHG_TO_EINT 0x1000
  263. #define WM8350_CHG_END_EINT 0x0800
  264. #define WM8350_CHG_START_EINT 0x0400
  265. #define WM8350_CHG_FAST_RDY_EINT 0x0200
  266. #define WM8350_RTC_PER_EINT 0x0080
  267. #define WM8350_RTC_SEC_EINT 0x0040
  268. #define WM8350_RTC_ALM_EINT 0x0020
  269. #define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004
  270. #define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002
  271. #define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001
  272. /*
  273. * R26 (0x1A) - Interrupt Status 2
  274. */
  275. #define WM8350_CS1_EINT 0x2000
  276. #define WM8350_CS2_EINT 0x1000
  277. #define WM8350_USB_LIMIT_EINT 0x0400
  278. #define WM8350_AUXADC_DATARDY_EINT 0x0100
  279. #define WM8350_AUXADC_DCOMP4_EINT 0x0080
  280. #define WM8350_AUXADC_DCOMP3_EINT 0x0040
  281. #define WM8350_AUXADC_DCOMP2_EINT 0x0020
  282. #define WM8350_AUXADC_DCOMP1_EINT 0x0010
  283. #define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008
  284. #define WM8350_SYS_CHIP_GT115_EINT 0x0004
  285. #define WM8350_SYS_CHIP_GT140_EINT 0x0002
  286. #define WM8350_SYS_WDOG_TO_EINT 0x0001
  287. /*
  288. * R27 (0x1B) - Power Up Interrupt Status
  289. */
  290. #define WM8350_PUTO_LDO4_EINT 0x0800
  291. #define WM8350_PUTO_LDO3_EINT 0x0400
  292. #define WM8350_PUTO_LDO2_EINT 0x0200
  293. #define WM8350_PUTO_LDO1_EINT 0x0100
  294. #define WM8350_PUTO_DC6_EINT 0x0020
  295. #define WM8350_PUTO_DC5_EINT 0x0010
  296. #define WM8350_PUTO_DC4_EINT 0x0008
  297. #define WM8350_PUTO_DC3_EINT 0x0004
  298. #define WM8350_PUTO_DC2_EINT 0x0002
  299. #define WM8350_PUTO_DC1_EINT 0x0001
  300. /*
  301. * R28 (0x1C) - Under Voltage Interrupt status
  302. */
  303. #define WM8350_UV_LDO4_EINT 0x0800
  304. #define WM8350_UV_LDO3_EINT 0x0400
  305. #define WM8350_UV_LDO2_EINT 0x0200
  306. #define WM8350_UV_LDO1_EINT 0x0100
  307. #define WM8350_UV_DC6_EINT 0x0020
  308. #define WM8350_UV_DC5_EINT 0x0010
  309. #define WM8350_UV_DC4_EINT 0x0008
  310. #define WM8350_UV_DC3_EINT 0x0004
  311. #define WM8350_UV_DC2_EINT 0x0002
  312. #define WM8350_UV_DC1_EINT 0x0001
  313. /*
  314. * R29 (0x1D) - Over Current Interrupt status
  315. */
  316. #define WM8350_OC_LS_EINT 0x8000
  317. /*
  318. * R30 (0x1E) - GPIO Interrupt Status
  319. */
  320. #define WM8350_GP12_EINT 0x1000
  321. #define WM8350_GP11_EINT 0x0800
  322. #define WM8350_GP10_EINT 0x0400
  323. #define WM8350_GP9_EINT 0x0200
  324. #define WM8350_GP8_EINT 0x0100
  325. #define WM8350_GP7_EINT 0x0080
  326. #define WM8350_GP6_EINT 0x0040
  327. #define WM8350_GP5_EINT 0x0020
  328. #define WM8350_GP4_EINT 0x0010
  329. #define WM8350_GP3_EINT 0x0008
  330. #define WM8350_GP2_EINT 0x0004
  331. #define WM8350_GP1_EINT 0x0002
  332. #define WM8350_GP0_EINT 0x0001
  333. /*
  334. * R31 (0x1F) - Comparator Interrupt Status
  335. */
  336. #define WM8350_EXT_USB_FB_EINT 0x8000
  337. #define WM8350_EXT_WALL_FB_EINT 0x4000
  338. #define WM8350_EXT_BAT_FB_EINT 0x2000
  339. #define WM8350_CODEC_JCK_DET_L_EINT 0x0800
  340. #define WM8350_CODEC_JCK_DET_R_EINT 0x0400
  341. #define WM8350_CODEC_MICSCD_EINT 0x0200
  342. #define WM8350_CODEC_MICD_EINT 0x0100
  343. #define WM8350_WKUP_OFF_STATE_EINT 0x0040
  344. #define WM8350_WKUP_HIB_STATE_EINT 0x0020
  345. #define WM8350_WKUP_CONV_FAULT_EINT 0x0010
  346. #define WM8350_WKUP_WDOG_RST_EINT 0x0008
  347. #define WM8350_WKUP_GP_PWR_ON_EINT 0x0004
  348. #define WM8350_WKUP_ONKEY_EINT 0x0002
  349. #define WM8350_WKUP_GP_WAKEUP_EINT 0x0001
  350. /*
  351. * R32 (0x20) - System Interrupts Mask
  352. */
  353. #define WM8350_IM_OC_INT 0x2000
  354. #define WM8350_IM_UV_INT 0x1000
  355. #define WM8350_IM_PUTO_INT 0x0800
  356. #define WM8350_IM_SPARE_INT 0x0400
  357. #define WM8350_IM_CS_INT 0x0200
  358. #define WM8350_IM_EXT_INT 0x0100
  359. #define WM8350_IM_CODEC_INT 0x0080
  360. #define WM8350_IM_GP_INT 0x0040
  361. #define WM8350_IM_AUXADC_INT 0x0020
  362. #define WM8350_IM_RTC_INT 0x0010
  363. #define WM8350_IM_SYS_INT 0x0008
  364. #define WM8350_IM_CHG_INT 0x0004
  365. #define WM8350_IM_USB_INT 0x0002
  366. #define WM8350_IM_WKUP_INT 0x0001
  367. /*
  368. * R33 (0x21) - Interrupt Status 1 Mask
  369. */
  370. #define WM8350_IM_CHG_BAT_HOT_EINT 0x8000
  371. #define WM8350_IM_CHG_BAT_COLD_EINT 0x4000
  372. #define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000
  373. #define WM8350_IM_CHG_TO_EINT 0x1000
  374. #define WM8350_IM_CHG_END_EINT 0x0800
  375. #define WM8350_IM_CHG_START_EINT 0x0400
  376. #define WM8350_IM_CHG_FAST_RDY_EINT 0x0200
  377. #define WM8350_IM_RTC_PER_EINT 0x0080
  378. #define WM8350_IM_RTC_SEC_EINT 0x0040
  379. #define WM8350_IM_RTC_ALM_EINT 0x0020
  380. #define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004
  381. #define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002
  382. #define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001
  383. /*
  384. * R34 (0x22) - Interrupt Status 2 Mask
  385. */
  386. #define WM8350_IM_SPARE2_EINT 0x8000
  387. #define WM8350_IM_SPARE1_EINT 0x4000
  388. #define WM8350_IM_CS1_EINT 0x2000
  389. #define WM8350_IM_CS2_EINT 0x1000
  390. #define WM8350_IM_USB_LIMIT_EINT 0x0400
  391. #define WM8350_IM_AUXADC_DATARDY_EINT 0x0100
  392. #define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080
  393. #define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040
  394. #define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020
  395. #define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010
  396. #define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008
  397. #define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004
  398. #define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002
  399. #define WM8350_IM_SYS_WDOG_TO_EINT 0x0001
  400. /*
  401. * R35 (0x23) - Power Up Interrupt Status Mask
  402. */
  403. #define WM8350_IM_PUTO_LDO4_EINT 0x0800
  404. #define WM8350_IM_PUTO_LDO3_EINT 0x0400
  405. #define WM8350_IM_PUTO_LDO2_EINT 0x0200
  406. #define WM8350_IM_PUTO_LDO1_EINT 0x0100
  407. #define WM8350_IM_PUTO_DC6_EINT 0x0020
  408. #define WM8350_IM_PUTO_DC5_EINT 0x0010
  409. #define WM8350_IM_PUTO_DC4_EINT 0x0008
  410. #define WM8350_IM_PUTO_DC3_EINT 0x0004
  411. #define WM8350_IM_PUTO_DC2_EINT 0x0002
  412. #define WM8350_IM_PUTO_DC1_EINT 0x0001
  413. /*
  414. * R36 (0x24) - Under Voltage Interrupt status Mask
  415. */
  416. #define WM8350_IM_UV_LDO4_EINT 0x0800
  417. #define WM8350_IM_UV_LDO3_EINT 0x0400
  418. #define WM8350_IM_UV_LDO2_EINT 0x0200
  419. #define WM8350_IM_UV_LDO1_EINT 0x0100
  420. #define WM8350_IM_UV_DC6_EINT 0x0020
  421. #define WM8350_IM_UV_DC5_EINT 0x0010
  422. #define WM8350_IM_UV_DC4_EINT 0x0008
  423. #define WM8350_IM_UV_DC3_EINT 0x0004
  424. #define WM8350_IM_UV_DC2_EINT 0x0002
  425. #define WM8350_IM_UV_DC1_EINT 0x0001
  426. /*
  427. * R37 (0x25) - Over Current Interrupt status Mask
  428. */
  429. #define WM8350_IM_OC_LS_EINT 0x8000
  430. /*
  431. * R38 (0x26) - GPIO Interrupt Status Mask
  432. */
  433. #define WM8350_IM_GP12_EINT 0x1000
  434. #define WM8350_IM_GP11_EINT 0x0800
  435. #define WM8350_IM_GP10_EINT 0x0400
  436. #define WM8350_IM_GP9_EINT 0x0200
  437. #define WM8350_IM_GP8_EINT 0x0100
  438. #define WM8350_IM_GP7_EINT 0x0080
  439. #define WM8350_IM_GP6_EINT 0x0040
  440. #define WM8350_IM_GP5_EINT 0x0020
  441. #define WM8350_IM_GP4_EINT 0x0010
  442. #define WM8350_IM_GP3_EINT 0x0008
  443. #define WM8350_IM_GP2_EINT 0x0004
  444. #define WM8350_IM_GP1_EINT 0x0002
  445. #define WM8350_IM_GP0_EINT 0x0001
  446. /*
  447. * R39 (0x27) - Comparator Interrupt Status Mask
  448. */
  449. #define WM8350_IM_EXT_USB_FB_EINT 0x8000
  450. #define WM8350_IM_EXT_WALL_FB_EINT 0x4000
  451. #define WM8350_IM_EXT_BAT_FB_EINT 0x2000
  452. #define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800
  453. #define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400
  454. #define WM8350_IM_CODEC_MICSCD_EINT 0x0200
  455. #define WM8350_IM_CODEC_MICD_EINT 0x0100
  456. #define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040
  457. #define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020
  458. #define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010
  459. #define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008
  460. #define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004
  461. #define WM8350_IM_WKUP_ONKEY_EINT 0x0002
  462. #define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001
  463. /*
  464. * R220 (0xDC) - RAM BIST 1
  465. */
  466. #define WM8350_READ_STATUS 0x0800
  467. #define WM8350_TSTRAM_CLK 0x0100
  468. #define WM8350_TSTRAM_CLK_ENA 0x0080
  469. #define WM8350_STARTSEQ 0x0040
  470. #define WM8350_READ_SRC 0x0020
  471. #define WM8350_COUNT_DIR 0x0010
  472. #define WM8350_TSTRAM_MODE_MASK 0x000E
  473. #define WM8350_TSTRAM_ENA 0x0001
  474. /*
  475. * R225 (0xE1) - DCDC/LDO status
  476. */
  477. #define WM8350_LS_STS 0x8000
  478. #define WM8350_LDO4_STS 0x0800
  479. #define WM8350_LDO3_STS 0x0400
  480. #define WM8350_LDO2_STS 0x0200
  481. #define WM8350_LDO1_STS 0x0100
  482. #define WM8350_DC6_STS 0x0020
  483. #define WM8350_DC5_STS 0x0010
  484. #define WM8350_DC4_STS 0x0008
  485. #define WM8350_DC3_STS 0x0004
  486. #define WM8350_DC2_STS 0x0002
  487. #define WM8350_DC1_STS 0x0001
  488. /*
  489. * R226 (0xE2) - Charger status
  490. */
  491. #define WM8350_CHG_BATT_HOT_OVRDE 0x8000
  492. #define WM8350_CHG_BATT_COLD_OVRDE 0x4000
  493. /*
  494. * R227 (0xE3) - Misc Overrides
  495. */
  496. #define WM8350_USB_LIMIT_OVRDE 0x0400
  497. /*
  498. * R227 (0xE7) - Comparator Overrides
  499. */
  500. #define WM8350_USB_FB_OVRDE 0x8000
  501. #define WM8350_WALL_FB_OVRDE 0x4000
  502. #define WM8350_BATT_FB_OVRDE 0x2000
  503. /*
  504. * R233 (0xE9) - State Machinine Status
  505. */
  506. #define WM8350_USB_SM_MASK 0x0700
  507. #define WM8350_USB_SM_SHIFT 8
  508. #define WM8350_USB_SM_100_SLV 1
  509. #define WM8350_USB_SM_500_SLV 5
  510. #define WM8350_USB_SM_STDBY_SLV 7
  511. /* WM8350 wake up conditions */
  512. #define WM8350_IRQ_WKUP_OFF_STATE 43
  513. #define WM8350_IRQ_WKUP_HIB_STATE 44
  514. #define WM8350_IRQ_WKUP_CONV_FAULT 45
  515. #define WM8350_IRQ_WKUP_WDOG_RST 46
  516. #define WM8350_IRQ_WKUP_GP_PWR_ON 47
  517. #define WM8350_IRQ_WKUP_ONKEY 48
  518. #define WM8350_IRQ_WKUP_GP_WAKEUP 49
  519. /* wm8350 chip revisions */
  520. #define WM8350_REV_E 0x4
  521. #define WM8350_REV_F 0x5
  522. #define WM8350_REV_G 0x6
  523. #define WM8350_REV_H 0x7
  524. #define WM8350_NUM_IRQ 63
  525. #define WM8350_NUM_IRQ_REGS 7
  526. struct wm8350_reg_access {
  527. u16 readable; /* Mask of readable bits */
  528. u16 writable; /* Mask of writable bits */
  529. u16 vol; /* Mask of volatile bits */
  530. };
  531. extern const struct wm8350_reg_access wm8350_reg_io_map[];
  532. extern const u16 wm8350_mode0_defaults[];
  533. extern const u16 wm8350_mode1_defaults[];
  534. extern const u16 wm8350_mode2_defaults[];
  535. extern const u16 wm8350_mode3_defaults[];
  536. extern const u16 wm8351_mode0_defaults[];
  537. extern const u16 wm8351_mode1_defaults[];
  538. extern const u16 wm8351_mode2_defaults[];
  539. extern const u16 wm8351_mode3_defaults[];
  540. extern const u16 wm8352_mode0_defaults[];
  541. extern const u16 wm8352_mode1_defaults[];
  542. extern const u16 wm8352_mode2_defaults[];
  543. extern const u16 wm8352_mode3_defaults[];
  544. struct wm8350;
  545. struct regmap;
  546. struct wm8350_hwmon {
  547. struct platform_device *pdev;
  548. struct device *classdev;
  549. };
  550. struct wm8350 {
  551. struct device *dev;
  552. /* device IO */
  553. struct regmap *regmap;
  554. u16 *reg_cache;
  555. struct mutex auxadc_mutex;
  556. struct completion auxadc_done;
  557. /* Interrupt handling */
  558. struct mutex irq_lock;
  559. int chip_irq;
  560. int irq_base;
  561. u16 irq_masks[WM8350_NUM_IRQ_REGS];
  562. /* Client devices */
  563. struct wm8350_codec codec;
  564. struct wm8350_gpio gpio;
  565. struct wm8350_hwmon hwmon;
  566. struct wm8350_pmic pmic;
  567. struct wm8350_power power;
  568. struct wm8350_rtc rtc;
  569. struct wm8350_wdt wdt;
  570. };
  571. /**
  572. * Data to be supplied by the platform to initialise the WM8350.
  573. *
  574. * @init: Function called during driver initialisation. Should be
  575. * used by the platform to configure GPIO functions and similar.
  576. * @irq_high: Set if WM8350 IRQ is active high.
  577. * @irq_base: Base IRQ for genirq (not currently used).
  578. * @gpio_base: Base for gpiolib.
  579. */
  580. struct wm8350_platform_data {
  581. int (*init)(struct wm8350 *wm8350);
  582. int irq_high;
  583. int irq_base;
  584. int gpio_base;
  585. };
  586. /*
  587. * WM8350 device initialisation and exit.
  588. */
  589. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  590. struct wm8350_platform_data *pdata);
  591. void wm8350_device_exit(struct wm8350 *wm8350);
  592. /*
  593. * WM8350 device IO
  594. */
  595. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
  596. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
  597. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
  598. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
  599. int wm8350_reg_lock(struct wm8350 *wm8350);
  600. int wm8350_reg_unlock(struct wm8350 *wm8350);
  601. int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
  602. int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
  603. /*
  604. * WM8350 internal interrupts
  605. */
  606. static inline int wm8350_register_irq(struct wm8350 *wm8350, int irq,
  607. irq_handler_t handler,
  608. unsigned long flags,
  609. const char *name, void *data)
  610. {
  611. if (!wm8350->irq_base)
  612. return -ENODEV;
  613. return request_threaded_irq(irq + wm8350->irq_base, NULL,
  614. handler, flags, name, data);
  615. }
  616. static inline void wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data)
  617. {
  618. free_irq(irq + wm8350->irq_base, data);
  619. }
  620. static inline void wm8350_mask_irq(struct wm8350 *wm8350, int irq)
  621. {
  622. disable_irq(irq + wm8350->irq_base);
  623. }
  624. static inline void wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
  625. {
  626. enable_irq(irq + wm8350->irq_base);
  627. }
  628. int wm8350_irq_init(struct wm8350 *wm8350, int irq,
  629. struct wm8350_platform_data *pdata);
  630. int wm8350_irq_exit(struct wm8350 *wm8350);
  631. #endif