i2c-imx.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713
  1. /*
  2. * Copyright (C) 2002 Motorola GSG-China
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version 2
  7. * of the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
  17. * USA.
  18. *
  19. * Author:
  20. * Darius Augulis, Teltonika Inc.
  21. *
  22. * Desc.:
  23. * Implementation of I2C Adapter/Algorithm Driver
  24. * for I2C Bus integrated in Freescale i.MX/MXC processors
  25. *
  26. * Derived from Motorola GSG China I2C example driver
  27. *
  28. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  29. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  30. * Copyright (C) 2007 RightHand Technologies, Inc.
  31. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  32. *
  33. * Copyright 2013 Freescale Semiconductor, Inc.
  34. *
  35. */
  36. /** Includes *******************************************************************
  37. *******************************************************************************/
  38. #include <linux/init.h>
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/errno.h>
  42. #include <linux/err.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/delay.h>
  45. #include <linux/i2c.h>
  46. #include <linux/io.h>
  47. #include <linux/sched.h>
  48. #include <linux/platform_device.h>
  49. #include <linux/clk.h>
  50. #include <linux/slab.h>
  51. #include <linux/of.h>
  52. #include <linux/of_device.h>
  53. #include <linux/of_i2c.h>
  54. #include <linux/platform_data/i2c-imx.h>
  55. /** Defines ********************************************************************
  56. *******************************************************************************/
  57. /* This will be the driver name the kernel reports */
  58. #define DRIVER_NAME "imx-i2c"
  59. /* Default value */
  60. #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
  61. /* IMX I2C registers:
  62. * the I2C register offset is different between SoCs,
  63. * to provid support for all these chips, split the
  64. * register offset into a fixed base address and a
  65. * variable shift value, then the full register offset
  66. * will be calculated by
  67. * reg_off = ( reg_base_addr << reg_shift)
  68. */
  69. #define IMX_I2C_IADR 0x00 /* i2c slave address */
  70. #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
  71. #define IMX_I2C_I2CR 0x02 /* i2c control */
  72. #define IMX_I2C_I2SR 0x03 /* i2c status */
  73. #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
  74. #define IMX_I2C_REGSHIFT 2
  75. /* Bits of IMX I2C registers */
  76. #define I2SR_RXAK 0x01
  77. #define I2SR_IIF 0x02
  78. #define I2SR_SRW 0x04
  79. #define I2SR_IAL 0x10
  80. #define I2SR_IBB 0x20
  81. #define I2SR_IAAS 0x40
  82. #define I2SR_ICF 0x80
  83. #define I2CR_RSTA 0x04
  84. #define I2CR_TXAK 0x08
  85. #define I2CR_MTX 0x10
  86. #define I2CR_MSTA 0x20
  87. #define I2CR_IIEN 0x40
  88. #define I2CR_IEN 0x80
  89. /* register bits different operating codes definition:
  90. * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  91. * - write zero to clear(w0c) INT flag on i.MX,
  92. * - but write one to clear(w1c) INT flag on Vybrid.
  93. * 2) I2CR: I2C module enable operation also differ between SoCs:
  94. * - set I2CR_IEN bit enable the module on i.MX,
  95. * - but clear I2CR_IEN bit enable the module on Vybrid.
  96. */
  97. #define I2SR_CLR_OPCODE_W0C 0x0
  98. #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
  99. #define I2CR_IEN_OPCODE_0 0x0
  100. #define I2CR_IEN_OPCODE_1 I2CR_IEN
  101. /** Variables ******************************************************************
  102. *******************************************************************************/
  103. /*
  104. * sorted list of clock divider, register value pairs
  105. * taken from table 26-5, p.26-9, Freescale i.MX
  106. * Integrated Portable System Processor Reference Manual
  107. * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
  108. *
  109. * Duplicated divider values removed from list
  110. */
  111. struct imx_i2c_clk_pair {
  112. u16 div;
  113. u16 val;
  114. };
  115. static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
  116. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  117. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  118. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  119. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  120. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  121. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  122. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  123. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  124. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  125. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  126. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  127. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  128. { 3072, 0x1E }, { 3840, 0x1F }
  129. };
  130. enum imx_i2c_type {
  131. IMX1_I2C,
  132. IMX21_I2C,
  133. };
  134. struct imx_i2c_hwdata {
  135. enum imx_i2c_type devtype;
  136. unsigned regshift;
  137. struct imx_i2c_clk_pair *clk_div;
  138. unsigned ndivs;
  139. unsigned i2sr_clr_opcode;
  140. unsigned i2cr_ien_opcode;
  141. };
  142. struct imx_i2c_struct {
  143. struct i2c_adapter adapter;
  144. struct clk *clk;
  145. void __iomem *base;
  146. wait_queue_head_t queue;
  147. unsigned long i2csr;
  148. unsigned int disable_delay;
  149. int stopped;
  150. unsigned int ifdr; /* IMX_I2C_IFDR */
  151. const struct imx_i2c_hwdata *hwdata;
  152. };
  153. static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
  154. .devtype = IMX1_I2C,
  155. .regshift = IMX_I2C_REGSHIFT,
  156. .clk_div = imx_i2c_clk_div,
  157. .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
  158. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
  159. .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
  160. };
  161. static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
  162. .devtype = IMX21_I2C,
  163. .regshift = IMX_I2C_REGSHIFT,
  164. .clk_div = imx_i2c_clk_div,
  165. .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
  166. .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
  167. .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
  168. };
  169. static struct platform_device_id imx_i2c_devtype[] = {
  170. {
  171. .name = "imx1-i2c",
  172. .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
  173. }, {
  174. .name = "imx21-i2c",
  175. .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
  176. }, {
  177. /* sentinel */
  178. }
  179. };
  180. MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
  181. static const struct of_device_id i2c_imx_dt_ids[] = {
  182. { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
  183. { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
  184. { /* sentinel */ }
  185. };
  186. MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
  187. static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
  188. {
  189. return i2c_imx->hwdata->devtype == IMX1_I2C;
  190. }
  191. static inline void imx_i2c_write_reg(unsigned int val,
  192. struct imx_i2c_struct *i2c_imx, unsigned int reg)
  193. {
  194. writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
  195. }
  196. static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
  197. unsigned int reg)
  198. {
  199. return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
  200. }
  201. /** Functions for IMX I2C adapter driver ***************************************
  202. *******************************************************************************/
  203. static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
  204. {
  205. unsigned long orig_jiffies = jiffies;
  206. unsigned int temp;
  207. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  208. while (1) {
  209. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  210. if (for_busy && (temp & I2SR_IBB))
  211. break;
  212. if (!for_busy && !(temp & I2SR_IBB))
  213. break;
  214. if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
  215. dev_dbg(&i2c_imx->adapter.dev,
  216. "<%s> I2C bus is busy\n", __func__);
  217. return -ETIMEDOUT;
  218. }
  219. schedule();
  220. }
  221. return 0;
  222. }
  223. static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
  224. {
  225. wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
  226. if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
  227. dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
  228. return -ETIMEDOUT;
  229. }
  230. dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
  231. i2c_imx->i2csr = 0;
  232. return 0;
  233. }
  234. static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
  235. {
  236. if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
  237. dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
  238. return -EIO; /* No ACK */
  239. }
  240. dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
  241. return 0;
  242. }
  243. static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
  244. {
  245. unsigned int temp = 0;
  246. int result;
  247. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  248. clk_prepare_enable(i2c_imx->clk);
  249. imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
  250. /* Enable I2C controller */
  251. imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
  252. imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
  253. /* Wait controller to be stable */
  254. udelay(50);
  255. /* Start I2C transaction */
  256. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  257. temp |= I2CR_MSTA;
  258. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  259. result = i2c_imx_bus_busy(i2c_imx, 1);
  260. if (result)
  261. return result;
  262. i2c_imx->stopped = 0;
  263. temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
  264. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  265. return result;
  266. }
  267. static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
  268. {
  269. unsigned int temp = 0;
  270. if (!i2c_imx->stopped) {
  271. /* Stop I2C transaction */
  272. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  273. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  274. temp &= ~(I2CR_MSTA | I2CR_MTX);
  275. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  276. }
  277. if (is_imx1_i2c(i2c_imx)) {
  278. /*
  279. * This delay caused by an i.MXL hardware bug.
  280. * If no (or too short) delay, no "STOP" bit will be generated.
  281. */
  282. udelay(i2c_imx->disable_delay);
  283. }
  284. if (!i2c_imx->stopped) {
  285. i2c_imx_bus_busy(i2c_imx, 0);
  286. i2c_imx->stopped = 1;
  287. }
  288. /* Disable I2C controller */
  289. temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
  290. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  291. clk_disable_unprepare(i2c_imx->clk);
  292. }
  293. static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
  294. unsigned int rate)
  295. {
  296. struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
  297. unsigned int i2c_clk_rate;
  298. unsigned int div;
  299. int i;
  300. /* Divider value calculation */
  301. i2c_clk_rate = clk_get_rate(i2c_imx->clk);
  302. div = (i2c_clk_rate + rate - 1) / rate;
  303. if (div < i2c_clk_div[0].div)
  304. i = 0;
  305. else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
  306. i = i2c_imx->hwdata->ndivs - 1;
  307. else
  308. for (i = 0; i2c_clk_div[i].div < div; i++);
  309. /* Store divider value */
  310. i2c_imx->ifdr = i2c_clk_div[i].val;
  311. /*
  312. * There dummy delay is calculated.
  313. * It should be about one I2C clock period long.
  314. * This delay is used in I2C bus disable function
  315. * to fix chip hardware bug.
  316. */
  317. i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
  318. + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
  319. /* dev_dbg() can't be used, because adapter is not yet registered */
  320. #ifdef CONFIG_I2C_DEBUG_BUS
  321. dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
  322. __func__, i2c_clk_rate, div);
  323. dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
  324. __func__, i2c_clk_div[i].val, i2c_clk_div[i].div);
  325. #endif
  326. }
  327. static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
  328. {
  329. struct imx_i2c_struct *i2c_imx = dev_id;
  330. unsigned int temp;
  331. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  332. if (temp & I2SR_IIF) {
  333. /* save status register */
  334. i2c_imx->i2csr = temp;
  335. temp &= ~I2SR_IIF;
  336. temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
  337. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
  338. wake_up(&i2c_imx->queue);
  339. return IRQ_HANDLED;
  340. }
  341. return IRQ_NONE;
  342. }
  343. static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
  344. {
  345. int i, result;
  346. dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
  347. __func__, msgs->addr << 1);
  348. /* write slave address */
  349. imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
  350. result = i2c_imx_trx_complete(i2c_imx);
  351. if (result)
  352. return result;
  353. result = i2c_imx_acked(i2c_imx);
  354. if (result)
  355. return result;
  356. dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
  357. /* write data */
  358. for (i = 0; i < msgs->len; i++) {
  359. dev_dbg(&i2c_imx->adapter.dev,
  360. "<%s> write byte: B%d=0x%X\n",
  361. __func__, i, msgs->buf[i]);
  362. imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
  363. result = i2c_imx_trx_complete(i2c_imx);
  364. if (result)
  365. return result;
  366. result = i2c_imx_acked(i2c_imx);
  367. if (result)
  368. return result;
  369. }
  370. return 0;
  371. }
  372. static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
  373. {
  374. int i, result;
  375. unsigned int temp;
  376. dev_dbg(&i2c_imx->adapter.dev,
  377. "<%s> write slave address: addr=0x%x\n",
  378. __func__, (msgs->addr << 1) | 0x01);
  379. /* write slave address */
  380. imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
  381. result = i2c_imx_trx_complete(i2c_imx);
  382. if (result)
  383. return result;
  384. result = i2c_imx_acked(i2c_imx);
  385. if (result)
  386. return result;
  387. dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
  388. /* setup bus to read data */
  389. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  390. temp &= ~I2CR_MTX;
  391. if (msgs->len - 1)
  392. temp &= ~I2CR_TXAK;
  393. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  394. imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
  395. dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
  396. /* read data */
  397. for (i = 0; i < msgs->len; i++) {
  398. result = i2c_imx_trx_complete(i2c_imx);
  399. if (result)
  400. return result;
  401. if (i == (msgs->len - 1)) {
  402. /* It must generate STOP before read I2DR to prevent
  403. controller from generating another clock cycle */
  404. dev_dbg(&i2c_imx->adapter.dev,
  405. "<%s> clear MSTA\n", __func__);
  406. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  407. temp &= ~(I2CR_MSTA | I2CR_MTX);
  408. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  409. i2c_imx_bus_busy(i2c_imx, 0);
  410. i2c_imx->stopped = 1;
  411. } else if (i == (msgs->len - 2)) {
  412. dev_dbg(&i2c_imx->adapter.dev,
  413. "<%s> set TXAK\n", __func__);
  414. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  415. temp |= I2CR_TXAK;
  416. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  417. }
  418. msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
  419. dev_dbg(&i2c_imx->adapter.dev,
  420. "<%s> read byte: B%d=0x%X\n",
  421. __func__, i, msgs->buf[i]);
  422. }
  423. return 0;
  424. }
  425. static int i2c_imx_xfer(struct i2c_adapter *adapter,
  426. struct i2c_msg *msgs, int num)
  427. {
  428. unsigned int i, temp;
  429. int result;
  430. struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
  431. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  432. /* Start I2C transfer */
  433. result = i2c_imx_start(i2c_imx);
  434. if (result)
  435. goto fail0;
  436. /* read/write data */
  437. for (i = 0; i < num; i++) {
  438. if (i) {
  439. dev_dbg(&i2c_imx->adapter.dev,
  440. "<%s> repeated start\n", __func__);
  441. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  442. temp |= I2CR_RSTA;
  443. imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
  444. result = i2c_imx_bus_busy(i2c_imx, 1);
  445. if (result)
  446. goto fail0;
  447. }
  448. dev_dbg(&i2c_imx->adapter.dev,
  449. "<%s> transfer message: %d\n", __func__, i);
  450. /* write/read data */
  451. #ifdef CONFIG_I2C_DEBUG_BUS
  452. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
  453. dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
  454. "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
  455. (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
  456. (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
  457. (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
  458. temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
  459. dev_dbg(&i2c_imx->adapter.dev,
  460. "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
  461. "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
  462. (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
  463. (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
  464. (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
  465. (temp & I2SR_RXAK ? 1 : 0));
  466. #endif
  467. if (msgs[i].flags & I2C_M_RD)
  468. result = i2c_imx_read(i2c_imx, &msgs[i]);
  469. else
  470. result = i2c_imx_write(i2c_imx, &msgs[i]);
  471. if (result)
  472. goto fail0;
  473. }
  474. fail0:
  475. /* Stop I2C transfer */
  476. i2c_imx_stop(i2c_imx);
  477. dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
  478. (result < 0) ? "error" : "success msg",
  479. (result < 0) ? result : num);
  480. return (result < 0) ? result : num;
  481. }
  482. static u32 i2c_imx_func(struct i2c_adapter *adapter)
  483. {
  484. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  485. }
  486. static struct i2c_algorithm i2c_imx_algo = {
  487. .master_xfer = i2c_imx_xfer,
  488. .functionality = i2c_imx_func,
  489. };
  490. static int __init i2c_imx_probe(struct platform_device *pdev)
  491. {
  492. const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
  493. &pdev->dev);
  494. struct imx_i2c_struct *i2c_imx;
  495. struct resource *res;
  496. struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
  497. void __iomem *base;
  498. int irq, ret;
  499. u32 bitrate;
  500. dev_dbg(&pdev->dev, "<%s>\n", __func__);
  501. irq = platform_get_irq(pdev, 0);
  502. if (irq < 0) {
  503. dev_err(&pdev->dev, "can't get irq number\n");
  504. return -ENOENT;
  505. }
  506. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  507. base = devm_ioremap_resource(&pdev->dev, res);
  508. if (IS_ERR(base))
  509. return PTR_ERR(base);
  510. i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
  511. GFP_KERNEL);
  512. if (!i2c_imx) {
  513. dev_err(&pdev->dev, "can't allocate interface\n");
  514. return -ENOMEM;
  515. }
  516. if (of_id)
  517. i2c_imx->hwdata = of_id->data;
  518. else
  519. i2c_imx->hwdata = (struct imx_i2c_hwdata *)
  520. platform_get_device_id(pdev)->driver_data;
  521. /* Setup i2c_imx driver structure */
  522. strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
  523. i2c_imx->adapter.owner = THIS_MODULE;
  524. i2c_imx->adapter.algo = &i2c_imx_algo;
  525. i2c_imx->adapter.dev.parent = &pdev->dev;
  526. i2c_imx->adapter.nr = pdev->id;
  527. i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
  528. i2c_imx->base = base;
  529. /* Get I2C clock */
  530. i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
  531. if (IS_ERR(i2c_imx->clk)) {
  532. dev_err(&pdev->dev, "can't get I2C clock\n");
  533. return PTR_ERR(i2c_imx->clk);
  534. }
  535. ret = clk_prepare_enable(i2c_imx->clk);
  536. if (ret) {
  537. dev_err(&pdev->dev, "can't enable I2C clock\n");
  538. return ret;
  539. }
  540. /* Request IRQ */
  541. ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
  542. pdev->name, i2c_imx);
  543. if (ret) {
  544. dev_err(&pdev->dev, "can't claim irq %d\n", irq);
  545. return ret;
  546. }
  547. /* Init queue */
  548. init_waitqueue_head(&i2c_imx->queue);
  549. /* Set up adapter data */
  550. i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
  551. /* Set up clock divider */
  552. bitrate = IMX_I2C_BIT_RATE;
  553. ret = of_property_read_u32(pdev->dev.of_node,
  554. "clock-frequency", &bitrate);
  555. if (ret < 0 && pdata && pdata->bitrate)
  556. bitrate = pdata->bitrate;
  557. i2c_imx_set_clk(i2c_imx, bitrate);
  558. /* Set up chip registers to defaults */
  559. imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
  560. i2c_imx, IMX_I2C_I2CR);
  561. imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
  562. /* Add I2C adapter */
  563. ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
  564. if (ret < 0) {
  565. dev_err(&pdev->dev, "registration failed\n");
  566. return ret;
  567. }
  568. of_i2c_register_devices(&i2c_imx->adapter);
  569. /* Set up platform driver data */
  570. platform_set_drvdata(pdev, i2c_imx);
  571. clk_disable_unprepare(i2c_imx->clk);
  572. dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
  573. dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
  574. res->start, res->end);
  575. dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
  576. resource_size(res), res->start);
  577. dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
  578. i2c_imx->adapter.name);
  579. dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
  580. return 0; /* Return OK */
  581. }
  582. static int __exit i2c_imx_remove(struct platform_device *pdev)
  583. {
  584. struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
  585. /* remove adapter */
  586. dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
  587. i2c_del_adapter(&i2c_imx->adapter);
  588. /* setup chip registers to defaults */
  589. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
  590. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
  591. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
  592. imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
  593. return 0;
  594. }
  595. static struct platform_driver i2c_imx_driver = {
  596. .remove = __exit_p(i2c_imx_remove),
  597. .driver = {
  598. .name = DRIVER_NAME,
  599. .owner = THIS_MODULE,
  600. .of_match_table = i2c_imx_dt_ids,
  601. },
  602. .id_table = imx_i2c_devtype,
  603. };
  604. static int __init i2c_adap_imx_init(void)
  605. {
  606. return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
  607. }
  608. subsys_initcall(i2c_adap_imx_init);
  609. static void __exit i2c_adap_imx_exit(void)
  610. {
  611. platform_driver_unregister(&i2c_imx_driver);
  612. }
  613. module_exit(i2c_adap_imx_exit);
  614. MODULE_LICENSE("GPL");
  615. MODULE_AUTHOR("Darius Augulis");
  616. MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
  617. MODULE_ALIAS("platform:" DRIVER_NAME);