sa1100.c 23 KB

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  1. /*
  2. * linux/drivers/char/sa1100.c
  3. *
  4. * Driver for SA11x0 serial ports
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. *
  8. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $
  25. *
  26. */
  27. #include <linux/config.h>
  28. #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  29. #define SUPPORT_SYSRQ
  30. #endif
  31. #include <linux/module.h>
  32. #include <linux/ioport.h>
  33. #include <linux/init.h>
  34. #include <linux/console.h>
  35. #include <linux/sysrq.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/tty.h>
  38. #include <linux/tty_flip.h>
  39. #include <linux/serial_core.h>
  40. #include <linux/serial.h>
  41. #include <asm/io.h>
  42. #include <asm/irq.h>
  43. #include <asm/hardware.h>
  44. #include <asm/mach/serial_sa1100.h>
  45. /* We've been assigned a range on the "Low-density serial ports" major */
  46. #define SERIAL_SA1100_MAJOR 204
  47. #define MINOR_START 5
  48. #define NR_PORTS 3
  49. #define SA1100_ISR_PASS_LIMIT 256
  50. /*
  51. * Convert from ignore_status_mask or read_status_mask to UTSR[01]
  52. */
  53. #define SM_TO_UTSR0(x) ((x) & 0xff)
  54. #define SM_TO_UTSR1(x) ((x) >> 8)
  55. #define UTSR0_TO_SM(x) ((x))
  56. #define UTSR1_TO_SM(x) ((x) << 8)
  57. #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
  58. #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
  59. #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
  60. #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
  61. #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
  62. #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
  63. #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
  64. #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
  65. #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
  66. #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
  67. #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
  68. #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
  69. #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
  70. #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
  71. /*
  72. * This is the size of our serial port register set.
  73. */
  74. #define UART_PORT_SIZE 0x24
  75. /*
  76. * This determines how often we check the modem status signals
  77. * for any change. They generally aren't connected to an IRQ
  78. * so we have to poll them. We also check immediately before
  79. * filling the TX fifo incase CTS has been dropped.
  80. */
  81. #define MCTRL_TIMEOUT (250*HZ/1000)
  82. struct sa1100_port {
  83. struct uart_port port;
  84. struct timer_list timer;
  85. unsigned int old_status;
  86. };
  87. /*
  88. * Handle any change of modem status signal since we were last called.
  89. */
  90. static void sa1100_mctrl_check(struct sa1100_port *sport)
  91. {
  92. unsigned int status, changed;
  93. status = sport->port.ops->get_mctrl(&sport->port);
  94. changed = status ^ sport->old_status;
  95. if (changed == 0)
  96. return;
  97. sport->old_status = status;
  98. if (changed & TIOCM_RI)
  99. sport->port.icount.rng++;
  100. if (changed & TIOCM_DSR)
  101. sport->port.icount.dsr++;
  102. if (changed & TIOCM_CAR)
  103. uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
  104. if (changed & TIOCM_CTS)
  105. uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
  106. wake_up_interruptible(&sport->port.info->delta_msr_wait);
  107. }
  108. /*
  109. * This is our per-port timeout handler, for checking the
  110. * modem status signals.
  111. */
  112. static void sa1100_timeout(unsigned long data)
  113. {
  114. struct sa1100_port *sport = (struct sa1100_port *)data;
  115. unsigned long flags;
  116. if (sport->port.info) {
  117. spin_lock_irqsave(&sport->port.lock, flags);
  118. sa1100_mctrl_check(sport);
  119. spin_unlock_irqrestore(&sport->port.lock, flags);
  120. mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
  121. }
  122. }
  123. /*
  124. * interrupts disabled on entry
  125. */
  126. static void sa1100_stop_tx(struct uart_port *port)
  127. {
  128. struct sa1100_port *sport = (struct sa1100_port *)port;
  129. u32 utcr3;
  130. utcr3 = UART_GET_UTCR3(sport);
  131. UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
  132. sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
  133. }
  134. /*
  135. * port locked and interrupts disabled
  136. */
  137. static void sa1100_start_tx(struct uart_port *port)
  138. {
  139. struct sa1100_port *sport = (struct sa1100_port *)port;
  140. u32 utcr3;
  141. utcr3 = UART_GET_UTCR3(sport);
  142. sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
  143. UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
  144. }
  145. /*
  146. * Interrupts enabled
  147. */
  148. static void sa1100_stop_rx(struct uart_port *port)
  149. {
  150. struct sa1100_port *sport = (struct sa1100_port *)port;
  151. u32 utcr3;
  152. utcr3 = UART_GET_UTCR3(sport);
  153. UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
  154. }
  155. /*
  156. * Set the modem control timer to fire immediately.
  157. */
  158. static void sa1100_enable_ms(struct uart_port *port)
  159. {
  160. struct sa1100_port *sport = (struct sa1100_port *)port;
  161. mod_timer(&sport->timer, jiffies);
  162. }
  163. static void
  164. sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs)
  165. {
  166. struct tty_struct *tty = sport->port.info->tty;
  167. unsigned int status, ch, flg;
  168. status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
  169. UTSR0_TO_SM(UART_GET_UTSR0(sport));
  170. while (status & UTSR1_TO_SM(UTSR1_RNE)) {
  171. ch = UART_GET_CHAR(sport);
  172. if (tty->flip.count >= TTY_FLIPBUF_SIZE)
  173. goto ignore_char;
  174. sport->port.icount.rx++;
  175. flg = TTY_NORMAL;
  176. /*
  177. * note that the error handling code is
  178. * out of the main execution path
  179. */
  180. if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
  181. if (status & UTSR1_TO_SM(UTSR1_PRE))
  182. sport->port.icount.parity++;
  183. else if (status & UTSR1_TO_SM(UTSR1_FRE))
  184. sport->port.icount.frame++;
  185. if (status & UTSR1_TO_SM(UTSR1_ROR))
  186. sport->port.icount.overrun++;
  187. status &= sport->port.read_status_mask;
  188. if (status & UTSR1_TO_SM(UTSR1_PRE))
  189. flg = TTY_PARITY;
  190. else if (status & UTSR1_TO_SM(UTSR1_FRE))
  191. flg = TTY_FRAME;
  192. #ifdef SUPPORT_SYSRQ
  193. sport->port.sysrq = 0;
  194. #endif
  195. }
  196. if (uart_handle_sysrq_char(&sport->port, ch, regs))
  197. goto ignore_char;
  198. uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
  199. ignore_char:
  200. status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
  201. UTSR0_TO_SM(UART_GET_UTSR0(sport));
  202. }
  203. tty_flip_buffer_push(tty);
  204. }
  205. static void sa1100_tx_chars(struct sa1100_port *sport)
  206. {
  207. struct circ_buf *xmit = &sport->port.info->xmit;
  208. if (sport->port.x_char) {
  209. UART_PUT_CHAR(sport, sport->port.x_char);
  210. sport->port.icount.tx++;
  211. sport->port.x_char = 0;
  212. return;
  213. }
  214. /*
  215. * Check the modem control lines before
  216. * transmitting anything.
  217. */
  218. sa1100_mctrl_check(sport);
  219. if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
  220. sa1100_stop_tx(&sport->port);
  221. return;
  222. }
  223. /*
  224. * Tried using FIFO (not checking TNF) for fifo fill:
  225. * still had the '4 bytes repeated' problem.
  226. */
  227. while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
  228. UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
  229. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  230. sport->port.icount.tx++;
  231. if (uart_circ_empty(xmit))
  232. break;
  233. }
  234. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  235. uart_write_wakeup(&sport->port);
  236. if (uart_circ_empty(xmit))
  237. sa1100_stop_tx(&sport->port);
  238. }
  239. static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs)
  240. {
  241. struct sa1100_port *sport = dev_id;
  242. unsigned int status, pass_counter = 0;
  243. spin_lock(&sport->port.lock);
  244. status = UART_GET_UTSR0(sport);
  245. status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
  246. do {
  247. if (status & (UTSR0_RFS | UTSR0_RID)) {
  248. /* Clear the receiver idle bit, if set */
  249. if (status & UTSR0_RID)
  250. UART_PUT_UTSR0(sport, UTSR0_RID);
  251. sa1100_rx_chars(sport, regs);
  252. }
  253. /* Clear the relevant break bits */
  254. if (status & (UTSR0_RBB | UTSR0_REB))
  255. UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
  256. if (status & UTSR0_RBB)
  257. sport->port.icount.brk++;
  258. if (status & UTSR0_REB)
  259. uart_handle_break(&sport->port);
  260. if (status & UTSR0_TFS)
  261. sa1100_tx_chars(sport);
  262. if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
  263. break;
  264. status = UART_GET_UTSR0(sport);
  265. status &= SM_TO_UTSR0(sport->port.read_status_mask) |
  266. ~UTSR0_TFS;
  267. } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
  268. spin_unlock(&sport->port.lock);
  269. return IRQ_HANDLED;
  270. }
  271. /*
  272. * Return TIOCSER_TEMT when transmitter is not busy.
  273. */
  274. static unsigned int sa1100_tx_empty(struct uart_port *port)
  275. {
  276. struct sa1100_port *sport = (struct sa1100_port *)port;
  277. return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
  278. }
  279. static unsigned int sa1100_get_mctrl(struct uart_port *port)
  280. {
  281. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  282. }
  283. static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
  284. {
  285. }
  286. /*
  287. * Interrupts always disabled.
  288. */
  289. static void sa1100_break_ctl(struct uart_port *port, int break_state)
  290. {
  291. struct sa1100_port *sport = (struct sa1100_port *)port;
  292. unsigned long flags;
  293. unsigned int utcr3;
  294. spin_lock_irqsave(&sport->port.lock, flags);
  295. utcr3 = UART_GET_UTCR3(sport);
  296. if (break_state == -1)
  297. utcr3 |= UTCR3_BRK;
  298. else
  299. utcr3 &= ~UTCR3_BRK;
  300. UART_PUT_UTCR3(sport, utcr3);
  301. spin_unlock_irqrestore(&sport->port.lock, flags);
  302. }
  303. static int sa1100_startup(struct uart_port *port)
  304. {
  305. struct sa1100_port *sport = (struct sa1100_port *)port;
  306. int retval;
  307. /*
  308. * Allocate the IRQ
  309. */
  310. retval = request_irq(sport->port.irq, sa1100_int, 0,
  311. "sa11x0-uart", sport);
  312. if (retval)
  313. return retval;
  314. /*
  315. * Finally, clear and enable interrupts
  316. */
  317. UART_PUT_UTSR0(sport, -1);
  318. UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
  319. /*
  320. * Enable modem status interrupts
  321. */
  322. spin_lock_irq(&sport->port.lock);
  323. sa1100_enable_ms(&sport->port);
  324. spin_unlock_irq(&sport->port.lock);
  325. return 0;
  326. }
  327. static void sa1100_shutdown(struct uart_port *port)
  328. {
  329. struct sa1100_port *sport = (struct sa1100_port *)port;
  330. /*
  331. * Stop our timer.
  332. */
  333. del_timer_sync(&sport->timer);
  334. /*
  335. * Free the interrupt
  336. */
  337. free_irq(sport->port.irq, sport);
  338. /*
  339. * Disable all interrupts, port and break condition.
  340. */
  341. UART_PUT_UTCR3(sport, 0);
  342. }
  343. static void
  344. sa1100_set_termios(struct uart_port *port, struct termios *termios,
  345. struct termios *old)
  346. {
  347. struct sa1100_port *sport = (struct sa1100_port *)port;
  348. unsigned long flags;
  349. unsigned int utcr0, old_utcr3, baud, quot;
  350. unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
  351. /*
  352. * We only support CS7 and CS8.
  353. */
  354. while ((termios->c_cflag & CSIZE) != CS7 &&
  355. (termios->c_cflag & CSIZE) != CS8) {
  356. termios->c_cflag &= ~CSIZE;
  357. termios->c_cflag |= old_csize;
  358. old_csize = CS8;
  359. }
  360. if ((termios->c_cflag & CSIZE) == CS8)
  361. utcr0 = UTCR0_DSS;
  362. else
  363. utcr0 = 0;
  364. if (termios->c_cflag & CSTOPB)
  365. utcr0 |= UTCR0_SBS;
  366. if (termios->c_cflag & PARENB) {
  367. utcr0 |= UTCR0_PE;
  368. if (!(termios->c_cflag & PARODD))
  369. utcr0 |= UTCR0_OES;
  370. }
  371. /*
  372. * Ask the core to calculate the divisor for us.
  373. */
  374. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  375. quot = uart_get_divisor(port, baud);
  376. spin_lock_irqsave(&sport->port.lock, flags);
  377. sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
  378. sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
  379. if (termios->c_iflag & INPCK)
  380. sport->port.read_status_mask |=
  381. UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
  382. if (termios->c_iflag & (BRKINT | PARMRK))
  383. sport->port.read_status_mask |=
  384. UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
  385. /*
  386. * Characters to ignore
  387. */
  388. sport->port.ignore_status_mask = 0;
  389. if (termios->c_iflag & IGNPAR)
  390. sport->port.ignore_status_mask |=
  391. UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
  392. if (termios->c_iflag & IGNBRK) {
  393. sport->port.ignore_status_mask |=
  394. UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
  395. /*
  396. * If we're ignoring parity and break indicators,
  397. * ignore overruns too (for real raw support).
  398. */
  399. if (termios->c_iflag & IGNPAR)
  400. sport->port.ignore_status_mask |=
  401. UTSR1_TO_SM(UTSR1_ROR);
  402. }
  403. del_timer_sync(&sport->timer);
  404. /*
  405. * Update the per-port timeout.
  406. */
  407. uart_update_timeout(port, termios->c_cflag, baud);
  408. /*
  409. * disable interrupts and drain transmitter
  410. */
  411. old_utcr3 = UART_GET_UTCR3(sport);
  412. UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
  413. while (UART_GET_UTSR1(sport) & UTSR1_TBY)
  414. barrier();
  415. /* then, disable everything */
  416. UART_PUT_UTCR3(sport, 0);
  417. /* set the parity, stop bits and data size */
  418. UART_PUT_UTCR0(sport, utcr0);
  419. /* set the baud rate */
  420. quot -= 1;
  421. UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
  422. UART_PUT_UTCR2(sport, (quot & 0xff));
  423. UART_PUT_UTSR0(sport, -1);
  424. UART_PUT_UTCR3(sport, old_utcr3);
  425. if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
  426. sa1100_enable_ms(&sport->port);
  427. spin_unlock_irqrestore(&sport->port.lock, flags);
  428. }
  429. static const char *sa1100_type(struct uart_port *port)
  430. {
  431. struct sa1100_port *sport = (struct sa1100_port *)port;
  432. return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
  433. }
  434. /*
  435. * Release the memory region(s) being used by 'port'.
  436. */
  437. static void sa1100_release_port(struct uart_port *port)
  438. {
  439. struct sa1100_port *sport = (struct sa1100_port *)port;
  440. release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
  441. }
  442. /*
  443. * Request the memory region(s) being used by 'port'.
  444. */
  445. static int sa1100_request_port(struct uart_port *port)
  446. {
  447. struct sa1100_port *sport = (struct sa1100_port *)port;
  448. return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
  449. "sa11x0-uart") != NULL ? 0 : -EBUSY;
  450. }
  451. /*
  452. * Configure/autoconfigure the port.
  453. */
  454. static void sa1100_config_port(struct uart_port *port, int flags)
  455. {
  456. struct sa1100_port *sport = (struct sa1100_port *)port;
  457. if (flags & UART_CONFIG_TYPE &&
  458. sa1100_request_port(&sport->port) == 0)
  459. sport->port.type = PORT_SA1100;
  460. }
  461. /*
  462. * Verify the new serial_struct (for TIOCSSERIAL).
  463. * The only change we allow are to the flags and type, and
  464. * even then only between PORT_SA1100 and PORT_UNKNOWN
  465. */
  466. static int
  467. sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
  468. {
  469. struct sa1100_port *sport = (struct sa1100_port *)port;
  470. int ret = 0;
  471. if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
  472. ret = -EINVAL;
  473. if (sport->port.irq != ser->irq)
  474. ret = -EINVAL;
  475. if (ser->io_type != SERIAL_IO_MEM)
  476. ret = -EINVAL;
  477. if (sport->port.uartclk / 16 != ser->baud_base)
  478. ret = -EINVAL;
  479. if ((void *)sport->port.mapbase != ser->iomem_base)
  480. ret = -EINVAL;
  481. if (sport->port.iobase != ser->port)
  482. ret = -EINVAL;
  483. if (ser->hub6 != 0)
  484. ret = -EINVAL;
  485. return ret;
  486. }
  487. static struct uart_ops sa1100_pops = {
  488. .tx_empty = sa1100_tx_empty,
  489. .set_mctrl = sa1100_set_mctrl,
  490. .get_mctrl = sa1100_get_mctrl,
  491. .stop_tx = sa1100_stop_tx,
  492. .start_tx = sa1100_start_tx,
  493. .stop_rx = sa1100_stop_rx,
  494. .enable_ms = sa1100_enable_ms,
  495. .break_ctl = sa1100_break_ctl,
  496. .startup = sa1100_startup,
  497. .shutdown = sa1100_shutdown,
  498. .set_termios = sa1100_set_termios,
  499. .type = sa1100_type,
  500. .release_port = sa1100_release_port,
  501. .request_port = sa1100_request_port,
  502. .config_port = sa1100_config_port,
  503. .verify_port = sa1100_verify_port,
  504. };
  505. static struct sa1100_port sa1100_ports[NR_PORTS];
  506. /*
  507. * Setup the SA1100 serial ports. Note that we don't include the IrDA
  508. * port here since we have our own SIR/FIR driver (see drivers/net/irda)
  509. *
  510. * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
  511. * Which serial port this ends up being depends on the machine you're
  512. * running this kernel on. I'm not convinced that this is a good idea,
  513. * but that's the way it traditionally works.
  514. *
  515. * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
  516. * used here.
  517. */
  518. static void __init sa1100_init_ports(void)
  519. {
  520. static int first = 1;
  521. int i;
  522. if (!first)
  523. return;
  524. first = 0;
  525. for (i = 0; i < NR_PORTS; i++) {
  526. sa1100_ports[i].port.uartclk = 3686400;
  527. sa1100_ports[i].port.ops = &sa1100_pops;
  528. sa1100_ports[i].port.fifosize = 8;
  529. sa1100_ports[i].port.line = i;
  530. sa1100_ports[i].port.iotype = SERIAL_IO_MEM;
  531. init_timer(&sa1100_ports[i].timer);
  532. sa1100_ports[i].timer.function = sa1100_timeout;
  533. sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
  534. }
  535. /*
  536. * make transmit lines outputs, so that when the port
  537. * is closed, the output is in the MARK state.
  538. */
  539. PPDR |= PPC_TXD1 | PPC_TXD3;
  540. PPSR |= PPC_TXD1 | PPC_TXD3;
  541. }
  542. void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns)
  543. {
  544. if (fns->get_mctrl)
  545. sa1100_pops.get_mctrl = fns->get_mctrl;
  546. if (fns->set_mctrl)
  547. sa1100_pops.set_mctrl = fns->set_mctrl;
  548. sa1100_pops.pm = fns->pm;
  549. sa1100_pops.set_wake = fns->set_wake;
  550. }
  551. void __init sa1100_register_uart(int idx, int port)
  552. {
  553. if (idx >= NR_PORTS) {
  554. printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
  555. return;
  556. }
  557. switch (port) {
  558. case 1:
  559. sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
  560. sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
  561. sa1100_ports[idx].port.irq = IRQ_Ser1UART;
  562. sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
  563. break;
  564. case 2:
  565. sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
  566. sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
  567. sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
  568. sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
  569. break;
  570. case 3:
  571. sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
  572. sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
  573. sa1100_ports[idx].port.irq = IRQ_Ser3UART;
  574. sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
  575. break;
  576. default:
  577. printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port);
  578. }
  579. }
  580. #ifdef CONFIG_SERIAL_SA1100_CONSOLE
  581. /*
  582. * Interrupts are disabled on entering
  583. */
  584. static void
  585. sa1100_console_write(struct console *co, const char *s, unsigned int count)
  586. {
  587. struct sa1100_port *sport = &sa1100_ports[co->index];
  588. unsigned int old_utcr3, status, i;
  589. /*
  590. * First, save UTCR3 and then disable interrupts
  591. */
  592. old_utcr3 = UART_GET_UTCR3(sport);
  593. UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
  594. UTCR3_TXE);
  595. /*
  596. * Now, do each character
  597. */
  598. for (i = 0; i < count; i++) {
  599. do {
  600. status = UART_GET_UTSR1(sport);
  601. } while (!(status & UTSR1_TNF));
  602. UART_PUT_CHAR(sport, s[i]);
  603. if (s[i] == '\n') {
  604. do {
  605. status = UART_GET_UTSR1(sport);
  606. } while (!(status & UTSR1_TNF));
  607. UART_PUT_CHAR(sport, '\r');
  608. }
  609. }
  610. /*
  611. * Finally, wait for transmitter to become empty
  612. * and restore UTCR3
  613. */
  614. do {
  615. status = UART_GET_UTSR1(sport);
  616. } while (status & UTSR1_TBY);
  617. UART_PUT_UTCR3(sport, old_utcr3);
  618. }
  619. /*
  620. * If the port was already initialised (eg, by a boot loader),
  621. * try to determine the current setup.
  622. */
  623. static void __init
  624. sa1100_console_get_options(struct sa1100_port *sport, int *baud,
  625. int *parity, int *bits)
  626. {
  627. unsigned int utcr3;
  628. utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
  629. if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
  630. /* ok, the port was enabled */
  631. unsigned int utcr0, quot;
  632. utcr0 = UART_GET_UTCR0(sport);
  633. *parity = 'n';
  634. if (utcr0 & UTCR0_PE) {
  635. if (utcr0 & UTCR0_OES)
  636. *parity = 'e';
  637. else
  638. *parity = 'o';
  639. }
  640. if (utcr0 & UTCR0_DSS)
  641. *bits = 8;
  642. else
  643. *bits = 7;
  644. quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
  645. quot &= 0xfff;
  646. *baud = sport->port.uartclk / (16 * (quot + 1));
  647. }
  648. }
  649. static int __init
  650. sa1100_console_setup(struct console *co, char *options)
  651. {
  652. struct sa1100_port *sport;
  653. int baud = 9600;
  654. int bits = 8;
  655. int parity = 'n';
  656. int flow = 'n';
  657. /*
  658. * Check whether an invalid uart number has been specified, and
  659. * if so, search for the first available port that does have
  660. * console support.
  661. */
  662. if (co->index == -1 || co->index >= NR_PORTS)
  663. co->index = 0;
  664. sport = &sa1100_ports[co->index];
  665. if (options)
  666. uart_parse_options(options, &baud, &parity, &bits, &flow);
  667. else
  668. sa1100_console_get_options(sport, &baud, &parity, &bits);
  669. return uart_set_options(&sport->port, co, baud, parity, bits, flow);
  670. }
  671. static struct uart_driver sa1100_reg;
  672. static struct console sa1100_console = {
  673. .name = "ttySA",
  674. .write = sa1100_console_write,
  675. .device = uart_console_device,
  676. .setup = sa1100_console_setup,
  677. .flags = CON_PRINTBUFFER,
  678. .index = -1,
  679. .data = &sa1100_reg,
  680. };
  681. static int __init sa1100_rs_console_init(void)
  682. {
  683. sa1100_init_ports();
  684. register_console(&sa1100_console);
  685. return 0;
  686. }
  687. console_initcall(sa1100_rs_console_init);
  688. #define SA1100_CONSOLE &sa1100_console
  689. #else
  690. #define SA1100_CONSOLE NULL
  691. #endif
  692. static struct uart_driver sa1100_reg = {
  693. .owner = THIS_MODULE,
  694. .driver_name = "ttySA",
  695. .dev_name = "ttySA",
  696. .devfs_name = "ttySA",
  697. .major = SERIAL_SA1100_MAJOR,
  698. .minor = MINOR_START,
  699. .nr = NR_PORTS,
  700. .cons = SA1100_CONSOLE,
  701. };
  702. static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
  703. {
  704. struct sa1100_port *sport = platform_get_drvdata(dev);
  705. if (sport)
  706. uart_suspend_port(&sa1100_reg, &sport->port);
  707. return 0;
  708. }
  709. static int sa1100_serial_resume(struct platform_device *dev)
  710. {
  711. struct sa1100_port *sport = platform_get_drvdata(dev);
  712. if (sport)
  713. uart_resume_port(&sa1100_reg, &sport->port);
  714. return 0;
  715. }
  716. static int sa1100_serial_probe(struct platform_device *dev)
  717. {
  718. struct resource *res = dev->resource;
  719. int i;
  720. for (i = 0; i < dev->num_resources; i++, res++)
  721. if (res->flags & IORESOURCE_MEM)
  722. break;
  723. if (i < dev->num_resources) {
  724. for (i = 0; i < NR_PORTS; i++) {
  725. if (sa1100_ports[i].port.mapbase != res->start)
  726. continue;
  727. sa1100_ports[i].port.dev = &dev->dev;
  728. uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
  729. platform_set_drvdata(dev, &sa1100_ports[i]);
  730. break;
  731. }
  732. }
  733. return 0;
  734. }
  735. static int sa1100_serial_remove(struct platform_device *pdev)
  736. {
  737. struct sa1100_port *sport = platform_get_drvdata(pdev);
  738. platform_set_drvdata(pdev, NULL);
  739. if (sport)
  740. uart_remove_one_port(&sa1100_reg, &sport->port);
  741. return 0;
  742. }
  743. static struct platform_driver sa11x0_serial_driver = {
  744. .probe = sa1100_serial_probe,
  745. .remove = sa1100_serial_remove,
  746. .suspend = sa1100_serial_suspend,
  747. .resume = sa1100_serial_resume,
  748. .driver = {
  749. .name = "sa11x0-uart",
  750. },
  751. };
  752. static int __init sa1100_serial_init(void)
  753. {
  754. int ret;
  755. printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n");
  756. sa1100_init_ports();
  757. ret = uart_register_driver(&sa1100_reg);
  758. if (ret == 0) {
  759. ret = platform_driver_register(&sa11x0_serial_driver);
  760. if (ret)
  761. uart_unregister_driver(&sa1100_reg);
  762. }
  763. return ret;
  764. }
  765. static void __exit sa1100_serial_exit(void)
  766. {
  767. platform_driver_unregister(&sa11x0_serial_driver);
  768. uart_unregister_driver(&sa1100_reg);
  769. }
  770. module_init(sa1100_serial_init);
  771. module_exit(sa1100_serial_exit);
  772. MODULE_AUTHOR("Deep Blue Solutions Ltd");
  773. MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $");
  774. MODULE_LICENSE("GPL");
  775. MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);