qeth_core_main.c 124 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm-s390/ebcdic.h>
  21. #include <asm-s390/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. #define QETH_DBF_TEXT_(name, level, text...) \
  26. do { \
  27. if (qeth_dbf_passes(qeth_dbf_##name, level)) { \
  28. char *dbf_txt_buf = \
  29. get_cpu_var(qeth_core_dbf_txt_buf); \
  30. sprintf(dbf_txt_buf, text); \
  31. debug_text_event(qeth_dbf_##name, level, dbf_txt_buf); \
  32. put_cpu_var(qeth_core_dbf_txt_buf); \
  33. } \
  34. } while (0)
  35. struct qeth_card_list_struct qeth_core_card_list;
  36. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  37. debug_info_t *qeth_dbf_setup;
  38. EXPORT_SYMBOL_GPL(qeth_dbf_setup);
  39. debug_info_t *qeth_dbf_data;
  40. EXPORT_SYMBOL_GPL(qeth_dbf_data);
  41. debug_info_t *qeth_dbf_misc;
  42. EXPORT_SYMBOL_GPL(qeth_dbf_misc);
  43. debug_info_t *qeth_dbf_control;
  44. EXPORT_SYMBOL_GPL(qeth_dbf_control);
  45. debug_info_t *qeth_dbf_trace;
  46. EXPORT_SYMBOL_GPL(qeth_dbf_trace);
  47. debug_info_t *qeth_dbf_sense;
  48. EXPORT_SYMBOL_GPL(qeth_dbf_sense);
  49. debug_info_t *qeth_dbf_qerr;
  50. EXPORT_SYMBOL_GPL(qeth_dbf_qerr);
  51. static struct device *qeth_core_root_dev;
  52. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  53. static struct lock_class_key qdio_out_skb_queue_key;
  54. static DEFINE_PER_CPU(char[256], qeth_core_dbf_txt_buf);
  55. static void qeth_send_control_data_cb(struct qeth_channel *,
  56. struct qeth_cmd_buffer *);
  57. static int qeth_issue_next_read(struct qeth_card *);
  58. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  59. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  60. static void qeth_free_buffer_pool(struct qeth_card *);
  61. static int qeth_qdio_establish(struct qeth_card *);
  62. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  63. struct qdio_buffer *buffer, int is_tso,
  64. int *next_element_to_fill)
  65. {
  66. struct skb_frag_struct *frag;
  67. int fragno;
  68. unsigned long addr;
  69. int element, cnt, dlen;
  70. fragno = skb_shinfo(skb)->nr_frags;
  71. element = *next_element_to_fill;
  72. dlen = 0;
  73. if (is_tso)
  74. buffer->element[element].flags =
  75. SBAL_FLAGS_MIDDLE_FRAG;
  76. else
  77. buffer->element[element].flags =
  78. SBAL_FLAGS_FIRST_FRAG;
  79. dlen = skb->len - skb->data_len;
  80. if (dlen) {
  81. buffer->element[element].addr = skb->data;
  82. buffer->element[element].length = dlen;
  83. element++;
  84. }
  85. for (cnt = 0; cnt < fragno; cnt++) {
  86. frag = &skb_shinfo(skb)->frags[cnt];
  87. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  88. frag->page_offset;
  89. buffer->element[element].addr = (char *)addr;
  90. buffer->element[element].length = frag->size;
  91. if (cnt < (fragno - 1))
  92. buffer->element[element].flags =
  93. SBAL_FLAGS_MIDDLE_FRAG;
  94. else
  95. buffer->element[element].flags =
  96. SBAL_FLAGS_LAST_FRAG;
  97. element++;
  98. }
  99. *next_element_to_fill = element;
  100. }
  101. static inline const char *qeth_get_cardname(struct qeth_card *card)
  102. {
  103. if (card->info.guestlan) {
  104. switch (card->info.type) {
  105. case QETH_CARD_TYPE_OSAE:
  106. return " Guest LAN QDIO";
  107. case QETH_CARD_TYPE_IQD:
  108. return " Guest LAN Hiper";
  109. default:
  110. return " unknown";
  111. }
  112. } else {
  113. switch (card->info.type) {
  114. case QETH_CARD_TYPE_OSAE:
  115. return " OSD Express";
  116. case QETH_CARD_TYPE_IQD:
  117. return " HiperSockets";
  118. case QETH_CARD_TYPE_OSN:
  119. return " OSN QDIO";
  120. default:
  121. return " unknown";
  122. }
  123. }
  124. return " n/a";
  125. }
  126. /* max length to be returned: 14 */
  127. const char *qeth_get_cardname_short(struct qeth_card *card)
  128. {
  129. if (card->info.guestlan) {
  130. switch (card->info.type) {
  131. case QETH_CARD_TYPE_OSAE:
  132. return "GuestLAN QDIO";
  133. case QETH_CARD_TYPE_IQD:
  134. return "GuestLAN Hiper";
  135. default:
  136. return "unknown";
  137. }
  138. } else {
  139. switch (card->info.type) {
  140. case QETH_CARD_TYPE_OSAE:
  141. switch (card->info.link_type) {
  142. case QETH_LINK_TYPE_FAST_ETH:
  143. return "OSD_100";
  144. case QETH_LINK_TYPE_HSTR:
  145. return "HSTR";
  146. case QETH_LINK_TYPE_GBIT_ETH:
  147. return "OSD_1000";
  148. case QETH_LINK_TYPE_10GBIT_ETH:
  149. return "OSD_10GIG";
  150. case QETH_LINK_TYPE_LANE_ETH100:
  151. return "OSD_FE_LANE";
  152. case QETH_LINK_TYPE_LANE_TR:
  153. return "OSD_TR_LANE";
  154. case QETH_LINK_TYPE_LANE_ETH1000:
  155. return "OSD_GbE_LANE";
  156. case QETH_LINK_TYPE_LANE:
  157. return "OSD_ATM_LANE";
  158. default:
  159. return "OSD_Express";
  160. }
  161. case QETH_CARD_TYPE_IQD:
  162. return "HiperSockets";
  163. case QETH_CARD_TYPE_OSN:
  164. return "OSN";
  165. default:
  166. return "unknown";
  167. }
  168. }
  169. return "n/a";
  170. }
  171. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  172. int clear_start_mask)
  173. {
  174. unsigned long flags;
  175. spin_lock_irqsave(&card->thread_mask_lock, flags);
  176. card->thread_allowed_mask = threads;
  177. if (clear_start_mask)
  178. card->thread_start_mask &= threads;
  179. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  180. wake_up(&card->wait_q);
  181. }
  182. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  183. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  184. {
  185. unsigned long flags;
  186. int rc = 0;
  187. spin_lock_irqsave(&card->thread_mask_lock, flags);
  188. rc = (card->thread_running_mask & threads);
  189. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  190. return rc;
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_threads_running);
  193. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  194. {
  195. return wait_event_interruptible(card->wait_q,
  196. qeth_threads_running(card, threads) == 0);
  197. }
  198. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  199. void qeth_clear_working_pool_list(struct qeth_card *card)
  200. {
  201. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  202. QETH_DBF_TEXT(trace, 5, "clwrklst");
  203. list_for_each_entry_safe(pool_entry, tmp,
  204. &card->qdio.in_buf_pool.entry_list, list){
  205. list_del(&pool_entry->list);
  206. }
  207. }
  208. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  209. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  210. {
  211. struct qeth_buffer_pool_entry *pool_entry;
  212. void *ptr;
  213. int i, j;
  214. QETH_DBF_TEXT(trace, 5, "alocpool");
  215. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  216. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  217. if (!pool_entry) {
  218. qeth_free_buffer_pool(card);
  219. return -ENOMEM;
  220. }
  221. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  222. ptr = (void *) __get_free_page(GFP_KERNEL|GFP_DMA);
  223. if (!ptr) {
  224. while (j > 0)
  225. free_page((unsigned long)
  226. pool_entry->elements[--j]);
  227. kfree(pool_entry);
  228. qeth_free_buffer_pool(card);
  229. return -ENOMEM;
  230. }
  231. pool_entry->elements[j] = ptr;
  232. }
  233. list_add(&pool_entry->init_list,
  234. &card->qdio.init_pool.entry_list);
  235. }
  236. return 0;
  237. }
  238. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  239. {
  240. QETH_DBF_TEXT(trace, 2, "realcbp");
  241. if ((card->state != CARD_STATE_DOWN) &&
  242. (card->state != CARD_STATE_RECOVER))
  243. return -EPERM;
  244. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  245. qeth_clear_working_pool_list(card);
  246. qeth_free_buffer_pool(card);
  247. card->qdio.in_buf_pool.buf_count = bufcnt;
  248. card->qdio.init_pool.buf_count = bufcnt;
  249. return qeth_alloc_buffer_pool(card);
  250. }
  251. int qeth_set_large_send(struct qeth_card *card,
  252. enum qeth_large_send_types type)
  253. {
  254. int rc = 0;
  255. if (card->dev == NULL) {
  256. card->options.large_send = type;
  257. return 0;
  258. }
  259. if (card->state == CARD_STATE_UP)
  260. netif_tx_disable(card->dev);
  261. card->options.large_send = type;
  262. switch (card->options.large_send) {
  263. case QETH_LARGE_SEND_EDDP:
  264. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  265. NETIF_F_HW_CSUM;
  266. break;
  267. case QETH_LARGE_SEND_TSO:
  268. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  269. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  270. NETIF_F_HW_CSUM;
  271. } else {
  272. PRINT_WARN("TSO not supported on %s. "
  273. "large_send set to 'no'.\n",
  274. card->dev->name);
  275. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  276. NETIF_F_HW_CSUM);
  277. card->options.large_send = QETH_LARGE_SEND_NO;
  278. rc = -EOPNOTSUPP;
  279. }
  280. break;
  281. default: /* includes QETH_LARGE_SEND_NO */
  282. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  283. NETIF_F_HW_CSUM);
  284. break;
  285. }
  286. if (card->state == CARD_STATE_UP)
  287. netif_wake_queue(card->dev);
  288. return rc;
  289. }
  290. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  291. static int qeth_issue_next_read(struct qeth_card *card)
  292. {
  293. int rc;
  294. struct qeth_cmd_buffer *iob;
  295. QETH_DBF_TEXT(trace, 5, "issnxrd");
  296. if (card->read.state != CH_STATE_UP)
  297. return -EIO;
  298. iob = qeth_get_buffer(&card->read);
  299. if (!iob) {
  300. PRINT_WARN("issue_next_read failed: no iob available!\n");
  301. return -ENOMEM;
  302. }
  303. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  304. QETH_DBF_TEXT(trace, 6, "noirqpnd");
  305. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  306. (addr_t) iob, 0, 0);
  307. if (rc) {
  308. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  309. atomic_set(&card->read.irq_pending, 0);
  310. qeth_schedule_recovery(card);
  311. wake_up(&card->wait_q);
  312. }
  313. return rc;
  314. }
  315. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  316. {
  317. struct qeth_reply *reply;
  318. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  319. if (reply) {
  320. atomic_set(&reply->refcnt, 1);
  321. atomic_set(&reply->received, 0);
  322. reply->card = card;
  323. };
  324. return reply;
  325. }
  326. static void qeth_get_reply(struct qeth_reply *reply)
  327. {
  328. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  329. atomic_inc(&reply->refcnt);
  330. }
  331. static void qeth_put_reply(struct qeth_reply *reply)
  332. {
  333. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  334. if (atomic_dec_and_test(&reply->refcnt))
  335. kfree(reply);
  336. }
  337. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd,
  338. struct qeth_card *card)
  339. {
  340. int rc;
  341. int com;
  342. char *ipa_name;
  343. com = cmd->hdr.command;
  344. rc = cmd->hdr.return_code;
  345. ipa_name = qeth_get_ipa_cmd_name(com);
  346. PRINT_ERR("%s(x%X) for %s returned x%X \"%s\"\n", ipa_name, com,
  347. QETH_CARD_IFNAME(card), rc, qeth_get_ipa_msg(rc));
  348. }
  349. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  350. struct qeth_cmd_buffer *iob)
  351. {
  352. struct qeth_ipa_cmd *cmd = NULL;
  353. QETH_DBF_TEXT(trace, 5, "chkipad");
  354. if (IS_IPA(iob->data)) {
  355. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  356. if (IS_IPA_REPLY(cmd)) {
  357. if (cmd->hdr.return_code &&
  358. (cmd->hdr.command < IPA_CMD_SETCCID ||
  359. cmd->hdr.command > IPA_CMD_MODCCID))
  360. qeth_issue_ipa_msg(cmd, card);
  361. return cmd;
  362. } else {
  363. switch (cmd->hdr.command) {
  364. case IPA_CMD_STOPLAN:
  365. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  366. "there is a network problem or "
  367. "someone pulled the cable or "
  368. "disabled the port.\n",
  369. QETH_CARD_IFNAME(card),
  370. card->info.chpid);
  371. card->lan_online = 0;
  372. if (card->dev && netif_carrier_ok(card->dev))
  373. netif_carrier_off(card->dev);
  374. return NULL;
  375. case IPA_CMD_STARTLAN:
  376. PRINT_INFO("Link reestablished on %s "
  377. "(CHPID 0x%X). Scheduling "
  378. "IP address reset.\n",
  379. QETH_CARD_IFNAME(card),
  380. card->info.chpid);
  381. netif_carrier_on(card->dev);
  382. qeth_schedule_recovery(card);
  383. return NULL;
  384. case IPA_CMD_MODCCID:
  385. return cmd;
  386. case IPA_CMD_REGISTER_LOCAL_ADDR:
  387. QETH_DBF_TEXT(trace, 3, "irla");
  388. break;
  389. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  390. QETH_DBF_TEXT(trace, 3, "urla");
  391. break;
  392. default:
  393. PRINT_WARN("Received data is IPA "
  394. "but not a reply!\n");
  395. break;
  396. }
  397. }
  398. }
  399. return cmd;
  400. }
  401. void qeth_clear_ipacmd_list(struct qeth_card *card)
  402. {
  403. struct qeth_reply *reply, *r;
  404. unsigned long flags;
  405. QETH_DBF_TEXT(trace, 4, "clipalst");
  406. spin_lock_irqsave(&card->lock, flags);
  407. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  408. qeth_get_reply(reply);
  409. reply->rc = -EIO;
  410. atomic_inc(&reply->received);
  411. list_del_init(&reply->list);
  412. wake_up(&reply->wait_q);
  413. qeth_put_reply(reply);
  414. }
  415. spin_unlock_irqrestore(&card->lock, flags);
  416. }
  417. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  418. static int qeth_check_idx_response(unsigned char *buffer)
  419. {
  420. if (!buffer)
  421. return 0;
  422. QETH_DBF_HEX(control, 2, buffer, QETH_DBF_CONTROL_LEN);
  423. if ((buffer[2] & 0xc0) == 0xc0) {
  424. PRINT_WARN("received an IDX TERMINATE "
  425. "with cause code 0x%02x%s\n",
  426. buffer[4],
  427. ((buffer[4] == 0x22) ?
  428. " -- try another portname" : ""));
  429. QETH_DBF_TEXT(trace, 2, "ckidxres");
  430. QETH_DBF_TEXT(trace, 2, " idxterm");
  431. QETH_DBF_TEXT_(trace, 2, " rc%d", -EIO);
  432. return -EIO;
  433. }
  434. return 0;
  435. }
  436. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  437. __u32 len)
  438. {
  439. struct qeth_card *card;
  440. QETH_DBF_TEXT(trace, 4, "setupccw");
  441. card = CARD_FROM_CDEV(channel->ccwdev);
  442. if (channel == &card->read)
  443. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  444. else
  445. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  446. channel->ccw.count = len;
  447. channel->ccw.cda = (__u32) __pa(iob);
  448. }
  449. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  450. {
  451. __u8 index;
  452. QETH_DBF_TEXT(trace, 6, "getbuff");
  453. index = channel->io_buf_no;
  454. do {
  455. if (channel->iob[index].state == BUF_STATE_FREE) {
  456. channel->iob[index].state = BUF_STATE_LOCKED;
  457. channel->io_buf_no = (channel->io_buf_no + 1) %
  458. QETH_CMD_BUFFER_NO;
  459. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  460. return channel->iob + index;
  461. }
  462. index = (index + 1) % QETH_CMD_BUFFER_NO;
  463. } while (index != channel->io_buf_no);
  464. return NULL;
  465. }
  466. void qeth_release_buffer(struct qeth_channel *channel,
  467. struct qeth_cmd_buffer *iob)
  468. {
  469. unsigned long flags;
  470. QETH_DBF_TEXT(trace, 6, "relbuff");
  471. spin_lock_irqsave(&channel->iob_lock, flags);
  472. memset(iob->data, 0, QETH_BUFSIZE);
  473. iob->state = BUF_STATE_FREE;
  474. iob->callback = qeth_send_control_data_cb;
  475. iob->rc = 0;
  476. spin_unlock_irqrestore(&channel->iob_lock, flags);
  477. }
  478. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  479. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  480. {
  481. struct qeth_cmd_buffer *buffer = NULL;
  482. unsigned long flags;
  483. spin_lock_irqsave(&channel->iob_lock, flags);
  484. buffer = __qeth_get_buffer(channel);
  485. spin_unlock_irqrestore(&channel->iob_lock, flags);
  486. return buffer;
  487. }
  488. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  489. {
  490. struct qeth_cmd_buffer *buffer;
  491. wait_event(channel->wait_q,
  492. ((buffer = qeth_get_buffer(channel)) != NULL));
  493. return buffer;
  494. }
  495. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  496. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  497. {
  498. int cnt;
  499. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  500. qeth_release_buffer(channel, &channel->iob[cnt]);
  501. channel->buf_no = 0;
  502. channel->io_buf_no = 0;
  503. }
  504. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  505. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  506. struct qeth_cmd_buffer *iob)
  507. {
  508. struct qeth_card *card;
  509. struct qeth_reply *reply, *r;
  510. struct qeth_ipa_cmd *cmd;
  511. unsigned long flags;
  512. int keep_reply;
  513. QETH_DBF_TEXT(trace, 4, "sndctlcb");
  514. card = CARD_FROM_CDEV(channel->ccwdev);
  515. if (qeth_check_idx_response(iob->data)) {
  516. qeth_clear_ipacmd_list(card);
  517. qeth_schedule_recovery(card);
  518. goto out;
  519. }
  520. cmd = qeth_check_ipa_data(card, iob);
  521. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  522. goto out;
  523. /*in case of OSN : check if cmd is set */
  524. if (card->info.type == QETH_CARD_TYPE_OSN &&
  525. cmd &&
  526. cmd->hdr.command != IPA_CMD_STARTLAN &&
  527. card->osn_info.assist_cb != NULL) {
  528. card->osn_info.assist_cb(card->dev, cmd);
  529. goto out;
  530. }
  531. spin_lock_irqsave(&card->lock, flags);
  532. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  533. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  534. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  535. qeth_get_reply(reply);
  536. list_del_init(&reply->list);
  537. spin_unlock_irqrestore(&card->lock, flags);
  538. keep_reply = 0;
  539. if (reply->callback != NULL) {
  540. if (cmd) {
  541. reply->offset = (__u16)((char *)cmd -
  542. (char *)iob->data);
  543. keep_reply = reply->callback(card,
  544. reply,
  545. (unsigned long)cmd);
  546. } else
  547. keep_reply = reply->callback(card,
  548. reply,
  549. (unsigned long)iob);
  550. }
  551. if (cmd)
  552. reply->rc = (u16) cmd->hdr.return_code;
  553. else if (iob->rc)
  554. reply->rc = iob->rc;
  555. if (keep_reply) {
  556. spin_lock_irqsave(&card->lock, flags);
  557. list_add_tail(&reply->list,
  558. &card->cmd_waiter_list);
  559. spin_unlock_irqrestore(&card->lock, flags);
  560. } else {
  561. atomic_inc(&reply->received);
  562. wake_up(&reply->wait_q);
  563. }
  564. qeth_put_reply(reply);
  565. goto out;
  566. }
  567. }
  568. spin_unlock_irqrestore(&card->lock, flags);
  569. out:
  570. memcpy(&card->seqno.pdu_hdr_ack,
  571. QETH_PDU_HEADER_SEQ_NO(iob->data),
  572. QETH_SEQ_NO_LENGTH);
  573. qeth_release_buffer(channel, iob);
  574. }
  575. static int qeth_setup_channel(struct qeth_channel *channel)
  576. {
  577. int cnt;
  578. QETH_DBF_TEXT(setup, 2, "setupch");
  579. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  580. channel->iob[cnt].data = (char *)
  581. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  582. if (channel->iob[cnt].data == NULL)
  583. break;
  584. channel->iob[cnt].state = BUF_STATE_FREE;
  585. channel->iob[cnt].channel = channel;
  586. channel->iob[cnt].callback = qeth_send_control_data_cb;
  587. channel->iob[cnt].rc = 0;
  588. }
  589. if (cnt < QETH_CMD_BUFFER_NO) {
  590. while (cnt-- > 0)
  591. kfree(channel->iob[cnt].data);
  592. return -ENOMEM;
  593. }
  594. channel->buf_no = 0;
  595. channel->io_buf_no = 0;
  596. atomic_set(&channel->irq_pending, 0);
  597. spin_lock_init(&channel->iob_lock);
  598. init_waitqueue_head(&channel->wait_q);
  599. return 0;
  600. }
  601. static int qeth_set_thread_start_bit(struct qeth_card *card,
  602. unsigned long thread)
  603. {
  604. unsigned long flags;
  605. spin_lock_irqsave(&card->thread_mask_lock, flags);
  606. if (!(card->thread_allowed_mask & thread) ||
  607. (card->thread_start_mask & thread)) {
  608. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  609. return -EPERM;
  610. }
  611. card->thread_start_mask |= thread;
  612. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  613. return 0;
  614. }
  615. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  616. {
  617. unsigned long flags;
  618. spin_lock_irqsave(&card->thread_mask_lock, flags);
  619. card->thread_start_mask &= ~thread;
  620. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  621. wake_up(&card->wait_q);
  622. }
  623. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  624. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  625. {
  626. unsigned long flags;
  627. spin_lock_irqsave(&card->thread_mask_lock, flags);
  628. card->thread_running_mask &= ~thread;
  629. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  630. wake_up(&card->wait_q);
  631. }
  632. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  633. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  634. {
  635. unsigned long flags;
  636. int rc = 0;
  637. spin_lock_irqsave(&card->thread_mask_lock, flags);
  638. if (card->thread_start_mask & thread) {
  639. if ((card->thread_allowed_mask & thread) &&
  640. !(card->thread_running_mask & thread)) {
  641. rc = 1;
  642. card->thread_start_mask &= ~thread;
  643. card->thread_running_mask |= thread;
  644. } else
  645. rc = -EPERM;
  646. }
  647. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  648. return rc;
  649. }
  650. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  651. {
  652. int rc = 0;
  653. wait_event(card->wait_q,
  654. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  655. return rc;
  656. }
  657. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  658. void qeth_schedule_recovery(struct qeth_card *card)
  659. {
  660. QETH_DBF_TEXT(trace, 2, "startrec");
  661. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  662. schedule_work(&card->kernel_thread_starter);
  663. }
  664. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  665. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  666. {
  667. int dstat, cstat;
  668. char *sense;
  669. sense = (char *) irb->ecw;
  670. cstat = irb->scsw.cstat;
  671. dstat = irb->scsw.dstat;
  672. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  673. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  674. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  675. QETH_DBF_TEXT(trace, 2, "CGENCHK");
  676. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  677. cdev->dev.bus_id, dstat, cstat);
  678. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  679. 16, 1, irb, 64, 1);
  680. return 1;
  681. }
  682. if (dstat & DEV_STAT_UNIT_CHECK) {
  683. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  684. SENSE_RESETTING_EVENT_FLAG) {
  685. QETH_DBF_TEXT(trace, 2, "REVIND");
  686. return 1;
  687. }
  688. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  689. SENSE_COMMAND_REJECT_FLAG) {
  690. QETH_DBF_TEXT(trace, 2, "CMDREJi");
  691. return 0;
  692. }
  693. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  694. QETH_DBF_TEXT(trace, 2, "AFFE");
  695. return 1;
  696. }
  697. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  698. QETH_DBF_TEXT(trace, 2, "ZEROSEN");
  699. return 0;
  700. }
  701. QETH_DBF_TEXT(trace, 2, "DGENCHK");
  702. return 1;
  703. }
  704. return 0;
  705. }
  706. static long __qeth_check_irb_error(struct ccw_device *cdev,
  707. unsigned long intparm, struct irb *irb)
  708. {
  709. if (!IS_ERR(irb))
  710. return 0;
  711. switch (PTR_ERR(irb)) {
  712. case -EIO:
  713. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  714. QETH_DBF_TEXT(trace, 2, "ckirberr");
  715. QETH_DBF_TEXT_(trace, 2, " rc%d", -EIO);
  716. break;
  717. case -ETIMEDOUT:
  718. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  719. QETH_DBF_TEXT(trace, 2, "ckirberr");
  720. QETH_DBF_TEXT_(trace, 2, " rc%d", -ETIMEDOUT);
  721. if (intparm == QETH_RCD_PARM) {
  722. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  723. if (card && (card->data.ccwdev == cdev)) {
  724. card->data.state = CH_STATE_DOWN;
  725. wake_up(&card->wait_q);
  726. }
  727. }
  728. break;
  729. default:
  730. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  731. cdev->dev.bus_id);
  732. QETH_DBF_TEXT(trace, 2, "ckirberr");
  733. QETH_DBF_TEXT(trace, 2, " rc???");
  734. }
  735. return PTR_ERR(irb);
  736. }
  737. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  738. struct irb *irb)
  739. {
  740. int rc;
  741. int cstat, dstat;
  742. struct qeth_cmd_buffer *buffer;
  743. struct qeth_channel *channel;
  744. struct qeth_card *card;
  745. struct qeth_cmd_buffer *iob;
  746. __u8 index;
  747. QETH_DBF_TEXT(trace, 5, "irq");
  748. if (__qeth_check_irb_error(cdev, intparm, irb))
  749. return;
  750. cstat = irb->scsw.cstat;
  751. dstat = irb->scsw.dstat;
  752. card = CARD_FROM_CDEV(cdev);
  753. if (!card)
  754. return;
  755. if (card->read.ccwdev == cdev) {
  756. channel = &card->read;
  757. QETH_DBF_TEXT(trace, 5, "read");
  758. } else if (card->write.ccwdev == cdev) {
  759. channel = &card->write;
  760. QETH_DBF_TEXT(trace, 5, "write");
  761. } else {
  762. channel = &card->data;
  763. QETH_DBF_TEXT(trace, 5, "data");
  764. }
  765. atomic_set(&channel->irq_pending, 0);
  766. if (irb->scsw.fctl & (SCSW_FCTL_CLEAR_FUNC))
  767. channel->state = CH_STATE_STOPPED;
  768. if (irb->scsw.fctl & (SCSW_FCTL_HALT_FUNC))
  769. channel->state = CH_STATE_HALTED;
  770. /*let's wake up immediately on data channel*/
  771. if ((channel == &card->data) && (intparm != 0) &&
  772. (intparm != QETH_RCD_PARM))
  773. goto out;
  774. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  775. QETH_DBF_TEXT(trace, 6, "clrchpar");
  776. /* we don't have to handle this further */
  777. intparm = 0;
  778. }
  779. if (intparm == QETH_HALT_CHANNEL_PARM) {
  780. QETH_DBF_TEXT(trace, 6, "hltchpar");
  781. /* we don't have to handle this further */
  782. intparm = 0;
  783. }
  784. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  785. (dstat & DEV_STAT_UNIT_CHECK) ||
  786. (cstat)) {
  787. if (irb->esw.esw0.erw.cons) {
  788. /* TODO: we should make this s390dbf */
  789. PRINT_WARN("sense data available on channel %s.\n",
  790. CHANNEL_ID(channel));
  791. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  792. print_hex_dump(KERN_WARNING, "qeth: irb ",
  793. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  794. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  795. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  796. }
  797. if (intparm == QETH_RCD_PARM) {
  798. channel->state = CH_STATE_DOWN;
  799. goto out;
  800. }
  801. rc = qeth_get_problem(cdev, irb);
  802. if (rc) {
  803. qeth_schedule_recovery(card);
  804. goto out;
  805. }
  806. }
  807. if (intparm == QETH_RCD_PARM) {
  808. channel->state = CH_STATE_RCD_DONE;
  809. goto out;
  810. }
  811. if (intparm) {
  812. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  813. buffer->state = BUF_STATE_PROCESSED;
  814. }
  815. if (channel == &card->data)
  816. return;
  817. if (channel == &card->read &&
  818. channel->state == CH_STATE_UP)
  819. qeth_issue_next_read(card);
  820. iob = channel->iob;
  821. index = channel->buf_no;
  822. while (iob[index].state == BUF_STATE_PROCESSED) {
  823. if (iob[index].callback != NULL)
  824. iob[index].callback(channel, iob + index);
  825. index = (index + 1) % QETH_CMD_BUFFER_NO;
  826. }
  827. channel->buf_no = index;
  828. out:
  829. wake_up(&card->wait_q);
  830. return;
  831. }
  832. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  833. struct qeth_qdio_out_buffer *buf)
  834. {
  835. int i;
  836. struct sk_buff *skb;
  837. /* is PCI flag set on buffer? */
  838. if (buf->buffer->element[0].flags & 0x40)
  839. atomic_dec(&queue->set_pci_flags_count);
  840. skb = skb_dequeue(&buf->skb_list);
  841. while (skb) {
  842. atomic_dec(&skb->users);
  843. dev_kfree_skb_any(skb);
  844. skb = skb_dequeue(&buf->skb_list);
  845. }
  846. qeth_eddp_buf_release_contexts(buf);
  847. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  848. buf->buffer->element[i].length = 0;
  849. buf->buffer->element[i].addr = NULL;
  850. buf->buffer->element[i].flags = 0;
  851. }
  852. buf->next_element_to_fill = 0;
  853. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  854. }
  855. void qeth_clear_qdio_buffers(struct qeth_card *card)
  856. {
  857. int i, j;
  858. QETH_DBF_TEXT(trace, 2, "clearqdbf");
  859. /* clear outbound buffers to free skbs */
  860. for (i = 0; i < card->qdio.no_out_queues; ++i)
  861. if (card->qdio.out_qs[i]) {
  862. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  863. qeth_clear_output_buffer(card->qdio.out_qs[i],
  864. &card->qdio.out_qs[i]->bufs[j]);
  865. }
  866. }
  867. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  868. static void qeth_free_buffer_pool(struct qeth_card *card)
  869. {
  870. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  871. int i = 0;
  872. QETH_DBF_TEXT(trace, 5, "freepool");
  873. list_for_each_entry_safe(pool_entry, tmp,
  874. &card->qdio.init_pool.entry_list, init_list){
  875. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  876. free_page((unsigned long)pool_entry->elements[i]);
  877. list_del(&pool_entry->init_list);
  878. kfree(pool_entry);
  879. }
  880. }
  881. static void qeth_free_qdio_buffers(struct qeth_card *card)
  882. {
  883. int i, j;
  884. QETH_DBF_TEXT(trace, 2, "freeqdbf");
  885. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  886. QETH_QDIO_UNINITIALIZED)
  887. return;
  888. kfree(card->qdio.in_q);
  889. card->qdio.in_q = NULL;
  890. /* inbound buffer pool */
  891. qeth_free_buffer_pool(card);
  892. /* free outbound qdio_qs */
  893. if (card->qdio.out_qs) {
  894. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  895. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  896. qeth_clear_output_buffer(card->qdio.out_qs[i],
  897. &card->qdio.out_qs[i]->bufs[j]);
  898. kfree(card->qdio.out_qs[i]);
  899. }
  900. kfree(card->qdio.out_qs);
  901. card->qdio.out_qs = NULL;
  902. }
  903. }
  904. static void qeth_clean_channel(struct qeth_channel *channel)
  905. {
  906. int cnt;
  907. QETH_DBF_TEXT(setup, 2, "freech");
  908. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  909. kfree(channel->iob[cnt].data);
  910. }
  911. static int qeth_is_1920_device(struct qeth_card *card)
  912. {
  913. int single_queue = 0;
  914. struct ccw_device *ccwdev;
  915. struct channelPath_dsc {
  916. u8 flags;
  917. u8 lsn;
  918. u8 desc;
  919. u8 chpid;
  920. u8 swla;
  921. u8 zeroes;
  922. u8 chla;
  923. u8 chpp;
  924. } *chp_dsc;
  925. QETH_DBF_TEXT(setup, 2, "chk_1920");
  926. ccwdev = card->data.ccwdev;
  927. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  928. if (chp_dsc != NULL) {
  929. /* CHPP field bit 6 == 1 -> single queue */
  930. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  931. kfree(chp_dsc);
  932. }
  933. QETH_DBF_TEXT_(setup, 2, "rc:%x", single_queue);
  934. return single_queue;
  935. }
  936. static void qeth_init_qdio_info(struct qeth_card *card)
  937. {
  938. QETH_DBF_TEXT(setup, 4, "intqdinf");
  939. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  940. /* inbound */
  941. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  942. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  943. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  944. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  945. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  946. }
  947. static void qeth_set_intial_options(struct qeth_card *card)
  948. {
  949. card->options.route4.type = NO_ROUTER;
  950. card->options.route6.type = NO_ROUTER;
  951. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  952. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  953. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  954. card->options.fake_broadcast = 0;
  955. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  956. card->options.fake_ll = 0;
  957. card->options.performance_stats = 0;
  958. card->options.rx_sg_cb = QETH_RX_SG_CB;
  959. }
  960. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  961. {
  962. unsigned long flags;
  963. int rc = 0;
  964. spin_lock_irqsave(&card->thread_mask_lock, flags);
  965. QETH_DBF_TEXT_(trace, 4, " %02x%02x%02x",
  966. (u8) card->thread_start_mask,
  967. (u8) card->thread_allowed_mask,
  968. (u8) card->thread_running_mask);
  969. rc = (card->thread_start_mask & thread);
  970. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  971. return rc;
  972. }
  973. static void qeth_start_kernel_thread(struct work_struct *work)
  974. {
  975. struct qeth_card *card = container_of(work, struct qeth_card,
  976. kernel_thread_starter);
  977. QETH_DBF_TEXT(trace , 2, "strthrd");
  978. if (card->read.state != CH_STATE_UP &&
  979. card->write.state != CH_STATE_UP)
  980. return;
  981. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  982. kthread_run(card->discipline.recover, (void *) card,
  983. "qeth_recover");
  984. }
  985. static int qeth_setup_card(struct qeth_card *card)
  986. {
  987. QETH_DBF_TEXT(setup, 2, "setupcrd");
  988. QETH_DBF_HEX(setup, 2, &card, sizeof(void *));
  989. card->read.state = CH_STATE_DOWN;
  990. card->write.state = CH_STATE_DOWN;
  991. card->data.state = CH_STATE_DOWN;
  992. card->state = CARD_STATE_DOWN;
  993. card->lan_online = 0;
  994. card->use_hard_stop = 0;
  995. card->dev = NULL;
  996. spin_lock_init(&card->vlanlock);
  997. spin_lock_init(&card->mclock);
  998. card->vlangrp = NULL;
  999. spin_lock_init(&card->lock);
  1000. spin_lock_init(&card->ip_lock);
  1001. spin_lock_init(&card->thread_mask_lock);
  1002. card->thread_start_mask = 0;
  1003. card->thread_allowed_mask = 0;
  1004. card->thread_running_mask = 0;
  1005. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1006. INIT_LIST_HEAD(&card->ip_list);
  1007. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1008. if (!card->ip_tbd_list) {
  1009. QETH_DBF_TEXT(setup, 0, "iptbdnom");
  1010. return -ENOMEM;
  1011. }
  1012. INIT_LIST_HEAD(card->ip_tbd_list);
  1013. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1014. init_waitqueue_head(&card->wait_q);
  1015. /* intial options */
  1016. qeth_set_intial_options(card);
  1017. /* IP address takeover */
  1018. INIT_LIST_HEAD(&card->ipato.entries);
  1019. card->ipato.enabled = 0;
  1020. card->ipato.invert4 = 0;
  1021. card->ipato.invert6 = 0;
  1022. /* init QDIO stuff */
  1023. qeth_init_qdio_info(card);
  1024. return 0;
  1025. }
  1026. static struct qeth_card *qeth_alloc_card(void)
  1027. {
  1028. struct qeth_card *card;
  1029. QETH_DBF_TEXT(setup, 2, "alloccrd");
  1030. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1031. if (!card)
  1032. return NULL;
  1033. QETH_DBF_HEX(setup, 2, &card, sizeof(void *));
  1034. if (qeth_setup_channel(&card->read)) {
  1035. kfree(card);
  1036. return NULL;
  1037. }
  1038. if (qeth_setup_channel(&card->write)) {
  1039. qeth_clean_channel(&card->read);
  1040. kfree(card);
  1041. return NULL;
  1042. }
  1043. card->options.layer2 = -1;
  1044. return card;
  1045. }
  1046. static int qeth_determine_card_type(struct qeth_card *card)
  1047. {
  1048. int i = 0;
  1049. QETH_DBF_TEXT(setup, 2, "detcdtyp");
  1050. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1051. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1052. while (known_devices[i][4]) {
  1053. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1054. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1055. card->info.type = known_devices[i][4];
  1056. card->qdio.no_out_queues = known_devices[i][8];
  1057. card->info.is_multicast_different = known_devices[i][9];
  1058. if (qeth_is_1920_device(card)) {
  1059. PRINT_INFO("Priority Queueing not able "
  1060. "due to hardware limitations!\n");
  1061. card->qdio.no_out_queues = 1;
  1062. card->qdio.default_out_queue = 0;
  1063. }
  1064. return 0;
  1065. }
  1066. i++;
  1067. }
  1068. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1069. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1070. return -ENOENT;
  1071. }
  1072. static int qeth_clear_channel(struct qeth_channel *channel)
  1073. {
  1074. unsigned long flags;
  1075. struct qeth_card *card;
  1076. int rc;
  1077. QETH_DBF_TEXT(trace, 3, "clearch");
  1078. card = CARD_FROM_CDEV(channel->ccwdev);
  1079. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1080. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1081. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1082. if (rc)
  1083. return rc;
  1084. rc = wait_event_interruptible_timeout(card->wait_q,
  1085. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1086. if (rc == -ERESTARTSYS)
  1087. return rc;
  1088. if (channel->state != CH_STATE_STOPPED)
  1089. return -ETIME;
  1090. channel->state = CH_STATE_DOWN;
  1091. return 0;
  1092. }
  1093. static int qeth_halt_channel(struct qeth_channel *channel)
  1094. {
  1095. unsigned long flags;
  1096. struct qeth_card *card;
  1097. int rc;
  1098. QETH_DBF_TEXT(trace, 3, "haltch");
  1099. card = CARD_FROM_CDEV(channel->ccwdev);
  1100. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1101. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1102. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1103. if (rc)
  1104. return rc;
  1105. rc = wait_event_interruptible_timeout(card->wait_q,
  1106. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1107. if (rc == -ERESTARTSYS)
  1108. return rc;
  1109. if (channel->state != CH_STATE_HALTED)
  1110. return -ETIME;
  1111. return 0;
  1112. }
  1113. static int qeth_halt_channels(struct qeth_card *card)
  1114. {
  1115. int rc1 = 0, rc2 = 0, rc3 = 0;
  1116. QETH_DBF_TEXT(trace, 3, "haltchs");
  1117. rc1 = qeth_halt_channel(&card->read);
  1118. rc2 = qeth_halt_channel(&card->write);
  1119. rc3 = qeth_halt_channel(&card->data);
  1120. if (rc1)
  1121. return rc1;
  1122. if (rc2)
  1123. return rc2;
  1124. return rc3;
  1125. }
  1126. static int qeth_clear_channels(struct qeth_card *card)
  1127. {
  1128. int rc1 = 0, rc2 = 0, rc3 = 0;
  1129. QETH_DBF_TEXT(trace, 3, "clearchs");
  1130. rc1 = qeth_clear_channel(&card->read);
  1131. rc2 = qeth_clear_channel(&card->write);
  1132. rc3 = qeth_clear_channel(&card->data);
  1133. if (rc1)
  1134. return rc1;
  1135. if (rc2)
  1136. return rc2;
  1137. return rc3;
  1138. }
  1139. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1140. {
  1141. int rc = 0;
  1142. QETH_DBF_TEXT(trace, 3, "clhacrd");
  1143. QETH_DBF_HEX(trace, 3, &card, sizeof(void *));
  1144. if (halt)
  1145. rc = qeth_halt_channels(card);
  1146. if (rc)
  1147. return rc;
  1148. return qeth_clear_channels(card);
  1149. }
  1150. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1151. {
  1152. int rc = 0;
  1153. QETH_DBF_TEXT(trace, 3, "qdioclr");
  1154. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1155. QETH_QDIO_CLEANING)) {
  1156. case QETH_QDIO_ESTABLISHED:
  1157. if (card->info.type == QETH_CARD_TYPE_IQD)
  1158. rc = qdio_cleanup(CARD_DDEV(card),
  1159. QDIO_FLAG_CLEANUP_USING_HALT);
  1160. else
  1161. rc = qdio_cleanup(CARD_DDEV(card),
  1162. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1163. if (rc)
  1164. QETH_DBF_TEXT_(trace, 3, "1err%d", rc);
  1165. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1166. break;
  1167. case QETH_QDIO_CLEANING:
  1168. return rc;
  1169. default:
  1170. break;
  1171. }
  1172. rc = qeth_clear_halt_card(card, use_halt);
  1173. if (rc)
  1174. QETH_DBF_TEXT_(trace, 3, "2err%d", rc);
  1175. card->state = CARD_STATE_DOWN;
  1176. return rc;
  1177. }
  1178. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1179. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1180. int *length)
  1181. {
  1182. struct ciw *ciw;
  1183. char *rcd_buf;
  1184. int ret;
  1185. struct qeth_channel *channel = &card->data;
  1186. unsigned long flags;
  1187. /*
  1188. * scan for RCD command in extended SenseID data
  1189. */
  1190. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1191. if (!ciw || ciw->cmd == 0)
  1192. return -EOPNOTSUPP;
  1193. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1194. if (!rcd_buf)
  1195. return -ENOMEM;
  1196. channel->ccw.cmd_code = ciw->cmd;
  1197. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1198. channel->ccw.count = ciw->count;
  1199. channel->ccw.flags = CCW_FLAG_SLI;
  1200. channel->state = CH_STATE_RCD;
  1201. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1202. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1203. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1204. QETH_RCD_TIMEOUT);
  1205. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1206. if (!ret)
  1207. wait_event(card->wait_q,
  1208. (channel->state == CH_STATE_RCD_DONE ||
  1209. channel->state == CH_STATE_DOWN));
  1210. if (channel->state == CH_STATE_DOWN)
  1211. ret = -EIO;
  1212. else
  1213. channel->state = CH_STATE_DOWN;
  1214. if (ret) {
  1215. kfree(rcd_buf);
  1216. *buffer = NULL;
  1217. *length = 0;
  1218. } else {
  1219. *length = ciw->count;
  1220. *buffer = rcd_buf;
  1221. }
  1222. return ret;
  1223. }
  1224. static int qeth_get_unitaddr(struct qeth_card *card)
  1225. {
  1226. int length;
  1227. char *prcd;
  1228. int rc;
  1229. QETH_DBF_TEXT(setup, 2, "getunit");
  1230. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1231. if (rc) {
  1232. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1233. CARD_DDEV_ID(card), rc);
  1234. return rc;
  1235. }
  1236. card->info.chpid = prcd[30];
  1237. card->info.unit_addr2 = prcd[31];
  1238. card->info.cula = prcd[63];
  1239. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1240. (prcd[0x11] == _ascebc['M']));
  1241. kfree(prcd);
  1242. return 0;
  1243. }
  1244. static void qeth_init_tokens(struct qeth_card *card)
  1245. {
  1246. card->token.issuer_rm_w = 0x00010103UL;
  1247. card->token.cm_filter_w = 0x00010108UL;
  1248. card->token.cm_connection_w = 0x0001010aUL;
  1249. card->token.ulp_filter_w = 0x0001010bUL;
  1250. card->token.ulp_connection_w = 0x0001010dUL;
  1251. }
  1252. static void qeth_init_func_level(struct qeth_card *card)
  1253. {
  1254. if (card->ipato.enabled) {
  1255. if (card->info.type == QETH_CARD_TYPE_IQD)
  1256. card->info.func_level =
  1257. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1258. else
  1259. card->info.func_level =
  1260. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1261. } else {
  1262. if (card->info.type == QETH_CARD_TYPE_IQD)
  1263. /*FIXME:why do we have same values for dis and ena for
  1264. osae??? */
  1265. card->info.func_level =
  1266. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1267. else
  1268. card->info.func_level =
  1269. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1270. }
  1271. }
  1272. static inline __u16 qeth_raw_devno_from_bus_id(char *id)
  1273. {
  1274. id += (strlen(id) - 4);
  1275. return (__u16) simple_strtoul(id, &id, 16);
  1276. }
  1277. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1278. void (*idx_reply_cb)(struct qeth_channel *,
  1279. struct qeth_cmd_buffer *))
  1280. {
  1281. struct qeth_cmd_buffer *iob;
  1282. unsigned long flags;
  1283. int rc;
  1284. struct qeth_card *card;
  1285. QETH_DBF_TEXT(setup, 2, "idxanswr");
  1286. card = CARD_FROM_CDEV(channel->ccwdev);
  1287. iob = qeth_get_buffer(channel);
  1288. iob->callback = idx_reply_cb;
  1289. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1290. channel->ccw.count = QETH_BUFSIZE;
  1291. channel->ccw.cda = (__u32) __pa(iob->data);
  1292. wait_event(card->wait_q,
  1293. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1294. QETH_DBF_TEXT(setup, 6, "noirqpnd");
  1295. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1296. rc = ccw_device_start(channel->ccwdev,
  1297. &channel->ccw, (addr_t) iob, 0, 0);
  1298. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1299. if (rc) {
  1300. PRINT_ERR("Error2 in activating channel rc=%d\n", rc);
  1301. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  1302. atomic_set(&channel->irq_pending, 0);
  1303. wake_up(&card->wait_q);
  1304. return rc;
  1305. }
  1306. rc = wait_event_interruptible_timeout(card->wait_q,
  1307. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1308. if (rc == -ERESTARTSYS)
  1309. return rc;
  1310. if (channel->state != CH_STATE_UP) {
  1311. rc = -ETIME;
  1312. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  1313. qeth_clear_cmd_buffers(channel);
  1314. } else
  1315. rc = 0;
  1316. return rc;
  1317. }
  1318. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1319. void (*idx_reply_cb)(struct qeth_channel *,
  1320. struct qeth_cmd_buffer *))
  1321. {
  1322. struct qeth_card *card;
  1323. struct qeth_cmd_buffer *iob;
  1324. unsigned long flags;
  1325. __u16 temp;
  1326. __u8 tmp;
  1327. int rc;
  1328. card = CARD_FROM_CDEV(channel->ccwdev);
  1329. QETH_DBF_TEXT(setup, 2, "idxactch");
  1330. iob = qeth_get_buffer(channel);
  1331. iob->callback = idx_reply_cb;
  1332. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1333. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1334. channel->ccw.cda = (__u32) __pa(iob->data);
  1335. if (channel == &card->write) {
  1336. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1337. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1338. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1339. card->seqno.trans_hdr++;
  1340. } else {
  1341. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1342. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1343. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1344. }
  1345. tmp = ((__u8)card->info.portno) | 0x80;
  1346. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1347. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1348. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1349. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1350. &card->info.func_level, sizeof(__u16));
  1351. temp = qeth_raw_devno_from_bus_id(CARD_DDEV_ID(card));
  1352. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp, 2);
  1353. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1354. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1355. wait_event(card->wait_q,
  1356. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1357. QETH_DBF_TEXT(setup, 6, "noirqpnd");
  1358. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1359. rc = ccw_device_start(channel->ccwdev,
  1360. &channel->ccw, (addr_t) iob, 0, 0);
  1361. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1362. if (rc) {
  1363. PRINT_ERR("Error1 in activating channel. rc=%d\n", rc);
  1364. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  1365. atomic_set(&channel->irq_pending, 0);
  1366. wake_up(&card->wait_q);
  1367. return rc;
  1368. }
  1369. rc = wait_event_interruptible_timeout(card->wait_q,
  1370. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1371. if (rc == -ERESTARTSYS)
  1372. return rc;
  1373. if (channel->state != CH_STATE_ACTIVATING) {
  1374. PRINT_WARN("IDX activate timed out!\n");
  1375. QETH_DBF_TEXT_(setup, 2, "2err%d", -ETIME);
  1376. qeth_clear_cmd_buffers(channel);
  1377. return -ETIME;
  1378. }
  1379. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1380. }
  1381. static int qeth_peer_func_level(int level)
  1382. {
  1383. if ((level & 0xff) == 8)
  1384. return (level & 0xff) + 0x400;
  1385. if (((level >> 8) & 3) == 1)
  1386. return (level & 0xff) + 0x200;
  1387. return level;
  1388. }
  1389. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1390. struct qeth_cmd_buffer *iob)
  1391. {
  1392. struct qeth_card *card;
  1393. __u16 temp;
  1394. QETH_DBF_TEXT(setup , 2, "idxwrcb");
  1395. if (channel->state == CH_STATE_DOWN) {
  1396. channel->state = CH_STATE_ACTIVATING;
  1397. goto out;
  1398. }
  1399. card = CARD_FROM_CDEV(channel->ccwdev);
  1400. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1401. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1402. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1403. "adapter exclusively used by another host\n",
  1404. CARD_WDEV_ID(card));
  1405. else
  1406. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1407. "negative reply\n", CARD_WDEV_ID(card));
  1408. goto out;
  1409. }
  1410. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1411. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1412. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1413. "function level mismatch "
  1414. "(sent: 0x%x, received: 0x%x)\n",
  1415. CARD_WDEV_ID(card), card->info.func_level, temp);
  1416. goto out;
  1417. }
  1418. channel->state = CH_STATE_UP;
  1419. out:
  1420. qeth_release_buffer(channel, iob);
  1421. }
  1422. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1423. struct qeth_cmd_buffer *iob)
  1424. {
  1425. struct qeth_card *card;
  1426. __u16 temp;
  1427. QETH_DBF_TEXT(setup , 2, "idxrdcb");
  1428. if (channel->state == CH_STATE_DOWN) {
  1429. channel->state = CH_STATE_ACTIVATING;
  1430. goto out;
  1431. }
  1432. card = CARD_FROM_CDEV(channel->ccwdev);
  1433. if (qeth_check_idx_response(iob->data))
  1434. goto out;
  1435. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1436. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1437. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1438. "adapter exclusively used by another host\n",
  1439. CARD_RDEV_ID(card));
  1440. else
  1441. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1442. "negative reply\n", CARD_RDEV_ID(card));
  1443. goto out;
  1444. }
  1445. /**
  1446. * temporary fix for microcode bug
  1447. * to revert it,replace OR by AND
  1448. */
  1449. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1450. (card->info.type == QETH_CARD_TYPE_OSAE))
  1451. card->info.portname_required = 1;
  1452. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1453. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1454. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1455. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1456. CARD_RDEV_ID(card), card->info.func_level, temp);
  1457. goto out;
  1458. }
  1459. memcpy(&card->token.issuer_rm_r,
  1460. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1461. QETH_MPC_TOKEN_LENGTH);
  1462. memcpy(&card->info.mcl_level[0],
  1463. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1464. channel->state = CH_STATE_UP;
  1465. out:
  1466. qeth_release_buffer(channel, iob);
  1467. }
  1468. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1469. struct qeth_cmd_buffer *iob)
  1470. {
  1471. qeth_setup_ccw(&card->write, iob->data, len);
  1472. iob->callback = qeth_release_buffer;
  1473. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1474. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1475. card->seqno.trans_hdr++;
  1476. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1477. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1478. card->seqno.pdu_hdr++;
  1479. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1480. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1481. QETH_DBF_HEX(control, 2, iob->data, QETH_DBF_CONTROL_LEN);
  1482. }
  1483. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1484. int qeth_send_control_data(struct qeth_card *card, int len,
  1485. struct qeth_cmd_buffer *iob,
  1486. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1487. unsigned long),
  1488. void *reply_param)
  1489. {
  1490. int rc;
  1491. unsigned long flags;
  1492. struct qeth_reply *reply = NULL;
  1493. unsigned long timeout;
  1494. QETH_DBF_TEXT(trace, 2, "sendctl");
  1495. reply = qeth_alloc_reply(card);
  1496. if (!reply) {
  1497. PRINT_WARN("Could no alloc qeth_reply!\n");
  1498. return -ENOMEM;
  1499. }
  1500. reply->callback = reply_cb;
  1501. reply->param = reply_param;
  1502. if (card->state == CARD_STATE_DOWN)
  1503. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1504. else
  1505. reply->seqno = card->seqno.ipa++;
  1506. init_waitqueue_head(&reply->wait_q);
  1507. spin_lock_irqsave(&card->lock, flags);
  1508. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1509. spin_unlock_irqrestore(&card->lock, flags);
  1510. QETH_DBF_HEX(control, 2, iob->data, QETH_DBF_CONTROL_LEN);
  1511. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1512. qeth_prepare_control_data(card, len, iob);
  1513. if (IS_IPA(iob->data))
  1514. timeout = jiffies + QETH_IPA_TIMEOUT;
  1515. else
  1516. timeout = jiffies + QETH_TIMEOUT;
  1517. QETH_DBF_TEXT(trace, 6, "noirqpnd");
  1518. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1519. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1520. (addr_t) iob, 0, 0);
  1521. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1522. if (rc) {
  1523. PRINT_WARN("qeth_send_control_data: "
  1524. "ccw_device_start rc = %i\n", rc);
  1525. QETH_DBF_TEXT_(trace, 2, " err%d", rc);
  1526. spin_lock_irqsave(&card->lock, flags);
  1527. list_del_init(&reply->list);
  1528. qeth_put_reply(reply);
  1529. spin_unlock_irqrestore(&card->lock, flags);
  1530. qeth_release_buffer(iob->channel, iob);
  1531. atomic_set(&card->write.irq_pending, 0);
  1532. wake_up(&card->wait_q);
  1533. return rc;
  1534. }
  1535. while (!atomic_read(&reply->received)) {
  1536. if (time_after(jiffies, timeout)) {
  1537. spin_lock_irqsave(&reply->card->lock, flags);
  1538. list_del_init(&reply->list);
  1539. spin_unlock_irqrestore(&reply->card->lock, flags);
  1540. reply->rc = -ETIME;
  1541. atomic_inc(&reply->received);
  1542. wake_up(&reply->wait_q);
  1543. }
  1544. cpu_relax();
  1545. };
  1546. rc = reply->rc;
  1547. qeth_put_reply(reply);
  1548. return rc;
  1549. }
  1550. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1551. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1552. unsigned long data)
  1553. {
  1554. struct qeth_cmd_buffer *iob;
  1555. QETH_DBF_TEXT(setup, 2, "cmenblcb");
  1556. iob = (struct qeth_cmd_buffer *) data;
  1557. memcpy(&card->token.cm_filter_r,
  1558. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1559. QETH_MPC_TOKEN_LENGTH);
  1560. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1561. return 0;
  1562. }
  1563. static int qeth_cm_enable(struct qeth_card *card)
  1564. {
  1565. int rc;
  1566. struct qeth_cmd_buffer *iob;
  1567. QETH_DBF_TEXT(setup, 2, "cmenable");
  1568. iob = qeth_wait_for_buffer(&card->write);
  1569. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1570. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1571. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1572. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1573. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1574. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1575. qeth_cm_enable_cb, NULL);
  1576. return rc;
  1577. }
  1578. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1579. unsigned long data)
  1580. {
  1581. struct qeth_cmd_buffer *iob;
  1582. QETH_DBF_TEXT(setup, 2, "cmsetpcb");
  1583. iob = (struct qeth_cmd_buffer *) data;
  1584. memcpy(&card->token.cm_connection_r,
  1585. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1586. QETH_MPC_TOKEN_LENGTH);
  1587. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1588. return 0;
  1589. }
  1590. static int qeth_cm_setup(struct qeth_card *card)
  1591. {
  1592. int rc;
  1593. struct qeth_cmd_buffer *iob;
  1594. QETH_DBF_TEXT(setup, 2, "cmsetup");
  1595. iob = qeth_wait_for_buffer(&card->write);
  1596. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1597. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1598. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1599. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1600. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1601. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1602. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1603. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1604. qeth_cm_setup_cb, NULL);
  1605. return rc;
  1606. }
  1607. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1608. {
  1609. switch (card->info.type) {
  1610. case QETH_CARD_TYPE_UNKNOWN:
  1611. return 1500;
  1612. case QETH_CARD_TYPE_IQD:
  1613. return card->info.max_mtu;
  1614. case QETH_CARD_TYPE_OSAE:
  1615. switch (card->info.link_type) {
  1616. case QETH_LINK_TYPE_HSTR:
  1617. case QETH_LINK_TYPE_LANE_TR:
  1618. return 2000;
  1619. default:
  1620. return 1492;
  1621. }
  1622. default:
  1623. return 1500;
  1624. }
  1625. }
  1626. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1627. {
  1628. switch (cardtype) {
  1629. case QETH_CARD_TYPE_UNKNOWN:
  1630. case QETH_CARD_TYPE_OSAE:
  1631. case QETH_CARD_TYPE_OSN:
  1632. return 61440;
  1633. case QETH_CARD_TYPE_IQD:
  1634. return 57344;
  1635. default:
  1636. return 1500;
  1637. }
  1638. }
  1639. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1640. {
  1641. switch (cardtype) {
  1642. case QETH_CARD_TYPE_IQD:
  1643. return 1;
  1644. default:
  1645. return 0;
  1646. }
  1647. }
  1648. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1649. {
  1650. switch (framesize) {
  1651. case 0x4000:
  1652. return 8192;
  1653. case 0x6000:
  1654. return 16384;
  1655. case 0xa000:
  1656. return 32768;
  1657. case 0xffff:
  1658. return 57344;
  1659. default:
  1660. return 0;
  1661. }
  1662. }
  1663. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1664. {
  1665. switch (card->info.type) {
  1666. case QETH_CARD_TYPE_OSAE:
  1667. return ((mtu >= 576) && (mtu <= 61440));
  1668. case QETH_CARD_TYPE_IQD:
  1669. return ((mtu >= 576) &&
  1670. (mtu <= card->info.max_mtu + 4096 - 32));
  1671. case QETH_CARD_TYPE_OSN:
  1672. case QETH_CARD_TYPE_UNKNOWN:
  1673. default:
  1674. return 1;
  1675. }
  1676. }
  1677. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1678. unsigned long data)
  1679. {
  1680. __u16 mtu, framesize;
  1681. __u16 len;
  1682. __u8 link_type;
  1683. struct qeth_cmd_buffer *iob;
  1684. QETH_DBF_TEXT(setup, 2, "ulpenacb");
  1685. iob = (struct qeth_cmd_buffer *) data;
  1686. memcpy(&card->token.ulp_filter_r,
  1687. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1688. QETH_MPC_TOKEN_LENGTH);
  1689. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1690. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1691. mtu = qeth_get_mtu_outof_framesize(framesize);
  1692. if (!mtu) {
  1693. iob->rc = -EINVAL;
  1694. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1695. return 0;
  1696. }
  1697. card->info.max_mtu = mtu;
  1698. card->info.initial_mtu = mtu;
  1699. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1700. } else {
  1701. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1702. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1703. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1704. }
  1705. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1706. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1707. memcpy(&link_type,
  1708. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1709. card->info.link_type = link_type;
  1710. } else
  1711. card->info.link_type = 0;
  1712. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1713. return 0;
  1714. }
  1715. static int qeth_ulp_enable(struct qeth_card *card)
  1716. {
  1717. int rc;
  1718. char prot_type;
  1719. struct qeth_cmd_buffer *iob;
  1720. /*FIXME: trace view callbacks*/
  1721. QETH_DBF_TEXT(setup, 2, "ulpenabl");
  1722. iob = qeth_wait_for_buffer(&card->write);
  1723. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1724. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1725. (__u8) card->info.portno;
  1726. if (card->options.layer2)
  1727. if (card->info.type == QETH_CARD_TYPE_OSN)
  1728. prot_type = QETH_PROT_OSN2;
  1729. else
  1730. prot_type = QETH_PROT_LAYER2;
  1731. else
  1732. prot_type = QETH_PROT_TCPIP;
  1733. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1734. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1735. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1736. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1737. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1738. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1739. card->info.portname, 9);
  1740. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1741. qeth_ulp_enable_cb, NULL);
  1742. return rc;
  1743. }
  1744. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1745. unsigned long data)
  1746. {
  1747. struct qeth_cmd_buffer *iob;
  1748. QETH_DBF_TEXT(setup, 2, "ulpstpcb");
  1749. iob = (struct qeth_cmd_buffer *) data;
  1750. memcpy(&card->token.ulp_connection_r,
  1751. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1752. QETH_MPC_TOKEN_LENGTH);
  1753. QETH_DBF_TEXT_(setup, 2, " rc%d", iob->rc);
  1754. return 0;
  1755. }
  1756. static int qeth_ulp_setup(struct qeth_card *card)
  1757. {
  1758. int rc;
  1759. __u16 temp;
  1760. struct qeth_cmd_buffer *iob;
  1761. struct ccw_dev_id dev_id;
  1762. QETH_DBF_TEXT(setup, 2, "ulpsetup");
  1763. iob = qeth_wait_for_buffer(&card->write);
  1764. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1765. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1766. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1767. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1768. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1769. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1770. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1771. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1772. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1773. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1774. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1775. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1776. qeth_ulp_setup_cb, NULL);
  1777. return rc;
  1778. }
  1779. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1780. {
  1781. int i, j;
  1782. QETH_DBF_TEXT(setup, 2, "allcqdbf");
  1783. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1784. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1785. return 0;
  1786. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1787. GFP_KERNEL|GFP_DMA);
  1788. if (!card->qdio.in_q)
  1789. goto out_nomem;
  1790. QETH_DBF_TEXT(setup, 2, "inq");
  1791. QETH_DBF_HEX(setup, 2, &card->qdio.in_q, sizeof(void *));
  1792. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1793. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1794. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1795. card->qdio.in_q->bufs[i].buffer =
  1796. &card->qdio.in_q->qdio_bufs[i];
  1797. /* inbound buffer pool */
  1798. if (qeth_alloc_buffer_pool(card))
  1799. goto out_freeinq;
  1800. /* outbound */
  1801. card->qdio.out_qs =
  1802. kmalloc(card->qdio.no_out_queues *
  1803. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1804. if (!card->qdio.out_qs)
  1805. goto out_freepool;
  1806. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1807. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1808. GFP_KERNEL|GFP_DMA);
  1809. if (!card->qdio.out_qs[i])
  1810. goto out_freeoutq;
  1811. QETH_DBF_TEXT_(setup, 2, "outq %i", i);
  1812. QETH_DBF_HEX(setup, 2, &card->qdio.out_qs[i], sizeof(void *));
  1813. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1814. card->qdio.out_qs[i]->queue_no = i;
  1815. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1816. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1817. card->qdio.out_qs[i]->bufs[j].buffer =
  1818. &card->qdio.out_qs[i]->qdio_bufs[j];
  1819. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1820. skb_list);
  1821. lockdep_set_class(
  1822. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1823. &qdio_out_skb_queue_key);
  1824. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1825. }
  1826. }
  1827. return 0;
  1828. out_freeoutq:
  1829. while (i > 0)
  1830. kfree(card->qdio.out_qs[--i]);
  1831. kfree(card->qdio.out_qs);
  1832. card->qdio.out_qs = NULL;
  1833. out_freepool:
  1834. qeth_free_buffer_pool(card);
  1835. out_freeinq:
  1836. kfree(card->qdio.in_q);
  1837. card->qdio.in_q = NULL;
  1838. out_nomem:
  1839. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1840. return -ENOMEM;
  1841. }
  1842. static void qeth_create_qib_param_field(struct qeth_card *card,
  1843. char *param_field)
  1844. {
  1845. param_field[0] = _ascebc['P'];
  1846. param_field[1] = _ascebc['C'];
  1847. param_field[2] = _ascebc['I'];
  1848. param_field[3] = _ascebc['T'];
  1849. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1850. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1851. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1852. }
  1853. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1854. char *param_field)
  1855. {
  1856. param_field[16] = _ascebc['B'];
  1857. param_field[17] = _ascebc['L'];
  1858. param_field[18] = _ascebc['K'];
  1859. param_field[19] = _ascebc['T'];
  1860. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1861. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1862. *((unsigned int *) (&param_field[28])) =
  1863. card->info.blkt.inter_packet_jumbo;
  1864. }
  1865. static int qeth_qdio_activate(struct qeth_card *card)
  1866. {
  1867. QETH_DBF_TEXT(setup, 3, "qdioact");
  1868. return qdio_activate(CARD_DDEV(card), 0);
  1869. }
  1870. static int qeth_dm_act(struct qeth_card *card)
  1871. {
  1872. int rc;
  1873. struct qeth_cmd_buffer *iob;
  1874. QETH_DBF_TEXT(setup, 2, "dmact");
  1875. iob = qeth_wait_for_buffer(&card->write);
  1876. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1877. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1878. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1879. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1880. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1881. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1882. return rc;
  1883. }
  1884. static int qeth_mpc_initialize(struct qeth_card *card)
  1885. {
  1886. int rc;
  1887. QETH_DBF_TEXT(setup, 2, "mpcinit");
  1888. rc = qeth_issue_next_read(card);
  1889. if (rc) {
  1890. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  1891. return rc;
  1892. }
  1893. rc = qeth_cm_enable(card);
  1894. if (rc) {
  1895. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  1896. goto out_qdio;
  1897. }
  1898. rc = qeth_cm_setup(card);
  1899. if (rc) {
  1900. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  1901. goto out_qdio;
  1902. }
  1903. rc = qeth_ulp_enable(card);
  1904. if (rc) {
  1905. QETH_DBF_TEXT_(setup, 2, "4err%d", rc);
  1906. goto out_qdio;
  1907. }
  1908. rc = qeth_ulp_setup(card);
  1909. if (rc) {
  1910. QETH_DBF_TEXT_(setup, 2, "5err%d", rc);
  1911. goto out_qdio;
  1912. }
  1913. rc = qeth_alloc_qdio_buffers(card);
  1914. if (rc) {
  1915. QETH_DBF_TEXT_(setup, 2, "5err%d", rc);
  1916. goto out_qdio;
  1917. }
  1918. rc = qeth_qdio_establish(card);
  1919. if (rc) {
  1920. QETH_DBF_TEXT_(setup, 2, "6err%d", rc);
  1921. qeth_free_qdio_buffers(card);
  1922. goto out_qdio;
  1923. }
  1924. rc = qeth_qdio_activate(card);
  1925. if (rc) {
  1926. QETH_DBF_TEXT_(setup, 2, "7err%d", rc);
  1927. goto out_qdio;
  1928. }
  1929. rc = qeth_dm_act(card);
  1930. if (rc) {
  1931. QETH_DBF_TEXT_(setup, 2, "8err%d", rc);
  1932. goto out_qdio;
  1933. }
  1934. return 0;
  1935. out_qdio:
  1936. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1937. return rc;
  1938. }
  1939. static void qeth_print_status_with_portname(struct qeth_card *card)
  1940. {
  1941. char dbf_text[15];
  1942. int i;
  1943. sprintf(dbf_text, "%s", card->info.portname + 1);
  1944. for (i = 0; i < 8; i++)
  1945. dbf_text[i] =
  1946. (char) _ebcasc[(__u8) dbf_text[i]];
  1947. dbf_text[8] = 0;
  1948. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1949. "with link type %s (portname: %s)\n",
  1950. CARD_RDEV_ID(card),
  1951. CARD_WDEV_ID(card),
  1952. CARD_DDEV_ID(card),
  1953. qeth_get_cardname(card),
  1954. (card->info.mcl_level[0]) ? " (level: " : "",
  1955. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1956. (card->info.mcl_level[0]) ? ")" : "",
  1957. qeth_get_cardname_short(card),
  1958. dbf_text);
  1959. }
  1960. static void qeth_print_status_no_portname(struct qeth_card *card)
  1961. {
  1962. if (card->info.portname[0])
  1963. PRINT_INFO("Device %s/%s/%s is a%s "
  1964. "card%s%s%s\nwith link type %s "
  1965. "(no portname needed by interface).\n",
  1966. CARD_RDEV_ID(card),
  1967. CARD_WDEV_ID(card),
  1968. CARD_DDEV_ID(card),
  1969. qeth_get_cardname(card),
  1970. (card->info.mcl_level[0]) ? " (level: " : "",
  1971. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1972. (card->info.mcl_level[0]) ? ")" : "",
  1973. qeth_get_cardname_short(card));
  1974. else
  1975. PRINT_INFO("Device %s/%s/%s is a%s "
  1976. "card%s%s%s\nwith link type %s.\n",
  1977. CARD_RDEV_ID(card),
  1978. CARD_WDEV_ID(card),
  1979. CARD_DDEV_ID(card),
  1980. qeth_get_cardname(card),
  1981. (card->info.mcl_level[0]) ? " (level: " : "",
  1982. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1983. (card->info.mcl_level[0]) ? ")" : "",
  1984. qeth_get_cardname_short(card));
  1985. }
  1986. void qeth_print_status_message(struct qeth_card *card)
  1987. {
  1988. switch (card->info.type) {
  1989. case QETH_CARD_TYPE_OSAE:
  1990. /* VM will use a non-zero first character
  1991. * to indicate a HiperSockets like reporting
  1992. * of the level OSA sets the first character to zero
  1993. * */
  1994. if (!card->info.mcl_level[0]) {
  1995. sprintf(card->info.mcl_level, "%02x%02x",
  1996. card->info.mcl_level[2],
  1997. card->info.mcl_level[3]);
  1998. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1999. break;
  2000. }
  2001. /* fallthrough */
  2002. case QETH_CARD_TYPE_IQD:
  2003. if (card->info.guestlan) {
  2004. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2005. card->info.mcl_level[0]];
  2006. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2007. card->info.mcl_level[1]];
  2008. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2009. card->info.mcl_level[2]];
  2010. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2011. card->info.mcl_level[3]];
  2012. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2013. }
  2014. break;
  2015. default:
  2016. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2017. }
  2018. if (card->info.portname_required)
  2019. qeth_print_status_with_portname(card);
  2020. else
  2021. qeth_print_status_no_portname(card);
  2022. }
  2023. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2024. void qeth_put_buffer_pool_entry(struct qeth_card *card,
  2025. struct qeth_buffer_pool_entry *entry)
  2026. {
  2027. QETH_DBF_TEXT(trace, 6, "ptbfplen");
  2028. list_add_tail(&entry->list, &card->qdio.in_buf_pool.entry_list);
  2029. }
  2030. EXPORT_SYMBOL_GPL(qeth_put_buffer_pool_entry);
  2031. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2032. {
  2033. struct qeth_buffer_pool_entry *entry;
  2034. QETH_DBF_TEXT(trace, 5, "inwrklst");
  2035. list_for_each_entry(entry,
  2036. &card->qdio.init_pool.entry_list, init_list) {
  2037. qeth_put_buffer_pool_entry(card, entry);
  2038. }
  2039. }
  2040. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2041. struct qeth_card *card)
  2042. {
  2043. struct list_head *plh;
  2044. struct qeth_buffer_pool_entry *entry;
  2045. int i, free;
  2046. struct page *page;
  2047. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2048. return NULL;
  2049. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2050. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2051. free = 1;
  2052. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2053. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2054. free = 0;
  2055. break;
  2056. }
  2057. }
  2058. if (free) {
  2059. list_del_init(&entry->list);
  2060. return entry;
  2061. }
  2062. }
  2063. /* no free buffer in pool so take first one and swap pages */
  2064. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2065. struct qeth_buffer_pool_entry, list);
  2066. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2067. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2068. page = alloc_page(GFP_ATOMIC|GFP_DMA);
  2069. if (!page) {
  2070. return NULL;
  2071. } else {
  2072. free_page((unsigned long)entry->elements[i]);
  2073. entry->elements[i] = page_address(page);
  2074. if (card->options.performance_stats)
  2075. card->perf_stats.sg_alloc_page_rx++;
  2076. }
  2077. }
  2078. }
  2079. list_del_init(&entry->list);
  2080. return entry;
  2081. }
  2082. static int qeth_init_input_buffer(struct qeth_card *card,
  2083. struct qeth_qdio_buffer *buf)
  2084. {
  2085. struct qeth_buffer_pool_entry *pool_entry;
  2086. int i;
  2087. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2088. if (!pool_entry)
  2089. return 1;
  2090. /*
  2091. * since the buffer is accessed only from the input_tasklet
  2092. * there shouldn't be a need to synchronize; also, since we use
  2093. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2094. * buffers
  2095. */
  2096. BUG_ON(!pool_entry);
  2097. buf->pool_entry = pool_entry;
  2098. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2099. buf->buffer->element[i].length = PAGE_SIZE;
  2100. buf->buffer->element[i].addr = pool_entry->elements[i];
  2101. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2102. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2103. else
  2104. buf->buffer->element[i].flags = 0;
  2105. }
  2106. return 0;
  2107. }
  2108. int qeth_init_qdio_queues(struct qeth_card *card)
  2109. {
  2110. int i, j;
  2111. int rc;
  2112. QETH_DBF_TEXT(setup, 2, "initqdqs");
  2113. /* inbound queue */
  2114. memset(card->qdio.in_q->qdio_bufs, 0,
  2115. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2116. qeth_initialize_working_pool_list(card);
  2117. /*give only as many buffers to hardware as we have buffer pool entries*/
  2118. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2119. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2120. card->qdio.in_q->next_buf_to_init =
  2121. card->qdio.in_buf_pool.buf_count - 1;
  2122. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2123. card->qdio.in_buf_pool.buf_count - 1, NULL);
  2124. if (rc) {
  2125. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  2126. return rc;
  2127. }
  2128. rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0);
  2129. if (rc) {
  2130. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  2131. return rc;
  2132. }
  2133. /* outbound queue */
  2134. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2135. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2136. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2137. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2138. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2139. &card->qdio.out_qs[i]->bufs[j]);
  2140. }
  2141. card->qdio.out_qs[i]->card = card;
  2142. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2143. card->qdio.out_qs[i]->do_pack = 0;
  2144. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2145. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2146. atomic_set(&card->qdio.out_qs[i]->state,
  2147. QETH_OUT_Q_UNLOCKED);
  2148. }
  2149. return 0;
  2150. }
  2151. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2152. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2153. {
  2154. switch (link_type) {
  2155. case QETH_LINK_TYPE_HSTR:
  2156. return 2;
  2157. default:
  2158. return 1;
  2159. }
  2160. }
  2161. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2162. struct qeth_ipa_cmd *cmd, __u8 command,
  2163. enum qeth_prot_versions prot)
  2164. {
  2165. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2166. cmd->hdr.command = command;
  2167. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2168. cmd->hdr.seqno = card->seqno.ipa;
  2169. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2170. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2171. if (card->options.layer2)
  2172. cmd->hdr.prim_version_no = 2;
  2173. else
  2174. cmd->hdr.prim_version_no = 1;
  2175. cmd->hdr.param_count = 1;
  2176. cmd->hdr.prot_version = prot;
  2177. cmd->hdr.ipa_supported = 0;
  2178. cmd->hdr.ipa_enabled = 0;
  2179. }
  2180. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2181. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2182. {
  2183. struct qeth_cmd_buffer *iob;
  2184. struct qeth_ipa_cmd *cmd;
  2185. iob = qeth_wait_for_buffer(&card->write);
  2186. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2187. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2188. return iob;
  2189. }
  2190. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2191. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2192. char prot_type)
  2193. {
  2194. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2195. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2196. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2197. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2198. }
  2199. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2200. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2201. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2202. unsigned long),
  2203. void *reply_param)
  2204. {
  2205. int rc;
  2206. char prot_type;
  2207. int cmd;
  2208. cmd = ((struct qeth_ipa_cmd *)
  2209. (iob->data+IPA_PDU_HEADER_SIZE))->hdr.command;
  2210. QETH_DBF_TEXT(trace, 4, "sendipa");
  2211. if (card->options.layer2)
  2212. if (card->info.type == QETH_CARD_TYPE_OSN)
  2213. prot_type = QETH_PROT_OSN2;
  2214. else
  2215. prot_type = QETH_PROT_LAYER2;
  2216. else
  2217. prot_type = QETH_PROT_TCPIP;
  2218. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2219. rc = qeth_send_control_data(card, IPA_CMD_LENGTH, iob,
  2220. reply_cb, reply_param);
  2221. if (rc != 0) {
  2222. char *ipa_cmd_name;
  2223. ipa_cmd_name = qeth_get_ipa_cmd_name(cmd);
  2224. PRINT_ERR("%s %s(%x) returned %s(%x)\n", __FUNCTION__,
  2225. ipa_cmd_name, cmd, qeth_get_ipa_msg(rc), rc);
  2226. }
  2227. return rc;
  2228. }
  2229. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2230. static int qeth_send_startstoplan(struct qeth_card *card,
  2231. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2232. {
  2233. int rc;
  2234. struct qeth_cmd_buffer *iob;
  2235. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2236. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2237. return rc;
  2238. }
  2239. int qeth_send_startlan(struct qeth_card *card)
  2240. {
  2241. int rc;
  2242. QETH_DBF_TEXT(setup, 2, "strtlan");
  2243. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2244. return rc;
  2245. }
  2246. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2247. int qeth_send_stoplan(struct qeth_card *card)
  2248. {
  2249. int rc = 0;
  2250. /*
  2251. * TODO: according to the IPA format document page 14,
  2252. * TCP/IP (we!) never issue a STOPLAN
  2253. * is this right ?!?
  2254. */
  2255. QETH_DBF_TEXT(setup, 2, "stoplan");
  2256. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2257. return rc;
  2258. }
  2259. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2260. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2261. struct qeth_reply *reply, unsigned long data)
  2262. {
  2263. struct qeth_ipa_cmd *cmd;
  2264. QETH_DBF_TEXT(trace, 4, "defadpcb");
  2265. cmd = (struct qeth_ipa_cmd *) data;
  2266. if (cmd->hdr.return_code == 0)
  2267. cmd->hdr.return_code =
  2268. cmd->data.setadapterparms.hdr.return_code;
  2269. return 0;
  2270. }
  2271. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2272. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2273. struct qeth_reply *reply, unsigned long data)
  2274. {
  2275. struct qeth_ipa_cmd *cmd;
  2276. QETH_DBF_TEXT(trace, 3, "quyadpcb");
  2277. cmd = (struct qeth_ipa_cmd *) data;
  2278. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2279. card->info.link_type =
  2280. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2281. card->options.adp.supported_funcs =
  2282. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2283. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2284. }
  2285. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2286. __u32 command, __u32 cmdlen)
  2287. {
  2288. struct qeth_cmd_buffer *iob;
  2289. struct qeth_ipa_cmd *cmd;
  2290. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2291. QETH_PROT_IPV4);
  2292. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2293. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2294. cmd->data.setadapterparms.hdr.command_code = command;
  2295. cmd->data.setadapterparms.hdr.used_total = 1;
  2296. cmd->data.setadapterparms.hdr.seq_no = 1;
  2297. return iob;
  2298. }
  2299. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2300. int qeth_query_setadapterparms(struct qeth_card *card)
  2301. {
  2302. int rc;
  2303. struct qeth_cmd_buffer *iob;
  2304. QETH_DBF_TEXT(trace, 3, "queryadp");
  2305. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2306. sizeof(struct qeth_ipacmd_setadpparms));
  2307. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2308. return rc;
  2309. }
  2310. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2311. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2312. unsigned int siga_error, const char *dbftext)
  2313. {
  2314. if (qdio_error || siga_error) {
  2315. QETH_DBF_TEXT(trace, 2, dbftext);
  2316. QETH_DBF_TEXT(qerr, 2, dbftext);
  2317. QETH_DBF_TEXT_(qerr, 2, " F15=%02X",
  2318. buf->element[15].flags & 0xff);
  2319. QETH_DBF_TEXT_(qerr, 2, " F14=%02X",
  2320. buf->element[14].flags & 0xff);
  2321. QETH_DBF_TEXT_(qerr, 2, " qerr=%X", qdio_error);
  2322. QETH_DBF_TEXT_(qerr, 2, " serr=%X", siga_error);
  2323. return 1;
  2324. }
  2325. return 0;
  2326. }
  2327. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2328. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2329. {
  2330. struct qeth_qdio_q *queue = card->qdio.in_q;
  2331. int count;
  2332. int i;
  2333. int rc;
  2334. int newcount = 0;
  2335. QETH_DBF_TEXT(trace, 6, "queinbuf");
  2336. count = (index < queue->next_buf_to_init)?
  2337. card->qdio.in_buf_pool.buf_count -
  2338. (queue->next_buf_to_init - index) :
  2339. card->qdio.in_buf_pool.buf_count -
  2340. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2341. /* only requeue at a certain threshold to avoid SIGAs */
  2342. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2343. for (i = queue->next_buf_to_init;
  2344. i < queue->next_buf_to_init + count; ++i) {
  2345. if (qeth_init_input_buffer(card,
  2346. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2347. break;
  2348. } else {
  2349. newcount++;
  2350. }
  2351. }
  2352. if (newcount < count) {
  2353. /* we are in memory shortage so we switch back to
  2354. traditional skb allocation and drop packages */
  2355. if (!atomic_read(&card->force_alloc_skb) &&
  2356. net_ratelimit())
  2357. PRINT_WARN("Switch to alloc skb\n");
  2358. atomic_set(&card->force_alloc_skb, 3);
  2359. count = newcount;
  2360. } else {
  2361. if ((atomic_read(&card->force_alloc_skb) == 1) &&
  2362. net_ratelimit())
  2363. PRINT_WARN("Switch to sg\n");
  2364. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2365. }
  2366. /*
  2367. * according to old code it should be avoided to requeue all
  2368. * 128 buffers in order to benefit from PCI avoidance.
  2369. * this function keeps at least one buffer (the buffer at
  2370. * 'index') un-requeued -> this buffer is the first buffer that
  2371. * will be requeued the next time
  2372. */
  2373. if (card->options.performance_stats) {
  2374. card->perf_stats.inbound_do_qdio_cnt++;
  2375. card->perf_stats.inbound_do_qdio_start_time =
  2376. qeth_get_micros();
  2377. }
  2378. rc = do_QDIO(CARD_DDEV(card),
  2379. QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT,
  2380. 0, queue->next_buf_to_init, count, NULL);
  2381. if (card->options.performance_stats)
  2382. card->perf_stats.inbound_do_qdio_time +=
  2383. qeth_get_micros() -
  2384. card->perf_stats.inbound_do_qdio_start_time;
  2385. if (rc) {
  2386. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2387. "return %i (device %s).\n",
  2388. rc, CARD_DDEV_ID(card));
  2389. QETH_DBF_TEXT(trace, 2, "qinberr");
  2390. QETH_DBF_TEXT_(trace, 2, "%s", CARD_BUS_ID(card));
  2391. }
  2392. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2393. QDIO_MAX_BUFFERS_PER_Q;
  2394. }
  2395. }
  2396. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2397. static int qeth_handle_send_error(struct qeth_card *card,
  2398. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err,
  2399. unsigned int siga_err)
  2400. {
  2401. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2402. int cc = siga_err & 3;
  2403. QETH_DBF_TEXT(trace, 6, "hdsnderr");
  2404. qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr");
  2405. switch (cc) {
  2406. case 0:
  2407. if (qdio_err) {
  2408. QETH_DBF_TEXT(trace, 1, "lnkfail");
  2409. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2410. QETH_DBF_TEXT_(trace, 1, "%04x %02x",
  2411. (u16)qdio_err, (u8)sbalf15);
  2412. return QETH_SEND_ERROR_LINK_FAILURE;
  2413. }
  2414. return QETH_SEND_ERROR_NONE;
  2415. case 2:
  2416. if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) {
  2417. QETH_DBF_TEXT(trace, 1, "SIGAcc2B");
  2418. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2419. return QETH_SEND_ERROR_KICK_IT;
  2420. }
  2421. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2422. return QETH_SEND_ERROR_RETRY;
  2423. return QETH_SEND_ERROR_LINK_FAILURE;
  2424. /* look at qdio_error and sbalf 15 */
  2425. case 1:
  2426. QETH_DBF_TEXT(trace, 1, "SIGAcc1");
  2427. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2428. return QETH_SEND_ERROR_LINK_FAILURE;
  2429. case 3:
  2430. default:
  2431. QETH_DBF_TEXT(trace, 1, "SIGAcc3");
  2432. QETH_DBF_TEXT_(trace, 1, "%s", CARD_BUS_ID(card));
  2433. return QETH_SEND_ERROR_KICK_IT;
  2434. }
  2435. }
  2436. /*
  2437. * Switched to packing state if the number of used buffers on a queue
  2438. * reaches a certain limit.
  2439. */
  2440. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2441. {
  2442. if (!queue->do_pack) {
  2443. if (atomic_read(&queue->used_buffers)
  2444. >= QETH_HIGH_WATERMARK_PACK){
  2445. /* switch non-PACKING -> PACKING */
  2446. QETH_DBF_TEXT(trace, 6, "np->pack");
  2447. if (queue->card->options.performance_stats)
  2448. queue->card->perf_stats.sc_dp_p++;
  2449. queue->do_pack = 1;
  2450. }
  2451. }
  2452. }
  2453. /*
  2454. * Switches from packing to non-packing mode. If there is a packing
  2455. * buffer on the queue this buffer will be prepared to be flushed.
  2456. * In that case 1 is returned to inform the caller. If no buffer
  2457. * has to be flushed, zero is returned.
  2458. */
  2459. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2460. {
  2461. struct qeth_qdio_out_buffer *buffer;
  2462. int flush_count = 0;
  2463. if (queue->do_pack) {
  2464. if (atomic_read(&queue->used_buffers)
  2465. <= QETH_LOW_WATERMARK_PACK) {
  2466. /* switch PACKING -> non-PACKING */
  2467. QETH_DBF_TEXT(trace, 6, "pack->np");
  2468. if (queue->card->options.performance_stats)
  2469. queue->card->perf_stats.sc_p_dp++;
  2470. queue->do_pack = 0;
  2471. /* flush packing buffers */
  2472. buffer = &queue->bufs[queue->next_buf_to_fill];
  2473. if ((atomic_read(&buffer->state) ==
  2474. QETH_QDIO_BUF_EMPTY) &&
  2475. (buffer->next_element_to_fill > 0)) {
  2476. atomic_set(&buffer->state,
  2477. QETH_QDIO_BUF_PRIMED);
  2478. flush_count++;
  2479. queue->next_buf_to_fill =
  2480. (queue->next_buf_to_fill + 1) %
  2481. QDIO_MAX_BUFFERS_PER_Q;
  2482. }
  2483. }
  2484. }
  2485. return flush_count;
  2486. }
  2487. /*
  2488. * Called to flush a packing buffer if no more pci flags are on the queue.
  2489. * Checks if there is a packing buffer and prepares it to be flushed.
  2490. * In that case returns 1, otherwise zero.
  2491. */
  2492. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2493. {
  2494. struct qeth_qdio_out_buffer *buffer;
  2495. buffer = &queue->bufs[queue->next_buf_to_fill];
  2496. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2497. (buffer->next_element_to_fill > 0)) {
  2498. /* it's a packing buffer */
  2499. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2500. queue->next_buf_to_fill =
  2501. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2502. return 1;
  2503. }
  2504. return 0;
  2505. }
  2506. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int,
  2507. int index, int count)
  2508. {
  2509. struct qeth_qdio_out_buffer *buf;
  2510. int rc;
  2511. int i;
  2512. unsigned int qdio_flags;
  2513. QETH_DBF_TEXT(trace, 6, "flushbuf");
  2514. for (i = index; i < index + count; ++i) {
  2515. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2516. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2517. SBAL_FLAGS_LAST_ENTRY;
  2518. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2519. continue;
  2520. if (!queue->do_pack) {
  2521. if ((atomic_read(&queue->used_buffers) >=
  2522. (QETH_HIGH_WATERMARK_PACK -
  2523. QETH_WATERMARK_PACK_FUZZ)) &&
  2524. !atomic_read(&queue->set_pci_flags_count)) {
  2525. /* it's likely that we'll go to packing
  2526. * mode soon */
  2527. atomic_inc(&queue->set_pci_flags_count);
  2528. buf->buffer->element[0].flags |= 0x40;
  2529. }
  2530. } else {
  2531. if (!atomic_read(&queue->set_pci_flags_count)) {
  2532. /*
  2533. * there's no outstanding PCI any more, so we
  2534. * have to request a PCI to be sure the the PCI
  2535. * will wake at some time in the future then we
  2536. * can flush packed buffers that might still be
  2537. * hanging around, which can happen if no
  2538. * further send was requested by the stack
  2539. */
  2540. atomic_inc(&queue->set_pci_flags_count);
  2541. buf->buffer->element[0].flags |= 0x40;
  2542. }
  2543. }
  2544. }
  2545. queue->card->dev->trans_start = jiffies;
  2546. if (queue->card->options.performance_stats) {
  2547. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2548. queue->card->perf_stats.outbound_do_qdio_start_time =
  2549. qeth_get_micros();
  2550. }
  2551. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2552. if (under_int)
  2553. qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT;
  2554. if (atomic_read(&queue->set_pci_flags_count))
  2555. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2556. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2557. queue->queue_no, index, count, NULL);
  2558. if (queue->card->options.performance_stats)
  2559. queue->card->perf_stats.outbound_do_qdio_time +=
  2560. qeth_get_micros() -
  2561. queue->card->perf_stats.outbound_do_qdio_start_time;
  2562. if (rc) {
  2563. QETH_DBF_TEXT(trace, 2, "flushbuf");
  2564. QETH_DBF_TEXT_(trace, 2, " err%d", rc);
  2565. QETH_DBF_TEXT_(trace, 2, "%s", CARD_DDEV_ID(queue->card));
  2566. queue->card->stats.tx_errors += count;
  2567. /* this must not happen under normal circumstances. if it
  2568. * happens something is really wrong -> recover */
  2569. qeth_schedule_recovery(queue->card);
  2570. return;
  2571. }
  2572. atomic_add(count, &queue->used_buffers);
  2573. if (queue->card->options.performance_stats)
  2574. queue->card->perf_stats.bufs_sent += count;
  2575. }
  2576. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2577. {
  2578. int index;
  2579. int flush_cnt = 0;
  2580. int q_was_packing = 0;
  2581. /*
  2582. * check if weed have to switch to non-packing mode or if
  2583. * we have to get a pci flag out on the queue
  2584. */
  2585. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2586. !atomic_read(&queue->set_pci_flags_count)) {
  2587. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2588. QETH_OUT_Q_UNLOCKED) {
  2589. /*
  2590. * If we get in here, there was no action in
  2591. * do_send_packet. So, we check if there is a
  2592. * packing buffer to be flushed here.
  2593. */
  2594. netif_stop_queue(queue->card->dev);
  2595. index = queue->next_buf_to_fill;
  2596. q_was_packing = queue->do_pack;
  2597. /* queue->do_pack may change */
  2598. barrier();
  2599. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2600. if (!flush_cnt &&
  2601. !atomic_read(&queue->set_pci_flags_count))
  2602. flush_cnt +=
  2603. qeth_flush_buffers_on_no_pci(queue);
  2604. if (queue->card->options.performance_stats &&
  2605. q_was_packing)
  2606. queue->card->perf_stats.bufs_sent_pack +=
  2607. flush_cnt;
  2608. if (flush_cnt)
  2609. qeth_flush_buffers(queue, 1, index, flush_cnt);
  2610. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2611. }
  2612. }
  2613. }
  2614. void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status,
  2615. unsigned int qdio_error, unsigned int siga_error,
  2616. unsigned int __queue, int first_element, int count,
  2617. unsigned long card_ptr)
  2618. {
  2619. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2620. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2621. struct qeth_qdio_out_buffer *buffer;
  2622. int i;
  2623. QETH_DBF_TEXT(trace, 6, "qdouhdl");
  2624. if (status & QDIO_STATUS_LOOK_FOR_ERROR) {
  2625. if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) {
  2626. QETH_DBF_TEXT(trace, 2, "achkcond");
  2627. QETH_DBF_TEXT_(trace, 2, "%s", CARD_BUS_ID(card));
  2628. QETH_DBF_TEXT_(trace, 2, "%08x", status);
  2629. netif_stop_queue(card->dev);
  2630. qeth_schedule_recovery(card);
  2631. return;
  2632. }
  2633. }
  2634. if (card->options.performance_stats) {
  2635. card->perf_stats.outbound_handler_cnt++;
  2636. card->perf_stats.outbound_handler_start_time =
  2637. qeth_get_micros();
  2638. }
  2639. for (i = first_element; i < (first_element + count); ++i) {
  2640. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2641. /*we only handle the KICK_IT error by doing a recovery */
  2642. if (qeth_handle_send_error(card, buffer,
  2643. qdio_error, siga_error)
  2644. == QETH_SEND_ERROR_KICK_IT){
  2645. netif_stop_queue(card->dev);
  2646. qeth_schedule_recovery(card);
  2647. return;
  2648. }
  2649. qeth_clear_output_buffer(queue, buffer);
  2650. }
  2651. atomic_sub(count, &queue->used_buffers);
  2652. /* check if we need to do something on this outbound queue */
  2653. if (card->info.type != QETH_CARD_TYPE_IQD)
  2654. qeth_check_outbound_queue(queue);
  2655. netif_wake_queue(queue->card->dev);
  2656. if (card->options.performance_stats)
  2657. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2658. card->perf_stats.outbound_handler_start_time;
  2659. }
  2660. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2661. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2662. {
  2663. int cast_type = RTN_UNSPEC;
  2664. if (card->info.type == QETH_CARD_TYPE_OSN)
  2665. return cast_type;
  2666. if (skb->dst && skb->dst->neighbour) {
  2667. cast_type = skb->dst->neighbour->type;
  2668. if ((cast_type == RTN_BROADCAST) ||
  2669. (cast_type == RTN_MULTICAST) ||
  2670. (cast_type == RTN_ANYCAST))
  2671. return cast_type;
  2672. else
  2673. return RTN_UNSPEC;
  2674. }
  2675. /* try something else */
  2676. if (skb->protocol == ETH_P_IPV6)
  2677. return (skb_network_header(skb)[24] == 0xff) ?
  2678. RTN_MULTICAST : 0;
  2679. else if (skb->protocol == ETH_P_IP)
  2680. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2681. RTN_MULTICAST : 0;
  2682. /* ... */
  2683. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2684. return RTN_BROADCAST;
  2685. else {
  2686. u16 hdr_mac;
  2687. hdr_mac = *((u16 *)skb->data);
  2688. /* tr multicast? */
  2689. switch (card->info.link_type) {
  2690. case QETH_LINK_TYPE_HSTR:
  2691. case QETH_LINK_TYPE_LANE_TR:
  2692. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2693. (hdr_mac == QETH_TR_MAC_C))
  2694. return RTN_MULTICAST;
  2695. break;
  2696. /* eth or so multicast? */
  2697. default:
  2698. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2699. (hdr_mac == QETH_ETH_MAC_V6))
  2700. return RTN_MULTICAST;
  2701. }
  2702. }
  2703. return cast_type;
  2704. }
  2705. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2706. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2707. int ipv, int cast_type)
  2708. {
  2709. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2710. return card->qdio.default_out_queue;
  2711. switch (card->qdio.no_out_queues) {
  2712. case 4:
  2713. if (cast_type && card->info.is_multicast_different)
  2714. return card->info.is_multicast_different &
  2715. (card->qdio.no_out_queues - 1);
  2716. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2717. const u8 tos = ip_hdr(skb)->tos;
  2718. if (card->qdio.do_prio_queueing ==
  2719. QETH_PRIO_Q_ING_TOS) {
  2720. if (tos & IP_TOS_NOTIMPORTANT)
  2721. return 3;
  2722. if (tos & IP_TOS_HIGHRELIABILITY)
  2723. return 2;
  2724. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2725. return 1;
  2726. if (tos & IP_TOS_LOWDELAY)
  2727. return 0;
  2728. }
  2729. if (card->qdio.do_prio_queueing ==
  2730. QETH_PRIO_Q_ING_PREC)
  2731. return 3 - (tos >> 6);
  2732. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2733. /* TODO: IPv6!!! */
  2734. }
  2735. return card->qdio.default_out_queue;
  2736. case 1: /* fallthrough for single-out-queue 1920-device */
  2737. default:
  2738. return card->qdio.default_out_queue;
  2739. }
  2740. }
  2741. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2742. static void __qeth_free_new_skb(struct sk_buff *orig_skb,
  2743. struct sk_buff *new_skb)
  2744. {
  2745. if (orig_skb != new_skb)
  2746. dev_kfree_skb_any(new_skb);
  2747. }
  2748. static inline struct sk_buff *qeth_realloc_headroom(struct qeth_card *card,
  2749. struct sk_buff *skb, int size)
  2750. {
  2751. struct sk_buff *new_skb = skb;
  2752. if (skb_headroom(skb) >= size)
  2753. return skb;
  2754. new_skb = skb_realloc_headroom(skb, size);
  2755. if (!new_skb)
  2756. PRINT_ERR("Could not realloc headroom for qeth_hdr "
  2757. "on interface %s", QETH_CARD_IFNAME(card));
  2758. return new_skb;
  2759. }
  2760. struct sk_buff *qeth_prepare_skb(struct qeth_card *card, struct sk_buff *skb,
  2761. struct qeth_hdr **hdr)
  2762. {
  2763. struct sk_buff *new_skb;
  2764. QETH_DBF_TEXT(trace, 6, "prepskb");
  2765. new_skb = qeth_realloc_headroom(card, skb,
  2766. sizeof(struct qeth_hdr));
  2767. if (!new_skb)
  2768. return NULL;
  2769. *hdr = ((struct qeth_hdr *)qeth_push_skb(card, new_skb,
  2770. sizeof(struct qeth_hdr)));
  2771. if (*hdr == NULL) {
  2772. __qeth_free_new_skb(skb, new_skb);
  2773. return NULL;
  2774. }
  2775. return new_skb;
  2776. }
  2777. EXPORT_SYMBOL_GPL(qeth_prepare_skb);
  2778. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2779. struct sk_buff *skb, int elems)
  2780. {
  2781. int elements_needed = 0;
  2782. if (skb_shinfo(skb)->nr_frags > 0)
  2783. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2784. if (elements_needed == 0)
  2785. elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
  2786. + skb->len) >> PAGE_SHIFT);
  2787. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2788. PRINT_ERR("Invalid size of IP packet "
  2789. "(Number=%d / Length=%d). Discarded.\n",
  2790. (elements_needed+elems), skb->len);
  2791. return 0;
  2792. }
  2793. return elements_needed;
  2794. }
  2795. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2796. static void __qeth_fill_buffer(struct sk_buff *skb, struct qdio_buffer *buffer,
  2797. int is_tso, int *next_element_to_fill)
  2798. {
  2799. int length = skb->len;
  2800. int length_here;
  2801. int element;
  2802. char *data;
  2803. int first_lap ;
  2804. element = *next_element_to_fill;
  2805. data = skb->data;
  2806. first_lap = (is_tso == 0 ? 1 : 0);
  2807. while (length > 0) {
  2808. /* length_here is the remaining amount of data in this page */
  2809. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2810. if (length < length_here)
  2811. length_here = length;
  2812. buffer->element[element].addr = data;
  2813. buffer->element[element].length = length_here;
  2814. length -= length_here;
  2815. if (!length) {
  2816. if (first_lap)
  2817. buffer->element[element].flags = 0;
  2818. else
  2819. buffer->element[element].flags =
  2820. SBAL_FLAGS_LAST_FRAG;
  2821. } else {
  2822. if (first_lap)
  2823. buffer->element[element].flags =
  2824. SBAL_FLAGS_FIRST_FRAG;
  2825. else
  2826. buffer->element[element].flags =
  2827. SBAL_FLAGS_MIDDLE_FRAG;
  2828. }
  2829. data += length_here;
  2830. element++;
  2831. first_lap = 0;
  2832. }
  2833. *next_element_to_fill = element;
  2834. }
  2835. static int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2836. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
  2837. {
  2838. struct qdio_buffer *buffer;
  2839. struct qeth_hdr_tso *hdr;
  2840. int flush_cnt = 0, hdr_len, large_send = 0;
  2841. QETH_DBF_TEXT(trace, 6, "qdfillbf");
  2842. buffer = buf->buffer;
  2843. atomic_inc(&skb->users);
  2844. skb_queue_tail(&buf->skb_list, skb);
  2845. hdr = (struct qeth_hdr_tso *) skb->data;
  2846. /*check first on TSO ....*/
  2847. if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2848. int element = buf->next_element_to_fill;
  2849. hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
  2850. /*fill first buffer entry only with header information */
  2851. buffer->element[element].addr = skb->data;
  2852. buffer->element[element].length = hdr_len;
  2853. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2854. buf->next_element_to_fill++;
  2855. skb->data += hdr_len;
  2856. skb->len -= hdr_len;
  2857. large_send = 1;
  2858. }
  2859. if (skb_shinfo(skb)->nr_frags == 0)
  2860. __qeth_fill_buffer(skb, buffer, large_send,
  2861. (int *)&buf->next_element_to_fill);
  2862. else
  2863. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2864. (int *)&buf->next_element_to_fill);
  2865. if (!queue->do_pack) {
  2866. QETH_DBF_TEXT(trace, 6, "fillbfnp");
  2867. /* set state to PRIMED -> will be flushed */
  2868. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2869. flush_cnt = 1;
  2870. } else {
  2871. QETH_DBF_TEXT(trace, 6, "fillbfpa");
  2872. if (queue->card->options.performance_stats)
  2873. queue->card->perf_stats.skbs_sent_pack++;
  2874. if (buf->next_element_to_fill >=
  2875. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2876. /*
  2877. * packed buffer if full -> set state PRIMED
  2878. * -> will be flushed
  2879. */
  2880. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2881. flush_cnt = 1;
  2882. }
  2883. }
  2884. return flush_cnt;
  2885. }
  2886. int qeth_do_send_packet_fast(struct qeth_card *card,
  2887. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2888. struct qeth_hdr *hdr, int elements_needed,
  2889. struct qeth_eddp_context *ctx)
  2890. {
  2891. struct qeth_qdio_out_buffer *buffer;
  2892. int buffers_needed = 0;
  2893. int flush_cnt = 0;
  2894. int index;
  2895. QETH_DBF_TEXT(trace, 6, "dosndpfa");
  2896. /* spin until we get the queue ... */
  2897. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2898. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2899. /* ... now we've got the queue */
  2900. index = queue->next_buf_to_fill;
  2901. buffer = &queue->bufs[queue->next_buf_to_fill];
  2902. /*
  2903. * check if buffer is empty to make sure that we do not 'overtake'
  2904. * ourselves and try to fill a buffer that is already primed
  2905. */
  2906. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2907. goto out;
  2908. if (ctx == NULL)
  2909. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2910. QDIO_MAX_BUFFERS_PER_Q;
  2911. else {
  2912. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2913. ctx);
  2914. if (buffers_needed < 0)
  2915. goto out;
  2916. queue->next_buf_to_fill =
  2917. (queue->next_buf_to_fill + buffers_needed) %
  2918. QDIO_MAX_BUFFERS_PER_Q;
  2919. }
  2920. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2921. if (ctx == NULL) {
  2922. qeth_fill_buffer(queue, buffer, skb);
  2923. qeth_flush_buffers(queue, 0, index, 1);
  2924. } else {
  2925. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2926. WARN_ON(buffers_needed != flush_cnt);
  2927. qeth_flush_buffers(queue, 0, index, flush_cnt);
  2928. }
  2929. return 0;
  2930. out:
  2931. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2932. return -EBUSY;
  2933. }
  2934. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2935. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2936. struct sk_buff *skb, struct qeth_hdr *hdr,
  2937. int elements_needed, struct qeth_eddp_context *ctx)
  2938. {
  2939. struct qeth_qdio_out_buffer *buffer;
  2940. int start_index;
  2941. int flush_count = 0;
  2942. int do_pack = 0;
  2943. int tmp;
  2944. int rc = 0;
  2945. QETH_DBF_TEXT(trace, 6, "dosndpkt");
  2946. /* spin until we get the queue ... */
  2947. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2948. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2949. start_index = queue->next_buf_to_fill;
  2950. buffer = &queue->bufs[queue->next_buf_to_fill];
  2951. /*
  2952. * check if buffer is empty to make sure that we do not 'overtake'
  2953. * ourselves and try to fill a buffer that is already primed
  2954. */
  2955. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2956. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2957. return -EBUSY;
  2958. }
  2959. /* check if we need to switch packing state of this queue */
  2960. qeth_switch_to_packing_if_needed(queue);
  2961. if (queue->do_pack) {
  2962. do_pack = 1;
  2963. if (ctx == NULL) {
  2964. /* does packet fit in current buffer? */
  2965. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2966. buffer->next_element_to_fill) < elements_needed) {
  2967. /* ... no -> set state PRIMED */
  2968. atomic_set(&buffer->state,
  2969. QETH_QDIO_BUF_PRIMED);
  2970. flush_count++;
  2971. queue->next_buf_to_fill =
  2972. (queue->next_buf_to_fill + 1) %
  2973. QDIO_MAX_BUFFERS_PER_Q;
  2974. buffer = &queue->bufs[queue->next_buf_to_fill];
  2975. /* we did a step forward, so check buffer state
  2976. * again */
  2977. if (atomic_read(&buffer->state) !=
  2978. QETH_QDIO_BUF_EMPTY){
  2979. qeth_flush_buffers(queue, 0,
  2980. start_index, flush_count);
  2981. atomic_set(&queue->state,
  2982. QETH_OUT_Q_UNLOCKED);
  2983. return -EBUSY;
  2984. }
  2985. }
  2986. } else {
  2987. /* check if we have enough elements (including following
  2988. * free buffers) to handle eddp context */
  2989. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2990. < 0) {
  2991. if (net_ratelimit())
  2992. PRINT_WARN("eddp tx_dropped 1\n");
  2993. rc = -EBUSY;
  2994. goto out;
  2995. }
  2996. }
  2997. }
  2998. if (ctx == NULL)
  2999. tmp = qeth_fill_buffer(queue, buffer, skb);
  3000. else {
  3001. tmp = qeth_eddp_fill_buffer(queue, ctx,
  3002. queue->next_buf_to_fill);
  3003. if (tmp < 0) {
  3004. PRINT_ERR("eddp tx_dropped 2\n");
  3005. rc = -EBUSY;
  3006. goto out;
  3007. }
  3008. }
  3009. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3010. QDIO_MAX_BUFFERS_PER_Q;
  3011. flush_count += tmp;
  3012. out:
  3013. if (flush_count)
  3014. qeth_flush_buffers(queue, 0, start_index, flush_count);
  3015. else if (!atomic_read(&queue->set_pci_flags_count))
  3016. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3017. /*
  3018. * queue->state will go from LOCKED -> UNLOCKED or from
  3019. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3020. * (switch packing state or flush buffer to get another pci flag out).
  3021. * In that case we will enter this loop
  3022. */
  3023. while (atomic_dec_return(&queue->state)) {
  3024. flush_count = 0;
  3025. start_index = queue->next_buf_to_fill;
  3026. /* check if we can go back to non-packing state */
  3027. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3028. /*
  3029. * check if we need to flush a packing buffer to get a pci
  3030. * flag out on the queue
  3031. */
  3032. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3033. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3034. if (flush_count)
  3035. qeth_flush_buffers(queue, 0, start_index, flush_count);
  3036. }
  3037. /* at this point the queue is UNLOCKED again */
  3038. if (queue->card->options.performance_stats && do_pack)
  3039. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3040. return rc;
  3041. }
  3042. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3043. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3044. struct qeth_reply *reply, unsigned long data)
  3045. {
  3046. struct qeth_ipa_cmd *cmd;
  3047. struct qeth_ipacmd_setadpparms *setparms;
  3048. QETH_DBF_TEXT(trace, 4, "prmadpcb");
  3049. cmd = (struct qeth_ipa_cmd *) data;
  3050. setparms = &(cmd->data.setadapterparms);
  3051. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3052. if (cmd->hdr.return_code) {
  3053. QETH_DBF_TEXT_(trace, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3054. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3055. }
  3056. card->info.promisc_mode = setparms->data.mode;
  3057. return 0;
  3058. }
  3059. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3060. {
  3061. enum qeth_ipa_promisc_modes mode;
  3062. struct net_device *dev = card->dev;
  3063. struct qeth_cmd_buffer *iob;
  3064. struct qeth_ipa_cmd *cmd;
  3065. QETH_DBF_TEXT(trace, 4, "setprom");
  3066. if (((dev->flags & IFF_PROMISC) &&
  3067. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3068. (!(dev->flags & IFF_PROMISC) &&
  3069. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3070. return;
  3071. mode = SET_PROMISC_MODE_OFF;
  3072. if (dev->flags & IFF_PROMISC)
  3073. mode = SET_PROMISC_MODE_ON;
  3074. QETH_DBF_TEXT_(trace, 4, "mode:%x", mode);
  3075. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3076. sizeof(struct qeth_ipacmd_setadpparms));
  3077. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3078. cmd->data.setadapterparms.data.mode = mode;
  3079. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3080. }
  3081. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3082. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3083. {
  3084. struct qeth_card *card;
  3085. char dbf_text[15];
  3086. card = netdev_priv(dev);
  3087. QETH_DBF_TEXT(trace, 4, "chgmtu");
  3088. sprintf(dbf_text, "%8x", new_mtu);
  3089. QETH_DBF_TEXT(trace, 4, dbf_text);
  3090. if (new_mtu < 64)
  3091. return -EINVAL;
  3092. if (new_mtu > 65535)
  3093. return -EINVAL;
  3094. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3095. (!qeth_mtu_is_valid(card, new_mtu)))
  3096. return -EINVAL;
  3097. dev->mtu = new_mtu;
  3098. return 0;
  3099. }
  3100. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3101. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3102. {
  3103. struct qeth_card *card;
  3104. card = netdev_priv(dev);
  3105. QETH_DBF_TEXT(trace, 5, "getstat");
  3106. return &card->stats;
  3107. }
  3108. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3109. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3110. struct qeth_reply *reply, unsigned long data)
  3111. {
  3112. struct qeth_ipa_cmd *cmd;
  3113. QETH_DBF_TEXT(trace, 4, "chgmaccb");
  3114. cmd = (struct qeth_ipa_cmd *) data;
  3115. if (!card->options.layer2 ||
  3116. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3117. memcpy(card->dev->dev_addr,
  3118. &cmd->data.setadapterparms.data.change_addr.addr,
  3119. OSA_ADDR_LEN);
  3120. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3121. }
  3122. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3123. return 0;
  3124. }
  3125. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3126. {
  3127. int rc;
  3128. struct qeth_cmd_buffer *iob;
  3129. struct qeth_ipa_cmd *cmd;
  3130. QETH_DBF_TEXT(trace, 4, "chgmac");
  3131. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3132. sizeof(struct qeth_ipacmd_setadpparms));
  3133. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3134. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3135. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3136. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3137. card->dev->dev_addr, OSA_ADDR_LEN);
  3138. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3139. NULL);
  3140. return rc;
  3141. }
  3142. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3143. void qeth_tx_timeout(struct net_device *dev)
  3144. {
  3145. struct qeth_card *card;
  3146. card = netdev_priv(dev);
  3147. card->stats.tx_errors++;
  3148. qeth_schedule_recovery(card);
  3149. }
  3150. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3151. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3152. {
  3153. struct qeth_card *card = netdev_priv(dev);
  3154. int rc = 0;
  3155. switch (regnum) {
  3156. case MII_BMCR: /* Basic mode control register */
  3157. rc = BMCR_FULLDPLX;
  3158. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3159. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3160. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3161. rc |= BMCR_SPEED100;
  3162. break;
  3163. case MII_BMSR: /* Basic mode status register */
  3164. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3165. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3166. BMSR_100BASE4;
  3167. break;
  3168. case MII_PHYSID1: /* PHYS ID 1 */
  3169. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3170. dev->dev_addr[2];
  3171. rc = (rc >> 5) & 0xFFFF;
  3172. break;
  3173. case MII_PHYSID2: /* PHYS ID 2 */
  3174. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3175. break;
  3176. case MII_ADVERTISE: /* Advertisement control reg */
  3177. rc = ADVERTISE_ALL;
  3178. break;
  3179. case MII_LPA: /* Link partner ability reg */
  3180. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3181. LPA_100BASE4 | LPA_LPACK;
  3182. break;
  3183. case MII_EXPANSION: /* Expansion register */
  3184. break;
  3185. case MII_DCOUNTER: /* disconnect counter */
  3186. break;
  3187. case MII_FCSCOUNTER: /* false carrier counter */
  3188. break;
  3189. case MII_NWAYTEST: /* N-way auto-neg test register */
  3190. break;
  3191. case MII_RERRCOUNTER: /* rx error counter */
  3192. rc = card->stats.rx_errors;
  3193. break;
  3194. case MII_SREVISION: /* silicon revision */
  3195. break;
  3196. case MII_RESV1: /* reserved 1 */
  3197. break;
  3198. case MII_LBRERROR: /* loopback, rx, bypass error */
  3199. break;
  3200. case MII_PHYADDR: /* physical address */
  3201. break;
  3202. case MII_RESV2: /* reserved 2 */
  3203. break;
  3204. case MII_TPISTATUS: /* TPI status for 10mbps */
  3205. break;
  3206. case MII_NCONFIG: /* network interface config */
  3207. break;
  3208. default:
  3209. break;
  3210. }
  3211. return rc;
  3212. }
  3213. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3214. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3215. struct qeth_cmd_buffer *iob, int len,
  3216. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3217. unsigned long),
  3218. void *reply_param)
  3219. {
  3220. u16 s1, s2;
  3221. QETH_DBF_TEXT(trace, 4, "sendsnmp");
  3222. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3223. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3224. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3225. /* adjust PDU length fields in IPA_PDU_HEADER */
  3226. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3227. s2 = (u32) len;
  3228. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3229. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3230. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3231. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3232. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3233. reply_cb, reply_param);
  3234. }
  3235. static int qeth_snmp_command_cb(struct qeth_card *card,
  3236. struct qeth_reply *reply, unsigned long sdata)
  3237. {
  3238. struct qeth_ipa_cmd *cmd;
  3239. struct qeth_arp_query_info *qinfo;
  3240. struct qeth_snmp_cmd *snmp;
  3241. unsigned char *data;
  3242. __u16 data_len;
  3243. QETH_DBF_TEXT(trace, 3, "snpcmdcb");
  3244. cmd = (struct qeth_ipa_cmd *) sdata;
  3245. data = (unsigned char *)((char *)cmd - reply->offset);
  3246. qinfo = (struct qeth_arp_query_info *) reply->param;
  3247. snmp = &cmd->data.setadapterparms.data.snmp;
  3248. if (cmd->hdr.return_code) {
  3249. QETH_DBF_TEXT_(trace, 4, "scer1%i", cmd->hdr.return_code);
  3250. return 0;
  3251. }
  3252. if (cmd->data.setadapterparms.hdr.return_code) {
  3253. cmd->hdr.return_code =
  3254. cmd->data.setadapterparms.hdr.return_code;
  3255. QETH_DBF_TEXT_(trace, 4, "scer2%i", cmd->hdr.return_code);
  3256. return 0;
  3257. }
  3258. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3259. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3260. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3261. else
  3262. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3263. /* check if there is enough room in userspace */
  3264. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3265. QETH_DBF_TEXT_(trace, 4, "scer3%i", -ENOMEM);
  3266. cmd->hdr.return_code = -ENOMEM;
  3267. return 0;
  3268. }
  3269. QETH_DBF_TEXT_(trace, 4, "snore%i",
  3270. cmd->data.setadapterparms.hdr.used_total);
  3271. QETH_DBF_TEXT_(trace, 4, "sseqn%i",
  3272. cmd->data.setadapterparms.hdr.seq_no);
  3273. /*copy entries to user buffer*/
  3274. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3275. memcpy(qinfo->udata + qinfo->udata_offset,
  3276. (char *)snmp,
  3277. data_len + offsetof(struct qeth_snmp_cmd, data));
  3278. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3279. } else {
  3280. memcpy(qinfo->udata + qinfo->udata_offset,
  3281. (char *)&snmp->request, data_len);
  3282. }
  3283. qinfo->udata_offset += data_len;
  3284. /* check if all replies received ... */
  3285. QETH_DBF_TEXT_(trace, 4, "srtot%i",
  3286. cmd->data.setadapterparms.hdr.used_total);
  3287. QETH_DBF_TEXT_(trace, 4, "srseq%i",
  3288. cmd->data.setadapterparms.hdr.seq_no);
  3289. if (cmd->data.setadapterparms.hdr.seq_no <
  3290. cmd->data.setadapterparms.hdr.used_total)
  3291. return 1;
  3292. return 0;
  3293. }
  3294. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3295. {
  3296. struct qeth_cmd_buffer *iob;
  3297. struct qeth_ipa_cmd *cmd;
  3298. struct qeth_snmp_ureq *ureq;
  3299. int req_len;
  3300. struct qeth_arp_query_info qinfo = {0, };
  3301. int rc = 0;
  3302. QETH_DBF_TEXT(trace, 3, "snmpcmd");
  3303. if (card->info.guestlan)
  3304. return -EOPNOTSUPP;
  3305. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3306. (!card->options.layer2)) {
  3307. PRINT_WARN("SNMP Query MIBS not supported "
  3308. "on %s!\n", QETH_CARD_IFNAME(card));
  3309. return -EOPNOTSUPP;
  3310. }
  3311. /* skip 4 bytes (data_len struct member) to get req_len */
  3312. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3313. return -EFAULT;
  3314. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3315. if (!ureq) {
  3316. QETH_DBF_TEXT(trace, 2, "snmpnome");
  3317. return -ENOMEM;
  3318. }
  3319. if (copy_from_user(ureq, udata,
  3320. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3321. kfree(ureq);
  3322. return -EFAULT;
  3323. }
  3324. qinfo.udata_len = ureq->hdr.data_len;
  3325. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3326. if (!qinfo.udata) {
  3327. kfree(ureq);
  3328. return -ENOMEM;
  3329. }
  3330. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3331. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3332. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3333. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3334. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3335. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3336. qeth_snmp_command_cb, (void *)&qinfo);
  3337. if (rc)
  3338. PRINT_WARN("SNMP command failed on %s: (0x%x)\n",
  3339. QETH_CARD_IFNAME(card), rc);
  3340. else {
  3341. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3342. rc = -EFAULT;
  3343. }
  3344. kfree(ureq);
  3345. kfree(qinfo.udata);
  3346. return rc;
  3347. }
  3348. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3349. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3350. {
  3351. switch (card->info.type) {
  3352. case QETH_CARD_TYPE_IQD:
  3353. return 2;
  3354. default:
  3355. return 0;
  3356. }
  3357. }
  3358. static int qeth_qdio_establish(struct qeth_card *card)
  3359. {
  3360. struct qdio_initialize init_data;
  3361. char *qib_param_field;
  3362. struct qdio_buffer **in_sbal_ptrs;
  3363. struct qdio_buffer **out_sbal_ptrs;
  3364. int i, j, k;
  3365. int rc = 0;
  3366. QETH_DBF_TEXT(setup, 2, "qdioest");
  3367. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3368. GFP_KERNEL);
  3369. if (!qib_param_field)
  3370. return -ENOMEM;
  3371. qeth_create_qib_param_field(card, qib_param_field);
  3372. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3373. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3374. GFP_KERNEL);
  3375. if (!in_sbal_ptrs) {
  3376. kfree(qib_param_field);
  3377. return -ENOMEM;
  3378. }
  3379. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3380. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3381. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3382. out_sbal_ptrs =
  3383. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3384. sizeof(void *), GFP_KERNEL);
  3385. if (!out_sbal_ptrs) {
  3386. kfree(in_sbal_ptrs);
  3387. kfree(qib_param_field);
  3388. return -ENOMEM;
  3389. }
  3390. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3391. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3392. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3393. card->qdio.out_qs[i]->bufs[j].buffer);
  3394. }
  3395. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3396. init_data.cdev = CARD_DDEV(card);
  3397. init_data.q_format = qeth_get_qdio_q_format(card);
  3398. init_data.qib_param_field_format = 0;
  3399. init_data.qib_param_field = qib_param_field;
  3400. init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD;
  3401. init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD;
  3402. init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD;
  3403. init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD;
  3404. init_data.no_input_qs = 1;
  3405. init_data.no_output_qs = card->qdio.no_out_queues;
  3406. init_data.input_handler = card->discipline.input_handler;
  3407. init_data.output_handler = card->discipline.output_handler;
  3408. init_data.int_parm = (unsigned long) card;
  3409. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3410. QDIO_OUTBOUND_0COPY_SBALS |
  3411. QDIO_USE_OUTBOUND_PCIS;
  3412. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3413. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3414. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3415. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3416. rc = qdio_initialize(&init_data);
  3417. if (rc)
  3418. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3419. }
  3420. kfree(out_sbal_ptrs);
  3421. kfree(in_sbal_ptrs);
  3422. kfree(qib_param_field);
  3423. return rc;
  3424. }
  3425. static void qeth_core_free_card(struct qeth_card *card)
  3426. {
  3427. QETH_DBF_TEXT(setup, 2, "freecrd");
  3428. QETH_DBF_HEX(setup, 2, &card, sizeof(void *));
  3429. qeth_clean_channel(&card->read);
  3430. qeth_clean_channel(&card->write);
  3431. if (card->dev)
  3432. free_netdev(card->dev);
  3433. kfree(card->ip_tbd_list);
  3434. qeth_free_qdio_buffers(card);
  3435. kfree(card);
  3436. }
  3437. static struct ccw_device_id qeth_ids[] = {
  3438. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3439. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3440. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3441. {},
  3442. };
  3443. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3444. static struct ccw_driver qeth_ccw_driver = {
  3445. .name = "qeth",
  3446. .ids = qeth_ids,
  3447. .probe = ccwgroup_probe_ccwdev,
  3448. .remove = ccwgroup_remove_ccwdev,
  3449. };
  3450. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3451. unsigned long driver_id)
  3452. {
  3453. const char *start, *end;
  3454. char bus_ids[3][BUS_ID_SIZE], *argv[3];
  3455. int i;
  3456. start = buf;
  3457. for (i = 0; i < 3; i++) {
  3458. static const char delim[] = { ',', ',', '\n' };
  3459. int len;
  3460. end = strchr(start, delim[i]);
  3461. if (!end)
  3462. return -EINVAL;
  3463. len = min_t(ptrdiff_t, BUS_ID_SIZE, end - start);
  3464. strncpy(bus_ids[i], start, len);
  3465. bus_ids[i][len] = '\0';
  3466. start = end + 1;
  3467. argv[i] = bus_ids[i];
  3468. }
  3469. return (ccwgroup_create(root_dev, driver_id,
  3470. &qeth_ccw_driver, 3, argv));
  3471. }
  3472. int qeth_core_hardsetup_card(struct qeth_card *card)
  3473. {
  3474. int retries = 3;
  3475. int mpno;
  3476. int rc;
  3477. QETH_DBF_TEXT(setup, 2, "hrdsetup");
  3478. atomic_set(&card->force_alloc_skb, 0);
  3479. retry:
  3480. if (retries < 3) {
  3481. PRINT_WARN("Retrying to do IDX activates.\n");
  3482. ccw_device_set_offline(CARD_DDEV(card));
  3483. ccw_device_set_offline(CARD_WDEV(card));
  3484. ccw_device_set_offline(CARD_RDEV(card));
  3485. ccw_device_set_online(CARD_RDEV(card));
  3486. ccw_device_set_online(CARD_WDEV(card));
  3487. ccw_device_set_online(CARD_DDEV(card));
  3488. }
  3489. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3490. if (rc == -ERESTARTSYS) {
  3491. QETH_DBF_TEXT(setup, 2, "break1");
  3492. return rc;
  3493. } else if (rc) {
  3494. QETH_DBF_TEXT_(setup, 2, "1err%d", rc);
  3495. if (--retries < 0)
  3496. goto out;
  3497. else
  3498. goto retry;
  3499. }
  3500. rc = qeth_get_unitaddr(card);
  3501. if (rc) {
  3502. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  3503. return rc;
  3504. }
  3505. mpno = QETH_MAX_PORTNO;
  3506. if (card->info.portno > mpno) {
  3507. PRINT_ERR("Device %s does not offer port number %d \n.",
  3508. CARD_BUS_ID(card), card->info.portno);
  3509. rc = -ENODEV;
  3510. goto out;
  3511. }
  3512. qeth_init_tokens(card);
  3513. qeth_init_func_level(card);
  3514. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3515. if (rc == -ERESTARTSYS) {
  3516. QETH_DBF_TEXT(setup, 2, "break2");
  3517. return rc;
  3518. } else if (rc) {
  3519. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  3520. if (--retries < 0)
  3521. goto out;
  3522. else
  3523. goto retry;
  3524. }
  3525. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3526. if (rc == -ERESTARTSYS) {
  3527. QETH_DBF_TEXT(setup, 2, "break3");
  3528. return rc;
  3529. } else if (rc) {
  3530. QETH_DBF_TEXT_(setup, 2, "4err%d", rc);
  3531. if (--retries < 0)
  3532. goto out;
  3533. else
  3534. goto retry;
  3535. }
  3536. rc = qeth_mpc_initialize(card);
  3537. if (rc) {
  3538. QETH_DBF_TEXT_(setup, 2, "5err%d", rc);
  3539. goto out;
  3540. }
  3541. return 0;
  3542. out:
  3543. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3544. return rc;
  3545. }
  3546. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3547. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3548. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3549. {
  3550. struct page *page = virt_to_page(element->addr);
  3551. if (*pskb == NULL) {
  3552. /* the upper protocol layers assume that there is data in the
  3553. * skb itself. Copy a small amount (64 bytes) to make them
  3554. * happy. */
  3555. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3556. if (!(*pskb))
  3557. return -ENOMEM;
  3558. skb_reserve(*pskb, ETH_HLEN);
  3559. if (data_len <= 64) {
  3560. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3561. data_len);
  3562. } else {
  3563. get_page(page);
  3564. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3565. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3566. data_len - 64);
  3567. (*pskb)->data_len += data_len - 64;
  3568. (*pskb)->len += data_len - 64;
  3569. (*pskb)->truesize += data_len - 64;
  3570. (*pfrag)++;
  3571. }
  3572. } else {
  3573. get_page(page);
  3574. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3575. (*pskb)->data_len += data_len;
  3576. (*pskb)->len += data_len;
  3577. (*pskb)->truesize += data_len;
  3578. (*pfrag)++;
  3579. }
  3580. return 0;
  3581. }
  3582. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3583. struct qdio_buffer *buffer,
  3584. struct qdio_buffer_element **__element, int *__offset,
  3585. struct qeth_hdr **hdr)
  3586. {
  3587. struct qdio_buffer_element *element = *__element;
  3588. int offset = *__offset;
  3589. struct sk_buff *skb = NULL;
  3590. int skb_len;
  3591. void *data_ptr;
  3592. int data_len;
  3593. int headroom = 0;
  3594. int use_rx_sg = 0;
  3595. int frag = 0;
  3596. QETH_DBF_TEXT(trace, 6, "nextskb");
  3597. /* qeth_hdr must not cross element boundaries */
  3598. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3599. if (qeth_is_last_sbale(element))
  3600. return NULL;
  3601. element++;
  3602. offset = 0;
  3603. if (element->length < sizeof(struct qeth_hdr))
  3604. return NULL;
  3605. }
  3606. *hdr = element->addr + offset;
  3607. offset += sizeof(struct qeth_hdr);
  3608. if (card->options.layer2) {
  3609. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3610. skb_len = (*hdr)->hdr.osn.pdu_length;
  3611. headroom = sizeof(struct qeth_hdr);
  3612. } else {
  3613. skb_len = (*hdr)->hdr.l2.pkt_length;
  3614. }
  3615. } else {
  3616. skb_len = (*hdr)->hdr.l3.length;
  3617. headroom = max((int)ETH_HLEN, (int)TR_HLEN);
  3618. }
  3619. if (!skb_len)
  3620. return NULL;
  3621. if ((skb_len >= card->options.rx_sg_cb) &&
  3622. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3623. (!atomic_read(&card->force_alloc_skb))) {
  3624. use_rx_sg = 1;
  3625. } else {
  3626. skb = dev_alloc_skb(skb_len + headroom);
  3627. if (!skb)
  3628. goto no_mem;
  3629. if (headroom)
  3630. skb_reserve(skb, headroom);
  3631. }
  3632. data_ptr = element->addr + offset;
  3633. while (skb_len) {
  3634. data_len = min(skb_len, (int)(element->length - offset));
  3635. if (data_len) {
  3636. if (use_rx_sg) {
  3637. if (qeth_create_skb_frag(element, &skb, offset,
  3638. &frag, data_len))
  3639. goto no_mem;
  3640. } else {
  3641. memcpy(skb_put(skb, data_len), data_ptr,
  3642. data_len);
  3643. }
  3644. }
  3645. skb_len -= data_len;
  3646. if (skb_len) {
  3647. if (qeth_is_last_sbale(element)) {
  3648. QETH_DBF_TEXT(trace, 4, "unexeob");
  3649. QETH_DBF_TEXT_(trace, 4, "%s",
  3650. CARD_BUS_ID(card));
  3651. QETH_DBF_TEXT(qerr, 2, "unexeob");
  3652. QETH_DBF_TEXT_(qerr, 2, "%s",
  3653. CARD_BUS_ID(card));
  3654. QETH_DBF_HEX(misc, 4, buffer, sizeof(*buffer));
  3655. dev_kfree_skb_any(skb);
  3656. card->stats.rx_errors++;
  3657. return NULL;
  3658. }
  3659. element++;
  3660. offset = 0;
  3661. data_ptr = element->addr;
  3662. } else {
  3663. offset += data_len;
  3664. }
  3665. }
  3666. *__element = element;
  3667. *__offset = offset;
  3668. if (use_rx_sg && card->options.performance_stats) {
  3669. card->perf_stats.sg_skbs_rx++;
  3670. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3671. }
  3672. return skb;
  3673. no_mem:
  3674. if (net_ratelimit()) {
  3675. PRINT_WARN("No memory for packet received on %s.\n",
  3676. QETH_CARD_IFNAME(card));
  3677. QETH_DBF_TEXT(trace, 2, "noskbmem");
  3678. QETH_DBF_TEXT_(trace, 2, "%s", CARD_BUS_ID(card));
  3679. }
  3680. card->stats.rx_dropped++;
  3681. return NULL;
  3682. }
  3683. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3684. static void qeth_unregister_dbf_views(void)
  3685. {
  3686. if (qeth_dbf_setup)
  3687. debug_unregister(qeth_dbf_setup);
  3688. if (qeth_dbf_qerr)
  3689. debug_unregister(qeth_dbf_qerr);
  3690. if (qeth_dbf_sense)
  3691. debug_unregister(qeth_dbf_sense);
  3692. if (qeth_dbf_misc)
  3693. debug_unregister(qeth_dbf_misc);
  3694. if (qeth_dbf_data)
  3695. debug_unregister(qeth_dbf_data);
  3696. if (qeth_dbf_control)
  3697. debug_unregister(qeth_dbf_control);
  3698. if (qeth_dbf_trace)
  3699. debug_unregister(qeth_dbf_trace);
  3700. }
  3701. static int qeth_register_dbf_views(void)
  3702. {
  3703. qeth_dbf_setup = debug_register(QETH_DBF_SETUP_NAME,
  3704. QETH_DBF_SETUP_PAGES,
  3705. QETH_DBF_SETUP_NR_AREAS,
  3706. QETH_DBF_SETUP_LEN);
  3707. qeth_dbf_misc = debug_register(QETH_DBF_MISC_NAME,
  3708. QETH_DBF_MISC_PAGES,
  3709. QETH_DBF_MISC_NR_AREAS,
  3710. QETH_DBF_MISC_LEN);
  3711. qeth_dbf_data = debug_register(QETH_DBF_DATA_NAME,
  3712. QETH_DBF_DATA_PAGES,
  3713. QETH_DBF_DATA_NR_AREAS,
  3714. QETH_DBF_DATA_LEN);
  3715. qeth_dbf_control = debug_register(QETH_DBF_CONTROL_NAME,
  3716. QETH_DBF_CONTROL_PAGES,
  3717. QETH_DBF_CONTROL_NR_AREAS,
  3718. QETH_DBF_CONTROL_LEN);
  3719. qeth_dbf_sense = debug_register(QETH_DBF_SENSE_NAME,
  3720. QETH_DBF_SENSE_PAGES,
  3721. QETH_DBF_SENSE_NR_AREAS,
  3722. QETH_DBF_SENSE_LEN);
  3723. qeth_dbf_qerr = debug_register(QETH_DBF_QERR_NAME,
  3724. QETH_DBF_QERR_PAGES,
  3725. QETH_DBF_QERR_NR_AREAS,
  3726. QETH_DBF_QERR_LEN);
  3727. qeth_dbf_trace = debug_register(QETH_DBF_TRACE_NAME,
  3728. QETH_DBF_TRACE_PAGES,
  3729. QETH_DBF_TRACE_NR_AREAS,
  3730. QETH_DBF_TRACE_LEN);
  3731. if ((qeth_dbf_setup == NULL) || (qeth_dbf_misc == NULL) ||
  3732. (qeth_dbf_data == NULL) || (qeth_dbf_control == NULL) ||
  3733. (qeth_dbf_sense == NULL) || (qeth_dbf_qerr == NULL) ||
  3734. (qeth_dbf_trace == NULL)) {
  3735. qeth_unregister_dbf_views();
  3736. return -ENOMEM;
  3737. }
  3738. debug_register_view(qeth_dbf_setup, &debug_hex_ascii_view);
  3739. debug_set_level(qeth_dbf_setup, QETH_DBF_SETUP_LEVEL);
  3740. debug_register_view(qeth_dbf_misc, &debug_hex_ascii_view);
  3741. debug_set_level(qeth_dbf_misc, QETH_DBF_MISC_LEVEL);
  3742. debug_register_view(qeth_dbf_data, &debug_hex_ascii_view);
  3743. debug_set_level(qeth_dbf_data, QETH_DBF_DATA_LEVEL);
  3744. debug_register_view(qeth_dbf_control, &debug_hex_ascii_view);
  3745. debug_set_level(qeth_dbf_control, QETH_DBF_CONTROL_LEVEL);
  3746. debug_register_view(qeth_dbf_sense, &debug_hex_ascii_view);
  3747. debug_set_level(qeth_dbf_sense, QETH_DBF_SENSE_LEVEL);
  3748. debug_register_view(qeth_dbf_qerr, &debug_hex_ascii_view);
  3749. debug_set_level(qeth_dbf_qerr, QETH_DBF_QERR_LEVEL);
  3750. debug_register_view(qeth_dbf_trace, &debug_hex_ascii_view);
  3751. debug_set_level(qeth_dbf_trace, QETH_DBF_TRACE_LEVEL);
  3752. return 0;
  3753. }
  3754. int qeth_core_load_discipline(struct qeth_card *card,
  3755. enum qeth_discipline_id discipline)
  3756. {
  3757. int rc = 0;
  3758. switch (discipline) {
  3759. case QETH_DISCIPLINE_LAYER3:
  3760. card->discipline.ccwgdriver = try_then_request_module(
  3761. symbol_get(qeth_l3_ccwgroup_driver),
  3762. "qeth_l3");
  3763. break;
  3764. case QETH_DISCIPLINE_LAYER2:
  3765. card->discipline.ccwgdriver = try_then_request_module(
  3766. symbol_get(qeth_l2_ccwgroup_driver),
  3767. "qeth_l2");
  3768. break;
  3769. }
  3770. if (!card->discipline.ccwgdriver) {
  3771. PRINT_ERR("Support for discipline %d not present\n",
  3772. discipline);
  3773. rc = -EINVAL;
  3774. }
  3775. return rc;
  3776. }
  3777. void qeth_core_free_discipline(struct qeth_card *card)
  3778. {
  3779. if (card->options.layer2)
  3780. symbol_put(qeth_l2_ccwgroup_driver);
  3781. else
  3782. symbol_put(qeth_l3_ccwgroup_driver);
  3783. card->discipline.ccwgdriver = NULL;
  3784. }
  3785. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3786. {
  3787. struct qeth_card *card;
  3788. struct device *dev;
  3789. int rc;
  3790. unsigned long flags;
  3791. QETH_DBF_TEXT(setup, 2, "probedev");
  3792. dev = &gdev->dev;
  3793. if (!get_device(dev))
  3794. return -ENODEV;
  3795. QETH_DBF_TEXT_(setup, 2, "%s", gdev->dev.bus_id);
  3796. card = qeth_alloc_card();
  3797. if (!card) {
  3798. QETH_DBF_TEXT_(setup, 2, "1err%d", -ENOMEM);
  3799. rc = -ENOMEM;
  3800. goto err_dev;
  3801. }
  3802. card->read.ccwdev = gdev->cdev[0];
  3803. card->write.ccwdev = gdev->cdev[1];
  3804. card->data.ccwdev = gdev->cdev[2];
  3805. dev_set_drvdata(&gdev->dev, card);
  3806. card->gdev = gdev;
  3807. gdev->cdev[0]->handler = qeth_irq;
  3808. gdev->cdev[1]->handler = qeth_irq;
  3809. gdev->cdev[2]->handler = qeth_irq;
  3810. rc = qeth_determine_card_type(card);
  3811. if (rc) {
  3812. PRINT_WARN("%s: not a valid card type\n", __func__);
  3813. QETH_DBF_TEXT_(setup, 2, "3err%d", rc);
  3814. goto err_card;
  3815. }
  3816. rc = qeth_setup_card(card);
  3817. if (rc) {
  3818. QETH_DBF_TEXT_(setup, 2, "2err%d", rc);
  3819. goto err_card;
  3820. }
  3821. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3822. rc = qeth_core_create_osn_attributes(dev);
  3823. if (rc)
  3824. goto err_card;
  3825. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3826. if (rc) {
  3827. qeth_core_remove_osn_attributes(dev);
  3828. goto err_card;
  3829. }
  3830. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3831. if (rc) {
  3832. qeth_core_free_discipline(card);
  3833. qeth_core_remove_osn_attributes(dev);
  3834. goto err_card;
  3835. }
  3836. } else {
  3837. rc = qeth_core_create_device_attributes(dev);
  3838. if (rc)
  3839. goto err_card;
  3840. }
  3841. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3842. list_add_tail(&card->list, &qeth_core_card_list.list);
  3843. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3844. return 0;
  3845. err_card:
  3846. qeth_core_free_card(card);
  3847. err_dev:
  3848. put_device(dev);
  3849. return rc;
  3850. }
  3851. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3852. {
  3853. unsigned long flags;
  3854. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3855. if (card->discipline.ccwgdriver) {
  3856. card->discipline.ccwgdriver->remove(gdev);
  3857. qeth_core_free_discipline(card);
  3858. }
  3859. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3860. qeth_core_remove_osn_attributes(&gdev->dev);
  3861. } else {
  3862. qeth_core_remove_device_attributes(&gdev->dev);
  3863. }
  3864. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3865. list_del(&card->list);
  3866. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3867. qeth_core_free_card(card);
  3868. dev_set_drvdata(&gdev->dev, NULL);
  3869. put_device(&gdev->dev);
  3870. return;
  3871. }
  3872. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3873. {
  3874. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3875. int rc = 0;
  3876. int def_discipline;
  3877. if (!card->discipline.ccwgdriver) {
  3878. if (card->info.type == QETH_CARD_TYPE_IQD)
  3879. def_discipline = QETH_DISCIPLINE_LAYER3;
  3880. else
  3881. def_discipline = QETH_DISCIPLINE_LAYER2;
  3882. rc = qeth_core_load_discipline(card, def_discipline);
  3883. if (rc)
  3884. goto err;
  3885. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3886. if (rc)
  3887. goto err;
  3888. }
  3889. rc = card->discipline.ccwgdriver->set_online(gdev);
  3890. err:
  3891. return rc;
  3892. }
  3893. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3894. {
  3895. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3896. return card->discipline.ccwgdriver->set_offline(gdev);
  3897. }
  3898. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3899. {
  3900. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3901. if (card->discipline.ccwgdriver &&
  3902. card->discipline.ccwgdriver->shutdown)
  3903. card->discipline.ccwgdriver->shutdown(gdev);
  3904. }
  3905. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3906. .owner = THIS_MODULE,
  3907. .name = "qeth",
  3908. .driver_id = 0xD8C5E3C8,
  3909. .probe = qeth_core_probe_device,
  3910. .remove = qeth_core_remove_device,
  3911. .set_online = qeth_core_set_online,
  3912. .set_offline = qeth_core_set_offline,
  3913. .shutdown = qeth_core_shutdown,
  3914. };
  3915. static ssize_t
  3916. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3917. size_t count)
  3918. {
  3919. int err;
  3920. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3921. qeth_core_ccwgroup_driver.driver_id);
  3922. if (err)
  3923. return err;
  3924. else
  3925. return count;
  3926. }
  3927. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3928. static struct {
  3929. const char str[ETH_GSTRING_LEN];
  3930. } qeth_ethtool_stats_keys[] = {
  3931. /* 0 */{"rx skbs"},
  3932. {"rx buffers"},
  3933. {"tx skbs"},
  3934. {"tx buffers"},
  3935. {"tx skbs no packing"},
  3936. {"tx buffers no packing"},
  3937. {"tx skbs packing"},
  3938. {"tx buffers packing"},
  3939. {"tx sg skbs"},
  3940. {"tx sg frags"},
  3941. /* 10 */{"rx sg skbs"},
  3942. {"rx sg frags"},
  3943. {"rx sg page allocs"},
  3944. {"tx large kbytes"},
  3945. {"tx large count"},
  3946. {"tx pk state ch n->p"},
  3947. {"tx pk state ch p->n"},
  3948. {"tx pk watermark low"},
  3949. {"tx pk watermark high"},
  3950. {"queue 0 buffer usage"},
  3951. /* 20 */{"queue 1 buffer usage"},
  3952. {"queue 2 buffer usage"},
  3953. {"queue 3 buffer usage"},
  3954. {"rx handler time"},
  3955. {"rx handler count"},
  3956. {"rx do_QDIO time"},
  3957. {"rx do_QDIO count"},
  3958. {"tx handler time"},
  3959. {"tx handler count"},
  3960. {"tx time"},
  3961. /* 30 */{"tx count"},
  3962. {"tx do_QDIO time"},
  3963. {"tx do_QDIO count"},
  3964. };
  3965. int qeth_core_get_stats_count(struct net_device *dev)
  3966. {
  3967. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3968. }
  3969. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3970. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3971. struct ethtool_stats *stats, u64 *data)
  3972. {
  3973. struct qeth_card *card = netdev_priv(dev);
  3974. data[0] = card->stats.rx_packets -
  3975. card->perf_stats.initial_rx_packets;
  3976. data[1] = card->perf_stats.bufs_rec;
  3977. data[2] = card->stats.tx_packets -
  3978. card->perf_stats.initial_tx_packets;
  3979. data[3] = card->perf_stats.bufs_sent;
  3980. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3981. - card->perf_stats.skbs_sent_pack;
  3982. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3983. data[6] = card->perf_stats.skbs_sent_pack;
  3984. data[7] = card->perf_stats.bufs_sent_pack;
  3985. data[8] = card->perf_stats.sg_skbs_sent;
  3986. data[9] = card->perf_stats.sg_frags_sent;
  3987. data[10] = card->perf_stats.sg_skbs_rx;
  3988. data[11] = card->perf_stats.sg_frags_rx;
  3989. data[12] = card->perf_stats.sg_alloc_page_rx;
  3990. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3991. data[14] = card->perf_stats.large_send_cnt;
  3992. data[15] = card->perf_stats.sc_dp_p;
  3993. data[16] = card->perf_stats.sc_p_dp;
  3994. data[17] = QETH_LOW_WATERMARK_PACK;
  3995. data[18] = QETH_HIGH_WATERMARK_PACK;
  3996. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3997. data[20] = (card->qdio.no_out_queues > 1) ?
  3998. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3999. data[21] = (card->qdio.no_out_queues > 2) ?
  4000. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4001. data[22] = (card->qdio.no_out_queues > 3) ?
  4002. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4003. data[23] = card->perf_stats.inbound_time;
  4004. data[24] = card->perf_stats.inbound_cnt;
  4005. data[25] = card->perf_stats.inbound_do_qdio_time;
  4006. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4007. data[27] = card->perf_stats.outbound_handler_time;
  4008. data[28] = card->perf_stats.outbound_handler_cnt;
  4009. data[29] = card->perf_stats.outbound_time;
  4010. data[30] = card->perf_stats.outbound_cnt;
  4011. data[31] = card->perf_stats.outbound_do_qdio_time;
  4012. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4013. }
  4014. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4015. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4016. {
  4017. switch (stringset) {
  4018. case ETH_SS_STATS:
  4019. memcpy(data, &qeth_ethtool_stats_keys,
  4020. sizeof(qeth_ethtool_stats_keys));
  4021. break;
  4022. default:
  4023. WARN_ON(1);
  4024. break;
  4025. }
  4026. }
  4027. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4028. void qeth_core_get_drvinfo(struct net_device *dev,
  4029. struct ethtool_drvinfo *info)
  4030. {
  4031. struct qeth_card *card = netdev_priv(dev);
  4032. if (card->options.layer2)
  4033. strcpy(info->driver, "qeth_l2");
  4034. else
  4035. strcpy(info->driver, "qeth_l3");
  4036. strcpy(info->version, "1.0");
  4037. strcpy(info->fw_version, card->info.mcl_level);
  4038. sprintf(info->bus_info, "%s/%s/%s",
  4039. CARD_RDEV_ID(card),
  4040. CARD_WDEV_ID(card),
  4041. CARD_DDEV_ID(card));
  4042. }
  4043. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4044. static int __init qeth_core_init(void)
  4045. {
  4046. int rc;
  4047. PRINT_INFO("loading core functions\n");
  4048. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4049. rwlock_init(&qeth_core_card_list.rwlock);
  4050. rc = qeth_register_dbf_views();
  4051. if (rc)
  4052. goto out_err;
  4053. rc = ccw_driver_register(&qeth_ccw_driver);
  4054. if (rc)
  4055. goto ccw_err;
  4056. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4057. if (rc)
  4058. goto ccwgroup_err;
  4059. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4060. &driver_attr_group);
  4061. if (rc)
  4062. goto driver_err;
  4063. qeth_core_root_dev = s390_root_dev_register("qeth");
  4064. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4065. if (rc)
  4066. goto register_err;
  4067. return 0;
  4068. register_err:
  4069. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4070. &driver_attr_group);
  4071. driver_err:
  4072. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4073. ccwgroup_err:
  4074. ccw_driver_unregister(&qeth_ccw_driver);
  4075. ccw_err:
  4076. qeth_unregister_dbf_views();
  4077. out_err:
  4078. PRINT_ERR("Initialization failed with code %d\n", rc);
  4079. return rc;
  4080. }
  4081. static void __exit qeth_core_exit(void)
  4082. {
  4083. s390_root_dev_unregister(qeth_core_root_dev);
  4084. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4085. &driver_attr_group);
  4086. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4087. ccw_driver_unregister(&qeth_ccw_driver);
  4088. qeth_unregister_dbf_views();
  4089. PRINT_INFO("core functions removed\n");
  4090. }
  4091. module_init(qeth_core_init);
  4092. module_exit(qeth_core_exit);
  4093. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4094. MODULE_DESCRIPTION("qeth core functions");
  4095. MODULE_LICENSE("GPL");