Kconfig 18 KB

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  1. comment "Processor Type"
  2. config CPU_32
  3. bool
  4. default y
  5. # Select CPU types depending on the architecture selected. This selects
  6. # which CPUs we support in the kernel image, and the compiler instruction
  7. # optimiser behaviour.
  8. # ARM610
  9. config CPU_ARM610
  10. bool "Support ARM610 processor" if ARCH_RPC
  11. select CPU_32v3
  12. select CPU_CACHE_V3
  13. select CPU_CACHE_VIVT
  14. select CPU_CP15_MMU
  15. select CPU_COPY_V3 if MMU
  16. select CPU_TLB_V3 if MMU
  17. select CPU_PABRT_NOIFAR
  18. help
  19. The ARM610 is the successor to the ARM3 processor
  20. and was produced by VLSI Technology Inc.
  21. Say Y if you want support for the ARM610 processor.
  22. Otherwise, say N.
  23. # ARM7TDMI
  24. config CPU_ARM7TDMI
  25. bool "Support ARM7TDMI processor"
  26. depends on !MMU
  27. select CPU_32v4T
  28. select CPU_ABRT_LV4T
  29. select CPU_PABRT_NOIFAR
  30. select CPU_CACHE_V4
  31. help
  32. A 32-bit RISC microprocessor based on the ARM7 processor core
  33. which has no memory control unit and cache.
  34. Say Y if you want support for the ARM7TDMI processor.
  35. Otherwise, say N.
  36. # ARM710
  37. config CPU_ARM710
  38. bool "Support ARM710 processor" if ARCH_RPC
  39. select CPU_32v3
  40. select CPU_CACHE_V3
  41. select CPU_CACHE_VIVT
  42. select CPU_CP15_MMU
  43. select CPU_COPY_V3 if MMU
  44. select CPU_TLB_V3 if MMU
  45. select CPU_PABRT_NOIFAR
  46. help
  47. A 32-bit RISC microprocessor based on the ARM7 processor core
  48. designed by Advanced RISC Machines Ltd. The ARM710 is the
  49. successor to the ARM610 processor. It was released in
  50. July 1994 by VLSI Technology Inc.
  51. Say Y if you want support for the ARM710 processor.
  52. Otherwise, say N.
  53. # ARM720T
  54. config CPU_ARM720T
  55. bool "Support ARM720T processor" if ARCH_INTEGRATOR
  56. select CPU_32v4T
  57. select CPU_ABRT_LV4T
  58. select CPU_PABRT_NOIFAR
  59. select CPU_CACHE_V4
  60. select CPU_CACHE_VIVT
  61. select CPU_CP15_MMU
  62. select CPU_COPY_V4WT if MMU
  63. select CPU_TLB_V4WT if MMU
  64. help
  65. A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  66. MMU built around an ARM7TDMI core.
  67. Say Y if you want support for the ARM720T processor.
  68. Otherwise, say N.
  69. # ARM740T
  70. config CPU_ARM740T
  71. bool "Support ARM740T processor" if ARCH_INTEGRATOR
  72. depends on !MMU
  73. select CPU_32v4T
  74. select CPU_ABRT_LV4T
  75. select CPU_PABRT_NOIFAR
  76. select CPU_CACHE_V3 # although the core is v4t
  77. select CPU_CP15_MPU
  78. help
  79. A 32-bit RISC processor with 8KB cache or 4KB variants,
  80. write buffer and MPU(Protection Unit) built around
  81. an ARM7TDMI core.
  82. Say Y if you want support for the ARM740T processor.
  83. Otherwise, say N.
  84. # ARM9TDMI
  85. config CPU_ARM9TDMI
  86. bool "Support ARM9TDMI processor"
  87. depends on !MMU
  88. select CPU_32v4T
  89. select CPU_ABRT_NOMMU
  90. select CPU_PABRT_NOIFAR
  91. select CPU_CACHE_V4
  92. help
  93. A 32-bit RISC microprocessor based on the ARM9 processor core
  94. which has no memory control unit and cache.
  95. Say Y if you want support for the ARM9TDMI processor.
  96. Otherwise, say N.
  97. # ARM920T
  98. config CPU_ARM920T
  99. bool "Support ARM920T processor" if ARCH_INTEGRATOR
  100. select CPU_32v4T
  101. select CPU_ABRT_EV4T
  102. select CPU_PABRT_NOIFAR
  103. select CPU_CACHE_V4WT
  104. select CPU_CACHE_VIVT
  105. select CPU_CP15_MMU
  106. select CPU_COPY_V4WB if MMU
  107. select CPU_TLB_V4WBI if MMU
  108. help
  109. The ARM920T is licensed to be produced by numerous vendors,
  110. and is used in the Maverick EP9312 and the Samsung S3C2410.
  111. More information on the Maverick EP9312 at
  112. <http://linuxdevices.com/products/PD2382866068.html>.
  113. Say Y if you want support for the ARM920T processor.
  114. Otherwise, say N.
  115. # ARM922T
  116. config CPU_ARM922T
  117. bool "Support ARM922T processor" if ARCH_INTEGRATOR
  118. select CPU_32v4T
  119. select CPU_ABRT_EV4T
  120. select CPU_PABRT_NOIFAR
  121. select CPU_CACHE_V4WT
  122. select CPU_CACHE_VIVT
  123. select CPU_CP15_MMU
  124. select CPU_COPY_V4WB if MMU
  125. select CPU_TLB_V4WBI if MMU
  126. help
  127. The ARM922T is a version of the ARM920T, but with smaller
  128. instruction and data caches. It is used in Altera's
  129. Excalibur XA device family and Micrel's KS8695 Centaur.
  130. Say Y if you want support for the ARM922T processor.
  131. Otherwise, say N.
  132. # ARM925T
  133. config CPU_ARM925T
  134. bool "Support ARM925T processor" if ARCH_OMAP1
  135. select CPU_32v4T
  136. select CPU_ABRT_EV4T
  137. select CPU_PABRT_NOIFAR
  138. select CPU_CACHE_V4WT
  139. select CPU_CACHE_VIVT
  140. select CPU_CP15_MMU
  141. select CPU_COPY_V4WB if MMU
  142. select CPU_TLB_V4WBI if MMU
  143. help
  144. The ARM925T is a mix between the ARM920T and ARM926T, but with
  145. different instruction and data caches. It is used in TI's OMAP
  146. device family.
  147. Say Y if you want support for the ARM925T processor.
  148. Otherwise, say N.
  149. # ARM926T
  150. config CPU_ARM926T
  151. bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
  152. select CPU_32v5
  153. select CPU_ABRT_EV5TJ
  154. select CPU_PABRT_NOIFAR
  155. select CPU_CACHE_VIVT
  156. select CPU_CP15_MMU
  157. select CPU_COPY_V4WB if MMU
  158. select CPU_TLB_V4WBI if MMU
  159. help
  160. This is a variant of the ARM920. It has slightly different
  161. instruction sequences for cache and TLB operations. Curiously,
  162. there is no documentation on it at the ARM corporate website.
  163. Say Y if you want support for the ARM926T processor.
  164. Otherwise, say N.
  165. # ARM940T
  166. config CPU_ARM940T
  167. bool "Support ARM940T processor" if ARCH_INTEGRATOR
  168. depends on !MMU
  169. select CPU_32v4T
  170. select CPU_ABRT_NOMMU
  171. select CPU_PABRT_NOIFAR
  172. select CPU_CACHE_VIVT
  173. select CPU_CP15_MPU
  174. help
  175. ARM940T is a member of the ARM9TDMI family of general-
  176. purpose microprocessors with MPU and separate 4KB
  177. instruction and 4KB data cases, each with a 4-word line
  178. length.
  179. Say Y if you want support for the ARM940T processor.
  180. Otherwise, say N.
  181. # ARM946E-S
  182. config CPU_ARM946E
  183. bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
  184. depends on !MMU
  185. select CPU_32v5
  186. select CPU_ABRT_NOMMU
  187. select CPU_PABRT_NOIFAR
  188. select CPU_CACHE_VIVT
  189. select CPU_CP15_MPU
  190. help
  191. ARM946E-S is a member of the ARM9E-S family of high-
  192. performance, 32-bit system-on-chip processor solutions.
  193. The TCM and ARMv5TE 32-bit instruction set is supported.
  194. Say Y if you want support for the ARM946E-S processor.
  195. Otherwise, say N.
  196. # ARM1020 - needs validating
  197. config CPU_ARM1020
  198. bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
  199. select CPU_32v5
  200. select CPU_ABRT_EV4T
  201. select CPU_PABRT_NOIFAR
  202. select CPU_CACHE_V4WT
  203. select CPU_CACHE_VIVT
  204. select CPU_CP15_MMU
  205. select CPU_COPY_V4WB if MMU
  206. select CPU_TLB_V4WBI if MMU
  207. help
  208. The ARM1020 is the 32K cached version of the ARM10 processor,
  209. with an addition of a floating-point unit.
  210. Say Y if you want support for the ARM1020 processor.
  211. Otherwise, say N.
  212. # ARM1020E - needs validating
  213. config CPU_ARM1020E
  214. bool "Support ARM1020E processor" if ARCH_INTEGRATOR
  215. select CPU_32v5
  216. select CPU_ABRT_EV4T
  217. select CPU_PABRT_NOIFAR
  218. select CPU_CACHE_V4WT
  219. select CPU_CACHE_VIVT
  220. select CPU_CP15_MMU
  221. select CPU_COPY_V4WB if MMU
  222. select CPU_TLB_V4WBI if MMU
  223. depends on n
  224. # ARM1022E
  225. config CPU_ARM1022
  226. bool "Support ARM1022E processor" if ARCH_INTEGRATOR
  227. select CPU_32v5
  228. select CPU_ABRT_EV4T
  229. select CPU_PABRT_NOIFAR
  230. select CPU_CACHE_VIVT
  231. select CPU_CP15_MMU
  232. select CPU_COPY_V4WB if MMU # can probably do better
  233. select CPU_TLB_V4WBI if MMU
  234. help
  235. The ARM1022E is an implementation of the ARMv5TE architecture
  236. based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
  237. embedded trace macrocell, and a floating-point unit.
  238. Say Y if you want support for the ARM1022E processor.
  239. Otherwise, say N.
  240. # ARM1026EJ-S
  241. config CPU_ARM1026
  242. bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
  243. select CPU_32v5
  244. select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
  245. select CPU_PABRT_NOIFAR
  246. select CPU_CACHE_VIVT
  247. select CPU_CP15_MMU
  248. select CPU_COPY_V4WB if MMU # can probably do better
  249. select CPU_TLB_V4WBI if MMU
  250. help
  251. The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
  252. based upon the ARM10 integer core.
  253. Say Y if you want support for the ARM1026EJ-S processor.
  254. Otherwise, say N.
  255. # SA110
  256. config CPU_SA110
  257. bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
  258. select CPU_32v3 if ARCH_RPC
  259. select CPU_32v4 if !ARCH_RPC
  260. select CPU_ABRT_EV4
  261. select CPU_PABRT_NOIFAR
  262. select CPU_CACHE_V4WB
  263. select CPU_CACHE_VIVT
  264. select CPU_CP15_MMU
  265. select CPU_COPY_V4WB if MMU
  266. select CPU_TLB_V4WB if MMU
  267. help
  268. The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
  269. is available at five speeds ranging from 100 MHz to 233 MHz.
  270. More information is available at
  271. <http://developer.intel.com/design/strong/sa110.htm>.
  272. Say Y if you want support for the SA-110 processor.
  273. Otherwise, say N.
  274. # SA1100
  275. config CPU_SA1100
  276. bool
  277. select CPU_32v4
  278. select CPU_ABRT_EV4
  279. select CPU_PABRT_NOIFAR
  280. select CPU_CACHE_V4WB
  281. select CPU_CACHE_VIVT
  282. select CPU_CP15_MMU
  283. select CPU_TLB_V4WB if MMU
  284. # XScale
  285. config CPU_XSCALE
  286. bool
  287. select CPU_32v5
  288. select CPU_ABRT_EV5T
  289. select CPU_PABRT_NOIFAR
  290. select CPU_CACHE_VIVT
  291. select CPU_CP15_MMU
  292. select CPU_TLB_V4WBI if MMU
  293. # XScale Core Version 3
  294. config CPU_XSC3
  295. bool
  296. select CPU_32v5
  297. select CPU_ABRT_EV5T
  298. select CPU_PABRT_NOIFAR
  299. select CPU_CACHE_VIVT
  300. select CPU_CP15_MMU
  301. select CPU_TLB_V4WBI if MMU
  302. select IO_36
  303. # Marvell PJ1 (Mohawk)
  304. config CPU_MOHAWK
  305. bool
  306. select CPU_32v5
  307. select CPU_ABRT_EV5T
  308. select CPU_PABRT_NOIFAR
  309. select CPU_CACHE_VIVT
  310. select CPU_CP15_MMU
  311. select CPU_TLB_V4WBI if MMU
  312. select CPU_COPY_V4WB if MMU
  313. # Feroceon
  314. config CPU_FEROCEON
  315. bool
  316. select CPU_32v5
  317. select CPU_ABRT_EV5T
  318. select CPU_PABRT_NOIFAR
  319. select CPU_CACHE_VIVT
  320. select CPU_CP15_MMU
  321. select CPU_COPY_FEROCEON if MMU
  322. select CPU_TLB_FEROCEON if MMU
  323. config CPU_FEROCEON_OLD_ID
  324. bool "Accept early Feroceon cores with an ARM926 ID"
  325. depends on CPU_FEROCEON && !CPU_ARM926T
  326. default y
  327. help
  328. This enables the usage of some old Feroceon cores
  329. for which the CPU ID is equal to the ARM926 ID.
  330. Relevant for Feroceon-1850 and early Feroceon-2850.
  331. # ARMv6
  332. config CPU_V6
  333. bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
  334. select CPU_32v6
  335. select CPU_ABRT_EV6
  336. select CPU_PABRT_NOIFAR
  337. select CPU_CACHE_V6
  338. select CPU_CACHE_VIPT
  339. select CPU_CP15_MMU
  340. select CPU_HAS_ASID if MMU
  341. select CPU_COPY_V6 if MMU
  342. select CPU_TLB_V6 if MMU
  343. # ARMv6k
  344. config CPU_32v6K
  345. bool "Support ARM V6K processor extensions" if !SMP
  346. depends on CPU_V6
  347. default y if SMP && !ARCH_MX3
  348. help
  349. Say Y here if your ARMv6 processor supports the 'K' extension.
  350. This enables the kernel to use some instructions not present
  351. on previous processors, and as such a kernel build with this
  352. enabled will not boot on processors with do not support these
  353. instructions.
  354. # ARMv7
  355. config CPU_V7
  356. bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
  357. select CPU_32v6K
  358. select CPU_32v7
  359. select CPU_ABRT_EV7
  360. select CPU_PABRT_IFAR
  361. select CPU_CACHE_V7
  362. select CPU_CACHE_VIPT
  363. select CPU_CP15_MMU
  364. select CPU_HAS_ASID if MMU
  365. select CPU_COPY_V6 if MMU
  366. select CPU_TLB_V7 if MMU
  367. # Figure out what processor architecture version we should be using.
  368. # This defines the compiler instruction set which depends on the machine type.
  369. config CPU_32v3
  370. bool
  371. select TLS_REG_EMUL if SMP || !MMU
  372. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  373. config CPU_32v4
  374. bool
  375. select TLS_REG_EMUL if SMP || !MMU
  376. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  377. config CPU_32v4T
  378. bool
  379. select TLS_REG_EMUL if SMP || !MMU
  380. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  381. config CPU_32v5
  382. bool
  383. select TLS_REG_EMUL if SMP || !MMU
  384. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  385. config CPU_32v6
  386. bool
  387. select TLS_REG_EMUL if !CPU_32v6K && !MMU
  388. config CPU_32v7
  389. bool
  390. # The abort model
  391. config CPU_ABRT_NOMMU
  392. bool
  393. config CPU_ABRT_EV4
  394. bool
  395. config CPU_ABRT_EV4T
  396. bool
  397. config CPU_ABRT_LV4T
  398. bool
  399. config CPU_ABRT_EV5T
  400. bool
  401. config CPU_ABRT_EV5TJ
  402. bool
  403. config CPU_ABRT_EV6
  404. bool
  405. config CPU_ABRT_EV7
  406. bool
  407. config CPU_PABRT_IFAR
  408. bool
  409. config CPU_PABRT_NOIFAR
  410. bool
  411. # The cache model
  412. config CPU_CACHE_V3
  413. bool
  414. config CPU_CACHE_V4
  415. bool
  416. config CPU_CACHE_V4WT
  417. bool
  418. config CPU_CACHE_V4WB
  419. bool
  420. config CPU_CACHE_V6
  421. bool
  422. config CPU_CACHE_V7
  423. bool
  424. config CPU_CACHE_VIVT
  425. bool
  426. config CPU_CACHE_VIPT
  427. bool
  428. if MMU
  429. # The copy-page model
  430. config CPU_COPY_V3
  431. bool
  432. config CPU_COPY_V4WT
  433. bool
  434. config CPU_COPY_V4WB
  435. bool
  436. config CPU_COPY_FEROCEON
  437. bool
  438. config CPU_COPY_V6
  439. bool
  440. # This selects the TLB model
  441. config CPU_TLB_V3
  442. bool
  443. help
  444. ARM Architecture Version 3 TLB.
  445. config CPU_TLB_V4WT
  446. bool
  447. help
  448. ARM Architecture Version 4 TLB with writethrough cache.
  449. config CPU_TLB_V4WB
  450. bool
  451. help
  452. ARM Architecture Version 4 TLB with writeback cache.
  453. config CPU_TLB_V4WBI
  454. bool
  455. help
  456. ARM Architecture Version 4 TLB with writeback cache and invalidate
  457. instruction cache entry.
  458. config CPU_TLB_FEROCEON
  459. bool
  460. help
  461. Feroceon TLB (v4wbi with non-outer-cachable page table walks).
  462. config CPU_TLB_V6
  463. bool
  464. config CPU_TLB_V7
  465. bool
  466. endif
  467. config CPU_HAS_ASID
  468. bool
  469. help
  470. This indicates whether the CPU has the ASID register; used to
  471. tag TLB and possibly cache entries.
  472. config CPU_CP15
  473. bool
  474. help
  475. Processor has the CP15 register.
  476. config CPU_CP15_MMU
  477. bool
  478. select CPU_CP15
  479. help
  480. Processor has the CP15 register, which has MMU related registers.
  481. config CPU_CP15_MPU
  482. bool
  483. select CPU_CP15
  484. help
  485. Processor has the CP15 register, which has MPU related registers.
  486. #
  487. # CPU supports 36-bit I/O
  488. #
  489. config IO_36
  490. bool
  491. comment "Processor Features"
  492. config ARM_THUMB
  493. bool "Support Thumb user binaries"
  494. depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
  495. default y
  496. help
  497. Say Y if you want to include kernel support for running user space
  498. Thumb binaries.
  499. The Thumb instruction set is a compressed form of the standard ARM
  500. instruction set resulting in smaller binaries at the expense of
  501. slightly less efficient code.
  502. If you don't know what this all is, saying Y is a safe choice.
  503. config ARM_THUMBEE
  504. bool "Enable ThumbEE CPU extension"
  505. depends on CPU_V7
  506. help
  507. Say Y here if you have a CPU with the ThumbEE extension and code to
  508. make use of it. Say N for code that can run on CPUs without ThumbEE.
  509. config CPU_BIG_ENDIAN
  510. bool "Build big-endian kernel"
  511. depends on ARCH_SUPPORTS_BIG_ENDIAN
  512. help
  513. Say Y if you plan on running a kernel in big-endian mode.
  514. Note that your board must be properly built and your board
  515. port must properly enable any big-endian related features
  516. of your chipset/board/processor.
  517. config CPU_HIGH_VECTOR
  518. depends on !MMU && CPU_CP15 && !CPU_ARM740T
  519. bool "Select the High exception vector"
  520. default n
  521. help
  522. Say Y here to select high exception vector(0xFFFF0000~).
  523. The exception vector can be vary depending on the platform
  524. design in nommu mode. If your platform needs to select
  525. high exception vector, say Y.
  526. Otherwise or if you are unsure, say N, and the low exception
  527. vector (0x00000000~) will be used.
  528. config CPU_ICACHE_DISABLE
  529. bool "Disable I-Cache (I-bit)"
  530. depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
  531. help
  532. Say Y here to disable the processor instruction cache. Unless
  533. you have a reason not to or are unsure, say N.
  534. config CPU_DCACHE_DISABLE
  535. bool "Disable D-Cache (C-bit)"
  536. depends on CPU_CP15
  537. help
  538. Say Y here to disable the processor data cache. Unless
  539. you have a reason not to or are unsure, say N.
  540. config CPU_DCACHE_SIZE
  541. hex
  542. depends on CPU_ARM740T || CPU_ARM946E
  543. default 0x00001000 if CPU_ARM740T
  544. default 0x00002000 # default size for ARM946E-S
  545. help
  546. Some cores are synthesizable to have various sized cache. For
  547. ARM946E-S case, it can vary from 0KB to 1MB.
  548. To support such cache operations, it is efficient to know the size
  549. before compile time.
  550. If your SoC is configured to have a different size, define the value
  551. here with proper conditions.
  552. config CPU_DCACHE_WRITETHROUGH
  553. bool "Force write through D-cache"
  554. depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
  555. default y if CPU_ARM925T
  556. help
  557. Say Y here to use the data cache in writethrough mode. Unless you
  558. specifically require this or are unsure, say N.
  559. config CPU_CACHE_ROUND_ROBIN
  560. bool "Round robin I and D cache replacement algorithm"
  561. depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
  562. help
  563. Say Y here to use the predictable round-robin cache replacement
  564. policy. Unless you specifically require this or are unsure, say N.
  565. config CPU_BPREDICT_DISABLE
  566. bool "Disable branch prediction"
  567. depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7
  568. help
  569. Say Y here to disable branch prediction. If unsure, say N.
  570. config TLS_REG_EMUL
  571. bool
  572. help
  573. An SMP system using a pre-ARMv6 processor (there are apparently
  574. a few prototypes like that in existence) and therefore access to
  575. that required register must be emulated.
  576. config HAS_TLS_REG
  577. bool
  578. depends on !TLS_REG_EMUL
  579. default y if SMP || CPU_32v7
  580. help
  581. This selects support for the CP15 thread register.
  582. It is defined to be available on some ARMv6 processors (including
  583. all SMP capable ARMv6's) or later processors. User space may
  584. assume directly accessing that register and always obtain the
  585. expected value only on ARMv7 and above.
  586. config NEEDS_SYSCALL_FOR_CMPXCHG
  587. bool
  588. help
  589. SMP on a pre-ARMv6 processor? Well OK then.
  590. Forget about fast user space cmpxchg support.
  591. It is just not possible.
  592. config OUTER_CACHE
  593. bool
  594. default n
  595. config CACHE_FEROCEON_L2
  596. bool "Enable the Feroceon L2 cache controller"
  597. depends on ARCH_KIRKWOOD || ARCH_MV78XX0
  598. default y
  599. select OUTER_CACHE
  600. help
  601. This option enables the Feroceon L2 cache controller.
  602. config CACHE_FEROCEON_L2_WRITETHROUGH
  603. bool "Force Feroceon L2 cache write through"
  604. depends on CACHE_FEROCEON_L2
  605. default n
  606. help
  607. Say Y here to use the Feroceon L2 cache in writethrough mode.
  608. Unless you specifically require this, say N for writeback mode.
  609. config CACHE_L2X0
  610. bool "Enable the L2x0 outer cache controller"
  611. depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP
  612. default y
  613. select OUTER_CACHE
  614. help
  615. This option enables the L2x0 PrimeCell.
  616. config CACHE_XSC3L2
  617. bool "Enable the L2 cache on XScale3"
  618. depends on CPU_XSC3
  619. default y
  620. select OUTER_CACHE
  621. help
  622. This option enables the L2 cache on XScale3.