azt3328.c 62 KB

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  1. /*
  2. * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005, 2006, 2007 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * GPL LICENSE
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. * NOTES
  28. * Since Aztech does not provide any chipset documentation,
  29. * even on repeated request to various addresses,
  30. * and the answer that was finally given was negative
  31. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  32. * in the first place >:-P}),
  33. * I was forced to base this driver on reverse engineering
  34. * (3 weeks' worth of evenings filled with driver work).
  35. * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
  36. *
  37. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  38. * for compatibility reasons) has the following features:
  39. *
  40. * - builtin AC97 conformant codec (SNR over 80dB)
  41. * Note that "conformant" != "compliant"!! this chip's mixer register layout
  42. * *differs* from the standard AC97 layout:
  43. * they chose to not implement the headphone register (which is not a
  44. * problem since it's merely optional), yet when doing this, they committed
  45. * the grave sin of letting other registers follow immediately instead of
  46. * keeping a headphone dummy register, thereby shifting the mixer register
  47. * addresses illegally. So far unfortunately it looks like the very flexible
  48. * ALSA AC97 support is still not enough to easily compensate for such a
  49. * grave layout violation despite all tweaks and quirks mechanisms it offers.
  50. * - builtin genuine OPL3
  51. * - full duplex 16bit playback/record at independent sampling rate
  52. * - MPU401 (+ legacy address support) FIXME: how to enable legacy addr??
  53. * - game port (legacy address support)
  54. * - builtin 3D enhancement (said to be YAMAHA Ymersion)
  55. * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
  56. * features supported)
  57. * - built-in General DirectX timer having a 20 bits counter
  58. * with 1us resolution (see below!)
  59. * - I2S serial port for external DAC
  60. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  61. * - supports hardware volume control
  62. * - single chip low cost solution (128 pin QFP)
  63. * - supports programmable Sub-vendor and Sub-system ID
  64. * required for Microsoft's logo compliance (FIXME: where?)
  65. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  66. *
  67. * Note that this driver now is actually *better* than the Windows driver,
  68. * since it additionally supports the card's 1MHz DirectX timer - just try
  69. * the following snd-seq module parameters etc.:
  70. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  71. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  72. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  73. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  74. * - "pmidi -p 128:0 jazz.mid"
  75. *
  76. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  77. * in some systems (resulting in sound crackling/clicking/popping),
  78. * probably because they don't have a DMA FIFO buffer or so.
  79. * Overview (PCI ID/PCI subID/PCI rev.):
  80. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  81. * - unknown performance: 0x50DC/0x1801/10
  82. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  83. *
  84. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  85. * supposed to be very fast and supposed to get rid of crackling much
  86. * better than a VIA, yet ironically I still get crackling, like many other
  87. * people with the same chipset.
  88. * Possible remedies:
  89. * - plug card into a different PCI slot, preferrably one that isn't shared
  90. * too much (this helps a lot, but not completely!)
  91. * - get rid of PCI VGA card, use AGP instead
  92. * - upgrade or downgrade BIOS
  93. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  94. * Not too helpful.
  95. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  96. *
  97. * BUGS
  98. * - full-duplex might *still* be problematic, not fully tested recently
  99. * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
  100. * if you set PCM output switch to "pre 3D" instead of "post 3D".
  101. * If this can't be set, then get a mixer application that Isn't Stupid (tm)
  102. * (e.g. kmix, gamix) - unfortunately several are!!
  103. *
  104. * TODO
  105. * - test MPU401 MIDI playback etc.
  106. * - add some power micro-management (disable various units of the card
  107. * as long as they're unused). However this requires I/O ports which I
  108. * haven't figured out yet and which thus might not even exist...
  109. * The standard suspend/resume functionality could probably make use of
  110. * some improvement, too...
  111. * - figure out what all unknown port bits are responsible for
  112. * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
  113. * fully accept our quite incompatible ""AC97"" mixer and thus save some
  114. * code (but I'm not too optimistic that doing this is possible at all)
  115. */
  116. #include <sound/driver.h>
  117. #include <asm/io.h>
  118. #include <linux/init.h>
  119. #include <linux/pci.h>
  120. #include <linux/delay.h>
  121. #include <linux/slab.h>
  122. #include <linux/gameport.h>
  123. #include <linux/moduleparam.h>
  124. #include <linux/dma-mapping.h>
  125. #include <sound/core.h>
  126. #include <sound/control.h>
  127. #include <sound/pcm.h>
  128. #include <sound/rawmidi.h>
  129. #include <sound/mpu401.h>
  130. #include <sound/opl3.h>
  131. #include <sound/initval.h>
  132. #include "azt3328.h"
  133. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  134. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  135. MODULE_LICENSE("GPL");
  136. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  137. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  138. #define SUPPORT_JOYSTICK 1
  139. #endif
  140. #define DEBUG_MISC 0
  141. #define DEBUG_CALLS 0
  142. #define DEBUG_MIXER 0
  143. #define DEBUG_PLAY_REC 0
  144. #define DEBUG_IO 0
  145. #define DEBUG_TIMER 0
  146. #define MIXER_TESTING 0
  147. #if DEBUG_MISC
  148. #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
  149. #else
  150. #define snd_azf3328_dbgmisc(format, args...)
  151. #endif
  152. #if DEBUG_CALLS
  153. #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
  154. #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__)
  155. #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__)
  156. #else
  157. #define snd_azf3328_dbgcalls(format, args...)
  158. #define snd_azf3328_dbgcallenter()
  159. #define snd_azf3328_dbgcallleave()
  160. #endif
  161. #if DEBUG_MIXER
  162. #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
  163. #else
  164. #define snd_azf3328_dbgmixer(format, args...)
  165. #endif
  166. #if DEBUG_PLAY_REC
  167. #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
  168. #else
  169. #define snd_azf3328_dbgplay(format, args...)
  170. #endif
  171. #if DEBUG_MISC
  172. #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
  173. #else
  174. #define snd_azf3328_dbgtimer(format, args...)
  175. #endif
  176. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  177. module_param_array(index, int, NULL, 0444);
  178. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  179. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  180. module_param_array(id, charp, NULL, 0444);
  181. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  182. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  183. module_param_array(enable, bool, NULL, 0444);
  184. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  185. #ifdef SUPPORT_JOYSTICK
  186. static int joystick[SNDRV_CARDS];
  187. module_param_array(joystick, bool, NULL, 0444);
  188. MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard.");
  189. #endif
  190. static int seqtimer_scaling = 128;
  191. module_param(seqtimer_scaling, int, 0444);
  192. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  193. struct snd_azf3328 {
  194. /* often-used fields towards beginning, then grouped */
  195. unsigned long codec_port;
  196. unsigned long io2_port;
  197. unsigned long mpu_port;
  198. unsigned long synth_port;
  199. unsigned long mixer_port;
  200. spinlock_t reg_lock;
  201. struct snd_timer *timer;
  202. struct snd_pcm *pcm;
  203. struct snd_pcm_substream *playback_substream;
  204. struct snd_pcm_substream *capture_substream;
  205. unsigned int is_playing;
  206. unsigned int is_recording;
  207. struct snd_card *card;
  208. struct snd_rawmidi *rmidi;
  209. #ifdef SUPPORT_JOYSTICK
  210. struct gameport *gameport;
  211. #endif
  212. struct pci_dev *pci;
  213. int irq;
  214. #ifdef CONFIG_PM
  215. /* register value containers for power management
  216. * Note: not always full I/O range preserved (just like Win driver!) */
  217. u16 saved_regs_codec [AZF_IO_SIZE_CODEC_PM / 2];
  218. u16 saved_regs_io2 [AZF_IO_SIZE_IO2_PM / 2];
  219. u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
  220. u16 saved_regs_synth[AZF_IO_SIZE_SYNTH_PM / 2];
  221. u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
  222. #endif
  223. };
  224. static const struct pci_device_id snd_azf3328_ids[] = {
  225. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  226. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  227. { 0, }
  228. };
  229. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  230. static inline void
  231. snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  232. {
  233. outb(value, chip->codec_port + reg);
  234. }
  235. static inline u8
  236. snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg)
  237. {
  238. return inb(chip->codec_port + reg);
  239. }
  240. static inline void
  241. snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  242. {
  243. outw(value, chip->codec_port + reg);
  244. }
  245. static inline u16
  246. snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg)
  247. {
  248. return inw(chip->codec_port + reg);
  249. }
  250. static inline void
  251. snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value)
  252. {
  253. outl(value, chip->codec_port + reg);
  254. }
  255. static inline void
  256. snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  257. {
  258. outb(value, chip->io2_port + reg);
  259. }
  260. static inline u8
  261. snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg)
  262. {
  263. return inb(chip->io2_port + reg);
  264. }
  265. static inline void
  266. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  267. {
  268. outw(value, chip->mixer_port + reg);
  269. }
  270. static inline u16
  271. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg)
  272. {
  273. return inw(chip->mixer_port + reg);
  274. }
  275. static void
  276. snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute)
  277. {
  278. unsigned long portbase = chip->mixer_port + reg + 1;
  279. unsigned char oldval;
  280. /* the mute bit is on the *second* (i.e. right) register of a
  281. * left/right channel setting */
  282. oldval = inb(portbase);
  283. if (do_mute)
  284. oldval |= 0x80;
  285. else
  286. oldval &= ~0x80;
  287. outb(oldval, portbase);
  288. }
  289. static void
  290. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay)
  291. {
  292. unsigned long portbase = chip->mixer_port + reg;
  293. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  294. int left_done = 0, right_done = 0;
  295. snd_azf3328_dbgcallenter();
  296. if (chan_sel & SET_CHAN_LEFT)
  297. curr_vol_left = inb(portbase + 1);
  298. else
  299. left_done = 1;
  300. if (chan_sel & SET_CHAN_RIGHT)
  301. curr_vol_right = inb(portbase + 0);
  302. else
  303. right_done = 1;
  304. /* take care of muting flag (0x80) contained in left channel */
  305. if (curr_vol_left & 0x80)
  306. dst_vol_left |= 0x80;
  307. else
  308. dst_vol_left &= ~0x80;
  309. do {
  310. if (!left_done) {
  311. if (curr_vol_left > dst_vol_left)
  312. curr_vol_left--;
  313. else
  314. if (curr_vol_left < dst_vol_left)
  315. curr_vol_left++;
  316. else
  317. left_done = 1;
  318. outb(curr_vol_left, portbase + 1);
  319. }
  320. if (!right_done) {
  321. if (curr_vol_right > dst_vol_right)
  322. curr_vol_right--;
  323. else
  324. if (curr_vol_right < dst_vol_right)
  325. curr_vol_right++;
  326. else
  327. right_done = 1;
  328. /* during volume change, the right channel is crackling
  329. * somewhat more than the left channel, unfortunately.
  330. * This seems to be a hardware issue. */
  331. outb(curr_vol_right, portbase + 0);
  332. }
  333. if (delay)
  334. mdelay(delay);
  335. } while ((!left_done) || (!right_done));
  336. snd_azf3328_dbgcallleave();
  337. }
  338. /*
  339. * general mixer element
  340. */
  341. struct azf3328_mixer_reg {
  342. unsigned int reg;
  343. unsigned int lchan_shift, rchan_shift;
  344. unsigned int mask;
  345. unsigned int invert: 1;
  346. unsigned int stereo: 1;
  347. unsigned int enum_c: 4;
  348. };
  349. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  350. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  351. (mask << 16) | \
  352. (invert << 24) | \
  353. (stereo << 25) | \
  354. (enum_c << 26))
  355. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  356. {
  357. r->reg = val & 0xff;
  358. r->lchan_shift = (val >> 8) & 0x0f;
  359. r->rchan_shift = (val >> 12) & 0x0f;
  360. r->mask = (val >> 16) & 0xff;
  361. r->invert = (val >> 24) & 1;
  362. r->stereo = (val >> 25) & 1;
  363. r->enum_c = (val >> 26) & 0x0f;
  364. }
  365. /*
  366. * mixer switches/volumes
  367. */
  368. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  369. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  370. .info = snd_azf3328_info_mixer, \
  371. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  372. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  373. }
  374. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  375. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  376. .info = snd_azf3328_info_mixer, \
  377. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  378. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  379. }
  380. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  381. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  382. .info = snd_azf3328_info_mixer, \
  383. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  384. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  385. }
  386. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  387. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  388. .info = snd_azf3328_info_mixer, \
  389. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  390. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  391. }
  392. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  393. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  394. .info = snd_azf3328_info_mixer_enum, \
  395. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  396. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  397. }
  398. static int
  399. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  400. struct snd_ctl_elem_info *uinfo)
  401. {
  402. struct azf3328_mixer_reg reg;
  403. snd_azf3328_dbgcallenter();
  404. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  405. uinfo->type = reg.mask == 1 ?
  406. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  407. uinfo->count = reg.stereo + 1;
  408. uinfo->value.integer.min = 0;
  409. uinfo->value.integer.max = reg.mask;
  410. snd_azf3328_dbgcallleave();
  411. return 0;
  412. }
  413. static int
  414. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  415. struct snd_ctl_elem_value *ucontrol)
  416. {
  417. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  418. struct azf3328_mixer_reg reg;
  419. unsigned int oreg, val;
  420. snd_azf3328_dbgcallenter();
  421. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  422. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  423. val = (oreg >> reg.lchan_shift) & reg.mask;
  424. if (reg.invert)
  425. val = reg.mask - val;
  426. ucontrol->value.integer.value[0] = val;
  427. if (reg.stereo) {
  428. val = (oreg >> reg.rchan_shift) & reg.mask;
  429. if (reg.invert)
  430. val = reg.mask - val;
  431. ucontrol->value.integer.value[1] = val;
  432. }
  433. snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
  434. "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  435. reg.reg, oreg,
  436. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  437. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  438. snd_azf3328_dbgcallleave();
  439. return 0;
  440. }
  441. static int
  442. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  443. struct snd_ctl_elem_value *ucontrol)
  444. {
  445. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  446. struct azf3328_mixer_reg reg;
  447. unsigned int oreg, nreg, val;
  448. snd_azf3328_dbgcallenter();
  449. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  450. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  451. val = ucontrol->value.integer.value[0] & reg.mask;
  452. if (reg.invert)
  453. val = reg.mask - val;
  454. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  455. nreg |= (val << reg.lchan_shift);
  456. if (reg.stereo) {
  457. val = ucontrol->value.integer.value[1] & reg.mask;
  458. if (reg.invert)
  459. val = reg.mask - val;
  460. nreg &= ~(reg.mask << reg.rchan_shift);
  461. nreg |= (val << reg.rchan_shift);
  462. }
  463. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  464. snd_azf3328_mixer_write_volume_gradually(
  465. chip, reg.reg, nreg >> 8, nreg & 0xff,
  466. /* just set both channels, doesn't matter */
  467. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  468. 0);
  469. else
  470. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  471. snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
  472. "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  473. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  474. oreg, reg.lchan_shift, reg.rchan_shift,
  475. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  476. snd_azf3328_dbgcallleave();
  477. return (nreg != oreg);
  478. }
  479. static int
  480. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  481. struct snd_ctl_elem_info *uinfo)
  482. {
  483. static const char * const texts1[] = {
  484. "Mic1", "Mic2"
  485. };
  486. static const char * const texts2[] = {
  487. "Mix", "Mic"
  488. };
  489. static const char * const texts3[] = {
  490. "Mic", "CD", "Video", "Aux",
  491. "Line", "Mix", "Mix Mono", "Phone"
  492. };
  493. static const char * const texts4[] = {
  494. "pre 3D", "post 3D"
  495. };
  496. struct azf3328_mixer_reg reg;
  497. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  498. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  499. uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
  500. uinfo->value.enumerated.items = reg.enum_c;
  501. if (uinfo->value.enumerated.item > reg.enum_c - 1U)
  502. uinfo->value.enumerated.item = reg.enum_c - 1U;
  503. if (reg.reg == IDX_MIXER_ADVCTL2) {
  504. switch(reg.lchan_shift) {
  505. case 8: /* modem out sel */
  506. strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]);
  507. break;
  508. case 9: /* mono sel source */
  509. strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]);
  510. break;
  511. case 15: /* PCM Out Path */
  512. strcpy(uinfo->value.enumerated.name, texts4[uinfo->value.enumerated.item]);
  513. break;
  514. }
  515. } else
  516. strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item]
  517. );
  518. return 0;
  519. }
  520. static int
  521. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  522. struct snd_ctl_elem_value *ucontrol)
  523. {
  524. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  525. struct azf3328_mixer_reg reg;
  526. unsigned short val;
  527. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  528. val = snd_azf3328_mixer_inw(chip, reg.reg);
  529. if (reg.reg == IDX_MIXER_REC_SELECT) {
  530. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  531. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  532. } else
  533. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  534. snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  535. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  536. reg.lchan_shift, reg.enum_c);
  537. return 0;
  538. }
  539. static int
  540. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  541. struct snd_ctl_elem_value *ucontrol)
  542. {
  543. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  544. struct azf3328_mixer_reg reg;
  545. unsigned int oreg, nreg, val;
  546. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  547. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  548. val = oreg;
  549. if (reg.reg == IDX_MIXER_REC_SELECT) {
  550. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  551. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  552. return -EINVAL;
  553. val = (ucontrol->value.enumerated.item[0] << 8) |
  554. (ucontrol->value.enumerated.item[1] << 0);
  555. } else {
  556. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  557. return -EINVAL;
  558. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  559. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  560. }
  561. snd_azf3328_mixer_outw(chip, reg.reg, val);
  562. nreg = val;
  563. snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  564. return (nreg != oreg);
  565. }
  566. static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
  567. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  568. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  569. AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  570. AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
  571. AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
  572. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  573. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  574. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  575. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  576. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  577. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  578. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  579. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  580. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  581. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  582. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  583. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  584. AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  585. AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  586. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  587. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  588. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  589. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  590. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  591. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  592. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  593. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  594. AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
  595. AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
  596. AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
  597. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  598. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  599. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  600. AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  601. AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  602. #if MIXER_TESTING
  603. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  604. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  605. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  606. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  607. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  608. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  609. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  610. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  611. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  612. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  613. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  614. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  615. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  616. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  617. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  618. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  619. #endif
  620. };
  621. static u16 __devinitdata snd_azf3328_init_values[][2] = {
  622. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  623. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  624. { IDX_MIXER_BASSTREBLE, 0x0000 },
  625. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  626. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  627. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  628. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  629. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  630. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  631. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  632. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  633. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  634. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  635. };
  636. static int __devinit
  637. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  638. {
  639. struct snd_card *card;
  640. const struct snd_kcontrol_new *sw;
  641. unsigned int idx;
  642. int err;
  643. snd_azf3328_dbgcallenter();
  644. snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
  645. card = chip->card;
  646. /* mixer reset */
  647. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  648. /* mute and zero volume channels */
  649. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) {
  650. snd_azf3328_mixer_outw(chip,
  651. snd_azf3328_init_values[idx][0],
  652. snd_azf3328_init_values[idx][1]);
  653. }
  654. /* add mixer controls */
  655. sw = snd_azf3328_mixer_controls;
  656. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) {
  657. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  658. return err;
  659. }
  660. snd_component_add(card, "AZF3328 mixer");
  661. strcpy(card->mixername, "AZF3328 mixer");
  662. snd_azf3328_dbgcallleave();
  663. return 0;
  664. }
  665. static int
  666. snd_azf3328_hw_params(struct snd_pcm_substream *substream,
  667. struct snd_pcm_hw_params *hw_params)
  668. {
  669. int res;
  670. snd_azf3328_dbgcallenter();
  671. res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  672. snd_azf3328_dbgcallleave();
  673. return res;
  674. }
  675. static int
  676. snd_azf3328_hw_free(struct snd_pcm_substream *substream)
  677. {
  678. snd_azf3328_dbgcallenter();
  679. snd_pcm_lib_free_pages(substream);
  680. snd_azf3328_dbgcallleave();
  681. return 0;
  682. }
  683. static void
  684. snd_azf3328_setfmt(struct snd_azf3328 *chip,
  685. unsigned int reg,
  686. unsigned int bitrate,
  687. unsigned int format_width,
  688. unsigned int channels
  689. )
  690. {
  691. u16 val = 0xff00;
  692. unsigned long flags;
  693. snd_azf3328_dbgcallenter();
  694. switch (bitrate) {
  695. case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  696. case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  697. case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */
  698. case 6620: val |= SOUNDFORMAT_FREQ_6620; break;
  699. case 8000: val |= SOUNDFORMAT_FREQ_8000; break;
  700. case 9600: val |= SOUNDFORMAT_FREQ_9600; break;
  701. case 11025: val |= SOUNDFORMAT_FREQ_11025; break;
  702. case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  703. case 16000: val |= SOUNDFORMAT_FREQ_16000; break;
  704. case 22050: val |= SOUNDFORMAT_FREQ_22050; break;
  705. case 32000: val |= SOUNDFORMAT_FREQ_32000; break;
  706. case 44100: val |= SOUNDFORMAT_FREQ_44100; break;
  707. case 48000: val |= SOUNDFORMAT_FREQ_48000; break;
  708. case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  709. default:
  710. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  711. val |= SOUNDFORMAT_FREQ_44100;
  712. break;
  713. }
  714. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  715. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  716. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  717. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  718. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  719. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  720. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  721. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  722. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  723. if (channels == 2)
  724. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  725. if (format_width == 16)
  726. val |= SOUNDFORMAT_FLAG_16BIT;
  727. spin_lock_irqsave(&chip->reg_lock, flags);
  728. /* set bitrate/format */
  729. snd_azf3328_codec_outw(chip, reg, val);
  730. /* changing the bitrate/format settings switches off the
  731. * audio output with an annoying click in case of 8/16bit format change
  732. * (maybe shutting down DAC/ADC?), thus immediately
  733. * do some tweaking to reenable it and get rid of the clicking
  734. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  735. * FIXME: does this have some side effects for full-duplex
  736. * or other dramatic side effects? */
  737. if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
  738. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  739. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
  740. DMA_PLAY_SOMETHING1 |
  741. DMA_PLAY_SOMETHING2 |
  742. SOMETHING_ALMOST_ALWAYS_SET |
  743. DMA_EPILOGUE_SOMETHING |
  744. DMA_SOMETHING_ELSE
  745. );
  746. spin_unlock_irqrestore(&chip->reg_lock, flags);
  747. snd_azf3328_dbgcallleave();
  748. }
  749. static void
  750. snd_azf3328_setdmaa(struct snd_azf3328 *chip,
  751. long unsigned int addr,
  752. unsigned int count,
  753. unsigned int size,
  754. int do_recording)
  755. {
  756. unsigned long flags, portbase;
  757. unsigned int is_running;
  758. snd_azf3328_dbgcallenter();
  759. if (do_recording) {
  760. /* access capture registers, i.e. skip playback reg section */
  761. portbase = chip->codec_port + 0x20;
  762. is_running = chip->is_recording;
  763. } else {
  764. /* access the playback register section */
  765. portbase = chip->codec_port + 0x00;
  766. is_running = chip->is_playing;
  767. }
  768. /* AZF3328 uses a two buffer pointer DMA playback approach */
  769. if (!is_running) {
  770. unsigned long addr_area2;
  771. unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */
  772. count_areas = size/2;
  773. addr_area2 = addr+count_areas;
  774. count_areas--; /* max. index */
  775. snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
  776. /* build combined I/O buffer length word */
  777. count_tmp = count_areas;
  778. count_areas |= (count_tmp << 16);
  779. spin_lock_irqsave(&chip->reg_lock, flags);
  780. outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
  781. outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
  782. outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
  783. spin_unlock_irqrestore(&chip->reg_lock, flags);
  784. }
  785. snd_azf3328_dbgcallleave();
  786. }
  787. static int
  788. snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
  789. {
  790. #if 0
  791. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  792. struct snd_pcm_runtime *runtime = substream->runtime;
  793. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  794. unsigned int count = snd_pcm_lib_period_bytes(substream);
  795. #endif
  796. snd_azf3328_dbgcallenter();
  797. #if 0
  798. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  799. runtime->rate,
  800. snd_pcm_format_width(runtime->format),
  801. runtime->channels);
  802. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 0);
  803. #endif
  804. snd_azf3328_dbgcallleave();
  805. return 0;
  806. }
  807. static int
  808. snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
  809. {
  810. #if 0
  811. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  812. struct snd_pcm_runtime *runtime = substream->runtime;
  813. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  814. unsigned int count = snd_pcm_lib_period_bytes(substream);
  815. #endif
  816. snd_azf3328_dbgcallenter();
  817. #if 0
  818. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  819. runtime->rate,
  820. snd_pcm_format_width(runtime->format),
  821. runtime->channels);
  822. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 1);
  823. #endif
  824. snd_azf3328_dbgcallleave();
  825. return 0;
  826. }
  827. static int
  828. snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  829. {
  830. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  831. struct snd_pcm_runtime *runtime = substream->runtime;
  832. int result = 0;
  833. unsigned int status1;
  834. snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
  835. switch (cmd) {
  836. case SNDRV_PCM_TRIGGER_START:
  837. snd_azf3328_dbgplay("START PLAYBACK\n");
  838. /* mute WaveOut */
  839. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  840. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  841. runtime->rate,
  842. snd_pcm_format_width(runtime->format),
  843. runtime->channels);
  844. spin_lock(&chip->reg_lock);
  845. /* stop playback */
  846. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  847. status1 &= ~DMA_RESUME;
  848. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  849. /* FIXME: clear interrupts or what??? */
  850. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
  851. spin_unlock(&chip->reg_lock);
  852. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  853. snd_pcm_lib_period_bytes(substream),
  854. snd_pcm_lib_buffer_bytes(substream),
  855. 0);
  856. spin_lock(&chip->reg_lock);
  857. #ifdef WIN9X
  858. /* FIXME: enable playback/recording??? */
  859. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  860. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  861. /* start playback again */
  862. /* FIXME: what is this value (0x0010)??? */
  863. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  864. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  865. #else /* NT4 */
  866. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  867. 0x0000);
  868. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  869. DMA_PLAY_SOMETHING1);
  870. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  871. DMA_PLAY_SOMETHING1 |
  872. DMA_PLAY_SOMETHING2);
  873. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  874. DMA_RESUME |
  875. SOMETHING_ALMOST_ALWAYS_SET |
  876. DMA_EPILOGUE_SOMETHING |
  877. DMA_SOMETHING_ELSE);
  878. #endif
  879. spin_unlock(&chip->reg_lock);
  880. /* now unmute WaveOut */
  881. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  882. chip->is_playing = 1;
  883. snd_azf3328_dbgplay("STARTED PLAYBACK\n");
  884. break;
  885. case SNDRV_PCM_TRIGGER_RESUME:
  886. snd_azf3328_dbgplay("RESUME PLAYBACK\n");
  887. /* resume playback if we were active */
  888. if (chip->is_playing)
  889. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  890. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME);
  891. break;
  892. case SNDRV_PCM_TRIGGER_STOP:
  893. snd_azf3328_dbgplay("STOP PLAYBACK\n");
  894. /* mute WaveOut */
  895. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  896. spin_lock(&chip->reg_lock);
  897. /* stop playback */
  898. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  899. status1 &= ~DMA_RESUME;
  900. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  901. /* hmm, is this really required? we're resetting the same bit
  902. * immediately thereafter... */
  903. status1 |= DMA_PLAY_SOMETHING1;
  904. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  905. status1 &= ~DMA_PLAY_SOMETHING1;
  906. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  907. spin_unlock(&chip->reg_lock);
  908. /* now unmute WaveOut */
  909. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  910. chip->is_playing = 0;
  911. snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
  912. break;
  913. case SNDRV_PCM_TRIGGER_SUSPEND:
  914. snd_azf3328_dbgplay("SUSPEND PLAYBACK\n");
  915. /* make sure playback is stopped */
  916. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  917. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME);
  918. break;
  919. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  920. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  921. break;
  922. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  923. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  924. break;
  925. default:
  926. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  927. return -EINVAL;
  928. }
  929. snd_azf3328_dbgcallleave();
  930. return result;
  931. }
  932. /* this is just analogous to playback; I'm not quite sure whether recording
  933. * should actually be triggered like that */
  934. static int
  935. snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  936. {
  937. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  938. struct snd_pcm_runtime *runtime = substream->runtime;
  939. int result = 0;
  940. unsigned int status1;
  941. snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
  942. switch (cmd) {
  943. case SNDRV_PCM_TRIGGER_START:
  944. snd_azf3328_dbgplay("START CAPTURE\n");
  945. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  946. runtime->rate,
  947. snd_pcm_format_width(runtime->format),
  948. runtime->channels);
  949. spin_lock(&chip->reg_lock);
  950. /* stop recording */
  951. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  952. status1 &= ~DMA_RESUME;
  953. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  954. /* FIXME: clear interrupts or what??? */
  955. snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
  956. spin_unlock(&chip->reg_lock);
  957. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  958. snd_pcm_lib_period_bytes(substream),
  959. snd_pcm_lib_buffer_bytes(substream),
  960. 1);
  961. spin_lock(&chip->reg_lock);
  962. #ifdef WIN9X
  963. /* FIXME: enable playback/recording??? */
  964. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  965. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  966. /* start capture again */
  967. /* FIXME: what is this value (0x0010)??? */
  968. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  969. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  970. #else
  971. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  972. 0x0000);
  973. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  974. DMA_PLAY_SOMETHING1);
  975. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  976. DMA_PLAY_SOMETHING1 |
  977. DMA_PLAY_SOMETHING2);
  978. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  979. DMA_RESUME |
  980. SOMETHING_ALMOST_ALWAYS_SET |
  981. DMA_EPILOGUE_SOMETHING |
  982. DMA_SOMETHING_ELSE);
  983. #endif
  984. spin_unlock(&chip->reg_lock);
  985. chip->is_recording = 1;
  986. snd_azf3328_dbgplay("STARTED CAPTURE\n");
  987. break;
  988. case SNDRV_PCM_TRIGGER_RESUME:
  989. snd_azf3328_dbgplay("RESUME CAPTURE\n");
  990. /* resume recording if we were active */
  991. if (chip->is_recording)
  992. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  993. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME);
  994. break;
  995. case SNDRV_PCM_TRIGGER_STOP:
  996. snd_azf3328_dbgplay("STOP CAPTURE\n");
  997. spin_lock(&chip->reg_lock);
  998. /* stop recording */
  999. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  1000. status1 &= ~DMA_RESUME;
  1001. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1002. status1 |= DMA_PLAY_SOMETHING1;
  1003. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1004. status1 &= ~DMA_PLAY_SOMETHING1;
  1005. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1006. spin_unlock(&chip->reg_lock);
  1007. chip->is_recording = 0;
  1008. snd_azf3328_dbgplay("STOPPED CAPTURE\n");
  1009. break;
  1010. case SNDRV_PCM_TRIGGER_SUSPEND:
  1011. snd_azf3328_dbgplay("SUSPEND CAPTURE\n");
  1012. /* make sure recording is stopped */
  1013. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  1014. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME);
  1015. break;
  1016. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1017. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  1018. break;
  1019. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1020. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  1021. break;
  1022. default:
  1023. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  1024. return -EINVAL;
  1025. }
  1026. snd_azf3328_dbgcallleave();
  1027. return result;
  1028. }
  1029. static snd_pcm_uframes_t
  1030. snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
  1031. {
  1032. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1033. unsigned long bufptr, result;
  1034. snd_pcm_uframes_t frmres;
  1035. #ifdef QUERY_HARDWARE
  1036. bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1);
  1037. #else
  1038. bufptr = substream->runtime->dma_addr;
  1039. #endif
  1040. result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS);
  1041. /* calculate offset */
  1042. result -= bufptr;
  1043. frmres = bytes_to_frames( substream->runtime, result);
  1044. snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
  1045. return frmres;
  1046. }
  1047. static snd_pcm_uframes_t
  1048. snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
  1049. {
  1050. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1051. unsigned long bufptr, result;
  1052. snd_pcm_uframes_t frmres;
  1053. #ifdef QUERY_HARDWARE
  1054. bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1);
  1055. #else
  1056. bufptr = substream->runtime->dma_addr;
  1057. #endif
  1058. result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS);
  1059. /* calculate offset */
  1060. result -= bufptr;
  1061. frmres = bytes_to_frames( substream->runtime, result);
  1062. snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
  1063. return frmres;
  1064. }
  1065. static irqreturn_t
  1066. snd_azf3328_interrupt(int irq, void *dev_id)
  1067. {
  1068. struct snd_azf3328 *chip = dev_id;
  1069. u8 status, which;
  1070. static unsigned long irq_count;
  1071. status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
  1072. /* fast path out, to ease interrupt sharing */
  1073. if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER)))
  1074. return IRQ_NONE; /* must be interrupt for another device */
  1075. snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
  1076. irq_count,
  1077. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
  1078. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
  1079. status);
  1080. if (status & IRQ_TIMER) {
  1081. /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */
  1082. if (chip->timer)
  1083. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1084. /* ACK timer */
  1085. spin_lock(&chip->reg_lock);
  1086. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1087. spin_unlock(&chip->reg_lock);
  1088. snd_azf3328_dbgplay("azt3328: timer IRQ\n");
  1089. }
  1090. if (status & IRQ_PLAYBACK) {
  1091. spin_lock(&chip->reg_lock);
  1092. which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
  1093. /* ack all IRQ types immediately */
  1094. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
  1095. spin_unlock(&chip->reg_lock);
  1096. if (chip->pcm && chip->playback_substream) {
  1097. snd_pcm_period_elapsed(chip->playback_substream);
  1098. snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
  1099. which,
  1100. inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS));
  1101. } else
  1102. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1103. if (which & IRQ_PLAY_SOMETHING)
  1104. snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
  1105. }
  1106. if (status & IRQ_RECORDING) {
  1107. spin_lock(&chip->reg_lock);
  1108. which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
  1109. /* ack all IRQ types immediately */
  1110. snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
  1111. spin_unlock(&chip->reg_lock);
  1112. if (chip->pcm && chip->capture_substream) {
  1113. snd_pcm_period_elapsed(chip->capture_substream);
  1114. snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
  1115. which,
  1116. inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS));
  1117. } else
  1118. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1119. if (which & IRQ_REC_SOMETHING)
  1120. snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
  1121. }
  1122. /* MPU401 has less critical IRQ requirements
  1123. * than timer and playback/recording, right? */
  1124. if (status & IRQ_MPU401) {
  1125. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1126. /* hmm, do we have to ack the IRQ here somehow?
  1127. * If so, then I don't know how... */
  1128. snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
  1129. }
  1130. irq_count++;
  1131. return IRQ_HANDLED;
  1132. }
  1133. /*****************************************************************/
  1134. static const struct snd_pcm_hardware snd_azf3328_playback =
  1135. {
  1136. /* FIXME!! Correct? */
  1137. .info = SNDRV_PCM_INFO_MMAP |
  1138. SNDRV_PCM_INFO_INTERLEAVED |
  1139. SNDRV_PCM_INFO_MMAP_VALID,
  1140. .formats = SNDRV_PCM_FMTBIT_S8 |
  1141. SNDRV_PCM_FMTBIT_U8 |
  1142. SNDRV_PCM_FMTBIT_S16_LE |
  1143. SNDRV_PCM_FMTBIT_U16_LE,
  1144. .rates = SNDRV_PCM_RATE_5512 |
  1145. SNDRV_PCM_RATE_8000_48000 |
  1146. SNDRV_PCM_RATE_KNOT,
  1147. .rate_min = 4000,
  1148. .rate_max = 66200,
  1149. .channels_min = 1,
  1150. .channels_max = 2,
  1151. .buffer_bytes_max = 65536,
  1152. .period_bytes_min = 64,
  1153. .period_bytes_max = 65536,
  1154. .periods_min = 1,
  1155. .periods_max = 1024,
  1156. /* FIXME: maybe that card actually has a FIFO?
  1157. * Hmm, it seems newer revisions do have one, but we still don't know
  1158. * its size... */
  1159. .fifo_size = 0,
  1160. };
  1161. static const struct snd_pcm_hardware snd_azf3328_capture =
  1162. {
  1163. /* FIXME */
  1164. .info = SNDRV_PCM_INFO_MMAP |
  1165. SNDRV_PCM_INFO_INTERLEAVED |
  1166. SNDRV_PCM_INFO_MMAP_VALID,
  1167. .formats = SNDRV_PCM_FMTBIT_S8 |
  1168. SNDRV_PCM_FMTBIT_U8 |
  1169. SNDRV_PCM_FMTBIT_S16_LE |
  1170. SNDRV_PCM_FMTBIT_U16_LE,
  1171. .rates = SNDRV_PCM_RATE_5512 |
  1172. SNDRV_PCM_RATE_8000_48000 |
  1173. SNDRV_PCM_RATE_KNOT,
  1174. .rate_min = 4000,
  1175. .rate_max = 66200,
  1176. .channels_min = 1,
  1177. .channels_max = 2,
  1178. .buffer_bytes_max = 65536,
  1179. .period_bytes_min = 64,
  1180. .period_bytes_max = 65536,
  1181. .periods_min = 1,
  1182. .periods_max = 1024,
  1183. .fifo_size = 0,
  1184. };
  1185. static unsigned int snd_azf3328_fixed_rates[] = {
  1186. 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000,
  1187. 44100, 48000, 66200 };
  1188. static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1189. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1190. .list = snd_azf3328_fixed_rates,
  1191. .mask = 0,
  1192. };
  1193. /*****************************************************************/
  1194. static int
  1195. snd_azf3328_playback_open(struct snd_pcm_substream *substream)
  1196. {
  1197. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1198. struct snd_pcm_runtime *runtime = substream->runtime;
  1199. snd_azf3328_dbgcallenter();
  1200. chip->playback_substream = substream;
  1201. runtime->hw = snd_azf3328_playback;
  1202. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1203. &snd_azf3328_hw_constraints_rates);
  1204. snd_azf3328_dbgcallleave();
  1205. return 0;
  1206. }
  1207. static int
  1208. snd_azf3328_capture_open(struct snd_pcm_substream *substream)
  1209. {
  1210. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1211. struct snd_pcm_runtime *runtime = substream->runtime;
  1212. snd_azf3328_dbgcallenter();
  1213. chip->capture_substream = substream;
  1214. runtime->hw = snd_azf3328_capture;
  1215. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1216. &snd_azf3328_hw_constraints_rates);
  1217. snd_azf3328_dbgcallleave();
  1218. return 0;
  1219. }
  1220. static int
  1221. snd_azf3328_playback_close(struct snd_pcm_substream *substream)
  1222. {
  1223. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1224. snd_azf3328_dbgcallenter();
  1225. chip->playback_substream = NULL;
  1226. snd_azf3328_dbgcallleave();
  1227. return 0;
  1228. }
  1229. static int
  1230. snd_azf3328_capture_close(struct snd_pcm_substream *substream)
  1231. {
  1232. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1233. snd_azf3328_dbgcallenter();
  1234. chip->capture_substream = NULL;
  1235. snd_azf3328_dbgcallleave();
  1236. return 0;
  1237. }
  1238. /******************************************************************/
  1239. static struct snd_pcm_ops snd_azf3328_playback_ops = {
  1240. .open = snd_azf3328_playback_open,
  1241. .close = snd_azf3328_playback_close,
  1242. .ioctl = snd_pcm_lib_ioctl,
  1243. .hw_params = snd_azf3328_hw_params,
  1244. .hw_free = snd_azf3328_hw_free,
  1245. .prepare = snd_azf3328_playback_prepare,
  1246. .trigger = snd_azf3328_playback_trigger,
  1247. .pointer = snd_azf3328_playback_pointer
  1248. };
  1249. static struct snd_pcm_ops snd_azf3328_capture_ops = {
  1250. .open = snd_azf3328_capture_open,
  1251. .close = snd_azf3328_capture_close,
  1252. .ioctl = snd_pcm_lib_ioctl,
  1253. .hw_params = snd_azf3328_hw_params,
  1254. .hw_free = snd_azf3328_hw_free,
  1255. .prepare = snd_azf3328_capture_prepare,
  1256. .trigger = snd_azf3328_capture_trigger,
  1257. .pointer = snd_azf3328_capture_pointer
  1258. };
  1259. static int __devinit
  1260. snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
  1261. {
  1262. struct snd_pcm *pcm;
  1263. int err;
  1264. snd_azf3328_dbgcallenter();
  1265. if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
  1266. return err;
  1267. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
  1268. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
  1269. pcm->private_data = chip;
  1270. pcm->info_flags = 0;
  1271. strcpy(pcm->name, chip->card->shortname);
  1272. chip->pcm = pcm;
  1273. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1274. snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
  1275. snd_azf3328_dbgcallleave();
  1276. return 0;
  1277. }
  1278. /******************************************************************/
  1279. #ifdef SUPPORT_JOYSTICK
  1280. static int __devinit
  1281. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev)
  1282. {
  1283. struct gameport *gp;
  1284. struct resource *r;
  1285. if (!joystick[dev])
  1286. return -ENODEV;
  1287. if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) {
  1288. printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n");
  1289. return -EBUSY;
  1290. }
  1291. chip->gameport = gp = gameport_allocate_port();
  1292. if (!gp) {
  1293. printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n");
  1294. release_and_free_resource(r);
  1295. return -ENOMEM;
  1296. }
  1297. gameport_set_name(gp, "AZF3328 Gameport");
  1298. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1299. gameport_set_dev_parent(gp, &chip->pci->dev);
  1300. gp->io = 0x200;
  1301. gameport_set_port_data(gp, r);
  1302. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1303. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY);
  1304. gameport_register_port(chip->gameport);
  1305. return 0;
  1306. }
  1307. static void
  1308. snd_azf3328_free_joystick(struct snd_azf3328 *chip)
  1309. {
  1310. if (chip->gameport) {
  1311. struct resource *r = gameport_get_port_data(chip->gameport);
  1312. gameport_unregister_port(chip->gameport);
  1313. chip->gameport = NULL;
  1314. /* disable gameport */
  1315. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1316. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1317. release_and_free_resource(r);
  1318. }
  1319. }
  1320. #else
  1321. static inline int
  1322. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1323. static inline void
  1324. snd_azf3328_free_joystick(struct snd_azf3328 *chip) { }
  1325. #endif
  1326. /******************************************************************/
  1327. static int
  1328. snd_azf3328_free(struct snd_azf3328 *chip)
  1329. {
  1330. if (chip->irq < 0)
  1331. goto __end_hw;
  1332. /* reset (close) mixer */
  1333. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */
  1334. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1335. /* interrupt setup - mask everything (FIXME!) */
  1336. /* well, at least we know how to disable the timer IRQ */
  1337. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00);
  1338. synchronize_irq(chip->irq);
  1339. __end_hw:
  1340. snd_azf3328_free_joystick(chip);
  1341. if (chip->irq >= 0)
  1342. free_irq(chip->irq, chip);
  1343. pci_release_regions(chip->pci);
  1344. pci_disable_device(chip->pci);
  1345. kfree(chip);
  1346. return 0;
  1347. }
  1348. static int
  1349. snd_azf3328_dev_free(struct snd_device *device)
  1350. {
  1351. struct snd_azf3328 *chip = device->device_data;
  1352. return snd_azf3328_free(chip);
  1353. }
  1354. /******************************************************************/
  1355. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second,
  1356. *** but announcing those attributes to user-space would make programs
  1357. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1358. *** timer IRQ storm.
  1359. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1360. *** calculate real timer countdown values internally.
  1361. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1362. ***/
  1363. static int
  1364. snd_azf3328_timer_start(struct snd_timer *timer)
  1365. {
  1366. struct snd_azf3328 *chip;
  1367. unsigned long flags;
  1368. unsigned int delay;
  1369. snd_azf3328_dbgcallenter();
  1370. chip = snd_timer_chip(timer);
  1371. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1372. if (delay < 49) {
  1373. /* uhoh, that's not good, since user-space won't know about
  1374. * this timing tweak
  1375. * (we need to do it to avoid a lockup, though) */
  1376. snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
  1377. delay = 49; /* minimum time is 49 ticks */
  1378. }
  1379. snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
  1380. delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ;
  1381. spin_lock_irqsave(&chip->reg_lock, flags);
  1382. snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1383. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1384. snd_azf3328_dbgcallleave();
  1385. return 0;
  1386. }
  1387. static int
  1388. snd_azf3328_timer_stop(struct snd_timer *timer)
  1389. {
  1390. struct snd_azf3328 *chip;
  1391. unsigned long flags;
  1392. snd_azf3328_dbgcallenter();
  1393. chip = snd_timer_chip(timer);
  1394. spin_lock_irqsave(&chip->reg_lock, flags);
  1395. /* disable timer countdown and interrupt */
  1396. /* FIXME: should we write TIMER_ACK_IRQ here? */
  1397. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
  1398. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1399. snd_azf3328_dbgcallleave();
  1400. return 0;
  1401. }
  1402. static int
  1403. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1404. unsigned long *num, unsigned long *den)
  1405. {
  1406. snd_azf3328_dbgcallenter();
  1407. *num = 1;
  1408. *den = 1024000 / seqtimer_scaling;
  1409. snd_azf3328_dbgcallleave();
  1410. return 0;
  1411. }
  1412. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1413. .flags = SNDRV_TIMER_HW_AUTO,
  1414. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1415. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1416. .start = snd_azf3328_timer_start,
  1417. .stop = snd_azf3328_timer_stop,
  1418. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1419. };
  1420. static int __devinit
  1421. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1422. {
  1423. struct snd_timer *timer = NULL;
  1424. struct snd_timer_id tid;
  1425. int err;
  1426. snd_azf3328_dbgcallenter();
  1427. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1428. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1429. tid.card = chip->card->number;
  1430. tid.device = device;
  1431. tid.subdevice = 0;
  1432. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1433. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1434. if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) {
  1435. goto out;
  1436. }
  1437. strcpy(timer->name, "AZF3328 timer");
  1438. timer->private_data = chip;
  1439. timer->hw = snd_azf3328_timer_hw;
  1440. chip->timer = timer;
  1441. err = 0;
  1442. out:
  1443. snd_azf3328_dbgcallleave();
  1444. return err;
  1445. }
  1446. /******************************************************************/
  1447. #if 0
  1448. /* check whether a bit can be modified */
  1449. static void
  1450. snd_azf3328_test_bit(unsigned int reg, int bit)
  1451. {
  1452. unsigned char val, valoff, valon;
  1453. val = inb(reg);
  1454. outb(val & ~(1 << bit), reg);
  1455. valoff = inb(reg);
  1456. outb(val|(1 << bit), reg);
  1457. valon = inb(reg);
  1458. outb(val, reg);
  1459. printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon);
  1460. }
  1461. #endif
  1462. #if DEBUG_MISC
  1463. static void
  1464. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  1465. {
  1466. u16 tmp;
  1467. snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq);
  1468. snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5));
  1469. for (tmp=0; tmp <= 0x01; tmp += 1)
  1470. snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp));
  1471. for (tmp = 0; tmp < AZF_IO_SIZE_CODEC; tmp += 2)
  1472. snd_azf3328_dbgmisc("codec 0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inw(chip, tmp));
  1473. for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
  1474. snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n", tmp, snd_azf3328_mixer_inw(chip, tmp));
  1475. }
  1476. #else
  1477. static inline void
  1478. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) {}
  1479. #endif
  1480. static int __devinit
  1481. snd_azf3328_create(struct snd_card *card,
  1482. struct pci_dev *pci,
  1483. unsigned long device_type,
  1484. struct snd_azf3328 ** rchip)
  1485. {
  1486. struct snd_azf3328 *chip;
  1487. int err;
  1488. static struct snd_device_ops ops = {
  1489. .dev_free = snd_azf3328_dev_free,
  1490. };
  1491. u16 tmp;
  1492. *rchip = NULL;
  1493. if ((err = pci_enable_device(pci)) < 0)
  1494. return err;
  1495. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1496. if (chip == NULL) {
  1497. err = -ENOMEM;
  1498. goto out_err;
  1499. }
  1500. spin_lock_init(&chip->reg_lock);
  1501. chip->card = card;
  1502. chip->pci = pci;
  1503. chip->irq = -1;
  1504. /* check if we can restrict PCI DMA transfers to 24 bits */
  1505. if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
  1506. pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
  1507. snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n");
  1508. err = -ENXIO;
  1509. goto out_err;
  1510. }
  1511. if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) {
  1512. goto out_err;
  1513. }
  1514. chip->codec_port = pci_resource_start(pci, 0);
  1515. chip->io2_port = pci_resource_start(pci, 1);
  1516. chip->mpu_port = pci_resource_start(pci, 2);
  1517. chip->synth_port = pci_resource_start(pci, 3);
  1518. chip->mixer_port = pci_resource_start(pci, 4);
  1519. if (request_irq(pci->irq, snd_azf3328_interrupt,
  1520. IRQF_SHARED, card->shortname, chip)) {
  1521. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1522. err = -EBUSY;
  1523. goto out_err;
  1524. }
  1525. chip->irq = pci->irq;
  1526. pci_set_master(pci);
  1527. synchronize_irq(chip->irq);
  1528. snd_azf3328_debug_show_ports(chip);
  1529. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1530. goto out_err;
  1531. }
  1532. /* create mixer interface & switches */
  1533. if ((err = snd_azf3328_mixer_new(chip)) < 0)
  1534. goto out_err;
  1535. #if 0
  1536. /* set very low bitrate to reduce noise and power consumption? */
  1537. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 5512, 8, 1);
  1538. #endif
  1539. /* standard chip init stuff */
  1540. /* default IRQ init value */
  1541. tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  1542. spin_lock_irq(&chip->reg_lock);
  1543. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
  1544. snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
  1545. snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
  1546. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */
  1547. spin_unlock_irq(&chip->reg_lock);
  1548. snd_card_set_dev(card, &pci->dev);
  1549. *rchip = chip;
  1550. err = 0;
  1551. goto out;
  1552. out_err:
  1553. if (chip)
  1554. snd_azf3328_free(chip);
  1555. pci_disable_device(pci);
  1556. out:
  1557. return err;
  1558. }
  1559. static int __devinit
  1560. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1561. {
  1562. static int dev;
  1563. struct snd_card *card;
  1564. struct snd_azf3328 *chip;
  1565. struct snd_opl3 *opl3;
  1566. int err;
  1567. snd_azf3328_dbgcallenter();
  1568. if (dev >= SNDRV_CARDS)
  1569. return -ENODEV;
  1570. if (!enable[dev]) {
  1571. dev++;
  1572. return -ENOENT;
  1573. }
  1574. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 );
  1575. if (card == NULL)
  1576. return -ENOMEM;
  1577. strcpy(card->driver, "AZF3328");
  1578. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  1579. if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1580. goto out_err;
  1581. }
  1582. card->private_data = chip;
  1583. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401,
  1584. chip->mpu_port, MPU401_INFO_INTEGRATED,
  1585. pci->irq, 0, &chip->rmidi)) < 0) {
  1586. snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port);
  1587. goto out_err;
  1588. }
  1589. if ((err = snd_azf3328_timer(chip, 0)) < 0) {
  1590. goto out_err;
  1591. }
  1592. if ((err = snd_azf3328_pcm(chip, 0)) < 0) {
  1593. goto out_err;
  1594. }
  1595. if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2,
  1596. OPL3_HW_AUTO, 1, &opl3) < 0) {
  1597. snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
  1598. chip->synth_port, chip->synth_port+2 );
  1599. } else {
  1600. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1601. goto out_err;
  1602. }
  1603. }
  1604. opl3->private_data = chip;
  1605. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1606. card->shortname, chip->codec_port, chip->irq);
  1607. if ((err = snd_card_register(card)) < 0) {
  1608. goto out_err;
  1609. }
  1610. #ifdef MODULE
  1611. printk(
  1612. "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
  1613. "azt3328: Hardware was completely undocumented, unfortunately.\n"
  1614. "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
  1615. "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  1616. 1024000 / seqtimer_scaling, seqtimer_scaling);
  1617. #endif
  1618. if (snd_azf3328_config_joystick(chip, dev) < 0)
  1619. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1620. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1621. pci_set_drvdata(pci, card);
  1622. dev++;
  1623. err = 0;
  1624. goto out;
  1625. out_err:
  1626. snd_card_free(card);
  1627. out:
  1628. snd_azf3328_dbgcallleave();
  1629. return err;
  1630. }
  1631. static void __devexit
  1632. snd_azf3328_remove(struct pci_dev *pci)
  1633. {
  1634. snd_azf3328_dbgcallenter();
  1635. snd_card_free(pci_get_drvdata(pci));
  1636. pci_set_drvdata(pci, NULL);
  1637. snd_azf3328_dbgcallleave();
  1638. }
  1639. #ifdef CONFIG_PM
  1640. static int
  1641. snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
  1642. {
  1643. struct snd_card *card = pci_get_drvdata(pci);
  1644. struct snd_azf3328 *chip = card->private_data;
  1645. int reg;
  1646. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1647. snd_pcm_suspend_all(chip->pcm);
  1648. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1649. chip->saved_regs_mixer[reg] = inw(chip->mixer_port + reg * 2);
  1650. /* make sure to disable master volume etc. to prevent looping sound */
  1651. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
  1652. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  1653. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1654. chip->saved_regs_codec[reg] = inw(chip->codec_port + reg * 2);
  1655. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1656. chip->saved_regs_io2[reg] = inw(chip->io2_port + reg * 2);
  1657. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1658. chip->saved_regs_mpu[reg] = inw(chip->mpu_port + reg * 2);
  1659. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1660. chip->saved_regs_synth[reg] = inw(chip->synth_port + reg * 2);
  1661. pci_disable_device(pci);
  1662. pci_save_state(pci);
  1663. pci_set_power_state(pci, pci_choose_state(pci, state));
  1664. return 0;
  1665. }
  1666. static int
  1667. snd_azf3328_resume(struct pci_dev *pci)
  1668. {
  1669. struct snd_card *card = pci_get_drvdata(pci);
  1670. struct snd_azf3328 *chip = card->private_data;
  1671. int reg;
  1672. pci_set_power_state(pci, PCI_D0);
  1673. pci_restore_state(pci);
  1674. if (pci_enable_device(pci) < 0) {
  1675. printk(KERN_ERR "azt3328: pci_enable_device failed, "
  1676. "disabling device\n");
  1677. snd_card_disconnect(card);
  1678. return -EIO;
  1679. }
  1680. pci_set_master(pci);
  1681. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1682. outw(chip->saved_regs_io2[reg], chip->io2_port + reg * 2);
  1683. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1684. outw(chip->saved_regs_mpu[reg], chip->mpu_port + reg * 2);
  1685. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1686. outw(chip->saved_regs_synth[reg], chip->synth_port + reg * 2);
  1687. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1688. outw(chip->saved_regs_mixer[reg], chip->mixer_port + reg * 2);
  1689. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1690. outw(chip->saved_regs_codec[reg], chip->codec_port + reg * 2);
  1691. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1692. return 0;
  1693. }
  1694. #endif
  1695. static struct pci_driver driver = {
  1696. .name = "AZF3328",
  1697. .id_table = snd_azf3328_ids,
  1698. .probe = snd_azf3328_probe,
  1699. .remove = __devexit_p(snd_azf3328_remove),
  1700. #ifdef CONFIG_PM
  1701. .suspend = snd_azf3328_suspend,
  1702. .resume = snd_azf3328_resume,
  1703. #endif
  1704. };
  1705. static int __init
  1706. alsa_card_azf3328_init(void)
  1707. {
  1708. int err;
  1709. snd_azf3328_dbgcallenter();
  1710. err = pci_register_driver(&driver);
  1711. snd_azf3328_dbgcallleave();
  1712. return err;
  1713. }
  1714. static void __exit
  1715. alsa_card_azf3328_exit(void)
  1716. {
  1717. snd_azf3328_dbgcallenter();
  1718. pci_unregister_driver(&driver);
  1719. snd_azf3328_dbgcallleave();
  1720. }
  1721. module_init(alsa_card_azf3328_init)
  1722. module_exit(alsa_card_azf3328_exit)