ehci-mem.c 6.1 KB

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  1. /*
  2. * Copyright (c) 2001 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. /*-------------------------------------------------------------------------*/
  20. /*
  21. * There's basically three types of memory:
  22. * - data used only by the HCD ... kmalloc is fine
  23. * - async and periodic schedules, shared by HC and HCD ... these
  24. * need to use dma_pool or dma_alloc_coherent
  25. * - driver buffers, read/written by HC ... single shot DMA mapped
  26. *
  27. * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
  28. * No memory seen by this driver is pageable.
  29. */
  30. /*-------------------------------------------------------------------------*/
  31. /* Allocate the key transfer structures from the previously allocated pool */
  32. static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
  33. dma_addr_t dma)
  34. {
  35. memset (qtd, 0, sizeof *qtd);
  36. qtd->qtd_dma = dma;
  37. qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
  38. qtd->hw_next = EHCI_LIST_END(ehci);
  39. qtd->hw_alt_next = EHCI_LIST_END(ehci);
  40. INIT_LIST_HEAD (&qtd->qtd_list);
  41. }
  42. static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
  43. {
  44. struct ehci_qtd *qtd;
  45. dma_addr_t dma;
  46. qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
  47. if (qtd != NULL) {
  48. ehci_qtd_init(ehci, qtd, dma);
  49. }
  50. return qtd;
  51. }
  52. static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  53. {
  54. dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
  55. }
  56. static void qh_destroy(struct ehci_qh *qh)
  57. {
  58. struct ehci_hcd *ehci = qh->ehci;
  59. /* clean qtds first, and know this is not linked */
  60. if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
  61. ehci_dbg (ehci, "unused qh not empty!\n");
  62. BUG ();
  63. }
  64. if (qh->dummy)
  65. ehci_qtd_free (ehci, qh->dummy);
  66. dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
  67. }
  68. static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
  69. {
  70. struct ehci_qh *qh;
  71. dma_addr_t dma;
  72. qh = (struct ehci_qh *)
  73. dma_pool_alloc (ehci->qh_pool, flags, &dma);
  74. if (!qh)
  75. return qh;
  76. memset (qh, 0, sizeof *qh);
  77. qh->refcount = 1;
  78. qh->ehci = ehci;
  79. qh->qh_dma = dma;
  80. // INIT_LIST_HEAD (&qh->qh_list);
  81. INIT_LIST_HEAD (&qh->qtd_list);
  82. #ifdef CONFIG_CPU_FREQ
  83. INIT_LIST_HEAD (&qh->split_intr_qhs);
  84. #endif
  85. /* dummy td enables safe urb queuing */
  86. qh->dummy = ehci_qtd_alloc (ehci, flags);
  87. if (qh->dummy == NULL) {
  88. ehci_dbg (ehci, "no dummy td\n");
  89. dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
  90. qh = NULL;
  91. }
  92. return qh;
  93. }
  94. /* to share a qh (cpu threads, or hc) */
  95. static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
  96. {
  97. WARN_ON(!qh->refcount);
  98. qh->refcount++;
  99. return qh;
  100. }
  101. static inline void qh_put (struct ehci_qh *qh)
  102. {
  103. if (!--qh->refcount)
  104. qh_destroy(qh);
  105. }
  106. /*-------------------------------------------------------------------------*/
  107. /* The queue heads and transfer descriptors are managed from pools tied
  108. * to each of the "per device" structures.
  109. * This is the initialisation and cleanup code.
  110. */
  111. static void ehci_mem_cleanup (struct ehci_hcd *ehci)
  112. {
  113. if (ehci->async)
  114. qh_put (ehci->async);
  115. ehci->async = NULL;
  116. /* DMA consistent memory and pools */
  117. if (ehci->qtd_pool)
  118. dma_pool_destroy (ehci->qtd_pool);
  119. ehci->qtd_pool = NULL;
  120. if (ehci->qh_pool) {
  121. dma_pool_destroy (ehci->qh_pool);
  122. ehci->qh_pool = NULL;
  123. }
  124. if (ehci->itd_pool)
  125. dma_pool_destroy (ehci->itd_pool);
  126. ehci->itd_pool = NULL;
  127. if (ehci->sitd_pool)
  128. dma_pool_destroy (ehci->sitd_pool);
  129. ehci->sitd_pool = NULL;
  130. if (ehci->periodic)
  131. dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
  132. ehci->periodic_size * sizeof (u32),
  133. ehci->periodic, ehci->periodic_dma);
  134. ehci->periodic = NULL;
  135. /* shadow periodic table */
  136. kfree(ehci->pshadow);
  137. ehci->pshadow = NULL;
  138. }
  139. /* remember to add cleanup code (above) if you add anything here */
  140. static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
  141. {
  142. int i;
  143. /* QTDs for control/bulk/intr transfers */
  144. ehci->qtd_pool = dma_pool_create ("ehci_qtd",
  145. ehci_to_hcd(ehci)->self.controller,
  146. sizeof (struct ehci_qtd),
  147. 32 /* byte alignment (for hw parts) */,
  148. 4096 /* can't cross 4K */);
  149. if (!ehci->qtd_pool) {
  150. goto fail;
  151. }
  152. /* QHs for control/bulk/intr transfers */
  153. ehci->qh_pool = dma_pool_create ("ehci_qh",
  154. ehci_to_hcd(ehci)->self.controller,
  155. sizeof (struct ehci_qh),
  156. 32 /* byte alignment (for hw parts) */,
  157. 4096 /* can't cross 4K */);
  158. if (!ehci->qh_pool) {
  159. goto fail;
  160. }
  161. ehci->async = ehci_qh_alloc (ehci, flags);
  162. if (!ehci->async) {
  163. goto fail;
  164. }
  165. /* ITD for high speed ISO transfers */
  166. ehci->itd_pool = dma_pool_create ("ehci_itd",
  167. ehci_to_hcd(ehci)->self.controller,
  168. sizeof (struct ehci_itd),
  169. 32 /* byte alignment (for hw parts) */,
  170. 4096 /* can't cross 4K */);
  171. if (!ehci->itd_pool) {
  172. goto fail;
  173. }
  174. /* SITD for full/low speed split ISO transfers */
  175. ehci->sitd_pool = dma_pool_create ("ehci_sitd",
  176. ehci_to_hcd(ehci)->self.controller,
  177. sizeof (struct ehci_sitd),
  178. 32 /* byte alignment (for hw parts) */,
  179. 4096 /* can't cross 4K */);
  180. if (!ehci->sitd_pool) {
  181. goto fail;
  182. }
  183. /* Hardware periodic table */
  184. ehci->periodic = (__le32 *)
  185. dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
  186. ehci->periodic_size * sizeof(__le32),
  187. &ehci->periodic_dma, 0);
  188. if (ehci->periodic == NULL) {
  189. goto fail;
  190. }
  191. for (i = 0; i < ehci->periodic_size; i++)
  192. ehci->periodic [i] = EHCI_LIST_END(ehci);
  193. /* software shadow of hardware table */
  194. ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
  195. if (ehci->pshadow != NULL)
  196. return 0;
  197. fail:
  198. ehci_dbg (ehci, "couldn't init memory\n");
  199. ehci_mem_cleanup (ehci);
  200. return -ENOMEM;
  201. }