m66592-udc.c 40 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/sched.h>
  25. #include <linux/smp_lock.h>
  26. #include <linux/errno.h>
  27. #include <linux/init.h>
  28. #include <linux/timer.h>
  29. #include <linux/delay.h>
  30. #include <linux/list.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/usb/ch9.h>
  34. #include <linux/usb_gadget.h>
  35. #include <asm/io.h>
  36. #include <asm/irq.h>
  37. #include <asm/system.h>
  38. #include "m66592-udc.h"
  39. MODULE_DESCRIPTION("M66592 USB gadget driiver");
  40. MODULE_LICENSE("GPL");
  41. MODULE_AUTHOR("Yoshihiro Shimoda");
  42. #define DRIVER_VERSION "29 May 2007"
  43. /* module parameters */
  44. static unsigned short clock = M66592_XTAL24;
  45. module_param(clock, ushort, 0644);
  46. MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=16384)");
  47. static unsigned short vif = M66592_LDRV;
  48. module_param(vif, ushort, 0644);
  49. MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)");
  50. static unsigned short endian = 0;
  51. module_param(endian, ushort, 0644);
  52. MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)");
  53. static unsigned short irq_sense = M66592_INTL;
  54. module_param(irq_sense, ushort, 0644);
  55. MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0(default=2)");
  56. static const char udc_name[] = "m66592_udc";
  57. static const char *m66592_ep_name[] = {
  58. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  59. };
  60. static void disable_controller(struct m66592 *m66592);
  61. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  62. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  63. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  64. gfp_t gfp_flags);
  65. static void transfer_complete(struct m66592_ep *ep,
  66. struct m66592_request *req,
  67. int status);
  68. /*-------------------------------------------------------------------------*/
  69. static inline u16 get_usb_speed(struct m66592 *m66592)
  70. {
  71. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  72. }
  73. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  74. unsigned long reg)
  75. {
  76. u16 tmp;
  77. tmp = m66592_read(m66592, M66592_INTENB0);
  78. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  79. M66592_INTENB0);
  80. m66592_bset(m66592, (1 << pipenum), reg);
  81. m66592_write(m66592, tmp, M66592_INTENB0);
  82. }
  83. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  84. unsigned long reg)
  85. {
  86. u16 tmp;
  87. tmp = m66592_read(m66592, M66592_INTENB0);
  88. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  89. M66592_INTENB0);
  90. m66592_bclr(m66592, (1 << pipenum), reg);
  91. m66592_write(m66592, tmp, M66592_INTENB0);
  92. }
  93. static void m66592_usb_connect(struct m66592 *m66592)
  94. {
  95. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  96. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  97. M66592_INTENB0);
  98. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  99. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  100. }
  101. static void m66592_usb_disconnect(struct m66592 *m66592)
  102. {
  103. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  104. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  105. M66592_INTENB0);
  106. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  107. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  108. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  109. spin_unlock(&m66592->lock);
  110. m66592->driver->disconnect(&m66592->gadget);
  111. spin_lock(&m66592->lock);
  112. disable_controller(m66592);
  113. INIT_LIST_HEAD(&m66592->ep[0].queue);
  114. }
  115. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  116. {
  117. u16 pid = 0;
  118. unsigned long offset;
  119. if (pipenum == 0)
  120. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  121. else if (pipenum < M66592_MAX_NUM_PIPE) {
  122. offset = get_pipectr_addr(pipenum);
  123. pid = m66592_read(m66592, offset) & M66592_PID;
  124. } else
  125. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  126. return pid;
  127. }
  128. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  129. u16 pid)
  130. {
  131. unsigned long offset;
  132. if (pipenum == 0)
  133. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  134. else if (pipenum < M66592_MAX_NUM_PIPE) {
  135. offset = get_pipectr_addr(pipenum);
  136. m66592_mdfy(m66592, pid, M66592_PID, offset);
  137. } else
  138. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  139. }
  140. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  141. {
  142. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  143. }
  144. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  145. {
  146. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  147. }
  148. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  149. {
  150. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  151. }
  152. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  153. {
  154. u16 ret = 0;
  155. unsigned long offset;
  156. if (pipenum == 0)
  157. ret = m66592_read(m66592, M66592_DCPCTR);
  158. else if (pipenum < M66592_MAX_NUM_PIPE) {
  159. offset = get_pipectr_addr(pipenum);
  160. ret = m66592_read(m66592, offset);
  161. } else
  162. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  163. return ret;
  164. }
  165. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  166. {
  167. unsigned long offset;
  168. pipe_stop(m66592, pipenum);
  169. if (pipenum == 0)
  170. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  171. else if (pipenum < M66592_MAX_NUM_PIPE) {
  172. offset = get_pipectr_addr(pipenum);
  173. m66592_bset(m66592, M66592_SQCLR, offset);
  174. } else
  175. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  176. }
  177. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  178. {
  179. u16 tmp;
  180. int size;
  181. if (pipenum == 0) {
  182. tmp = m66592_read(m66592, M66592_DCPCFG);
  183. if ((tmp & M66592_CNTMD) != 0)
  184. size = 256;
  185. else {
  186. tmp = m66592_read(m66592, M66592_DCPMAXP);
  187. size = tmp & M66592_MAXP;
  188. }
  189. } else {
  190. m66592_write(m66592, pipenum, M66592_PIPESEL);
  191. tmp = m66592_read(m66592, M66592_PIPECFG);
  192. if ((tmp & M66592_CNTMD) != 0) {
  193. tmp = m66592_read(m66592, M66592_PIPEBUF);
  194. size = ((tmp >> 10) + 1) * 64;
  195. } else {
  196. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  197. size = tmp & M66592_MXPS;
  198. }
  199. }
  200. return size;
  201. }
  202. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  203. {
  204. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  205. if (ep->use_dma)
  206. return;
  207. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  208. ndelay(450);
  209. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  210. }
  211. static int pipe_buffer_setting(struct m66592 *m66592,
  212. struct m66592_pipe_info *info)
  213. {
  214. u16 bufnum = 0, buf_bsize = 0;
  215. u16 pipecfg = 0;
  216. if (info->pipe == 0)
  217. return -EINVAL;
  218. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  219. if (info->dir_in)
  220. pipecfg |= M66592_DIR;
  221. pipecfg |= info->type;
  222. pipecfg |= info->epnum;
  223. switch (info->type) {
  224. case M66592_INT:
  225. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  226. buf_bsize = 0;
  227. break;
  228. case M66592_BULK:
  229. bufnum = m66592->bi_bufnum +
  230. (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
  231. m66592->bi_bufnum += 16;
  232. buf_bsize = 7;
  233. pipecfg |= M66592_DBLB;
  234. if (!info->dir_in)
  235. pipecfg |= M66592_SHTNAK;
  236. break;
  237. case M66592_ISO:
  238. bufnum = m66592->bi_bufnum +
  239. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  240. m66592->bi_bufnum += 16;
  241. buf_bsize = 7;
  242. break;
  243. }
  244. if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
  245. printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n",
  246. m66592->bi_bufnum);
  247. return -ENOMEM;
  248. }
  249. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  250. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  251. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  252. if (info->interval)
  253. info->interval--;
  254. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  255. return 0;
  256. }
  257. static void pipe_buffer_release(struct m66592 *m66592,
  258. struct m66592_pipe_info *info)
  259. {
  260. if (info->pipe == 0)
  261. return;
  262. switch (info->type) {
  263. case M66592_BULK:
  264. if (is_bulk_pipe(info->pipe))
  265. m66592->bi_bufnum -= 16;
  266. break;
  267. case M66592_ISO:
  268. if (is_isoc_pipe(info->pipe))
  269. m66592->bi_bufnum -= 16;
  270. break;
  271. }
  272. if (is_bulk_pipe(info->pipe)) {
  273. m66592->bulk--;
  274. } else if (is_interrupt_pipe(info->pipe))
  275. m66592->interrupt--;
  276. else if (is_isoc_pipe(info->pipe)) {
  277. m66592->isochronous--;
  278. if (info->type == M66592_BULK)
  279. m66592->bulk--;
  280. } else
  281. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  282. info->pipe);
  283. }
  284. static void pipe_initialize(struct m66592_ep *ep)
  285. {
  286. struct m66592 *m66592 = ep->m66592;
  287. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  288. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  289. m66592_write(m66592, 0, ep->pipectr);
  290. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  291. if (ep->use_dma) {
  292. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  293. ndelay(450);
  294. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  295. }
  296. }
  297. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  298. const struct usb_endpoint_descriptor *desc,
  299. u16 pipenum, int dma)
  300. {
  301. if ((pipenum != 0) && dma) {
  302. if (m66592->num_dma == 0) {
  303. m66592->num_dma++;
  304. ep->use_dma = 1;
  305. ep->fifoaddr = M66592_D0FIFO;
  306. ep->fifosel = M66592_D0FIFOSEL;
  307. ep->fifoctr = M66592_D0FIFOCTR;
  308. ep->fifotrn = M66592_D0FIFOTRN;
  309. } else if (m66592->num_dma == 1) {
  310. m66592->num_dma++;
  311. ep->use_dma = 1;
  312. ep->fifoaddr = M66592_D1FIFO;
  313. ep->fifosel = M66592_D1FIFOSEL;
  314. ep->fifoctr = M66592_D1FIFOCTR;
  315. ep->fifotrn = M66592_D1FIFOTRN;
  316. } else {
  317. ep->use_dma = 0;
  318. ep->fifoaddr = M66592_CFIFO;
  319. ep->fifosel = M66592_CFIFOSEL;
  320. ep->fifoctr = M66592_CFIFOCTR;
  321. ep->fifotrn = 0;
  322. }
  323. } else {
  324. ep->use_dma = 0;
  325. ep->fifoaddr = M66592_CFIFO;
  326. ep->fifosel = M66592_CFIFOSEL;
  327. ep->fifoctr = M66592_CFIFOCTR;
  328. ep->fifotrn = 0;
  329. }
  330. ep->pipectr = get_pipectr_addr(pipenum);
  331. ep->pipenum = pipenum;
  332. ep->ep.maxpacket = desc->wMaxPacketSize;
  333. m66592->pipenum2ep[pipenum] = ep;
  334. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  335. INIT_LIST_HEAD(&ep->queue);
  336. }
  337. static void m66592_ep_release(struct m66592_ep *ep)
  338. {
  339. struct m66592 *m66592 = ep->m66592;
  340. u16 pipenum = ep->pipenum;
  341. if (pipenum == 0)
  342. return;
  343. if (ep->use_dma)
  344. m66592->num_dma--;
  345. ep->pipenum = 0;
  346. ep->busy = 0;
  347. ep->use_dma = 0;
  348. }
  349. static int alloc_pipe_config(struct m66592_ep *ep,
  350. const struct usb_endpoint_descriptor *desc)
  351. {
  352. struct m66592 *m66592 = ep->m66592;
  353. struct m66592_pipe_info info;
  354. int dma = 0;
  355. int *counter;
  356. int ret;
  357. ep->desc = desc;
  358. BUG_ON(ep->pipenum);
  359. switch(desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  360. case USB_ENDPOINT_XFER_BULK:
  361. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  362. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  363. printk(KERN_ERR "bulk pipe is insufficient\n");
  364. return -ENODEV;
  365. } else {
  366. info.pipe = M66592_BASE_PIPENUM_ISOC +
  367. m66592->isochronous;
  368. counter = &m66592->isochronous;
  369. }
  370. } else {
  371. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  372. counter = &m66592->bulk;
  373. }
  374. info.type = M66592_BULK;
  375. dma = 1;
  376. break;
  377. case USB_ENDPOINT_XFER_INT:
  378. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  379. printk(KERN_ERR "interrupt pipe is insufficient\n");
  380. return -ENODEV;
  381. }
  382. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  383. info.type = M66592_INT;
  384. counter = &m66592->interrupt;
  385. break;
  386. case USB_ENDPOINT_XFER_ISOC:
  387. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  388. printk(KERN_ERR "isochronous pipe is insufficient\n");
  389. return -ENODEV;
  390. }
  391. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  392. info.type = M66592_ISO;
  393. counter = &m66592->isochronous;
  394. break;
  395. default:
  396. printk(KERN_ERR "unexpect xfer type\n");
  397. return -EINVAL;
  398. }
  399. ep->type = info.type;
  400. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  401. info.maxpacket = desc->wMaxPacketSize;
  402. info.interval = desc->bInterval;
  403. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  404. info.dir_in = 1;
  405. else
  406. info.dir_in = 0;
  407. ret = pipe_buffer_setting(m66592, &info);
  408. if (ret < 0) {
  409. printk(KERN_ERR "pipe_buffer_setting fail\n");
  410. return ret;
  411. }
  412. (*counter)++;
  413. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  414. m66592->bulk++;
  415. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  416. pipe_initialize(ep);
  417. return 0;
  418. }
  419. static int free_pipe_config(struct m66592_ep *ep)
  420. {
  421. struct m66592 *m66592 = ep->m66592;
  422. struct m66592_pipe_info info;
  423. info.pipe = ep->pipenum;
  424. info.type = ep->type;
  425. pipe_buffer_release(m66592, &info);
  426. m66592_ep_release(ep);
  427. return 0;
  428. }
  429. /*-------------------------------------------------------------------------*/
  430. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  431. {
  432. enable_irq_ready(m66592, pipenum);
  433. enable_irq_nrdy(m66592, pipenum);
  434. }
  435. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  436. {
  437. disable_irq_ready(m66592, pipenum);
  438. disable_irq_nrdy(m66592, pipenum);
  439. }
  440. /* if complete is true, gadget driver complete function is not call */
  441. static void control_end(struct m66592 *m66592, unsigned ccpl)
  442. {
  443. m66592->ep[0].internal_ccpl = ccpl;
  444. pipe_start(m66592, 0);
  445. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  446. }
  447. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  448. {
  449. struct m66592 *m66592 = ep->m66592;
  450. pipe_change(m66592, ep->pipenum);
  451. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  452. (M66592_ISEL | M66592_CURPIPE),
  453. M66592_CFIFOSEL);
  454. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  455. if (req->req.length == 0) {
  456. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  457. pipe_start(m66592, 0);
  458. transfer_complete(ep, req, 0);
  459. } else {
  460. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  461. irq_ep0_write(ep, req);
  462. }
  463. }
  464. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  465. {
  466. struct m66592 *m66592 = ep->m66592;
  467. u16 tmp;
  468. pipe_change(m66592, ep->pipenum);
  469. disable_irq_empty(m66592, ep->pipenum);
  470. pipe_start(m66592, ep->pipenum);
  471. tmp = m66592_read(m66592, ep->fifoctr);
  472. if (unlikely((tmp & M66592_FRDY) == 0))
  473. pipe_irq_enable(m66592, ep->pipenum);
  474. else
  475. irq_packet_write(ep, req);
  476. }
  477. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  478. {
  479. struct m66592 *m66592 = ep->m66592;
  480. u16 pipenum = ep->pipenum;
  481. if (ep->pipenum == 0) {
  482. m66592_mdfy(m66592, M66592_PIPE0,
  483. (M66592_ISEL | M66592_CURPIPE),
  484. M66592_CFIFOSEL);
  485. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  486. pipe_start(m66592, pipenum);
  487. pipe_irq_enable(m66592, pipenum);
  488. } else {
  489. if (ep->use_dma) {
  490. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  491. pipe_change(m66592, pipenum);
  492. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  493. m66592_write(m66592,
  494. (req->req.length + ep->ep.maxpacket - 1) /
  495. ep->ep.maxpacket, ep->fifotrn);
  496. }
  497. pipe_start(m66592, pipenum); /* trigger once */
  498. pipe_irq_enable(m66592, pipenum);
  499. }
  500. }
  501. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  502. {
  503. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  504. start_packet_write(ep, req);
  505. else
  506. start_packet_read(ep, req);
  507. }
  508. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  509. {
  510. u16 ctsq;
  511. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  512. switch (ctsq) {
  513. case M66592_CS_RDDS:
  514. start_ep0_write(ep, req);
  515. break;
  516. case M66592_CS_WRDS:
  517. start_packet_read(ep, req);
  518. break;
  519. case M66592_CS_WRND:
  520. control_end(ep->m66592, 0);
  521. break;
  522. default:
  523. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  524. break;
  525. }
  526. }
  527. static void init_controller(struct m66592 *m66592)
  528. {
  529. m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  530. M66592_PINCFG);
  531. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  532. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
  533. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  534. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  535. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  536. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  537. msleep(3);
  538. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  539. msleep(1);
  540. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  541. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  542. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  543. M66592_DMA0CFG);
  544. }
  545. static void disable_controller(struct m66592 *m66592)
  546. {
  547. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  548. udelay(1);
  549. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  550. udelay(1);
  551. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  552. udelay(1);
  553. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  554. }
  555. static void m66592_start_xclock(struct m66592 *m66592)
  556. {
  557. u16 tmp;
  558. tmp = m66592_read(m66592, M66592_SYSCFG);
  559. if (!(tmp & M66592_XCKE))
  560. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  561. }
  562. /*-------------------------------------------------------------------------*/
  563. static void transfer_complete(struct m66592_ep *ep,
  564. struct m66592_request *req,
  565. int status)
  566. {
  567. int restart = 0;
  568. if (unlikely(ep->pipenum == 0)) {
  569. if (ep->internal_ccpl) {
  570. ep->internal_ccpl = 0;
  571. return;
  572. }
  573. }
  574. list_del_init(&req->queue);
  575. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  576. req->req.status = -ESHUTDOWN;
  577. else
  578. req->req.status = status;
  579. if (!list_empty(&ep->queue))
  580. restart = 1;
  581. if (likely(req->req.complete))
  582. req->req.complete(&ep->ep, &req->req);
  583. if (restart) {
  584. req = list_entry(ep->queue.next, struct m66592_request, queue);
  585. if (ep->desc)
  586. start_packet(ep, req);
  587. }
  588. }
  589. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  590. {
  591. int i;
  592. volatile u16 tmp;
  593. unsigned bufsize;
  594. size_t size;
  595. void *buf;
  596. u16 pipenum = ep->pipenum;
  597. struct m66592 *m66592 = ep->m66592;
  598. pipe_change(m66592, pipenum);
  599. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  600. i = 0;
  601. do {
  602. tmp = m66592_read(m66592, ep->fifoctr);
  603. if (i++ > 100000) {
  604. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  605. "conflict. please power off this controller.");
  606. return;
  607. }
  608. ndelay(1);
  609. } while ((tmp & M66592_FRDY) == 0);
  610. /* prepare parameters */
  611. bufsize = get_buffer_size(m66592, pipenum);
  612. buf = req->req.buf + req->req.actual;
  613. size = min(bufsize, req->req.length - req->req.actual);
  614. /* write fifo */
  615. if (req->req.buf) {
  616. if (size > 0)
  617. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  618. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  619. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  620. }
  621. /* update parameters */
  622. req->req.actual += size;
  623. /* check transfer finish */
  624. if ((!req->req.zero && (req->req.actual == req->req.length)) ||
  625. (size % ep->ep.maxpacket) || (size == 0)) {
  626. disable_irq_ready(m66592, pipenum);
  627. disable_irq_empty(m66592, pipenum);
  628. } else {
  629. disable_irq_ready(m66592, pipenum);
  630. enable_irq_empty(m66592, pipenum);
  631. }
  632. pipe_start(m66592, pipenum);
  633. }
  634. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  635. {
  636. u16 tmp;
  637. unsigned bufsize;
  638. size_t size;
  639. void *buf;
  640. u16 pipenum = ep->pipenum;
  641. struct m66592 *m66592 = ep->m66592;
  642. pipe_change(m66592, pipenum);
  643. tmp = m66592_read(m66592, ep->fifoctr);
  644. if (unlikely((tmp & M66592_FRDY) == 0)) {
  645. pipe_stop(m66592, pipenum);
  646. pipe_irq_disable(m66592, pipenum);
  647. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  648. return;
  649. }
  650. /* prepare parameters */
  651. bufsize = get_buffer_size(m66592, pipenum);
  652. buf = req->req.buf + req->req.actual;
  653. size = min(bufsize, req->req.length - req->req.actual);
  654. /* write fifo */
  655. if (req->req.buf) {
  656. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  657. if ((size == 0) || ((size % ep->ep.maxpacket) != 0) ||
  658. ((bufsize != ep->ep.maxpacket) && (bufsize > size)))
  659. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  660. }
  661. /* update parameters */
  662. req->req.actual += size;
  663. /* check transfer finish */
  664. if ((!req->req.zero && (req->req.actual == req->req.length)) ||
  665. (size % ep->ep.maxpacket) || (size == 0)) {
  666. disable_irq_ready(m66592, pipenum);
  667. enable_irq_empty(m66592, pipenum);
  668. } else {
  669. disable_irq_empty(m66592, pipenum);
  670. pipe_irq_enable(m66592, pipenum);
  671. }
  672. }
  673. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  674. {
  675. u16 tmp;
  676. int rcv_len, bufsize, req_len;
  677. int size;
  678. void *buf;
  679. u16 pipenum = ep->pipenum;
  680. struct m66592 *m66592 = ep->m66592;
  681. int finish = 0;
  682. pipe_change(m66592, pipenum);
  683. tmp = m66592_read(m66592, ep->fifoctr);
  684. if (unlikely((tmp & M66592_FRDY) == 0)) {
  685. req->req.status = -EPIPE;
  686. pipe_stop(m66592, pipenum);
  687. pipe_irq_disable(m66592, pipenum);
  688. printk(KERN_ERR "read fifo not ready");
  689. return;
  690. }
  691. /* prepare parameters */
  692. rcv_len = tmp & M66592_DTLN;
  693. bufsize = get_buffer_size(m66592, pipenum);
  694. buf = req->req.buf + req->req.actual;
  695. req_len = req->req.length - req->req.actual;
  696. if (rcv_len < bufsize)
  697. size = min(rcv_len, req_len);
  698. else
  699. size = min(bufsize, req_len);
  700. /* update parameters */
  701. req->req.actual += size;
  702. /* check transfer finish */
  703. if ((!req->req.zero && (req->req.actual == req->req.length)) ||
  704. (size % ep->ep.maxpacket) || (size == 0)) {
  705. pipe_stop(m66592, pipenum);
  706. pipe_irq_disable(m66592, pipenum);
  707. finish = 1;
  708. }
  709. /* read fifo */
  710. if (req->req.buf) {
  711. if (size == 0)
  712. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  713. else
  714. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  715. }
  716. if ((ep->pipenum != 0) && finish)
  717. transfer_complete(ep, req, 0);
  718. }
  719. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  720. {
  721. u16 check;
  722. u16 pipenum;
  723. struct m66592_ep *ep;
  724. struct m66592_request *req;
  725. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  726. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  727. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  728. M66592_CFIFOSEL);
  729. ep = &m66592->ep[0];
  730. req = list_entry(ep->queue.next, struct m66592_request, queue);
  731. irq_packet_read(ep, req);
  732. } else {
  733. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  734. check = 1 << pipenum;
  735. if ((status & check) && (enb & check)) {
  736. m66592_write(m66592, ~check, M66592_BRDYSTS);
  737. ep = m66592->pipenum2ep[pipenum];
  738. req = list_entry(ep->queue.next,
  739. struct m66592_request, queue);
  740. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  741. irq_packet_write(ep, req);
  742. else
  743. irq_packet_read(ep, req);
  744. }
  745. }
  746. }
  747. }
  748. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  749. {
  750. u16 tmp;
  751. u16 check;
  752. u16 pipenum;
  753. struct m66592_ep *ep;
  754. struct m66592_request *req;
  755. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  756. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  757. ep = &m66592->ep[0];
  758. req = list_entry(ep->queue.next, struct m66592_request, queue);
  759. irq_ep0_write(ep, req);
  760. } else {
  761. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  762. check = 1 << pipenum;
  763. if ((status & check) && (enb & check)) {
  764. m66592_write(m66592, ~check, M66592_BEMPSTS);
  765. tmp = control_reg_get(m66592, pipenum);
  766. if ((tmp & M66592_INBUFM) == 0) {
  767. disable_irq_empty(m66592, pipenum);
  768. pipe_irq_disable(m66592, pipenum);
  769. pipe_stop(m66592, pipenum);
  770. ep = m66592->pipenum2ep[pipenum];
  771. req = list_entry(ep->queue.next,
  772. struct m66592_request,
  773. queue);
  774. if (!list_empty(&ep->queue))
  775. transfer_complete(ep, req, 0);
  776. }
  777. }
  778. }
  779. }
  780. }
  781. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  782. {
  783. struct m66592_ep *ep;
  784. u16 pid;
  785. u16 status = 0;
  786. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  787. case USB_RECIP_DEVICE:
  788. status = 1; /* selfpower */
  789. break;
  790. case USB_RECIP_INTERFACE:
  791. status = 0;
  792. break;
  793. case USB_RECIP_ENDPOINT:
  794. ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK];
  795. pid = control_reg_get_pid(m66592, ep->pipenum);
  796. if (pid == M66592_PID_STALL)
  797. status = 1;
  798. else
  799. status = 0;
  800. break;
  801. default:
  802. pipe_stall(m66592, 0);
  803. return; /* exit */
  804. }
  805. *m66592->ep0_buf = status;
  806. m66592->ep0_req->buf = m66592->ep0_buf;
  807. m66592->ep0_req->length = 2;
  808. /* AV: what happens if we get called again before that gets through? */
  809. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  810. }
  811. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  812. {
  813. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  814. case USB_RECIP_DEVICE:
  815. control_end(m66592, 1);
  816. break;
  817. case USB_RECIP_INTERFACE:
  818. control_end(m66592, 1);
  819. break;
  820. case USB_RECIP_ENDPOINT: {
  821. struct m66592_ep *ep;
  822. struct m66592_request *req;
  823. ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK];
  824. pipe_stop(m66592, ep->pipenum);
  825. control_reg_sqclr(m66592, ep->pipenum);
  826. control_end(m66592, 1);
  827. req = list_entry(ep->queue.next,
  828. struct m66592_request, queue);
  829. if (ep->busy) {
  830. ep->busy = 0;
  831. if (list_empty(&ep->queue))
  832. break;
  833. start_packet(ep, req);
  834. } else if (!list_empty(&ep->queue))
  835. pipe_start(m66592, ep->pipenum);
  836. }
  837. break;
  838. default:
  839. pipe_stall(m66592, 0);
  840. break;
  841. }
  842. }
  843. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  844. {
  845. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  846. case USB_RECIP_DEVICE:
  847. control_end(m66592, 1);
  848. break;
  849. case USB_RECIP_INTERFACE:
  850. control_end(m66592, 1);
  851. break;
  852. case USB_RECIP_ENDPOINT: {
  853. struct m66592_ep *ep;
  854. ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK];
  855. pipe_stall(m66592, ep->pipenum);
  856. control_end(m66592, 1);
  857. }
  858. break;
  859. default:
  860. pipe_stall(m66592, 0);
  861. break;
  862. }
  863. }
  864. /* if return value is true, call class driver's setup() */
  865. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  866. {
  867. u16 *p = (u16 *)ctrl;
  868. unsigned long offset = M66592_USBREQ;
  869. int i, ret = 0;
  870. /* read fifo */
  871. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  872. for (i = 0; i < 4; i++)
  873. p[i] = m66592_read(m66592, offset + i*2);
  874. /* check request */
  875. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  876. switch (ctrl->bRequest) {
  877. case USB_REQ_GET_STATUS:
  878. get_status(m66592, ctrl);
  879. break;
  880. case USB_REQ_CLEAR_FEATURE:
  881. clear_feature(m66592, ctrl);
  882. break;
  883. case USB_REQ_SET_FEATURE:
  884. set_feature(m66592, ctrl);
  885. break;
  886. default:
  887. ret = 1;
  888. break;
  889. }
  890. } else
  891. ret = 1;
  892. return ret;
  893. }
  894. static void m66592_update_usb_speed(struct m66592 *m66592)
  895. {
  896. u16 speed = get_usb_speed(m66592);
  897. switch (speed) {
  898. case M66592_HSMODE:
  899. m66592->gadget.speed = USB_SPEED_HIGH;
  900. break;
  901. case M66592_FSMODE:
  902. m66592->gadget.speed = USB_SPEED_FULL;
  903. break;
  904. default:
  905. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  906. printk(KERN_ERR "USB speed unknown\n");
  907. }
  908. }
  909. static void irq_device_state(struct m66592 *m66592)
  910. {
  911. u16 dvsq;
  912. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  913. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  914. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  915. m66592->driver->disconnect(&m66592->gadget);
  916. m66592_update_usb_speed(m66592);
  917. }
  918. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  919. m66592_update_usb_speed(m66592);
  920. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS) &&
  921. m66592->gadget.speed == USB_SPEED_UNKNOWN)
  922. m66592_update_usb_speed(m66592);
  923. m66592->old_dvsq = dvsq;
  924. }
  925. static void irq_control_stage(struct m66592 *m66592)
  926. {
  927. struct usb_ctrlrequest ctrl;
  928. u16 ctsq;
  929. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  930. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  931. switch (ctsq) {
  932. case M66592_CS_IDST: {
  933. struct m66592_ep *ep;
  934. struct m66592_request *req;
  935. ep = &m66592->ep[0];
  936. req = list_entry(ep->queue.next, struct m66592_request, queue);
  937. transfer_complete(ep, req, 0);
  938. }
  939. break;
  940. case M66592_CS_RDDS:
  941. case M66592_CS_WRDS:
  942. case M66592_CS_WRND:
  943. if (setup_packet(m66592, &ctrl)) {
  944. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  945. pipe_stall(m66592, 0);
  946. }
  947. break;
  948. case M66592_CS_RDSS:
  949. case M66592_CS_WRSS:
  950. control_end(m66592, 0);
  951. break;
  952. default:
  953. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  954. break;
  955. }
  956. }
  957. static irqreturn_t m66592_irq(int irq, void *_m66592)
  958. {
  959. struct m66592 *m66592 = _m66592;
  960. u16 intsts0;
  961. u16 intenb0;
  962. u16 brdysts, nrdysts, bempsts;
  963. u16 brdyenb, nrdyenb, bempenb;
  964. u16 savepipe;
  965. u16 mask0;
  966. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  967. intenb0 = m66592_read(m66592, M66592_INTENB0);
  968. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  969. mask0 = intsts0 & intenb0;
  970. if (mask0) {
  971. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  972. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  973. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  974. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  975. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  976. bempenb = m66592_read(m66592, M66592_BEMPENB);
  977. if (mask0 & M66592_VBINT) {
  978. m66592_write(m66592, (u16)~M66592_VBINT,
  979. M66592_INTSTS0);
  980. m66592_start_xclock(m66592);
  981. /* start vbus sampling */
  982. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  983. & M66592_VBSTS;
  984. m66592->scount = M66592_MAX_SAMPLING;
  985. mod_timer(&m66592->timer,
  986. jiffies + msecs_to_jiffies(50));
  987. }
  988. if (intsts0 & M66592_DVSQ)
  989. irq_device_state(m66592);
  990. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE) &&
  991. (brdysts & brdyenb)) {
  992. irq_pipe_ready(m66592, brdysts, brdyenb);
  993. }
  994. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE) &&
  995. (bempsts & bempenb)) {
  996. irq_pipe_empty(m66592, bempsts, bempenb);
  997. }
  998. if (intsts0 & M66592_CTRT)
  999. irq_control_stage(m66592);
  1000. }
  1001. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1002. return IRQ_HANDLED;
  1003. }
  1004. static void m66592_timer(unsigned long _m66592)
  1005. {
  1006. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1007. unsigned long flags;
  1008. u16 tmp;
  1009. spin_lock_irqsave(&m66592->lock, flags);
  1010. tmp = m66592_read(m66592, M66592_SYSCFG);
  1011. if (!(tmp & M66592_RCKE)) {
  1012. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1013. udelay(10);
  1014. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1015. }
  1016. if (m66592->scount > 0) {
  1017. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1018. if (tmp == m66592->old_vbus) {
  1019. m66592->scount--;
  1020. if (m66592->scount == 0) {
  1021. if (tmp == M66592_VBSTS)
  1022. m66592_usb_connect(m66592);
  1023. else
  1024. m66592_usb_disconnect(m66592);
  1025. } else {
  1026. mod_timer(&m66592->timer,
  1027. jiffies + msecs_to_jiffies(50));
  1028. }
  1029. } else {
  1030. m66592->scount = M66592_MAX_SAMPLING;
  1031. m66592->old_vbus = tmp;
  1032. mod_timer(&m66592->timer,
  1033. jiffies + msecs_to_jiffies(50));
  1034. }
  1035. }
  1036. spin_unlock_irqrestore(&m66592->lock, flags);
  1037. }
  1038. /*-------------------------------------------------------------------------*/
  1039. static int m66592_enable(struct usb_ep *_ep,
  1040. const struct usb_endpoint_descriptor *desc)
  1041. {
  1042. struct m66592_ep *ep;
  1043. ep = container_of(_ep, struct m66592_ep, ep);
  1044. return alloc_pipe_config(ep, desc);
  1045. }
  1046. static int m66592_disable(struct usb_ep *_ep)
  1047. {
  1048. struct m66592_ep *ep;
  1049. struct m66592_request *req;
  1050. unsigned long flags;
  1051. ep = container_of(_ep, struct m66592_ep, ep);
  1052. BUG_ON(!ep);
  1053. while (!list_empty(&ep->queue)) {
  1054. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1055. spin_lock_irqsave(&ep->m66592->lock, flags);
  1056. transfer_complete(ep, req, -ECONNRESET);
  1057. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1058. }
  1059. pipe_irq_disable(ep->m66592, ep->pipenum);
  1060. return free_pipe_config(ep);
  1061. }
  1062. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1063. gfp_t gfp_flags)
  1064. {
  1065. struct m66592_request *req;
  1066. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1067. if (!req)
  1068. return NULL;
  1069. INIT_LIST_HEAD(&req->queue);
  1070. return &req->req;
  1071. }
  1072. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1073. {
  1074. struct m66592_request *req;
  1075. req = container_of(_req, struct m66592_request, req);
  1076. kfree(req);
  1077. }
  1078. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1079. gfp_t gfp_flags)
  1080. {
  1081. struct m66592_ep *ep;
  1082. struct m66592_request *req;
  1083. unsigned long flags;
  1084. int request = 0;
  1085. ep = container_of(_ep, struct m66592_ep, ep);
  1086. req = container_of(_req, struct m66592_request, req);
  1087. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1088. return -ESHUTDOWN;
  1089. spin_lock_irqsave(&ep->m66592->lock, flags);
  1090. if (list_empty(&ep->queue))
  1091. request = 1;
  1092. list_add_tail(&req->queue, &ep->queue);
  1093. req->req.actual = 0;
  1094. req->req.status = -EINPROGRESS;
  1095. if (ep->desc == 0) /* control */
  1096. start_ep0(ep, req);
  1097. else {
  1098. if (request && !ep->busy)
  1099. start_packet(ep, req);
  1100. }
  1101. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1102. return 0;
  1103. }
  1104. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1105. {
  1106. struct m66592_ep *ep;
  1107. struct m66592_request *req;
  1108. unsigned long flags;
  1109. ep = container_of(_ep, struct m66592_ep, ep);
  1110. req = container_of(_req, struct m66592_request, req);
  1111. spin_lock_irqsave(&ep->m66592->lock, flags);
  1112. if (!list_empty(&ep->queue))
  1113. transfer_complete(ep, req, -ECONNRESET);
  1114. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1115. return 0;
  1116. }
  1117. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1118. {
  1119. struct m66592_ep *ep;
  1120. struct m66592_request *req;
  1121. unsigned long flags;
  1122. int ret = 0;
  1123. ep = container_of(_ep, struct m66592_ep, ep);
  1124. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1125. spin_lock_irqsave(&ep->m66592->lock, flags);
  1126. if (!list_empty(&ep->queue)) {
  1127. ret = -EAGAIN;
  1128. goto out;
  1129. }
  1130. if (value) {
  1131. ep->busy = 1;
  1132. pipe_stall(ep->m66592, ep->pipenum);
  1133. } else {
  1134. ep->busy = 0;
  1135. pipe_stop(ep->m66592, ep->pipenum);
  1136. }
  1137. out:
  1138. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1139. return ret;
  1140. }
  1141. static int m66592_fifo_status(struct usb_ep *_ep)
  1142. {
  1143. return -EOPNOTSUPP;
  1144. }
  1145. static void m66592_fifo_flush(struct usb_ep *_ep)
  1146. {
  1147. struct m66592_ep *ep;
  1148. unsigned long flags;
  1149. ep = container_of(_ep, struct m66592_ep, ep);
  1150. spin_lock_irqsave(&ep->m66592->lock, flags);
  1151. if (list_empty(&ep->queue) && !ep->busy) {
  1152. pipe_stop(ep->m66592, ep->pipenum);
  1153. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1154. }
  1155. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1156. }
  1157. static struct usb_ep_ops m66592_ep_ops = {
  1158. .enable = m66592_enable,
  1159. .disable = m66592_disable,
  1160. .alloc_request = m66592_alloc_request,
  1161. .free_request = m66592_free_request,
  1162. .queue = m66592_queue,
  1163. .dequeue = m66592_dequeue,
  1164. .set_halt = m66592_set_halt,
  1165. .fifo_status = m66592_fifo_status,
  1166. .fifo_flush = m66592_fifo_flush,
  1167. };
  1168. /*-------------------------------------------------------------------------*/
  1169. static struct m66592 *the_controller;
  1170. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1171. {
  1172. struct m66592 *m66592 = the_controller;
  1173. int retval;
  1174. if (!driver ||
  1175. driver->speed != USB_SPEED_HIGH ||
  1176. !driver->bind ||
  1177. !driver->unbind ||
  1178. !driver->setup)
  1179. return -EINVAL;
  1180. if (!m66592)
  1181. return -ENODEV;
  1182. if (m66592->driver)
  1183. return -EBUSY;
  1184. /* hook up the driver */
  1185. driver->driver.bus = NULL;
  1186. m66592->driver = driver;
  1187. m66592->gadget.dev.driver = &driver->driver;
  1188. retval = device_add(&m66592->gadget.dev);
  1189. if (retval) {
  1190. printk(KERN_ERR "device_add error (%d)\n", retval);
  1191. goto error;
  1192. }
  1193. retval = driver->bind (&m66592->gadget);
  1194. if (retval) {
  1195. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1196. device_del(&m66592->gadget.dev);
  1197. goto error;
  1198. }
  1199. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1200. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1201. m66592_start_xclock(m66592);
  1202. /* start vbus sampling */
  1203. m66592->old_vbus = m66592_read(m66592,
  1204. M66592_INTSTS0) & M66592_VBSTS;
  1205. m66592->scount = M66592_MAX_SAMPLING;
  1206. mod_timer(&m66592->timer,
  1207. jiffies + msecs_to_jiffies(50));
  1208. }
  1209. return 0;
  1210. error:
  1211. m66592->driver = NULL;
  1212. m66592->gadget.dev.driver = NULL;
  1213. return retval;
  1214. }
  1215. EXPORT_SYMBOL(usb_gadget_register_driver);
  1216. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1217. {
  1218. struct m66592 *m66592 = the_controller;
  1219. unsigned long flags;
  1220. spin_lock_irqsave(&m66592->lock, flags);
  1221. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1222. m66592_usb_disconnect(m66592);
  1223. spin_unlock_irqrestore(&m66592->lock, flags);
  1224. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1225. driver->unbind(&m66592->gadget);
  1226. init_controller(m66592);
  1227. disable_controller(m66592);
  1228. device_del(&m66592->gadget.dev);
  1229. m66592->driver = NULL;
  1230. return 0;
  1231. }
  1232. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1233. /*-------------------------------------------------------------------------*/
  1234. static int m66592_get_frame(struct usb_gadget *_gadget)
  1235. {
  1236. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1237. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1238. }
  1239. static struct usb_gadget_ops m66592_gadget_ops = {
  1240. .get_frame = m66592_get_frame,
  1241. };
  1242. #if defined(CONFIG_PM)
  1243. static int m66592_suspend(struct platform_device *pdev, pm_message_t state)
  1244. {
  1245. pdev->dev.power.power_state = state;
  1246. return 0;
  1247. }
  1248. static int m66592_resume(struct platform_device *pdev)
  1249. {
  1250. pdev->dev.power.power_state = PMSG_ON;
  1251. return 0;
  1252. }
  1253. #else /* if defined(CONFIG_PM) */
  1254. #define m66592_suspend NULL
  1255. #define m66592_resume NULL
  1256. #endif
  1257. static int __init_or_module m66592_remove(struct platform_device *pdev)
  1258. {
  1259. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1260. del_timer_sync(&m66592->timer);
  1261. iounmap(m66592->reg);
  1262. free_irq(platform_get_irq(pdev, 0), m66592);
  1263. kfree(m66592);
  1264. return 0;
  1265. }
  1266. #define resource_len(r) (((r)->end - (r)->start) + 1)
  1267. static int __init m66592_probe(struct platform_device *pdev)
  1268. {
  1269. struct resource *res = NULL;
  1270. int irq = -1;
  1271. void __iomem *reg = NULL;
  1272. struct m66592 *m66592 = NULL;
  1273. int ret = 0;
  1274. int i;
  1275. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1276. (char *)udc_name);
  1277. if (!res) {
  1278. ret = -ENODEV;
  1279. printk(KERN_ERR "platform_get_resource_byname error.\n");
  1280. goto clean_up;
  1281. }
  1282. irq = platform_get_irq(pdev, 0);
  1283. if (irq < 0) {
  1284. ret = -ENODEV;
  1285. printk(KERN_ERR "platform_get_irq error.\n");
  1286. goto clean_up;
  1287. }
  1288. reg = ioremap(res->start, resource_len(res));
  1289. if (reg == NULL) {
  1290. ret = -ENOMEM;
  1291. printk(KERN_ERR "ioremap error.\n");
  1292. goto clean_up;
  1293. }
  1294. /* initialize ucd */
  1295. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1296. if (m66592 == NULL) {
  1297. printk(KERN_ERR "kzalloc error\n");
  1298. goto clean_up;
  1299. }
  1300. spin_lock_init(&m66592->lock);
  1301. dev_set_drvdata(&pdev->dev, m66592);
  1302. m66592->gadget.ops = &m66592_gadget_ops;
  1303. device_initialize(&m66592->gadget.dev);
  1304. strcpy(m66592->gadget.dev.bus_id, "gadget");
  1305. m66592->gadget.is_dualspeed = 1;
  1306. m66592->gadget.dev.parent = &pdev->dev;
  1307. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1308. m66592->gadget.dev.release = pdev->dev.release;
  1309. m66592->gadget.name = udc_name;
  1310. init_timer(&m66592->timer);
  1311. m66592->timer.function = m66592_timer;
  1312. m66592->timer.data = (unsigned long)m66592;
  1313. m66592->reg = reg;
  1314. m66592->bi_bufnum = M66592_BASE_BUFNUM;
  1315. ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1316. udc_name, m66592);
  1317. if (ret < 0) {
  1318. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1319. goto clean_up;
  1320. }
  1321. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1322. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1323. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1324. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1325. struct m66592_ep *ep = &m66592->ep[i];
  1326. if (i != 0) {
  1327. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1328. list_add_tail(&m66592->ep[i].ep.ep_list,
  1329. &m66592->gadget.ep_list);
  1330. }
  1331. ep->m66592 = m66592;
  1332. INIT_LIST_HEAD(&ep->queue);
  1333. ep->ep.name = m66592_ep_name[i];
  1334. ep->ep.ops = &m66592_ep_ops;
  1335. ep->ep.maxpacket = 512;
  1336. }
  1337. m66592->ep[0].ep.maxpacket = 64;
  1338. m66592->ep[0].pipenum = 0;
  1339. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1340. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1341. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1342. m66592->ep[0].fifotrn = 0;
  1343. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1344. m66592->pipenum2ep[0] = &m66592->ep[0];
  1345. m66592->epaddr2ep[0] = &m66592->ep[0];
  1346. the_controller = m66592;
  1347. /* AV: leaks */
  1348. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1349. if (m66592->ep0_req == NULL)
  1350. goto clean_up;
  1351. /* AV: leaks, and do we really need it separately allocated? */
  1352. m66592->ep0_buf = kzalloc(2, GFP_KERNEL);
  1353. if (m66592->ep0_buf == NULL)
  1354. goto clean_up;
  1355. init_controller(m66592);
  1356. printk("driver %s, %s\n", udc_name, DRIVER_VERSION);
  1357. return 0;
  1358. clean_up:
  1359. if (m66592) {
  1360. if (m66592->ep0_req)
  1361. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1362. kfree(m66592);
  1363. }
  1364. if (reg)
  1365. iounmap(reg);
  1366. return ret;
  1367. }
  1368. /*-------------------------------------------------------------------------*/
  1369. static struct platform_driver m66592_driver = {
  1370. .probe = m66592_probe,
  1371. .remove = m66592_remove,
  1372. .suspend = m66592_suspend,
  1373. .resume = m66592_resume,
  1374. .driver = {
  1375. .name = (char *) udc_name,
  1376. },
  1377. };
  1378. static int __init m66592_udc_init(void)
  1379. {
  1380. return platform_driver_register(&m66592_driver);
  1381. }
  1382. module_init(m66592_udc_init);
  1383. static void __exit m66592_udc_cleanup(void)
  1384. {
  1385. platform_driver_unregister(&m66592_driver);
  1386. }
  1387. module_exit(m66592_udc_cleanup);