cpm_uart_cpm1.c 8.2 KB

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  1. /*
  2. * linux/drivers/serial/cpm_uart.c
  3. *
  4. * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
  5. *
  6. * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
  7. * Pantelis Antoniou (panto@intracom.gr) (CPM1)
  8. *
  9. * Copyright (C) 2004 Freescale Semiconductor, Inc.
  10. * (C) 2004 Intracom, S.A.
  11. * (C) 2006 MontaVista Software, Inc.
  12. * Vitaly Bordug <vbordug@ru.mvista.com>
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  27. *
  28. */
  29. #include <linux/module.h>
  30. #include <linux/tty.h>
  31. #include <linux/ioport.h>
  32. #include <linux/init.h>
  33. #include <linux/serial.h>
  34. #include <linux/console.h>
  35. #include <linux/sysrq.h>
  36. #include <linux/device.h>
  37. #include <linux/bootmem.h>
  38. #include <linux/dma-mapping.h>
  39. #include <asm/io.h>
  40. #include <asm/irq.h>
  41. #include <asm/fs_pd.h>
  42. #include <linux/serial_core.h>
  43. #include <linux/kernel.h>
  44. #include "cpm_uart.h"
  45. /**************************************************************/
  46. void cpm_line_cr_cmd(int line, int cmd)
  47. {
  48. ushort val;
  49. volatile cpm8xx_t *cp = cpmp;
  50. switch (line) {
  51. case UART_SMC1:
  52. val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
  53. break;
  54. case UART_SMC2:
  55. val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
  56. break;
  57. case UART_SCC1:
  58. val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
  59. break;
  60. case UART_SCC2:
  61. val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
  62. break;
  63. case UART_SCC3:
  64. val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
  65. break;
  66. case UART_SCC4:
  67. val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
  68. break;
  69. default:
  70. return;
  71. }
  72. cp->cp_cpcr = val;
  73. while (cp->cp_cpcr & CPM_CR_FLG) ;
  74. }
  75. void smc1_lineif(struct uart_cpm_port *pinfo)
  76. {
  77. pinfo->brg = 1;
  78. }
  79. void smc2_lineif(struct uart_cpm_port *pinfo)
  80. {
  81. pinfo->brg = 2;
  82. }
  83. void scc1_lineif(struct uart_cpm_port *pinfo)
  84. {
  85. /* XXX SCC1: insert port configuration here */
  86. pinfo->brg = 1;
  87. }
  88. void scc2_lineif(struct uart_cpm_port *pinfo)
  89. {
  90. /* XXX SCC2: insert port configuration here */
  91. pinfo->brg = 2;
  92. }
  93. void scc3_lineif(struct uart_cpm_port *pinfo)
  94. {
  95. /* XXX SCC3: insert port configuration here */
  96. pinfo->brg = 3;
  97. }
  98. void scc4_lineif(struct uart_cpm_port *pinfo)
  99. {
  100. /* XXX SCC4: insert port configuration here */
  101. pinfo->brg = 4;
  102. }
  103. /*
  104. * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
  105. * receive buffer descriptors from dual port ram, and a character
  106. * buffer area from host mem. If we are allocating for the console we need
  107. * to do it from bootmem
  108. */
  109. int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
  110. {
  111. int dpmemsz, memsz;
  112. u8 *dp_mem;
  113. unsigned long dp_offset;
  114. u8 *mem_addr;
  115. dma_addr_t dma_addr = 0;
  116. pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
  117. dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
  118. dp_offset = cpm_dpalloc(dpmemsz, 8);
  119. if (IS_ERR_VALUE(dp_offset)) {
  120. printk(KERN_ERR
  121. "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
  122. return -ENOMEM;
  123. }
  124. dp_mem = cpm_dpram_addr(dp_offset);
  125. memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
  126. L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
  127. if (is_con) {
  128. /* was hostalloc but changed cause it blows away the */
  129. /* large tlb mapping when pinning the kernel area */
  130. mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
  131. dma_addr = (u32)cpm_dpram_phys(mem_addr);
  132. } else
  133. mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
  134. GFP_KERNEL);
  135. if (mem_addr == NULL) {
  136. cpm_dpfree(dp_offset);
  137. printk(KERN_ERR
  138. "cpm_uart_cpm1.c: could not allocate coherent memory\n");
  139. return -ENOMEM;
  140. }
  141. pinfo->dp_addr = dp_offset;
  142. pinfo->mem_addr = mem_addr; /* virtual address*/
  143. pinfo->dma_addr = dma_addr; /* physical address*/
  144. pinfo->mem_size = memsz;
  145. pinfo->rx_buf = mem_addr;
  146. pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
  147. * pinfo->rx_fifosize);
  148. pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
  149. pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
  150. return 0;
  151. }
  152. void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
  153. {
  154. dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
  155. pinfo->rx_fifosize) +
  156. L1_CACHE_ALIGN(pinfo->tx_nrfifos *
  157. pinfo->tx_fifosize), pinfo->mem_addr,
  158. pinfo->dma_addr);
  159. cpm_dpfree(pinfo->dp_addr);
  160. }
  161. /* Setup any dynamic params in the uart desc */
  162. int cpm_uart_init_portdesc(void)
  163. {
  164. pr_debug("CPM uart[-]:init portdesc\n");
  165. cpm_uart_nr = 0;
  166. #ifdef CONFIG_SERIAL_CPM_SMC1
  167. cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
  168. /*
  169. * Is SMC1 being relocated?
  170. */
  171. # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
  172. cpm_uart_ports[UART_SMC1].smcup =
  173. (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
  174. # else
  175. cpm_uart_ports[UART_SMC1].smcup =
  176. (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
  177. # endif
  178. cpm_uart_ports[UART_SMC1].port.mapbase =
  179. (unsigned long)&cpmp->cp_smc[0];
  180. cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
  181. cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  182. cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
  183. cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
  184. #endif
  185. #ifdef CONFIG_SERIAL_CPM_SMC2
  186. cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
  187. cpm_uart_ports[UART_SMC2].smcup =
  188. (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
  189. cpm_uart_ports[UART_SMC2].port.mapbase =
  190. (unsigned long)&cpmp->cp_smc[1];
  191. cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
  192. cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  193. cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
  194. cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
  195. #endif
  196. #ifdef CONFIG_SERIAL_CPM_SCC1
  197. cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
  198. cpm_uart_ports[UART_SCC1].sccup =
  199. (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
  200. cpm_uart_ports[UART_SCC1].port.mapbase =
  201. (unsigned long)&cpmp->cp_scc[0];
  202. cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
  203. ~(UART_SCCM_TX | UART_SCCM_RX);
  204. cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
  205. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  206. cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
  207. cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
  208. #endif
  209. #ifdef CONFIG_SERIAL_CPM_SCC2
  210. cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
  211. cpm_uart_ports[UART_SCC2].sccup =
  212. (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
  213. cpm_uart_ports[UART_SCC2].port.mapbase =
  214. (unsigned long)&cpmp->cp_scc[1];
  215. cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
  216. ~(UART_SCCM_TX | UART_SCCM_RX);
  217. cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
  218. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  219. cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
  220. cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
  221. #endif
  222. #ifdef CONFIG_SERIAL_CPM_SCC3
  223. cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
  224. cpm_uart_ports[UART_SCC3].sccup =
  225. (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
  226. cpm_uart_ports[UART_SCC3].port.mapbase =
  227. (unsigned long)&cpmp->cp_scc[2];
  228. cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
  229. ~(UART_SCCM_TX | UART_SCCM_RX);
  230. cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
  231. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  232. cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
  233. cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
  234. #endif
  235. #ifdef CONFIG_SERIAL_CPM_SCC4
  236. cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
  237. cpm_uart_ports[UART_SCC4].sccup =
  238. (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
  239. cpm_uart_ports[UART_SCC4].port.mapbase =
  240. (unsigned long)&cpmp->cp_scc[3];
  241. cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
  242. ~(UART_SCCM_TX | UART_SCCM_RX);
  243. cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
  244. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  245. cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
  246. cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
  247. #endif
  248. return 0;
  249. }