sata_sil24.c 31 KB

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  1. /*
  2. * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
  3. *
  4. * Copyright 2005 Tejun Heo
  5. *
  6. * Based on preview driver from Silicon Image.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2, or (at your option) any
  11. * later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/blkdev.h>
  23. #include <linux/delay.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/device.h>
  27. #include <scsi/scsi_host.h>
  28. #include <scsi/scsi_cmnd.h>
  29. #include <linux/libata.h>
  30. #define DRV_NAME "sata_sil24"
  31. #define DRV_VERSION "0.9"
  32. /*
  33. * Port request block (PRB) 32 bytes
  34. */
  35. struct sil24_prb {
  36. __le16 ctrl;
  37. __le16 prot;
  38. __le32 rx_cnt;
  39. u8 fis[6 * 4];
  40. };
  41. /*
  42. * Scatter gather entry (SGE) 16 bytes
  43. */
  44. struct sil24_sge {
  45. __le64 addr;
  46. __le32 cnt;
  47. __le32 flags;
  48. };
  49. /*
  50. * Port multiplier
  51. */
  52. struct sil24_port_multiplier {
  53. __le32 diag;
  54. __le32 sactive;
  55. };
  56. enum {
  57. SIL24_HOST_BAR = 0,
  58. SIL24_PORT_BAR = 2,
  59. /*
  60. * Global controller registers (128 bytes @ BAR0)
  61. */
  62. /* 32 bit regs */
  63. HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
  64. HOST_CTRL = 0x40,
  65. HOST_IRQ_STAT = 0x44,
  66. HOST_PHY_CFG = 0x48,
  67. HOST_BIST_CTRL = 0x50,
  68. HOST_BIST_PTRN = 0x54,
  69. HOST_BIST_STAT = 0x58,
  70. HOST_MEM_BIST_STAT = 0x5c,
  71. HOST_FLASH_CMD = 0x70,
  72. /* 8 bit regs */
  73. HOST_FLASH_DATA = 0x74,
  74. HOST_TRANSITION_DETECT = 0x75,
  75. HOST_GPIO_CTRL = 0x76,
  76. HOST_I2C_ADDR = 0x78, /* 32 bit */
  77. HOST_I2C_DATA = 0x7c,
  78. HOST_I2C_XFER_CNT = 0x7e,
  79. HOST_I2C_CTRL = 0x7f,
  80. /* HOST_SLOT_STAT bits */
  81. HOST_SSTAT_ATTN = (1 << 31),
  82. /* HOST_CTRL bits */
  83. HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
  84. HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
  85. HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
  86. HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
  87. HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
  88. HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
  89. /*
  90. * Port registers
  91. * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
  92. */
  93. PORT_REGS_SIZE = 0x2000,
  94. PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
  95. PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
  96. PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
  97. PORT_PMP_STATUS = 0x0000, /* port device status offset */
  98. PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
  99. PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
  100. /* 32 bit regs */
  101. PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
  102. PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
  103. PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
  104. PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
  105. PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
  106. PORT_ACTIVATE_UPPER_ADDR= 0x101c,
  107. PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
  108. PORT_CMD_ERR = 0x1024, /* command error number */
  109. PORT_FIS_CFG = 0x1028,
  110. PORT_FIFO_THRES = 0x102c,
  111. /* 16 bit regs */
  112. PORT_DECODE_ERR_CNT = 0x1040,
  113. PORT_DECODE_ERR_THRESH = 0x1042,
  114. PORT_CRC_ERR_CNT = 0x1044,
  115. PORT_CRC_ERR_THRESH = 0x1046,
  116. PORT_HSHK_ERR_CNT = 0x1048,
  117. PORT_HSHK_ERR_THRESH = 0x104a,
  118. /* 32 bit regs */
  119. PORT_PHY_CFG = 0x1050,
  120. PORT_SLOT_STAT = 0x1800,
  121. PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
  122. PORT_CONTEXT = 0x1e04,
  123. PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
  124. PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
  125. PORT_SCONTROL = 0x1f00,
  126. PORT_SSTATUS = 0x1f04,
  127. PORT_SERROR = 0x1f08,
  128. PORT_SACTIVE = 0x1f0c,
  129. /* PORT_CTRL_STAT bits */
  130. PORT_CS_PORT_RST = (1 << 0), /* port reset */
  131. PORT_CS_DEV_RST = (1 << 1), /* device reset */
  132. PORT_CS_INIT = (1 << 2), /* port initialize */
  133. PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
  134. PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
  135. PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
  136. PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
  137. PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
  138. PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
  139. /* PORT_IRQ_STAT/ENABLE_SET/CLR */
  140. /* bits[11:0] are masked */
  141. PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
  142. PORT_IRQ_ERROR = (1 << 1), /* command execution error */
  143. PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
  144. PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
  145. PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
  146. PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
  147. PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
  148. PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
  149. PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
  150. PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
  151. PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
  152. PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
  153. DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
  154. PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
  155. PORT_IRQ_UNK_FIS,
  156. /* bits[27:16] are unmasked (raw) */
  157. PORT_IRQ_RAW_SHIFT = 16,
  158. PORT_IRQ_MASKED_MASK = 0x7ff,
  159. PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
  160. /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
  161. PORT_IRQ_STEER_SHIFT = 30,
  162. PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
  163. /* PORT_CMD_ERR constants */
  164. PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
  165. PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
  166. PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
  167. PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
  168. PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
  169. PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
  170. PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
  171. PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
  172. PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
  173. PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
  174. PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
  175. PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
  176. PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
  177. PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
  178. PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
  179. PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
  180. PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
  181. PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
  182. PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
  183. PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
  184. PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
  185. PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
  186. /* bits of PRB control field */
  187. PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
  188. PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
  189. PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
  190. PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
  191. PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
  192. /* PRB protocol field */
  193. PRB_PROT_PACKET = (1 << 0),
  194. PRB_PROT_TCQ = (1 << 1),
  195. PRB_PROT_NCQ = (1 << 2),
  196. PRB_PROT_READ = (1 << 3),
  197. PRB_PROT_WRITE = (1 << 4),
  198. PRB_PROT_TRANSPARENT = (1 << 5),
  199. /*
  200. * Other constants
  201. */
  202. SGE_TRM = (1 << 31), /* Last SGE in chain */
  203. SGE_LNK = (1 << 30), /* linked list
  204. Points to SGT, not SGE */
  205. SGE_DRD = (1 << 29), /* discard data read (/dev/null)
  206. data address ignored */
  207. SIL24_MAX_CMDS = 31,
  208. /* board id */
  209. BID_SIL3124 = 0,
  210. BID_SIL3132 = 1,
  211. BID_SIL3131 = 2,
  212. /* host flags */
  213. SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  214. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  215. ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY |
  216. ATA_FLAG_ACPI_SATA,
  217. SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
  218. IRQ_STAT_4PORTS = 0xf,
  219. };
  220. struct sil24_ata_block {
  221. struct sil24_prb prb;
  222. struct sil24_sge sge[LIBATA_MAX_PRD];
  223. };
  224. struct sil24_atapi_block {
  225. struct sil24_prb prb;
  226. u8 cdb[16];
  227. struct sil24_sge sge[LIBATA_MAX_PRD - 1];
  228. };
  229. union sil24_cmd_block {
  230. struct sil24_ata_block ata;
  231. struct sil24_atapi_block atapi;
  232. };
  233. static struct sil24_cerr_info {
  234. unsigned int err_mask, action;
  235. const char *desc;
  236. } sil24_cerr_db[] = {
  237. [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
  238. "device error" },
  239. [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
  240. "device error via D2H FIS" },
  241. [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
  242. "device error via SDB FIS" },
  243. [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
  244. "error in data FIS" },
  245. [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
  246. "failed to transmit command FIS" },
  247. [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
  248. "protocol mismatch" },
  249. [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
  250. "data directon mismatch" },
  251. [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
  252. "ran out of SGEs while writing" },
  253. [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
  254. "ran out of SGEs while reading" },
  255. [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
  256. "invalid data directon for ATAPI CDB" },
  257. [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
  258. "SGT no on qword boundary" },
  259. [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  260. "PCI target abort while fetching SGT" },
  261. [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  262. "PCI master abort while fetching SGT" },
  263. [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  264. "PCI parity error while fetching SGT" },
  265. [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
  266. "PRB not on qword boundary" },
  267. [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  268. "PCI target abort while fetching PRB" },
  269. [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  270. "PCI master abort while fetching PRB" },
  271. [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  272. "PCI parity error while fetching PRB" },
  273. [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  274. "undefined error while transferring data" },
  275. [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  276. "PCI target abort while transferring data" },
  277. [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  278. "PCI master abort while transferring data" },
  279. [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
  280. "PCI parity error while transferring data" },
  281. [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
  282. "FIS received while sending service FIS" },
  283. };
  284. /*
  285. * ap->private_data
  286. *
  287. * The preview driver always returned 0 for status. We emulate it
  288. * here from the previous interrupt.
  289. */
  290. struct sil24_port_priv {
  291. union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
  292. dma_addr_t cmd_block_dma; /* DMA base addr for them */
  293. struct ata_taskfile tf; /* Cached taskfile registers */
  294. };
  295. static void sil24_dev_config(struct ata_device *dev);
  296. static u8 sil24_check_status(struct ata_port *ap);
  297. static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
  298. static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
  299. static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
  300. static void sil24_qc_prep(struct ata_queued_cmd *qc);
  301. static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
  302. static void sil24_irq_clear(struct ata_port *ap);
  303. static void sil24_freeze(struct ata_port *ap);
  304. static void sil24_thaw(struct ata_port *ap);
  305. static void sil24_error_handler(struct ata_port *ap);
  306. static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
  307. static int sil24_port_start(struct ata_port *ap);
  308. static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  309. #ifdef CONFIG_PM
  310. static int sil24_pci_device_resume(struct pci_dev *pdev);
  311. #endif
  312. static const struct pci_device_id sil24_pci_tbl[] = {
  313. { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
  314. { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
  315. { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
  316. { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
  317. { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
  318. { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
  319. { } /* terminate list */
  320. };
  321. static struct pci_driver sil24_pci_driver = {
  322. .name = DRV_NAME,
  323. .id_table = sil24_pci_tbl,
  324. .probe = sil24_init_one,
  325. .remove = ata_pci_remove_one,
  326. #ifdef CONFIG_PM
  327. .suspend = ata_pci_device_suspend,
  328. .resume = sil24_pci_device_resume,
  329. #endif
  330. };
  331. static struct scsi_host_template sil24_sht = {
  332. .module = THIS_MODULE,
  333. .name = DRV_NAME,
  334. .ioctl = ata_scsi_ioctl,
  335. .queuecommand = ata_scsi_queuecmd,
  336. .change_queue_depth = ata_scsi_change_queue_depth,
  337. .can_queue = SIL24_MAX_CMDS,
  338. .this_id = ATA_SHT_THIS_ID,
  339. .sg_tablesize = LIBATA_MAX_PRD,
  340. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  341. .emulated = ATA_SHT_EMULATED,
  342. .use_clustering = ATA_SHT_USE_CLUSTERING,
  343. .proc_name = DRV_NAME,
  344. .dma_boundary = ATA_DMA_BOUNDARY,
  345. .slave_configure = ata_scsi_slave_config,
  346. .slave_destroy = ata_scsi_slave_destroy,
  347. .bios_param = ata_std_bios_param,
  348. };
  349. static const struct ata_port_operations sil24_ops = {
  350. .port_disable = ata_port_disable,
  351. .dev_config = sil24_dev_config,
  352. .check_status = sil24_check_status,
  353. .check_altstatus = sil24_check_status,
  354. .dev_select = ata_noop_dev_select,
  355. .tf_read = sil24_tf_read,
  356. .qc_prep = sil24_qc_prep,
  357. .qc_issue = sil24_qc_issue,
  358. .irq_clear = sil24_irq_clear,
  359. .irq_on = ata_dummy_irq_on,
  360. .irq_ack = ata_dummy_irq_ack,
  361. .scr_read = sil24_scr_read,
  362. .scr_write = sil24_scr_write,
  363. .freeze = sil24_freeze,
  364. .thaw = sil24_thaw,
  365. .error_handler = sil24_error_handler,
  366. .post_internal_cmd = sil24_post_internal_cmd,
  367. .port_start = sil24_port_start,
  368. };
  369. /*
  370. * Use bits 30-31 of port_flags to encode available port numbers.
  371. * Current maxium is 4.
  372. */
  373. #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
  374. #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
  375. static const struct ata_port_info sil24_port_info[] = {
  376. /* sil_3124 */
  377. {
  378. .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
  379. SIL24_FLAG_PCIX_IRQ_WOC,
  380. .pio_mask = 0x1f, /* pio0-4 */
  381. .mwdma_mask = 0x07, /* mwdma0-2 */
  382. .udma_mask = ATA_UDMA5, /* udma0-5 */
  383. .port_ops = &sil24_ops,
  384. },
  385. /* sil_3132 */
  386. {
  387. .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
  388. .pio_mask = 0x1f, /* pio0-4 */
  389. .mwdma_mask = 0x07, /* mwdma0-2 */
  390. .udma_mask = ATA_UDMA5, /* udma0-5 */
  391. .port_ops = &sil24_ops,
  392. },
  393. /* sil_3131/sil_3531 */
  394. {
  395. .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
  396. .pio_mask = 0x1f, /* pio0-4 */
  397. .mwdma_mask = 0x07, /* mwdma0-2 */
  398. .udma_mask = ATA_UDMA5, /* udma0-5 */
  399. .port_ops = &sil24_ops,
  400. },
  401. };
  402. static int sil24_tag(int tag)
  403. {
  404. if (unlikely(ata_tag_internal(tag)))
  405. return 0;
  406. return tag;
  407. }
  408. static void sil24_dev_config(struct ata_device *dev)
  409. {
  410. void __iomem *port = dev->ap->ioaddr.cmd_addr;
  411. if (dev->cdb_len == 16)
  412. writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
  413. else
  414. writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
  415. }
  416. static inline void sil24_update_tf(struct ata_port *ap)
  417. {
  418. struct sil24_port_priv *pp = ap->private_data;
  419. void __iomem *port = ap->ioaddr.cmd_addr;
  420. struct sil24_prb __iomem *prb = port;
  421. u8 fis[6 * 4];
  422. memcpy_fromio(fis, prb->fis, 6 * 4);
  423. ata_tf_from_fis(fis, &pp->tf);
  424. }
  425. static u8 sil24_check_status(struct ata_port *ap)
  426. {
  427. struct sil24_port_priv *pp = ap->private_data;
  428. return pp->tf.command;
  429. }
  430. static int sil24_scr_map[] = {
  431. [SCR_CONTROL] = 0,
  432. [SCR_STATUS] = 1,
  433. [SCR_ERROR] = 2,
  434. [SCR_ACTIVE] = 3,
  435. };
  436. static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
  437. {
  438. void __iomem *scr_addr = ap->ioaddr.scr_addr;
  439. if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
  440. void __iomem *addr;
  441. addr = scr_addr + sil24_scr_map[sc_reg] * 4;
  442. return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
  443. }
  444. return 0xffffffffU;
  445. }
  446. static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
  447. {
  448. void __iomem *scr_addr = ap->ioaddr.scr_addr;
  449. if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
  450. void __iomem *addr;
  451. addr = scr_addr + sil24_scr_map[sc_reg] * 4;
  452. writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
  453. }
  454. }
  455. static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  456. {
  457. struct sil24_port_priv *pp = ap->private_data;
  458. *tf = pp->tf;
  459. }
  460. static int sil24_init_port(struct ata_port *ap)
  461. {
  462. void __iomem *port = ap->ioaddr.cmd_addr;
  463. u32 tmp;
  464. writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
  465. ata_wait_register(port + PORT_CTRL_STAT,
  466. PORT_CS_INIT, PORT_CS_INIT, 10, 100);
  467. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  468. PORT_CS_RDY, 0, 10, 100);
  469. if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
  470. return -EIO;
  471. return 0;
  472. }
  473. static int sil24_softreset(struct ata_port *ap, unsigned int *class,
  474. unsigned long deadline)
  475. {
  476. void __iomem *port = ap->ioaddr.cmd_addr;
  477. struct sil24_port_priv *pp = ap->private_data;
  478. struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
  479. dma_addr_t paddr = pp->cmd_block_dma;
  480. u32 mask, irq_stat;
  481. const char *reason;
  482. DPRINTK("ENTER\n");
  483. if (ata_port_offline(ap)) {
  484. DPRINTK("PHY reports no device\n");
  485. *class = ATA_DEV_NONE;
  486. goto out;
  487. }
  488. /* put the port into known state */
  489. if (sil24_init_port(ap)) {
  490. reason ="port not ready";
  491. goto err;
  492. }
  493. /* do SRST */
  494. prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
  495. prb->fis[1] = 0; /* no PMP yet */
  496. writel((u32)paddr, port + PORT_CMD_ACTIVATE);
  497. writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
  498. mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
  499. irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
  500. 100, jiffies_to_msecs(deadline - jiffies));
  501. writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
  502. irq_stat >>= PORT_IRQ_RAW_SHIFT;
  503. if (!(irq_stat & PORT_IRQ_COMPLETE)) {
  504. if (irq_stat & PORT_IRQ_ERROR)
  505. reason = "SRST command error";
  506. else
  507. reason = "timeout";
  508. goto err;
  509. }
  510. sil24_update_tf(ap);
  511. *class = ata_dev_classify(&pp->tf);
  512. if (*class == ATA_DEV_UNKNOWN)
  513. *class = ATA_DEV_NONE;
  514. out:
  515. DPRINTK("EXIT, class=%u\n", *class);
  516. return 0;
  517. err:
  518. ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
  519. return -EIO;
  520. }
  521. static int sil24_hardreset(struct ata_port *ap, unsigned int *class,
  522. unsigned long deadline)
  523. {
  524. void __iomem *port = ap->ioaddr.cmd_addr;
  525. const char *reason;
  526. int tout_msec, rc;
  527. u32 tmp;
  528. /* sil24 does the right thing(tm) without any protection */
  529. sata_set_spd(ap);
  530. tout_msec = 100;
  531. if (ata_port_online(ap))
  532. tout_msec = 5000;
  533. writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
  534. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  535. PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
  536. /* SStatus oscillates between zero and valid status after
  537. * DEV_RST, debounce it.
  538. */
  539. rc = sata_phy_debounce(ap, sata_deb_timing_long, deadline);
  540. if (rc) {
  541. reason = "PHY debouncing failed";
  542. goto err;
  543. }
  544. if (tmp & PORT_CS_DEV_RST) {
  545. if (ata_port_offline(ap))
  546. return 0;
  547. reason = "link not ready";
  548. goto err;
  549. }
  550. /* Sil24 doesn't store signature FIS after hardreset, so we
  551. * can't wait for BSY to clear. Some devices take a long time
  552. * to get ready and those devices will choke if we don't wait
  553. * for BSY clearance here. Tell libata to perform follow-up
  554. * softreset.
  555. */
  556. return -EAGAIN;
  557. err:
  558. ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
  559. return -EIO;
  560. }
  561. static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
  562. struct sil24_sge *sge)
  563. {
  564. struct scatterlist *sg;
  565. ata_for_each_sg(sg, qc) {
  566. sge->addr = cpu_to_le64(sg_dma_address(sg));
  567. sge->cnt = cpu_to_le32(sg_dma_len(sg));
  568. if (ata_sg_is_last(sg, qc))
  569. sge->flags = cpu_to_le32(SGE_TRM);
  570. else
  571. sge->flags = 0;
  572. sge++;
  573. }
  574. }
  575. static void sil24_qc_prep(struct ata_queued_cmd *qc)
  576. {
  577. struct ata_port *ap = qc->ap;
  578. struct sil24_port_priv *pp = ap->private_data;
  579. union sil24_cmd_block *cb;
  580. struct sil24_prb *prb;
  581. struct sil24_sge *sge;
  582. u16 ctrl = 0;
  583. cb = &pp->cmd_block[sil24_tag(qc->tag)];
  584. switch (qc->tf.protocol) {
  585. case ATA_PROT_PIO:
  586. case ATA_PROT_DMA:
  587. case ATA_PROT_NCQ:
  588. case ATA_PROT_NODATA:
  589. prb = &cb->ata.prb;
  590. sge = cb->ata.sge;
  591. break;
  592. case ATA_PROT_ATAPI:
  593. case ATA_PROT_ATAPI_DMA:
  594. case ATA_PROT_ATAPI_NODATA:
  595. prb = &cb->atapi.prb;
  596. sge = cb->atapi.sge;
  597. memset(cb->atapi.cdb, 0, 32);
  598. memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
  599. if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
  600. if (qc->tf.flags & ATA_TFLAG_WRITE)
  601. ctrl = PRB_CTRL_PACKET_WRITE;
  602. else
  603. ctrl = PRB_CTRL_PACKET_READ;
  604. }
  605. break;
  606. default:
  607. prb = NULL; /* shut up, gcc */
  608. sge = NULL;
  609. BUG();
  610. }
  611. prb->ctrl = cpu_to_le16(ctrl);
  612. ata_tf_to_fis(&qc->tf, prb->fis, 0);
  613. if (qc->flags & ATA_QCFLAG_DMAMAP)
  614. sil24_fill_sg(qc, sge);
  615. }
  616. static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
  617. {
  618. struct ata_port *ap = qc->ap;
  619. struct sil24_port_priv *pp = ap->private_data;
  620. void __iomem *port = ap->ioaddr.cmd_addr;
  621. unsigned int tag = sil24_tag(qc->tag);
  622. dma_addr_t paddr;
  623. void __iomem *activate;
  624. paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
  625. activate = port + PORT_CMD_ACTIVATE + tag * 8;
  626. writel((u32)paddr, activate);
  627. writel((u64)paddr >> 32, activate + 4);
  628. return 0;
  629. }
  630. static void sil24_irq_clear(struct ata_port *ap)
  631. {
  632. /* unused */
  633. }
  634. static void sil24_freeze(struct ata_port *ap)
  635. {
  636. void __iomem *port = ap->ioaddr.cmd_addr;
  637. /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
  638. * PORT_IRQ_ENABLE instead.
  639. */
  640. writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
  641. }
  642. static void sil24_thaw(struct ata_port *ap)
  643. {
  644. void __iomem *port = ap->ioaddr.cmd_addr;
  645. u32 tmp;
  646. /* clear IRQ */
  647. tmp = readl(port + PORT_IRQ_STAT);
  648. writel(tmp, port + PORT_IRQ_STAT);
  649. /* turn IRQ back on */
  650. writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
  651. }
  652. static void sil24_error_intr(struct ata_port *ap)
  653. {
  654. void __iomem *port = ap->ioaddr.cmd_addr;
  655. struct ata_eh_info *ehi = &ap->eh_info;
  656. int freeze = 0;
  657. u32 irq_stat;
  658. /* on error, we need to clear IRQ explicitly */
  659. irq_stat = readl(port + PORT_IRQ_STAT);
  660. writel(irq_stat, port + PORT_IRQ_STAT);
  661. /* first, analyze and record host port events */
  662. ata_ehi_clear_desc(ehi);
  663. ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
  664. if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
  665. ata_ehi_hotplugged(ehi);
  666. ata_ehi_push_desc(ehi, ", %s",
  667. irq_stat & PORT_IRQ_PHYRDY_CHG ?
  668. "PHY RDY changed" : "device exchanged");
  669. freeze = 1;
  670. }
  671. if (irq_stat & PORT_IRQ_UNK_FIS) {
  672. ehi->err_mask |= AC_ERR_HSM;
  673. ehi->action |= ATA_EH_SOFTRESET;
  674. ata_ehi_push_desc(ehi , ", unknown FIS");
  675. freeze = 1;
  676. }
  677. /* deal with command error */
  678. if (irq_stat & PORT_IRQ_ERROR) {
  679. struct sil24_cerr_info *ci = NULL;
  680. unsigned int err_mask = 0, action = 0;
  681. struct ata_queued_cmd *qc;
  682. u32 cerr;
  683. /* analyze CMD_ERR */
  684. cerr = readl(port + PORT_CMD_ERR);
  685. if (cerr < ARRAY_SIZE(sil24_cerr_db))
  686. ci = &sil24_cerr_db[cerr];
  687. if (ci && ci->desc) {
  688. err_mask |= ci->err_mask;
  689. action |= ci->action;
  690. ata_ehi_push_desc(ehi, ", %s", ci->desc);
  691. } else {
  692. err_mask |= AC_ERR_OTHER;
  693. action |= ATA_EH_SOFTRESET;
  694. ata_ehi_push_desc(ehi, ", unknown command error %d",
  695. cerr);
  696. }
  697. /* record error info */
  698. qc = ata_qc_from_tag(ap, ap->active_tag);
  699. if (qc) {
  700. sil24_update_tf(ap);
  701. qc->err_mask |= err_mask;
  702. } else
  703. ehi->err_mask |= err_mask;
  704. ehi->action |= action;
  705. }
  706. /* freeze or abort */
  707. if (freeze)
  708. ata_port_freeze(ap);
  709. else
  710. ata_port_abort(ap);
  711. }
  712. static void sil24_finish_qc(struct ata_queued_cmd *qc)
  713. {
  714. if (qc->flags & ATA_QCFLAG_RESULT_TF)
  715. sil24_update_tf(qc->ap);
  716. }
  717. static inline void sil24_host_intr(struct ata_port *ap)
  718. {
  719. void __iomem *port = ap->ioaddr.cmd_addr;
  720. u32 slot_stat, qc_active;
  721. int rc;
  722. slot_stat = readl(port + PORT_SLOT_STAT);
  723. if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
  724. sil24_error_intr(ap);
  725. return;
  726. }
  727. if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
  728. writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
  729. qc_active = slot_stat & ~HOST_SSTAT_ATTN;
  730. rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
  731. if (rc > 0)
  732. return;
  733. if (rc < 0) {
  734. struct ata_eh_info *ehi = &ap->eh_info;
  735. ehi->err_mask |= AC_ERR_HSM;
  736. ehi->action |= ATA_EH_SOFTRESET;
  737. ata_port_freeze(ap);
  738. return;
  739. }
  740. if (ata_ratelimit())
  741. ata_port_printk(ap, KERN_INFO, "spurious interrupt "
  742. "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
  743. slot_stat, ap->active_tag, ap->sactive);
  744. }
  745. static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
  746. {
  747. struct ata_host *host = dev_instance;
  748. void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
  749. unsigned handled = 0;
  750. u32 status;
  751. int i;
  752. status = readl(host_base + HOST_IRQ_STAT);
  753. if (status == 0xffffffff) {
  754. printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
  755. "PCI fault or device removal?\n");
  756. goto out;
  757. }
  758. if (!(status & IRQ_STAT_4PORTS))
  759. goto out;
  760. spin_lock(&host->lock);
  761. for (i = 0; i < host->n_ports; i++)
  762. if (status & (1 << i)) {
  763. struct ata_port *ap = host->ports[i];
  764. if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
  765. sil24_host_intr(ap);
  766. handled++;
  767. } else
  768. printk(KERN_ERR DRV_NAME
  769. ": interrupt from disabled port %d\n", i);
  770. }
  771. spin_unlock(&host->lock);
  772. out:
  773. return IRQ_RETVAL(handled);
  774. }
  775. static void sil24_error_handler(struct ata_port *ap)
  776. {
  777. struct ata_eh_context *ehc = &ap->eh_context;
  778. if (sil24_init_port(ap)) {
  779. ata_eh_freeze_port(ap);
  780. ehc->i.action |= ATA_EH_HARDRESET;
  781. }
  782. /* perform recovery */
  783. ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
  784. ata_std_postreset);
  785. }
  786. static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
  787. {
  788. struct ata_port *ap = qc->ap;
  789. /* make DMA engine forget about the failed command */
  790. if (qc->flags & ATA_QCFLAG_FAILED)
  791. sil24_init_port(ap);
  792. }
  793. static int sil24_port_start(struct ata_port *ap)
  794. {
  795. struct device *dev = ap->host->dev;
  796. struct sil24_port_priv *pp;
  797. union sil24_cmd_block *cb;
  798. size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
  799. dma_addr_t cb_dma;
  800. int rc;
  801. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  802. if (!pp)
  803. return -ENOMEM;
  804. pp->tf.command = ATA_DRDY;
  805. cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
  806. if (!cb)
  807. return -ENOMEM;
  808. memset(cb, 0, cb_size);
  809. rc = ata_pad_alloc(ap, dev);
  810. if (rc)
  811. return rc;
  812. pp->cmd_block = cb;
  813. pp->cmd_block_dma = cb_dma;
  814. ap->private_data = pp;
  815. return 0;
  816. }
  817. static void sil24_init_controller(struct ata_host *host)
  818. {
  819. void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
  820. void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
  821. u32 tmp;
  822. int i;
  823. /* GPIO off */
  824. writel(0, host_base + HOST_FLASH_CMD);
  825. /* clear global reset & mask interrupts during initialization */
  826. writel(0, host_base + HOST_CTRL);
  827. /* init ports */
  828. for (i = 0; i < host->n_ports; i++) {
  829. void __iomem *port = port_base + i * PORT_REGS_SIZE;
  830. /* Initial PHY setting */
  831. writel(0x20c, port + PORT_PHY_CFG);
  832. /* Clear port RST */
  833. tmp = readl(port + PORT_CTRL_STAT);
  834. if (tmp & PORT_CS_PORT_RST) {
  835. writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
  836. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  837. PORT_CS_PORT_RST,
  838. PORT_CS_PORT_RST, 10, 100);
  839. if (tmp & PORT_CS_PORT_RST)
  840. dev_printk(KERN_ERR, host->dev,
  841. "failed to clear port RST\n");
  842. }
  843. /* Configure IRQ WoC */
  844. if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
  845. writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
  846. else
  847. writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
  848. /* Zero error counters. */
  849. writel(0x8000, port + PORT_DECODE_ERR_THRESH);
  850. writel(0x8000, port + PORT_CRC_ERR_THRESH);
  851. writel(0x8000, port + PORT_HSHK_ERR_THRESH);
  852. writel(0x0000, port + PORT_DECODE_ERR_CNT);
  853. writel(0x0000, port + PORT_CRC_ERR_CNT);
  854. writel(0x0000, port + PORT_HSHK_ERR_CNT);
  855. /* Always use 64bit activation */
  856. writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
  857. /* Clear port multiplier enable and resume bits */
  858. writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
  859. port + PORT_CTRL_CLR);
  860. }
  861. /* Turn on interrupts */
  862. writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
  863. }
  864. static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  865. {
  866. static int printed_version = 0;
  867. struct ata_port_info pi = sil24_port_info[ent->driver_data];
  868. const struct ata_port_info *ppi[] = { &pi, NULL };
  869. void __iomem * const *iomap;
  870. struct ata_host *host;
  871. int i, rc;
  872. u32 tmp;
  873. if (!printed_version++)
  874. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  875. /* acquire resources */
  876. rc = pcim_enable_device(pdev);
  877. if (rc)
  878. return rc;
  879. rc = pcim_iomap_regions(pdev,
  880. (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
  881. DRV_NAME);
  882. if (rc)
  883. return rc;
  884. iomap = pcim_iomap_table(pdev);
  885. /* apply workaround for completion IRQ loss on PCI-X errata */
  886. if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
  887. tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
  888. if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
  889. dev_printk(KERN_INFO, &pdev->dev,
  890. "Applying completion IRQ loss on PCI-X "
  891. "errata fix\n");
  892. else
  893. pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
  894. }
  895. /* allocate and fill host */
  896. host = ata_host_alloc_pinfo(&pdev->dev, ppi,
  897. SIL24_FLAG2NPORTS(ppi[0]->flags));
  898. if (!host)
  899. return -ENOMEM;
  900. host->iomap = iomap;
  901. for (i = 0; i < host->n_ports; i++) {
  902. void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
  903. host->ports[i]->ioaddr.cmd_addr = port;
  904. host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
  905. ata_std_ports(&host->ports[i]->ioaddr);
  906. }
  907. /* configure and activate the device */
  908. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  909. rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  910. if (rc) {
  911. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  912. if (rc) {
  913. dev_printk(KERN_ERR, &pdev->dev,
  914. "64-bit DMA enable failed\n");
  915. return rc;
  916. }
  917. }
  918. } else {
  919. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  920. if (rc) {
  921. dev_printk(KERN_ERR, &pdev->dev,
  922. "32-bit DMA enable failed\n");
  923. return rc;
  924. }
  925. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  926. if (rc) {
  927. dev_printk(KERN_ERR, &pdev->dev,
  928. "32-bit consistent DMA enable failed\n");
  929. return rc;
  930. }
  931. }
  932. sil24_init_controller(host);
  933. pci_set_master(pdev);
  934. return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
  935. &sil24_sht);
  936. }
  937. #ifdef CONFIG_PM
  938. static int sil24_pci_device_resume(struct pci_dev *pdev)
  939. {
  940. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  941. void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
  942. int rc;
  943. rc = ata_pci_device_do_resume(pdev);
  944. if (rc)
  945. return rc;
  946. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
  947. writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
  948. sil24_init_controller(host);
  949. ata_host_resume(host);
  950. return 0;
  951. }
  952. #endif
  953. static int __init sil24_init(void)
  954. {
  955. return pci_register_driver(&sil24_pci_driver);
  956. }
  957. static void __exit sil24_exit(void)
  958. {
  959. pci_unregister_driver(&sil24_pci_driver);
  960. }
  961. MODULE_AUTHOR("Tejun Heo");
  962. MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
  963. MODULE_LICENSE("GPL");
  964. MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
  965. module_init(sil24_init);
  966. module_exit(sil24_exit);