mpc85xx_cds.c 6.4 KB

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  1. /*
  2. * MPC85xx setup and early boot code plus other random bits.
  3. *
  4. * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5. *
  6. * Copyright 2005 Freescale Semiconductor Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/stddef.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/reboot.h>
  18. #include <linux/pci.h>
  19. #include <linux/kdev_t.h>
  20. #include <linux/major.h>
  21. #include <linux/console.h>
  22. #include <linux/delay.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/initrd.h>
  25. #include <linux/module.h>
  26. #include <linux/fsl_devices.h>
  27. #include <asm/system.h>
  28. #include <asm/pgtable.h>
  29. #include <asm/page.h>
  30. #include <asm/atomic.h>
  31. #include <asm/time.h>
  32. #include <asm/io.h>
  33. #include <asm/machdep.h>
  34. #include <asm/ipic.h>
  35. #include <asm/bootinfo.h>
  36. #include <asm/pci-bridge.h>
  37. #include <asm/mpc85xx.h>
  38. #include <asm/irq.h>
  39. #include <mm/mmu_decl.h>
  40. #include <asm/prom.h>
  41. #include <asm/udbg.h>
  42. #include <asm/mpic.h>
  43. #include <asm/i8259.h>
  44. #include <sysdev/fsl_soc.h>
  45. #include "mpc85xx.h"
  46. static int cds_pci_slot = 2;
  47. static volatile u8 *cadmus;
  48. #ifdef CONFIG_PCI
  49. #define ARCADIA_HOST_BRIDGE_IDSEL 17
  50. #define ARCADIA_2ND_BRIDGE_IDSEL 3
  51. static int mpc85xx_exclude_device(struct pci_controller *hose,
  52. u_char bus, u_char devfn)
  53. {
  54. if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
  55. return PCIBIOS_DEVICE_NOT_FOUND;
  56. /* We explicitly do not go past the Tundra 320 Bridge */
  57. if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  58. return PCIBIOS_DEVICE_NOT_FOUND;
  59. if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  60. return PCIBIOS_DEVICE_NOT_FOUND;
  61. else
  62. return PCIBIOS_SUCCESSFUL;
  63. }
  64. static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
  65. {
  66. u_char c;
  67. if (dev->vendor == PCI_VENDOR_ID_VIA) {
  68. switch (dev->device) {
  69. case PCI_DEVICE_ID_VIA_82C586_1:
  70. /*
  71. * U-Boot does not set the enable bits
  72. * for the IDE device. Force them on here.
  73. */
  74. pci_read_config_byte(dev, 0x40, &c);
  75. c |= 0x03; /* IDE: Chip Enable Bits */
  76. pci_write_config_byte(dev, 0x40, c);
  77. /*
  78. * Since only primary interface works, force the
  79. * IDE function to standard primary IDE interrupt
  80. * w/ 8259 offset
  81. */
  82. dev->irq = 14;
  83. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  84. break;
  85. /*
  86. * Force legacy USB interrupt routing
  87. */
  88. case PCI_DEVICE_ID_VIA_82C586_2:
  89. /* There are two USB controllers.
  90. * Identify them by functon number
  91. */
  92. if (PCI_FUNC(dev->devfn))
  93. dev->irq = 11;
  94. else
  95. dev->irq = 10;
  96. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  97. default:
  98. break;
  99. }
  100. }
  101. }
  102. #ifdef CONFIG_PPC_I8259
  103. #warning The i8259 PIC support is currently broken
  104. static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
  105. {
  106. unsigned int cascade_irq = i8259_irq();
  107. if (cascade_irq != NO_IRQ)
  108. generic_handle_irq(cascade_irq);
  109. desc->chip->eoi(irq);
  110. }
  111. #endif /* PPC_I8259 */
  112. #endif /* CONFIG_PCI */
  113. static void __init mpc85xx_cds_pic_init(void)
  114. {
  115. struct mpic *mpic;
  116. struct resource r;
  117. struct device_node *np = NULL;
  118. #ifdef CONFIG_PPC_I8259
  119. struct device_node *cascade_node = NULL;
  120. int cascade_irq;
  121. #endif
  122. np = of_find_node_by_type(np, "open-pic");
  123. if (np == NULL) {
  124. printk(KERN_ERR "Could not find open-pic node\n");
  125. return;
  126. }
  127. if (of_address_to_resource(np, 0, &r)) {
  128. printk(KERN_ERR "Failed to map mpic register space\n");
  129. of_node_put(np);
  130. return;
  131. }
  132. mpic = mpic_alloc(np, r.start,
  133. MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  134. 0, 256, " OpenPIC ");
  135. BUG_ON(mpic == NULL);
  136. /* Return the mpic node */
  137. of_node_put(np);
  138. mpic_init(mpic);
  139. #ifdef CONFIG_PPC_I8259
  140. /* Initialize the i8259 controller */
  141. for_each_node_by_type(np, "interrupt-controller")
  142. if (of_device_is_compatible(np, "chrp,iic")) {
  143. cascade_node = np;
  144. break;
  145. }
  146. if (cascade_node == NULL) {
  147. printk(KERN_DEBUG "Could not find i8259 PIC\n");
  148. return;
  149. }
  150. cascade_irq = irq_of_parse_and_map(cascade_node, 0);
  151. if (cascade_irq == NO_IRQ) {
  152. printk(KERN_ERR "Failed to map cascade interrupt\n");
  153. return;
  154. }
  155. i8259_init(cascade_node, 0);
  156. of_node_put(cascade_node);
  157. set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
  158. #endif /* CONFIG_PPC_I8259 */
  159. }
  160. /*
  161. * Setup the architecture
  162. */
  163. static void __init mpc85xx_cds_setup_arch(void)
  164. {
  165. struct device_node *cpu;
  166. #ifdef CONFIG_PCI
  167. struct device_node *np;
  168. #endif
  169. if (ppc_md.progress)
  170. ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
  171. cpu = of_find_node_by_type(NULL, "cpu");
  172. if (cpu != 0) {
  173. const unsigned int *fp;
  174. fp = of_get_property(cpu, "clock-frequency", NULL);
  175. if (fp != 0)
  176. loops_per_jiffy = *fp / HZ;
  177. else
  178. loops_per_jiffy = 500000000 / HZ;
  179. of_node_put(cpu);
  180. }
  181. cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
  182. cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
  183. if (ppc_md.progress) {
  184. char buf[40];
  185. snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
  186. cadmus[CM_VER], cds_pci_slot);
  187. ppc_md.progress(buf, 0);
  188. }
  189. #ifdef CONFIG_PCI
  190. for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
  191. mpc85xx_add_bridge(np);
  192. ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
  193. ppc_md.pci_exclude_device = mpc85xx_exclude_device;
  194. #endif
  195. }
  196. static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
  197. {
  198. uint pvid, svid, phid1;
  199. uint memsize = total_memory;
  200. pvid = mfspr(SPRN_PVR);
  201. svid = mfspr(SPRN_SVR);
  202. seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  203. seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
  204. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  205. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  206. /* Display cpu Pll setting */
  207. phid1 = mfspr(SPRN_HID1);
  208. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  209. /* Display the amount of memory */
  210. seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
  211. }
  212. /*
  213. * Called very early, device-tree isn't unflattened
  214. */
  215. static int __init mpc85xx_cds_probe(void)
  216. {
  217. unsigned long root = of_get_flat_dt_root();
  218. return of_flat_dt_is_compatible(root, "MPC85xxCDS");
  219. }
  220. define_machine(mpc85xx_cds) {
  221. .name = "MPC85xx CDS",
  222. .probe = mpc85xx_cds_probe,
  223. .setup_arch = mpc85xx_cds_setup_arch,
  224. .init_IRQ = mpc85xx_cds_pic_init,
  225. .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
  226. .get_irq = mpic_get_irq,
  227. .restart = mpc85xx_restart,
  228. .calibrate_decr = generic_calibrate_decr,
  229. .progress = udbg_progress,
  230. };