mpc885ads.dts 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183
  1. /*
  2. * MPC885 ADS Device Tree Source
  3. *
  4. * Copyright 2006 MontaVista Software, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC885ADS";
  13. compatible = "mpc8xx";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,885@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <2000>; // L1, 8K
  25. i-cache-size = <2000>; // L1, 8K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. 32-bit;
  30. interrupts = <f 2>; // decrementer interrupt
  31. interrupt-parent = <&Mpc8xx_pic>;
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <00000000 800000>;
  37. };
  38. soc885@ff000000 {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. #interrupt-cells = <2>;
  42. device_type = "soc";
  43. ranges = <0 ff000000 00100000>;
  44. reg = <ff000000 00000200>;
  45. bus-frequency = <0>;
  46. mdio@e80 {
  47. device_type = "mdio";
  48. compatible = "fs_enet";
  49. reg = <e80 8>;
  50. #address-cells = <1>;
  51. #size-cells = <0>;
  52. Phy0: ethernet-phy@0 {
  53. reg = <0>;
  54. device_type = "ethernet-phy";
  55. };
  56. Phy1: ethernet-phy@1 {
  57. reg = <1>;
  58. device_type = "ethernet-phy";
  59. };
  60. Phy2: ethernet-phy@2 {
  61. reg = <2>;
  62. device_type = "ethernet-phy";
  63. };
  64. };
  65. fec@e00 {
  66. device_type = "network";
  67. compatible = "fs_enet";
  68. model = "FEC";
  69. device-id = <1>;
  70. reg = <e00 188>;
  71. mac-address = [ 00 00 0C 00 01 FD ];
  72. interrupts = <3 1>;
  73. interrupt-parent = <&Mpc8xx_pic>;
  74. phy-handle = <&Phy1>;
  75. };
  76. fec@1e00 {
  77. device_type = "network";
  78. compatible = "fs_enet";
  79. model = "FEC";
  80. device-id = <2>;
  81. reg = <1e00 188>;
  82. mac-address = [ 00 00 0C 00 02 FD ];
  83. interrupts = <7 1>;
  84. interrupt-parent = <&Mpc8xx_pic>;
  85. phy-handle = <&Phy2>;
  86. };
  87. Mpc8xx_pic: pic@ff000000 {
  88. interrupt-controller;
  89. #address-cells = <0>;
  90. #interrupt-cells = <2>;
  91. reg = <0 24>;
  92. built-in;
  93. device_type = "mpc8xx-pic";
  94. compatible = "CPM";
  95. };
  96. pcmcia@0080 {
  97. #address-cells = <3>;
  98. #interrupt-cells = <1>;
  99. #size-cells = <2>;
  100. compatible = "fsl,pq-pcmcia";
  101. device_type = "pcmcia";
  102. reg = <80 80>;
  103. interrupt-parent = <&Mpc8xx_pic>;
  104. interrupts = <d 1>;
  105. };
  106. cpm@ff000000 {
  107. #address-cells = <1>;
  108. #size-cells = <1>;
  109. #interrupt-cells = <2>;
  110. device_type = "cpm";
  111. model = "CPM";
  112. ranges = <0 0 4000>;
  113. reg = <860 f0>;
  114. command-proc = <9c0>;
  115. brg-frequency = <0>;
  116. interrupts = <0 2>; // cpm error interrupt
  117. interrupt-parent = <&Cpm_pic>;
  118. Cpm_pic: pic@930 {
  119. interrupt-controller;
  120. #address-cells = <0>;
  121. #interrupt-cells = <2>;
  122. interrupts = <5 2 0 2>;
  123. interrupt-parent = <&Mpc8xx_pic>;
  124. reg = <930 20>;
  125. built-in;
  126. device_type = "cpm-pic";
  127. compatible = "CPM";
  128. };
  129. smc@a80 {
  130. device_type = "serial";
  131. compatible = "cpm_uart";
  132. model = "SMC";
  133. device-id = <1>;
  134. reg = <a80 10 3e80 40>;
  135. clock-setup = <00ffffff 0>;
  136. rx-clock = <1>;
  137. tx-clock = <1>;
  138. current-speed = <0>;
  139. interrupts = <4 3>;
  140. interrupt-parent = <&Cpm_pic>;
  141. };
  142. smc@a90 {
  143. device_type = "serial";
  144. compatible = "cpm_uart";
  145. model = "SMC";
  146. device-id = <2>;
  147. reg = <a90 20 3f80 40>;
  148. clock-setup = <ff00ffff 90000>;
  149. rx-clock = <2>;
  150. tx-clock = <2>;
  151. current-speed = <0>;
  152. interrupts = <3 3>;
  153. interrupt-parent = <&Cpm_pic>;
  154. };
  155. scc@a40 {
  156. device_type = "network";
  157. compatible = "fs_enet";
  158. model = "SCC";
  159. device-id = <3>;
  160. reg = <a40 18 3e00 80>;
  161. mac-address = [ 00 00 0C 00 03 FD ];
  162. interrupts = <1c 3>;
  163. interrupt-parent = <&Cpm_pic>;
  164. phy-handle = <&Phy2>;
  165. };
  166. };
  167. };
  168. };