mpc8540ads.dts 6.2 KB

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  1. /*
  2. * MPC8540 ADS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8540ADS";
  13. compatible = "MPC8540ADS", "MPC85xxADS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8540@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <8000>; // L1, 32K
  25. i-cache-size = <8000>; // L1, 32K
  26. timebase-frequency = <0>; // 33 MHz, from uboot
  27. bus-frequency = <0>; // 166 MHz
  28. clock-frequency = <0>; // 825 MHz, from uboot
  29. 32-bit;
  30. };
  31. };
  32. memory {
  33. device_type = "memory";
  34. reg = <00000000 08000000>; // 128M at 0x0
  35. };
  36. soc8540@e0000000 {
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. #interrupt-cells = <2>;
  40. device_type = "soc";
  41. ranges = <0 e0000000 00100000>;
  42. reg = <e0000000 00100000>; // CCSRBAR 1M
  43. bus-frequency = <0>;
  44. memory-controller@2000 {
  45. compatible = "fsl,8540-memory-controller";
  46. reg = <2000 1000>;
  47. interrupt-parent = <&mpic>;
  48. interrupts = <12 2>;
  49. };
  50. l2-cache-controller@20000 {
  51. compatible = "fsl,8540-l2-cache-controller";
  52. reg = <20000 1000>;
  53. cache-line-size = <20>; // 32 bytes
  54. cache-size = <40000>; // L2, 256K
  55. interrupt-parent = <&mpic>;
  56. interrupts = <10 2>;
  57. };
  58. i2c@3000 {
  59. device_type = "i2c";
  60. compatible = "fsl-i2c";
  61. reg = <3000 100>;
  62. interrupts = <2b 2>;
  63. interrupt-parent = <&mpic>;
  64. dfsrr;
  65. };
  66. mdio@24520 {
  67. #address-cells = <1>;
  68. #size-cells = <0>;
  69. device_type = "mdio";
  70. compatible = "gianfar";
  71. reg = <24520 20>;
  72. phy0: ethernet-phy@0 {
  73. interrupt-parent = <&mpic>;
  74. interrupts = <5 1>;
  75. reg = <0>;
  76. device_type = "ethernet-phy";
  77. };
  78. phy1: ethernet-phy@1 {
  79. interrupt-parent = <&mpic>;
  80. interrupts = <5 1>;
  81. reg = <1>;
  82. device_type = "ethernet-phy";
  83. };
  84. phy3: ethernet-phy@3 {
  85. interrupt-parent = <&mpic>;
  86. interrupts = <7 1>;
  87. reg = <3>;
  88. device_type = "ethernet-phy";
  89. };
  90. };
  91. ethernet@24000 {
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. device_type = "network";
  95. model = "TSEC";
  96. compatible = "gianfar";
  97. reg = <24000 1000>;
  98. /*
  99. * address is deprecated and will be removed
  100. * in 2.6.25. Only recent versions of
  101. * U-Boot support local-mac-address, however.
  102. */
  103. address = [ 00 00 00 00 00 00 ];
  104. local-mac-address = [ 00 00 00 00 00 00 ];
  105. interrupts = <1d 2 1e 2 22 2>;
  106. interrupt-parent = <&mpic>;
  107. phy-handle = <&phy0>;
  108. };
  109. ethernet@25000 {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. device_type = "network";
  113. model = "TSEC";
  114. compatible = "gianfar";
  115. reg = <25000 1000>;
  116. /*
  117. * address is deprecated and will be removed
  118. * in 2.6.25. Only recent versions of
  119. * U-Boot support local-mac-address, however.
  120. */
  121. address = [ 00 00 00 00 00 00 ];
  122. local-mac-address = [ 00 00 00 00 00 00 ];
  123. interrupts = <23 2 24 2 28 2>;
  124. interrupt-parent = <&mpic>;
  125. phy-handle = <&phy1>;
  126. };
  127. ethernet@26000 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. device_type = "network";
  131. model = "FEC";
  132. compatible = "gianfar";
  133. reg = <26000 1000>;
  134. /*
  135. * address is deprecated and will be removed
  136. * in 2.6.25. Only recent versions of
  137. * U-Boot support local-mac-address, however.
  138. */
  139. address = [ 00 00 00 00 00 00 ];
  140. local-mac-address = [ 00 00 00 00 00 00 ];
  141. interrupts = <29 2>;
  142. interrupt-parent = <&mpic>;
  143. phy-handle = <&phy3>;
  144. };
  145. serial@4500 {
  146. device_type = "serial";
  147. compatible = "ns16550";
  148. reg = <4500 100>; // reg base, size
  149. clock-frequency = <0>; // should we fill in in uboot?
  150. interrupts = <2a 2>;
  151. interrupt-parent = <&mpic>;
  152. };
  153. serial@4600 {
  154. device_type = "serial";
  155. compatible = "ns16550";
  156. reg = <4600 100>; // reg base, size
  157. clock-frequency = <0>; // should we fill in in uboot?
  158. interrupts = <2a 2>;
  159. interrupt-parent = <&mpic>;
  160. };
  161. pci@8000 {
  162. interrupt-map-mask = <f800 0 0 7>;
  163. interrupt-map = <
  164. /* IDSEL 0x02 */
  165. 1000 0 0 1 &mpic 1 1
  166. 1000 0 0 2 &mpic 2 1
  167. 1000 0 0 3 &mpic 3 1
  168. 1000 0 0 4 &mpic 4 1
  169. /* IDSEL 0x03 */
  170. 1800 0 0 1 &mpic 4 1
  171. 1800 0 0 2 &mpic 1 1
  172. 1800 0 0 3 &mpic 2 1
  173. 1800 0 0 4 &mpic 3 1
  174. /* IDSEL 0x04 */
  175. 2000 0 0 1 &mpic 3 1
  176. 2000 0 0 2 &mpic 4 1
  177. 2000 0 0 3 &mpic 1 1
  178. 2000 0 0 4 &mpic 2 1
  179. /* IDSEL 0x05 */
  180. 2800 0 0 1 &mpic 2 1
  181. 2800 0 0 2 &mpic 3 1
  182. 2800 0 0 3 &mpic 4 1
  183. 2800 0 0 4 &mpic 1 1
  184. /* IDSEL 0x0c */
  185. 6000 0 0 1 &mpic 1 1
  186. 6000 0 0 2 &mpic 2 1
  187. 6000 0 0 3 &mpic 3 1
  188. 6000 0 0 4 &mpic 4 1
  189. /* IDSEL 0x0d */
  190. 6800 0 0 1 &mpic 4 1
  191. 6800 0 0 2 &mpic 1 1
  192. 6800 0 0 3 &mpic 2 1
  193. 6800 0 0 4 &mpic 3 1
  194. /* IDSEL 0x0e */
  195. 7000 0 0 1 &mpic 3 1
  196. 7000 0 0 2 &mpic 4 1
  197. 7000 0 0 3 &mpic 1 1
  198. 7000 0 0 4 &mpic 2 1
  199. /* IDSEL 0x0f */
  200. 7800 0 0 1 &mpic 2 1
  201. 7800 0 0 2 &mpic 3 1
  202. 7800 0 0 3 &mpic 4 1
  203. 7800 0 0 4 &mpic 1 1
  204. /* IDSEL 0x12 */
  205. 9000 0 0 1 &mpic 1 1
  206. 9000 0 0 2 &mpic 2 1
  207. 9000 0 0 3 &mpic 3 1
  208. 9000 0 0 4 &mpic 4 1
  209. /* IDSEL 0x13 */
  210. 9800 0 0 1 &mpic 4 1
  211. 9800 0 0 2 &mpic 1 1
  212. 9800 0 0 3 &mpic 2 1
  213. 9800 0 0 4 &mpic 3 1
  214. /* IDSEL 0x14 */
  215. a000 0 0 1 &mpic 3 1
  216. a000 0 0 2 &mpic 4 1
  217. a000 0 0 3 &mpic 1 1
  218. a000 0 0 4 &mpic 2 1
  219. /* IDSEL 0x15 */
  220. a800 0 0 1 &mpic 2 1
  221. a800 0 0 2 &mpic 3 1
  222. a800 0 0 3 &mpic 4 1
  223. a800 0 0 4 &mpic 1 1>;
  224. interrupt-parent = <&mpic>;
  225. interrupts = <18 2>;
  226. bus-range = <0 0>;
  227. ranges = <02000000 0 80000000 80000000 0 20000000
  228. 01000000 0 00000000 e2000000 0 00100000>;
  229. clock-frequency = <3f940aa>;
  230. #interrupt-cells = <1>;
  231. #size-cells = <2>;
  232. #address-cells = <3>;
  233. reg = <8000 1000>;
  234. compatible = "85xx";
  235. device_type = "pci";
  236. };
  237. mpic: pic@40000 {
  238. clock-frequency = <0>;
  239. interrupt-controller;
  240. #address-cells = <0>;
  241. #interrupt-cells = <2>;
  242. reg = <40000 40000>;
  243. built-in;
  244. compatible = "chrp,open-pic";
  245. device_type = "open-pic";
  246. big-endian;
  247. };
  248. };
  249. };