mpc832x_mds.dts 7.7 KB

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  1. /*
  2. * MPC8323E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323EMDS";
  13. compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8323@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. 32-bit;
  30. };
  31. };
  32. memory {
  33. device_type = "memory";
  34. reg = <00000000 08000000>;
  35. };
  36. bcsr@f8000000 {
  37. device_type = "board-control";
  38. reg = <f8000000 8000>;
  39. };
  40. soc8323@e0000000 {
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. #interrupt-cells = <2>;
  44. device_type = "soc";
  45. ranges = <0 e0000000 00100000>;
  46. reg = <e0000000 00000200>;
  47. bus-frequency = <7DE2900>;
  48. wdt@200 {
  49. device_type = "watchdog";
  50. compatible = "mpc83xx_wdt";
  51. reg = <200 100>;
  52. };
  53. i2c@3000 {
  54. device_type = "i2c";
  55. compatible = "fsl-i2c";
  56. reg = <3000 100>;
  57. interrupts = <e 8>;
  58. interrupt-parent = < &ipic >;
  59. dfsrr;
  60. };
  61. serial@4500 {
  62. device_type = "serial";
  63. compatible = "ns16550";
  64. reg = <4500 100>;
  65. clock-frequency = <0>;
  66. interrupts = <9 8>;
  67. interrupt-parent = < &ipic >;
  68. };
  69. serial@4600 {
  70. device_type = "serial";
  71. compatible = "ns16550";
  72. reg = <4600 100>;
  73. clock-frequency = <0>;
  74. interrupts = <a 8>;
  75. interrupt-parent = < &ipic >;
  76. };
  77. crypto@30000 {
  78. device_type = "crypto";
  79. model = "SEC2";
  80. compatible = "talitos";
  81. reg = <30000 7000>;
  82. interrupts = <b 8>;
  83. interrupt-parent = < &ipic >;
  84. /* Rev. 2.2 */
  85. num-channels = <1>;
  86. channel-fifo-len = <18>;
  87. exec-units-mask = <0000004c>;
  88. descriptor-types-mask = <0122003f>;
  89. };
  90. pci@8500 {
  91. interrupt-map-mask = <f800 0 0 7>;
  92. interrupt-map = <
  93. /* IDSEL 0x11 AD17 */
  94. 8800 0 0 1 &ipic 14 8
  95. 8800 0 0 2 &ipic 15 8
  96. 8800 0 0 3 &ipic 16 8
  97. 8800 0 0 4 &ipic 17 8
  98. /* IDSEL 0x12 AD18 */
  99. 9000 0 0 1 &ipic 16 8
  100. 9000 0 0 2 &ipic 17 8
  101. 9000 0 0 3 &ipic 14 8
  102. 9000 0 0 4 &ipic 15 8
  103. /* IDSEL 0x13 AD19 */
  104. 9800 0 0 1 &ipic 17 8
  105. 9800 0 0 2 &ipic 14 8
  106. 9800 0 0 3 &ipic 15 8
  107. 9800 0 0 4 &ipic 16 8
  108. /* IDSEL 0x15 AD21*/
  109. a800 0 0 1 &ipic 14 8
  110. a800 0 0 2 &ipic 15 8
  111. a800 0 0 3 &ipic 16 8
  112. a800 0 0 4 &ipic 17 8
  113. /* IDSEL 0x16 AD22*/
  114. b000 0 0 1 &ipic 17 8
  115. b000 0 0 2 &ipic 14 8
  116. b000 0 0 3 &ipic 15 8
  117. b000 0 0 4 &ipic 16 8
  118. /* IDSEL 0x17 AD23*/
  119. b800 0 0 1 &ipic 16 8
  120. b800 0 0 2 &ipic 17 8
  121. b800 0 0 3 &ipic 14 8
  122. b800 0 0 4 &ipic 15 8
  123. /* IDSEL 0x18 AD24*/
  124. c000 0 0 1 &ipic 15 8
  125. c000 0 0 2 &ipic 16 8
  126. c000 0 0 3 &ipic 17 8
  127. c000 0 0 4 &ipic 14 8>;
  128. interrupt-parent = < &ipic >;
  129. interrupts = <42 8>;
  130. bus-range = <0 0>;
  131. ranges = <02000000 0 90000000 90000000 0 10000000
  132. 42000000 0 80000000 80000000 0 10000000
  133. 01000000 0 00000000 d0000000 0 00100000>;
  134. clock-frequency = <0>;
  135. #interrupt-cells = <1>;
  136. #size-cells = <2>;
  137. #address-cells = <3>;
  138. reg = <8500 100>;
  139. compatible = "83xx";
  140. device_type = "pci";
  141. };
  142. ipic: pic@700 {
  143. interrupt-controller;
  144. #address-cells = <0>;
  145. #interrupt-cells = <2>;
  146. reg = <700 100>;
  147. built-in;
  148. device_type = "ipic";
  149. };
  150. par_io@1400 {
  151. reg = <1400 100>;
  152. device_type = "par_io";
  153. num-ports = <7>;
  154. pio3: ucc_pin@03 {
  155. pio-map = <
  156. /* port pin dir open_drain assignment has_irq */
  157. 3 4 3 0 2 0 /* MDIO */
  158. 3 5 1 0 2 0 /* MDC */
  159. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  160. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  161. 1 1 1 0 1 0 /* TxD1 */
  162. 1 0 1 0 1 0 /* TxD0 */
  163. 1 1 1 0 1 0 /* TxD1 */
  164. 1 2 1 0 1 0 /* TxD2 */
  165. 1 3 1 0 1 0 /* TxD3 */
  166. 1 4 2 0 1 0 /* RxD0 */
  167. 1 5 2 0 1 0 /* RxD1 */
  168. 1 6 2 0 1 0 /* RxD2 */
  169. 1 7 2 0 1 0 /* RxD3 */
  170. 1 8 2 0 1 0 /* RX_ER */
  171. 1 9 1 0 1 0 /* TX_ER */
  172. 1 a 2 0 1 0 /* RX_DV */
  173. 1 b 2 0 1 0 /* COL */
  174. 1 c 1 0 1 0 /* TX_EN */
  175. 1 d 2 0 1 0>;/* CRS */
  176. };
  177. pio4: ucc_pin@04 {
  178. pio-map = <
  179. /* port pin dir open_drain assignment has_irq */
  180. 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
  181. 3 6 2 0 1 0 /* TX_CLK (CLK8) */
  182. 1 12 1 0 1 0 /* TxD0 */
  183. 1 13 1 0 1 0 /* TxD1 */
  184. 1 14 1 0 1 0 /* TxD2 */
  185. 1 15 1 0 1 0 /* TxD3 */
  186. 1 16 2 0 1 0 /* RxD0 */
  187. 1 17 2 0 1 0 /* RxD1 */
  188. 1 18 2 0 1 0 /* RxD2 */
  189. 1 19 2 0 1 0 /* RxD3 */
  190. 1 1a 2 0 1 0 /* RX_ER */
  191. 1 1b 1 0 1 0 /* TX_ER */
  192. 1 1c 2 0 1 0 /* RX_DV */
  193. 1 1d 2 0 1 0 /* COL */
  194. 1 1e 1 0 1 0 /* TX_EN */
  195. 1 1f 2 0 1 0>;/* CRS */
  196. };
  197. };
  198. };
  199. qe@e0100000 {
  200. #address-cells = <1>;
  201. #size-cells = <1>;
  202. device_type = "qe";
  203. model = "QE";
  204. ranges = <0 e0100000 00100000>;
  205. reg = <e0100000 480>;
  206. brg-frequency = <0>;
  207. bus-frequency = <BCD3D80>;
  208. muram@10000 {
  209. device_type = "muram";
  210. ranges = <0 00010000 00004000>;
  211. data-only@0 {
  212. reg = <0 4000>;
  213. };
  214. };
  215. spi@4c0 {
  216. device_type = "spi";
  217. compatible = "fsl_spi";
  218. reg = <4c0 40>;
  219. interrupts = <2>;
  220. interrupt-parent = < &qeic >;
  221. mode = "cpu";
  222. };
  223. spi@500 {
  224. device_type = "spi";
  225. compatible = "fsl_spi";
  226. reg = <500 40>;
  227. interrupts = <1>;
  228. interrupt-parent = < &qeic >;
  229. mode = "cpu";
  230. };
  231. usb@6c0 {
  232. device_type = "usb";
  233. compatible = "qe_udc";
  234. reg = <6c0 40 8B00 100>;
  235. interrupts = <b>;
  236. interrupt-parent = < &qeic >;
  237. mode = "slave";
  238. };
  239. ucc@2200 {
  240. device_type = "network";
  241. compatible = "ucc_geth";
  242. model = "UCC";
  243. device-id = <3>;
  244. reg = <2200 200>;
  245. interrupts = <22>;
  246. interrupt-parent = < &qeic >;
  247. /*
  248. * mac-address is deprecated and will be removed
  249. * in 2.6.25. Only recent versions of
  250. * U-Boot support local-mac-address, however.
  251. */
  252. mac-address = [ 00 00 00 00 00 00 ];
  253. local-mac-address = [ 00 00 00 00 00 00 ];
  254. rx-clock = <19>;
  255. tx-clock = <1a>;
  256. phy-handle = < &phy3 >;
  257. pio-handle = < &pio3 >;
  258. };
  259. ucc@3200 {
  260. device_type = "network";
  261. compatible = "ucc_geth";
  262. model = "UCC";
  263. device-id = <4>;
  264. reg = <3000 200>;
  265. interrupts = <23>;
  266. interrupt-parent = < &qeic >;
  267. /*
  268. * mac-address is deprecated and will be removed
  269. * in 2.6.25. Only recent versions of
  270. * U-Boot support local-mac-address, however.
  271. */
  272. mac-address = [ 00 00 00 00 00 00 ];
  273. local-mac-address = [ 00 00 00 00 00 00 ];
  274. rx-clock = <17>;
  275. tx-clock = <18>;
  276. phy-handle = < &phy4 >;
  277. pio-handle = < &pio4 >;
  278. };
  279. mdio@2320 {
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. reg = <2320 18>;
  283. device_type = "mdio";
  284. compatible = "ucc_geth_phy";
  285. phy3: ethernet-phy@03 {
  286. interrupt-parent = < &ipic >;
  287. interrupts = <11 8>;
  288. reg = <3>;
  289. device_type = "ethernet-phy";
  290. };
  291. phy4: ethernet-phy@04 {
  292. interrupt-parent = < &ipic >;
  293. interrupts = <12 8>;
  294. reg = <4>;
  295. device_type = "ethernet-phy";
  296. };
  297. };
  298. qeic: qeic@80 {
  299. interrupt-controller;
  300. device_type = "qeic";
  301. #address-cells = <0>;
  302. #interrupt-cells = <1>;
  303. reg = <80 80>;
  304. built-in;
  305. big-endian;
  306. interrupts = <20 8 21 8>; //high:32 low:33
  307. interrupt-parent = < &ipic >;
  308. };
  309. };
  310. };