mpc8272ads.dts 8.2 KB

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  1. /*
  2. * MPC8272 ADS Device Tree Source
  3. *
  4. * Copyright 2005 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8272ADS";
  13. compatible = "MPC8260ADS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8272@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. 32-bit;
  30. };
  31. };
  32. pci_pic: interrupt-controller@f8200000 {
  33. #address-cells = <0>;
  34. #interrupt-cells = <2>;
  35. interrupt-controller;
  36. reg = <f8200000 f8200004>;
  37. built-in;
  38. device_type = "pci-pic";
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <00000000 4000000 f4500000 00000020>;
  43. };
  44. chosen {
  45. name = "chosen";
  46. linux,platform = <0>;
  47. interrupt-controller = <&Cpm_pic>;
  48. };
  49. soc8272@f0000000 {
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. #interrupt-cells = <2>;
  53. device_type = "soc";
  54. ranges = <00000000 f0000000 00053000>;
  55. reg = <f0000000 10000>;
  56. mdio@0 {
  57. device_type = "mdio";
  58. compatible = "fs_enet";
  59. reg = <0 0>;
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. phy0:ethernet-phy@0 {
  63. interrupt-parent = <&Cpm_pic>;
  64. interrupts = <17 4>;
  65. reg = <0>;
  66. bitbang = [ 12 12 13 02 02 01 ];
  67. device_type = "ethernet-phy";
  68. };
  69. phy1:ethernet-phy@1 {
  70. interrupt-parent = <&Cpm_pic>;
  71. interrupts = <17 4>;
  72. bitbang = [ 12 12 13 02 02 01 ];
  73. reg = <3>;
  74. device_type = "ethernet-phy";
  75. };
  76. };
  77. ethernet@24000 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. device_type = "network";
  81. device-id = <1>;
  82. compatible = "fs_enet";
  83. model = "FCC";
  84. reg = <11300 20 8400 100 11380 30>;
  85. mac-address = [ 00 11 2F 99 43 54 ];
  86. interrupts = <20 2>;
  87. interrupt-parent = <&Cpm_pic>;
  88. phy-handle = <&Phy0>;
  89. rx-clock = <13>;
  90. tx-clock = <12>;
  91. };
  92. ethernet@25000 {
  93. device_type = "network";
  94. device-id = <2>;
  95. compatible = "fs_enet";
  96. model = "FCC";
  97. reg = <11320 20 8500 100 113b0 30>;
  98. mac-address = [ 00 11 2F 99 44 54 ];
  99. interrupts = <21 2>;
  100. interrupt-parent = <&Cpm_pic>;
  101. phy-handle = <&Phy1>;
  102. rx-clock = <17>;
  103. tx-clock = <18>;
  104. };
  105. cpm@f0000000 {
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. #interrupt-cells = <2>;
  109. device_type = "cpm";
  110. model = "CPM2";
  111. ranges = <00000000 00000000 20000>;
  112. reg = <0 20000>;
  113. command-proc = <119c0>;
  114. brg-frequency = <17D7840>;
  115. cpm_clk = <BEBC200>;
  116. scc@11a00 {
  117. device_type = "serial";
  118. compatible = "cpm_uart";
  119. model = "SCC";
  120. device-id = <1>;
  121. reg = <11a00 20 8000 100>;
  122. current-speed = <1c200>;
  123. interrupts = <28 2>;
  124. interrupt-parent = <&Cpm_pic>;
  125. clock-setup = <0 00ffffff>;
  126. rx-clock = <1>;
  127. tx-clock = <1>;
  128. };
  129. scc@11a60 {
  130. device_type = "serial";
  131. compatible = "cpm_uart";
  132. model = "SCC";
  133. device-id = <4>;
  134. reg = <11a60 20 8300 100>;
  135. current-speed = <1c200>;
  136. interrupts = <2b 2>;
  137. interrupt-parent = <&Cpm_pic>;
  138. clock-setup = <1b ffffff00>;
  139. rx-clock = <4>;
  140. tx-clock = <4>;
  141. };
  142. };
  143. cpm_pic:interrupt-controller@10c00 {
  144. #address-cells = <0>;
  145. #interrupt-cells = <2>;
  146. interrupt-controller;
  147. reg = <10c00 80>;
  148. built-in;
  149. device_type = "cpm-pic";
  150. compatible = "CPM2";
  151. };
  152. pci@0500 {
  153. #interrupt-cells = <1>;
  154. #size-cells = <2>;
  155. #address-cells = <3>;
  156. compatible = "8272";
  157. device_type = "pci";
  158. reg = <10430 4dc>;
  159. clock-frequency = <3f940aa>;
  160. interrupt-map-mask = <f800 0 0 7>;
  161. interrupt-map = <
  162. /* IDSEL 0x16 */
  163. b000 0 0 1 f8200000 40 8
  164. b000 0 0 2 f8200000 41 8
  165. b000 0 0 3 f8200000 42 8
  166. b000 0 0 4 f8200000 43 8
  167. /* IDSEL 0x17 */
  168. b800 0 0 1 f8200000 43 8
  169. b800 0 0 2 f8200000 40 8
  170. b800 0 0 3 f8200000 41 8
  171. b800 0 0 4 f8200000 42 8
  172. /* IDSEL 0x18 */
  173. c000 0 0 1 f8200000 42 8
  174. c000 0 0 2 f8200000 43 8
  175. c000 0 0 3 f8200000 40 8
  176. c000 0 0 4 f8200000 41 8>;
  177. interrupt-parent = <&Cpm_pic>;
  178. interrupts = <14 8>;
  179. bus-range = <0 0>;
  180. ranges = <02000000 0 80000000 80000000 0 40000000
  181. 01000000 0 00000000 f6000000 0 02000000>;
  182. };
  183. /* May need to remove if on a part without crypto engine */
  184. crypto@30000 {
  185. device_type = "crypto";
  186. model = "SEC2";
  187. compatible = "talitos";
  188. reg = <30000 10000>;
  189. interrupts = <b 2>;
  190. interrupt-parent = <&Cpm_pic>;
  191. num-channels = <4>;
  192. channel-fifo-len = <18>;
  193. exec-units-mask = <0000007e>;
  194. /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
  195. descriptor-types-mask = <01010ebf>;
  196. };
  197. };
  198. };