setup.c 15 KB

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  1. /*
  2. * linux/arch/mips/txx9/generic/setup.c
  3. *
  4. * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
  5. * and RBTX49xx patch from CELF patch archive.
  6. *
  7. * 2003-2005 (c) MontaVista Software, Inc.
  8. * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  9. *
  10. * This file is subject to the terms and conditions of the GNU General Public
  11. * License. See the file "COPYING" in the main directory of this archive
  12. * for more details.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/types.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/string.h>
  19. #include <linux/module.h>
  20. #include <linux/clk.h>
  21. #include <linux/err.h>
  22. #include <linux/gpio.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/serial_core.h>
  25. #include <linux/mtd/physmap.h>
  26. #include <asm/bootinfo.h>
  27. #include <asm/time.h>
  28. #include <asm/reboot.h>
  29. #include <asm/r4kcache.h>
  30. #include <asm/txx9/generic.h>
  31. #include <asm/txx9/pci.h>
  32. #include <asm/txx9tmr.h>
  33. #ifdef CONFIG_CPU_TX49XX
  34. #include <asm/txx9/tx4938.h>
  35. #endif
  36. /* EBUSC settings of TX4927, etc. */
  37. struct resource txx9_ce_res[8];
  38. static char txx9_ce_res_name[8][4]; /* "CEn" */
  39. /* pcode, internal register */
  40. unsigned int txx9_pcode;
  41. char txx9_pcode_str[8];
  42. static struct resource txx9_reg_res = {
  43. .name = txx9_pcode_str,
  44. .flags = IORESOURCE_MEM,
  45. };
  46. void __init
  47. txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
  48. {
  49. int i;
  50. for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
  51. sprintf(txx9_ce_res_name[i], "CE%d", i);
  52. txx9_ce_res[i].flags = IORESOURCE_MEM;
  53. txx9_ce_res[i].name = txx9_ce_res_name[i];
  54. }
  55. txx9_pcode = pcode;
  56. sprintf(txx9_pcode_str, "TX%x", pcode);
  57. if (base) {
  58. txx9_reg_res.start = base & 0xfffffffffULL;
  59. txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
  60. request_resource(&iomem_resource, &txx9_reg_res);
  61. }
  62. }
  63. /* clocks */
  64. unsigned int txx9_master_clock;
  65. unsigned int txx9_cpu_clock;
  66. unsigned int txx9_gbus_clock;
  67. #ifdef CONFIG_CPU_TX39XX
  68. /* don't enable by default - see errata */
  69. int txx9_ccfg_toeon __initdata;
  70. #else
  71. int txx9_ccfg_toeon __initdata = 1;
  72. #endif
  73. /* Minimum CLK support */
  74. struct clk *clk_get(struct device *dev, const char *id)
  75. {
  76. if (!strcmp(id, "spi-baseclk"))
  77. return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);
  78. if (!strcmp(id, "imbus_clk"))
  79. return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
  80. return ERR_PTR(-ENOENT);
  81. }
  82. EXPORT_SYMBOL(clk_get);
  83. int clk_enable(struct clk *clk)
  84. {
  85. return 0;
  86. }
  87. EXPORT_SYMBOL(clk_enable);
  88. void clk_disable(struct clk *clk)
  89. {
  90. }
  91. EXPORT_SYMBOL(clk_disable);
  92. unsigned long clk_get_rate(struct clk *clk)
  93. {
  94. return (unsigned long)clk;
  95. }
  96. EXPORT_SYMBOL(clk_get_rate);
  97. void clk_put(struct clk *clk)
  98. {
  99. }
  100. EXPORT_SYMBOL(clk_put);
  101. /* GPIO support */
  102. #ifdef CONFIG_GENERIC_GPIO
  103. int gpio_to_irq(unsigned gpio)
  104. {
  105. return -EINVAL;
  106. }
  107. EXPORT_SYMBOL(gpio_to_irq);
  108. int irq_to_gpio(unsigned irq)
  109. {
  110. return -EINVAL;
  111. }
  112. EXPORT_SYMBOL(irq_to_gpio);
  113. #endif
  114. #define BOARD_VEC(board) extern struct txx9_board_vec board;
  115. #include <asm/txx9/boards.h>
  116. #undef BOARD_VEC
  117. struct txx9_board_vec *txx9_board_vec __initdata;
  118. static char txx9_system_type[32];
  119. static struct txx9_board_vec *board_vecs[] __initdata = {
  120. #define BOARD_VEC(board) &board,
  121. #include <asm/txx9/boards.h>
  122. #undef BOARD_VEC
  123. };
  124. static struct txx9_board_vec *__init find_board_byname(const char *name)
  125. {
  126. int i;
  127. /* search board_vecs table */
  128. for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
  129. if (strstr(board_vecs[i]->system, name))
  130. return board_vecs[i];
  131. }
  132. return NULL;
  133. }
  134. static void __init prom_init_cmdline(void)
  135. {
  136. int argc = (int)fw_arg0;
  137. int *argv32 = (int *)fw_arg1;
  138. int i; /* Always ignore the "-c" at argv[0] */
  139. char builtin[CL_SIZE];
  140. /* ignore all built-in args if any f/w args given */
  141. /*
  142. * But if built-in strings was started with '+', append them
  143. * to command line args. If built-in was started with '-',
  144. * ignore all f/w args.
  145. */
  146. builtin[0] = '\0';
  147. if (arcs_cmdline[0] == '+')
  148. strcpy(builtin, arcs_cmdline + 1);
  149. else if (arcs_cmdline[0] == '-') {
  150. strcpy(builtin, arcs_cmdline + 1);
  151. argc = 0;
  152. } else if (argc <= 1)
  153. strcpy(builtin, arcs_cmdline);
  154. arcs_cmdline[0] = '\0';
  155. for (i = 1; i < argc; i++) {
  156. char *str = (char *)(long)argv32[i];
  157. if (i != 1)
  158. strcat(arcs_cmdline, " ");
  159. if (strchr(str, ' ')) {
  160. strcat(arcs_cmdline, "\"");
  161. strcat(arcs_cmdline, str);
  162. strcat(arcs_cmdline, "\"");
  163. } else
  164. strcat(arcs_cmdline, str);
  165. }
  166. /* append saved builtin args */
  167. if (builtin[0]) {
  168. if (arcs_cmdline[0])
  169. strcat(arcs_cmdline, " ");
  170. strcat(arcs_cmdline, builtin);
  171. }
  172. }
  173. static int txx9_ic_disable __initdata;
  174. static int txx9_dc_disable __initdata;
  175. #if defined(CONFIG_CPU_TX49XX)
  176. /* flush all cache on very early stage (before 4k_cache_init) */
  177. static void __init early_flush_dcache(void)
  178. {
  179. unsigned int conf = read_c0_config();
  180. unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
  181. unsigned int linesz = 32;
  182. unsigned long addr, end;
  183. end = INDEX_BASE + dc_size / 4;
  184. /* 4way, waybit=0 */
  185. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  186. cache_op(Index_Writeback_Inv_D, addr | 0);
  187. cache_op(Index_Writeback_Inv_D, addr | 1);
  188. cache_op(Index_Writeback_Inv_D, addr | 2);
  189. cache_op(Index_Writeback_Inv_D, addr | 3);
  190. }
  191. }
  192. static void __init txx9_cache_fixup(void)
  193. {
  194. unsigned int conf;
  195. conf = read_c0_config();
  196. /* flush and disable */
  197. if (txx9_ic_disable) {
  198. conf |= TX49_CONF_IC;
  199. write_c0_config(conf);
  200. }
  201. if (txx9_dc_disable) {
  202. early_flush_dcache();
  203. conf |= TX49_CONF_DC;
  204. write_c0_config(conf);
  205. }
  206. /* enable cache */
  207. conf = read_c0_config();
  208. if (!txx9_ic_disable)
  209. conf &= ~TX49_CONF_IC;
  210. if (!txx9_dc_disable)
  211. conf &= ~TX49_CONF_DC;
  212. write_c0_config(conf);
  213. if (conf & TX49_CONF_IC)
  214. pr_info("TX49XX I-Cache disabled.\n");
  215. if (conf & TX49_CONF_DC)
  216. pr_info("TX49XX D-Cache disabled.\n");
  217. }
  218. #elif defined(CONFIG_CPU_TX39XX)
  219. /* flush all cache on very early stage (before tx39_cache_init) */
  220. static void __init early_flush_dcache(void)
  221. {
  222. unsigned int conf = read_c0_config();
  223. unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
  224. TX39_CONF_DCS_SHIFT));
  225. unsigned int linesz = 16;
  226. unsigned long addr, end;
  227. end = INDEX_BASE + dc_size / 2;
  228. /* 2way, waybit=0 */
  229. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  230. cache_op(Index_Writeback_Inv_D, addr | 0);
  231. cache_op(Index_Writeback_Inv_D, addr | 1);
  232. }
  233. }
  234. static void __init txx9_cache_fixup(void)
  235. {
  236. unsigned int conf;
  237. conf = read_c0_config();
  238. /* flush and disable */
  239. if (txx9_ic_disable) {
  240. conf &= ~TX39_CONF_ICE;
  241. write_c0_config(conf);
  242. }
  243. if (txx9_dc_disable) {
  244. early_flush_dcache();
  245. conf &= ~TX39_CONF_DCE;
  246. write_c0_config(conf);
  247. }
  248. /* enable cache */
  249. conf = read_c0_config();
  250. if (!txx9_ic_disable)
  251. conf |= TX39_CONF_ICE;
  252. if (!txx9_dc_disable)
  253. conf |= TX39_CONF_DCE;
  254. write_c0_config(conf);
  255. if (!(conf & TX39_CONF_ICE))
  256. pr_info("TX39XX I-Cache disabled.\n");
  257. if (!(conf & TX39_CONF_DCE))
  258. pr_info("TX39XX D-Cache disabled.\n");
  259. }
  260. #else
  261. static inline void txx9_cache_fixup(void)
  262. {
  263. }
  264. #endif
  265. static void __init preprocess_cmdline(void)
  266. {
  267. char cmdline[CL_SIZE];
  268. char *s;
  269. strcpy(cmdline, arcs_cmdline);
  270. s = cmdline;
  271. arcs_cmdline[0] = '\0';
  272. while (s && *s) {
  273. char *str = strsep(&s, " ");
  274. if (strncmp(str, "board=", 6) == 0) {
  275. txx9_board_vec = find_board_byname(str + 6);
  276. continue;
  277. } else if (strncmp(str, "masterclk=", 10) == 0) {
  278. unsigned long val;
  279. if (strict_strtoul(str + 10, 10, &val) == 0)
  280. txx9_master_clock = val;
  281. continue;
  282. } else if (strcmp(str, "icdisable") == 0) {
  283. txx9_ic_disable = 1;
  284. continue;
  285. } else if (strcmp(str, "dcdisable") == 0) {
  286. txx9_dc_disable = 1;
  287. continue;
  288. } else if (strcmp(str, "toeoff") == 0) {
  289. txx9_ccfg_toeon = 0;
  290. continue;
  291. } else if (strcmp(str, "toeon") == 0) {
  292. txx9_ccfg_toeon = 1;
  293. continue;
  294. }
  295. if (arcs_cmdline[0])
  296. strcat(arcs_cmdline, " ");
  297. strcat(arcs_cmdline, str);
  298. }
  299. txx9_cache_fixup();
  300. }
  301. static void __init select_board(void)
  302. {
  303. const char *envstr;
  304. /* first, determine by "board=" argument in preprocess_cmdline() */
  305. if (txx9_board_vec)
  306. return;
  307. /* next, determine by "board" envvar */
  308. envstr = prom_getenv("board");
  309. if (envstr) {
  310. txx9_board_vec = find_board_byname(envstr);
  311. if (txx9_board_vec)
  312. return;
  313. }
  314. /* select "default" board */
  315. #ifdef CONFIG_CPU_TX39XX
  316. txx9_board_vec = &jmr3927_vec;
  317. #endif
  318. #ifdef CONFIG_CPU_TX49XX
  319. switch (TX4938_REV_PCODE()) {
  320. #ifdef CONFIG_TOSHIBA_RBTX4927
  321. case 0x4927:
  322. txx9_board_vec = &rbtx4927_vec;
  323. break;
  324. case 0x4937:
  325. txx9_board_vec = &rbtx4937_vec;
  326. break;
  327. #endif
  328. #ifdef CONFIG_TOSHIBA_RBTX4938
  329. case 0x4938:
  330. txx9_board_vec = &rbtx4938_vec;
  331. break;
  332. #endif
  333. }
  334. #endif
  335. }
  336. void __init prom_init(void)
  337. {
  338. prom_init_cmdline();
  339. preprocess_cmdline();
  340. select_board();
  341. strcpy(txx9_system_type, txx9_board_vec->system);
  342. txx9_board_vec->prom_init();
  343. }
  344. void __init prom_free_prom_memory(void)
  345. {
  346. }
  347. const char *get_system_type(void)
  348. {
  349. return txx9_system_type;
  350. }
  351. char * __init prom_getcmdline(void)
  352. {
  353. return &(arcs_cmdline[0]);
  354. }
  355. const char *__init prom_getenv(const char *name)
  356. {
  357. const s32 *str = (const s32 *)fw_arg2;
  358. if (!str)
  359. return NULL;
  360. /* YAMON style ("name", "value" pairs) */
  361. while (str[0] && str[1]) {
  362. if (!strcmp((const char *)(unsigned long)str[0], name))
  363. return (const char *)(unsigned long)str[1];
  364. str += 2;
  365. }
  366. return NULL;
  367. }
  368. static void __noreturn txx9_machine_halt(void)
  369. {
  370. local_irq_disable();
  371. clear_c0_status(ST0_IM);
  372. while (1) {
  373. if (cpu_wait) {
  374. (*cpu_wait)();
  375. if (cpu_has_counter) {
  376. /*
  377. * Clear counter interrupt while it
  378. * breaks WAIT instruction even if
  379. * masked.
  380. */
  381. write_c0_compare(0);
  382. }
  383. }
  384. }
  385. }
  386. /* Watchdog support */
  387. void __init txx9_wdt_init(unsigned long base)
  388. {
  389. struct resource res = {
  390. .start = base,
  391. .end = base + 0x100 - 1,
  392. .flags = IORESOURCE_MEM,
  393. };
  394. platform_device_register_simple("txx9wdt", -1, &res, 1);
  395. }
  396. void txx9_wdt_now(unsigned long base)
  397. {
  398. struct txx9_tmr_reg __iomem *tmrptr =
  399. ioremap(base, sizeof(struct txx9_tmr_reg));
  400. /* disable watch dog timer */
  401. __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
  402. __raw_writel(0, &tmrptr->tcr);
  403. /* kick watchdog */
  404. __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
  405. __raw_writel(1, &tmrptr->cpra); /* immediate */
  406. __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
  407. &tmrptr->tcr);
  408. }
  409. /* SPI support */
  410. void __init txx9_spi_init(int busid, unsigned long base, int irq)
  411. {
  412. struct resource res[] = {
  413. {
  414. .start = base,
  415. .end = base + 0x20 - 1,
  416. .flags = IORESOURCE_MEM,
  417. }, {
  418. .start = irq,
  419. .flags = IORESOURCE_IRQ,
  420. },
  421. };
  422. platform_device_register_simple("spi_txx9", busid,
  423. res, ARRAY_SIZE(res));
  424. }
  425. void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
  426. {
  427. struct platform_device *pdev =
  428. platform_device_alloc("tc35815-mac", id);
  429. if (!pdev ||
  430. platform_device_add_data(pdev, ethaddr, 6) ||
  431. platform_device_add(pdev))
  432. platform_device_put(pdev);
  433. }
  434. void __init txx9_sio_init(unsigned long baseaddr, int irq,
  435. unsigned int line, unsigned int sclk, int nocts)
  436. {
  437. #ifdef CONFIG_SERIAL_TXX9
  438. struct uart_port req;
  439. memset(&req, 0, sizeof(req));
  440. req.line = line;
  441. req.iotype = UPIO_MEM;
  442. req.membase = ioremap(baseaddr, 0x24);
  443. req.mapbase = baseaddr;
  444. req.irq = irq;
  445. if (!nocts)
  446. req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
  447. if (sclk) {
  448. req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
  449. req.uartclk = sclk;
  450. } else
  451. req.uartclk = TXX9_IMCLK;
  452. early_serial_txx9_setup(&req);
  453. #endif /* CONFIG_SERIAL_TXX9 */
  454. }
  455. #ifdef CONFIG_EARLY_PRINTK
  456. static void __init null_prom_putchar(char c)
  457. {
  458. }
  459. void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar;
  460. void __init prom_putchar(char c)
  461. {
  462. txx9_prom_putchar(c);
  463. }
  464. static void __iomem *early_txx9_sio_port;
  465. static void __init early_txx9_sio_putchar(char c)
  466. {
  467. #define TXX9_SICISR 0x0c
  468. #define TXX9_SITFIFO 0x1c
  469. #define TXX9_SICISR_TXALS 0x00000002
  470. while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
  471. TXX9_SICISR_TXALS))
  472. ;
  473. __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
  474. }
  475. void __init txx9_sio_putchar_init(unsigned long baseaddr)
  476. {
  477. early_txx9_sio_port = ioremap(baseaddr, 0x24);
  478. txx9_prom_putchar = early_txx9_sio_putchar;
  479. }
  480. #endif /* CONFIG_EARLY_PRINTK */
  481. /* wrappers */
  482. void __init plat_mem_setup(void)
  483. {
  484. ioport_resource.start = 0;
  485. ioport_resource.end = ~0UL; /* no limit */
  486. iomem_resource.start = 0;
  487. iomem_resource.end = ~0UL; /* no limit */
  488. /* fallback restart/halt routines */
  489. _machine_restart = (void (*)(char *))txx9_machine_halt;
  490. _machine_halt = txx9_machine_halt;
  491. pm_power_off = txx9_machine_halt;
  492. #ifdef CONFIG_PCI
  493. pcibios_plat_setup = txx9_pcibios_setup;
  494. #endif
  495. txx9_board_vec->mem_setup();
  496. }
  497. void __init arch_init_irq(void)
  498. {
  499. txx9_board_vec->irq_setup();
  500. }
  501. void __init plat_time_init(void)
  502. {
  503. #ifdef CONFIG_CPU_TX49XX
  504. mips_hpt_frequency = txx9_cpu_clock / 2;
  505. #endif
  506. txx9_board_vec->time_init();
  507. }
  508. static int __init _txx9_arch_init(void)
  509. {
  510. if (txx9_board_vec->arch_init)
  511. txx9_board_vec->arch_init();
  512. return 0;
  513. }
  514. arch_initcall(_txx9_arch_init);
  515. static int __init _txx9_device_init(void)
  516. {
  517. if (txx9_board_vec->device_init)
  518. txx9_board_vec->device_init();
  519. return 0;
  520. }
  521. device_initcall(_txx9_device_init);
  522. int (*txx9_irq_dispatch)(int pending);
  523. asmlinkage void plat_irq_dispatch(void)
  524. {
  525. int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  526. int irq = txx9_irq_dispatch(pending);
  527. if (likely(irq >= 0))
  528. do_IRQ(irq);
  529. else
  530. spurious_interrupt();
  531. }
  532. /* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
  533. #ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
  534. static unsigned long __swizzle_addr_none(unsigned long port)
  535. {
  536. return port;
  537. }
  538. unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
  539. EXPORT_SYMBOL(__swizzle_addr_b);
  540. #endif
  541. void __init txx9_physmap_flash_init(int no, unsigned long addr,
  542. unsigned long size,
  543. const struct physmap_flash_data *pdata)
  544. {
  545. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  546. struct resource res = {
  547. .start = addr,
  548. .end = addr + size - 1,
  549. .flags = IORESOURCE_MEM,
  550. };
  551. struct platform_device *pdev;
  552. #ifdef CONFIG_MTD_PARTITIONS
  553. static struct mtd_partition parts[2];
  554. struct physmap_flash_data pdata_part;
  555. /* If this area contained boot area, make separate partition */
  556. if (pdata->nr_parts == 0 && !pdata->parts &&
  557. addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
  558. !parts[0].name) {
  559. parts[0].name = "boot";
  560. parts[0].offset = 0x1fc00000 - addr;
  561. parts[0].size = addr + size - 0x1fc00000;
  562. parts[1].name = "user";
  563. parts[1].offset = 0;
  564. parts[1].size = 0x1fc00000 - addr;
  565. pdata_part = *pdata;
  566. pdata_part.nr_parts = ARRAY_SIZE(parts);
  567. pdata_part.parts = parts;
  568. pdata = &pdata_part;
  569. }
  570. #endif
  571. pdev = platform_device_alloc("physmap-flash", no);
  572. if (!pdev ||
  573. platform_device_add_resources(pdev, &res, 1) ||
  574. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  575. platform_device_add(pdev))
  576. platform_device_put(pdev);
  577. #endif
  578. }