spectraswconfig.h 2.4 KB

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  1. /*
  2. * NAND Flash Controller Device Driver
  3. * Copyright (c) 2009, Intel Corporation and its suppliers.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. #ifndef _SPECTRASWCONFIG_
  20. #define _SPECTRASWCONFIG_
  21. /* NAND driver version */
  22. #define GLOB_VERSION "driver version 20100311"
  23. /***** Common Parameters *****/
  24. #define RETRY_TIMES 3
  25. #define READ_BADBLOCK_INFO 1
  26. #define READBACK_VERIFY 0
  27. #define AUTO_FORMAT_FLASH 0
  28. /***** Cache Parameters *****/
  29. #define CACHE_ITEM_NUM 128
  30. #define BLK_NUM_FOR_L2_CACHE 16
  31. /***** Block Table Parameters *****/
  32. #define BLOCK_TABLE_INDEX 0
  33. /***** Wear Leveling Parameters *****/
  34. #define WEAR_LEVELING_GATE 0x10
  35. #define WEAR_LEVELING_BLOCK_NUM 10
  36. #define DEBUG_BNDRY 0
  37. /***** Product Feature Support *****/
  38. #define FLASH_EMU defined(CONFIG_MRST_NAND_EMU)
  39. #define FLASH_NAND defined(CONFIG_MRST_NAND_HW)
  40. #define CMD_DMA 0
  41. #define SPECTRA_PARTITION_ID 0
  42. /* Enable this macro if the number of flash blocks is larger than 16K. */
  43. #define SUPPORT_LARGE_BLOCKNUM 1
  44. /**** Block Table and Reserved Block Parameters *****/
  45. #define SPECTRA_START_BLOCK 3
  46. //#define NUM_FREE_BLOCKS_GATE 30
  47. #define NUM_FREE_BLOCKS_GATE 60
  48. /**** Hardware Parameters ****/
  49. #define GLOB_HWCTL_REG_BASE 0xFFA40000
  50. #define GLOB_HWCTL_REG_SIZE 4096
  51. #define GLOB_HWCTL_MEM_BASE 0xFFA48000
  52. #define GLOB_HWCTL_MEM_SIZE 4096
  53. /* KBV - Updated to LNW scratch register address */
  54. #define SCRATCH_REG_ADDR 0xFF108018
  55. #define SCRATCH_REG_SIZE 64
  56. #define GLOB_HWCTL_DEFAULT_BLKS 2048
  57. #define SUPPORT_15BITECC 1
  58. #define SUPPORT_8BITECC 1
  59. #define ONFI_BLOOM_TIME 0
  60. #define MODE5_WORKAROUND 1
  61. #endif /*_SPECTRASWCONFIG_*/