radeon_mode.h 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622
  1. /*
  2. * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  3. * VA Linux Systems Inc., Fremont, California.
  4. * Copyright 2008 Red Hat Inc.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Original Authors:
  25. * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26. *
  27. * Kernel port Author: Dave Airlie
  28. */
  29. #ifndef RADEON_MODE_H
  30. #define RADEON_MODE_H
  31. #include <drm_crtc.h>
  32. #include <drm_mode.h>
  33. #include <drm_edid.h>
  34. #include <drm_dp_helper.h>
  35. #include <drm_fixed.h>
  36. #include <linux/i2c.h>
  37. #include <linux/i2c-id.h>
  38. #include <linux/i2c-algo-bit.h>
  39. struct radeon_bo;
  40. struct radeon_device;
  41. #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  42. #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  43. #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  44. #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  45. enum radeon_rmx_type {
  46. RMX_OFF,
  47. RMX_FULL,
  48. RMX_CENTER,
  49. RMX_ASPECT
  50. };
  51. enum radeon_tv_std {
  52. TV_STD_NTSC,
  53. TV_STD_PAL,
  54. TV_STD_PAL_M,
  55. TV_STD_PAL_60,
  56. TV_STD_NTSC_J,
  57. TV_STD_SCART_PAL,
  58. TV_STD_SECAM,
  59. TV_STD_PAL_CN,
  60. TV_STD_PAL_N,
  61. };
  62. enum radeon_underscan_type {
  63. UNDERSCAN_OFF,
  64. UNDERSCAN_ON,
  65. UNDERSCAN_AUTO,
  66. };
  67. enum radeon_hpd_id {
  68. RADEON_HPD_1 = 0,
  69. RADEON_HPD_2,
  70. RADEON_HPD_3,
  71. RADEON_HPD_4,
  72. RADEON_HPD_5,
  73. RADEON_HPD_6,
  74. RADEON_HPD_NONE = 0xff,
  75. };
  76. #define RADEON_MAX_I2C_BUS 16
  77. /* radeon gpio-based i2c
  78. * 1. "mask" reg and bits
  79. * grabs the gpio pins for software use
  80. * 0=not held 1=held
  81. * 2. "a" reg and bits
  82. * output pin value
  83. * 0=low 1=high
  84. * 3. "en" reg and bits
  85. * sets the pin direction
  86. * 0=input 1=output
  87. * 4. "y" reg and bits
  88. * input pin value
  89. * 0=low 1=high
  90. */
  91. struct radeon_i2c_bus_rec {
  92. bool valid;
  93. /* id used by atom */
  94. uint8_t i2c_id;
  95. /* id used by atom */
  96. enum radeon_hpd_id hpd;
  97. /* can be used with hw i2c engine */
  98. bool hw_capable;
  99. /* uses multi-media i2c engine */
  100. bool mm_i2c;
  101. /* regs and bits */
  102. uint32_t mask_clk_reg;
  103. uint32_t mask_data_reg;
  104. uint32_t a_clk_reg;
  105. uint32_t a_data_reg;
  106. uint32_t en_clk_reg;
  107. uint32_t en_data_reg;
  108. uint32_t y_clk_reg;
  109. uint32_t y_data_reg;
  110. uint32_t mask_clk_mask;
  111. uint32_t mask_data_mask;
  112. uint32_t a_clk_mask;
  113. uint32_t a_data_mask;
  114. uint32_t en_clk_mask;
  115. uint32_t en_data_mask;
  116. uint32_t y_clk_mask;
  117. uint32_t y_data_mask;
  118. };
  119. struct radeon_tmds_pll {
  120. uint32_t freq;
  121. uint32_t value;
  122. };
  123. #define RADEON_MAX_BIOS_CONNECTOR 16
  124. /* pll flags */
  125. #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
  126. #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
  127. #define RADEON_PLL_USE_REF_DIV (1 << 2)
  128. #define RADEON_PLL_LEGACY (1 << 3)
  129. #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 4)
  130. #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 5)
  131. #define RADEON_PLL_USE_POST_DIV (1 << 6)
  132. #define RADEON_PLL_IS_LCD (1 << 7)
  133. struct radeon_pll {
  134. /* reference frequency */
  135. uint32_t reference_freq;
  136. /* fixed dividers */
  137. uint32_t reference_div;
  138. uint32_t post_div;
  139. /* pll in/out limits */
  140. uint32_t pll_in_min;
  141. uint32_t pll_in_max;
  142. uint32_t pll_out_min;
  143. uint32_t pll_out_max;
  144. uint32_t lcd_pll_out_min;
  145. uint32_t lcd_pll_out_max;
  146. uint32_t best_vco;
  147. /* divider limits */
  148. uint32_t min_ref_div;
  149. uint32_t max_ref_div;
  150. uint32_t min_post_div;
  151. uint32_t max_post_div;
  152. uint32_t min_feedback_div;
  153. uint32_t max_feedback_div;
  154. uint32_t min_frac_feedback_div;
  155. uint32_t max_frac_feedback_div;
  156. /* flags for the current clock */
  157. uint32_t flags;
  158. /* pll id */
  159. uint32_t id;
  160. };
  161. struct radeon_i2c_chan {
  162. struct i2c_adapter adapter;
  163. struct drm_device *dev;
  164. union {
  165. struct i2c_algo_bit_data bit;
  166. struct i2c_algo_dp_aux_data dp;
  167. } algo;
  168. struct radeon_i2c_bus_rec rec;
  169. };
  170. /* mostly for macs, but really any system without connector tables */
  171. enum radeon_connector_table {
  172. CT_NONE = 0,
  173. CT_GENERIC,
  174. CT_IBOOK,
  175. CT_POWERBOOK_EXTERNAL,
  176. CT_POWERBOOK_INTERNAL,
  177. CT_POWERBOOK_VGA,
  178. CT_MINI_EXTERNAL,
  179. CT_MINI_INTERNAL,
  180. CT_IMAC_G5_ISIGHT,
  181. CT_EMAC,
  182. CT_RN50_POWER,
  183. CT_MAC_X800,
  184. };
  185. enum radeon_dvo_chip {
  186. DVO_SIL164,
  187. DVO_SIL1178,
  188. };
  189. struct radeon_fbdev;
  190. struct radeon_mode_info {
  191. struct atom_context *atom_context;
  192. struct card_info *atom_card_info;
  193. enum radeon_connector_table connector_table;
  194. bool mode_config_initialized;
  195. struct radeon_crtc *crtcs[6];
  196. /* DVI-I properties */
  197. struct drm_property *coherent_mode_property;
  198. /* DAC enable load detect */
  199. struct drm_property *load_detect_property;
  200. /* TV standard */
  201. struct drm_property *tv_std_property;
  202. /* legacy TMDS PLL detect */
  203. struct drm_property *tmds_pll_property;
  204. /* underscan */
  205. struct drm_property *underscan_property;
  206. struct drm_property *underscan_hborder_property;
  207. struct drm_property *underscan_vborder_property;
  208. /* hardcoded DFP edid from BIOS */
  209. struct edid *bios_hardcoded_edid;
  210. /* pointer to fbdev info structure */
  211. struct radeon_fbdev *rfbdev;
  212. };
  213. #define MAX_H_CODE_TIMING_LEN 32
  214. #define MAX_V_CODE_TIMING_LEN 32
  215. /* need to store these as reading
  216. back code tables is excessive */
  217. struct radeon_tv_regs {
  218. uint32_t tv_uv_adr;
  219. uint32_t timing_cntl;
  220. uint32_t hrestart;
  221. uint32_t vrestart;
  222. uint32_t frestart;
  223. uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
  224. uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
  225. };
  226. struct radeon_crtc {
  227. struct drm_crtc base;
  228. int crtc_id;
  229. u16 lut_r[256], lut_g[256], lut_b[256];
  230. bool enabled;
  231. bool can_tile;
  232. uint32_t crtc_offset;
  233. struct drm_gem_object *cursor_bo;
  234. uint64_t cursor_addr;
  235. int cursor_width;
  236. int cursor_height;
  237. uint32_t legacy_display_base_addr;
  238. uint32_t legacy_cursor_offset;
  239. enum radeon_rmx_type rmx_type;
  240. u8 h_border;
  241. u8 v_border;
  242. fixed20_12 vsc;
  243. fixed20_12 hsc;
  244. struct drm_display_mode native_mode;
  245. int pll_id;
  246. };
  247. struct radeon_encoder_primary_dac {
  248. /* legacy primary dac */
  249. uint32_t ps2_pdac_adj;
  250. };
  251. struct radeon_encoder_lvds {
  252. /* legacy lvds */
  253. uint16_t panel_vcc_delay;
  254. uint8_t panel_pwr_delay;
  255. uint8_t panel_digon_delay;
  256. uint8_t panel_blon_delay;
  257. uint16_t panel_ref_divider;
  258. uint8_t panel_post_divider;
  259. uint16_t panel_fb_divider;
  260. bool use_bios_dividers;
  261. uint32_t lvds_gen_cntl;
  262. /* panel mode */
  263. struct drm_display_mode native_mode;
  264. };
  265. struct radeon_encoder_tv_dac {
  266. /* legacy tv dac */
  267. uint32_t ps2_tvdac_adj;
  268. uint32_t ntsc_tvdac_adj;
  269. uint32_t pal_tvdac_adj;
  270. int h_pos;
  271. int v_pos;
  272. int h_size;
  273. int supported_tv_stds;
  274. bool tv_on;
  275. enum radeon_tv_std tv_std;
  276. struct radeon_tv_regs tv;
  277. };
  278. struct radeon_encoder_int_tmds {
  279. /* legacy int tmds */
  280. struct radeon_tmds_pll tmds_pll[4];
  281. };
  282. struct radeon_encoder_ext_tmds {
  283. /* tmds over dvo */
  284. struct radeon_i2c_chan *i2c_bus;
  285. uint8_t slave_addr;
  286. enum radeon_dvo_chip dvo_chip;
  287. };
  288. /* spread spectrum */
  289. struct radeon_atom_ss {
  290. uint16_t percentage;
  291. uint8_t type;
  292. uint8_t step;
  293. uint8_t delay;
  294. uint8_t range;
  295. uint8_t refdiv;
  296. };
  297. struct radeon_encoder_atom_dig {
  298. bool linkb;
  299. /* atom dig */
  300. bool coherent_mode;
  301. int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
  302. /* atom lvds */
  303. uint32_t lvds_misc;
  304. uint16_t panel_pwr_delay;
  305. struct radeon_atom_ss *ss;
  306. /* panel mode */
  307. struct drm_display_mode native_mode;
  308. };
  309. struct radeon_encoder_atom_dac {
  310. enum radeon_tv_std tv_std;
  311. };
  312. struct radeon_encoder {
  313. struct drm_encoder base;
  314. uint32_t encoder_enum;
  315. uint32_t encoder_id;
  316. uint32_t devices;
  317. uint32_t active_device;
  318. uint32_t flags;
  319. uint32_t pixel_clock;
  320. enum radeon_rmx_type rmx_type;
  321. enum radeon_underscan_type underscan_type;
  322. uint32_t underscan_hborder;
  323. uint32_t underscan_vborder;
  324. struct drm_display_mode native_mode;
  325. void *enc_priv;
  326. int audio_polling_active;
  327. int hdmi_offset;
  328. int hdmi_config_offset;
  329. int hdmi_audio_workaround;
  330. int hdmi_buffer_status;
  331. };
  332. struct radeon_connector_atom_dig {
  333. uint32_t igp_lane_info;
  334. /* displayport */
  335. struct radeon_i2c_chan *dp_i2c_bus;
  336. u8 dpcd[8];
  337. u8 dp_sink_type;
  338. int dp_clock;
  339. int dp_lane_count;
  340. };
  341. struct radeon_gpio_rec {
  342. bool valid;
  343. u8 id;
  344. u32 reg;
  345. u32 mask;
  346. };
  347. struct radeon_hpd {
  348. enum radeon_hpd_id hpd;
  349. u8 plugged_state;
  350. struct radeon_gpio_rec gpio;
  351. };
  352. struct radeon_router {
  353. bool valid;
  354. u32 router_id;
  355. struct radeon_i2c_bus_rec i2c_info;
  356. u8 i2c_addr;
  357. u8 mux_type;
  358. u8 mux_control_pin;
  359. u8 mux_state;
  360. };
  361. struct radeon_connector {
  362. struct drm_connector base;
  363. uint32_t connector_id;
  364. uint32_t devices;
  365. struct radeon_i2c_chan *ddc_bus;
  366. /* some systems have an hdmi and vga port with a shared ddc line */
  367. bool shared_ddc;
  368. bool use_digital;
  369. /* we need to mind the EDID between detect
  370. and get modes due to analog/digital/tvencoder */
  371. struct edid *edid;
  372. void *con_priv;
  373. bool dac_load_detect;
  374. uint16_t connector_object_id;
  375. struct radeon_hpd hpd;
  376. struct radeon_router router;
  377. struct radeon_i2c_chan *router_bus;
  378. };
  379. struct radeon_framebuffer {
  380. struct drm_framebuffer base;
  381. struct drm_gem_object *obj;
  382. };
  383. extern enum radeon_tv_std
  384. radeon_combios_get_tv_info(struct radeon_device *rdev);
  385. extern enum radeon_tv_std
  386. radeon_atombios_get_tv_info(struct radeon_device *rdev);
  387. extern struct drm_connector *
  388. radeon_get_connector_for_encoder(struct drm_encoder *encoder);
  389. extern void radeon_connector_hotplug(struct drm_connector *connector);
  390. extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
  391. extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
  392. struct drm_display_mode *mode);
  393. extern void radeon_dp_set_link_config(struct drm_connector *connector,
  394. struct drm_display_mode *mode);
  395. extern void dp_link_train(struct drm_encoder *encoder,
  396. struct drm_connector *connector);
  397. extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
  398. extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
  399. extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
  400. extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
  401. int action, uint8_t lane_num,
  402. uint8_t lane_set);
  403. extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  404. uint8_t write_byte, uint8_t *read_byte);
  405. extern void radeon_i2c_init(struct radeon_device *rdev);
  406. extern void radeon_i2c_fini(struct radeon_device *rdev);
  407. extern void radeon_combios_i2c_init(struct radeon_device *rdev);
  408. extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
  409. extern void radeon_i2c_add(struct radeon_device *rdev,
  410. struct radeon_i2c_bus_rec *rec,
  411. const char *name);
  412. extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
  413. struct radeon_i2c_bus_rec *i2c_bus);
  414. extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
  415. struct radeon_i2c_bus_rec *rec,
  416. const char *name);
  417. extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
  418. struct radeon_i2c_bus_rec *rec,
  419. const char *name);
  420. extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
  421. extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
  422. u8 slave_addr,
  423. u8 addr,
  424. u8 *val);
  425. extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
  426. u8 slave_addr,
  427. u8 addr,
  428. u8 val);
  429. extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
  430. extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
  431. extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
  432. extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
  433. extern void radeon_compute_pll(struct radeon_pll *pll,
  434. uint64_t freq,
  435. uint32_t *dot_clock_p,
  436. uint32_t *fb_div_p,
  437. uint32_t *frac_fb_div_p,
  438. uint32_t *ref_div_p,
  439. uint32_t *post_div_p);
  440. extern void radeon_setup_encoder_clones(struct drm_device *dev);
  441. struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
  442. struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  443. struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  444. struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
  445. struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
  446. extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
  447. extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
  448. extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
  449. extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
  450. extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
  451. extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  452. struct drm_framebuffer *old_fb);
  453. extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
  454. struct drm_display_mode *mode,
  455. struct drm_display_mode *adjusted_mode,
  456. int x, int y,
  457. struct drm_framebuffer *old_fb);
  458. extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
  459. extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  460. struct drm_framebuffer *old_fb);
  461. extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
  462. struct drm_file *file_priv,
  463. uint32_t handle,
  464. uint32_t width,
  465. uint32_t height);
  466. extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
  467. int x, int y);
  468. extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
  469. extern struct edid *
  470. radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
  471. extern bool radeon_atom_get_clock_info(struct drm_device *dev);
  472. extern bool radeon_combios_get_clock_info(struct drm_device *dev);
  473. extern struct radeon_encoder_atom_dig *
  474. radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
  475. extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
  476. struct radeon_encoder_int_tmds *tmds);
  477. extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
  478. struct radeon_encoder_int_tmds *tmds);
  479. extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
  480. struct radeon_encoder_int_tmds *tmds);
  481. extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
  482. struct radeon_encoder_ext_tmds *tmds);
  483. extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
  484. struct radeon_encoder_ext_tmds *tmds);
  485. extern struct radeon_encoder_primary_dac *
  486. radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
  487. extern struct radeon_encoder_tv_dac *
  488. radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
  489. extern struct radeon_encoder_lvds *
  490. radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
  491. extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
  492. extern struct radeon_encoder_tv_dac *
  493. radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
  494. extern struct radeon_encoder_primary_dac *
  495. radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
  496. extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
  497. extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
  498. extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
  499. extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
  500. extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
  501. extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
  502. extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
  503. extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
  504. extern void
  505. radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  506. extern void
  507. radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  508. extern void
  509. radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  510. extern void
  511. radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  512. extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  513. u16 blue, int regno);
  514. extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  515. u16 *blue, int regno);
  516. void radeon_framebuffer_init(struct drm_device *dev,
  517. struct radeon_framebuffer *rfb,
  518. struct drm_mode_fb_cmd *mode_cmd,
  519. struct drm_gem_object *obj);
  520. int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
  521. bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
  522. bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
  523. void radeon_atombios_init_crtc(struct drm_device *dev,
  524. struct radeon_crtc *radeon_crtc);
  525. void radeon_legacy_init_crtc(struct drm_device *dev,
  526. struct radeon_crtc *radeon_crtc);
  527. void radeon_get_clock_info(struct drm_device *dev);
  528. extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
  529. extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
  530. void radeon_enc_destroy(struct drm_encoder *encoder);
  531. void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
  532. void radeon_combios_asic_init(struct drm_device *dev);
  533. bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
  534. struct drm_display_mode *mode,
  535. struct drm_display_mode *adjusted_mode);
  536. void radeon_panel_mode_fixup(struct drm_encoder *encoder,
  537. struct drm_display_mode *adjusted_mode);
  538. void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
  539. /* legacy tv */
  540. void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
  541. uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
  542. uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
  543. void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
  544. uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
  545. uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
  546. void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
  547. uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
  548. uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
  549. void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
  550. struct drm_display_mode *mode,
  551. struct drm_display_mode *adjusted_mode);
  552. /* fbdev layer */
  553. int radeon_fbdev_init(struct radeon_device *rdev);
  554. void radeon_fbdev_fini(struct radeon_device *rdev);
  555. void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
  556. int radeon_fbdev_total_size(struct radeon_device *rdev);
  557. bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
  558. void radeon_fb_output_poll_changed(struct radeon_device *rdev);
  559. #endif