omap_hwmod_3xxx_data.c 96 KB

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  1. /*
  2. * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
  3. *
  4. * Copyright (C) 2009-2011 Nokia Corporation
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. * Paul Walmsley
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * The data in this file should be completely autogeneratable from
  13. * the TI hardware database or other technical documentation.
  14. *
  15. * XXX these should be marked initdata for multi-OMAP kernels
  16. */
  17. #include <linux/i2c-omap.h>
  18. #include <linux/power/smartreflex.h>
  19. #include <linux/platform_data/gpio-omap.h>
  20. #include <linux/omap-dma.h>
  21. #include "l3_3xxx.h"
  22. #include "l4_3xxx.h"
  23. #include <linux/platform_data/asoc-ti-mcbsp.h>
  24. #include <linux/platform_data/spi-omap2-mcspi.h>
  25. #include <plat/dmtimer.h>
  26. #include <plat/iommu.h>
  27. #include "am35xx.h"
  28. #include "soc.h"
  29. #include "omap_hwmod.h"
  30. #include "omap_hwmod_common_data.h"
  31. #include "prm-regbits-34xx.h"
  32. #include "cm-regbits-34xx.h"
  33. #include "dma.h"
  34. #include "i2c.h"
  35. #include "mmc.h"
  36. #include "wd_timer.h"
  37. #include "serial.h"
  38. /*
  39. * OMAP3xxx hardware module integration data
  40. *
  41. * All of the data in this section should be autogeneratable from the
  42. * TI hardware database or other technical documentation. Data that
  43. * is driver-specific or driver-kernel integration-specific belongs
  44. * elsewhere.
  45. */
  46. /*
  47. * IP blocks
  48. */
  49. /* L3 */
  50. static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  51. { .irq = 9 + OMAP_INTC_START, },
  52. { .irq = 10 + OMAP_INTC_START, },
  53. { .irq = -1 },
  54. };
  55. static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  56. .name = "l3_main",
  57. .class = &l3_hwmod_class,
  58. .mpu_irqs = omap3xxx_l3_main_irqs,
  59. .flags = HWMOD_NO_IDLEST,
  60. };
  61. /* L4 CORE */
  62. static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  63. .name = "l4_core",
  64. .class = &l4_hwmod_class,
  65. .flags = HWMOD_NO_IDLEST,
  66. };
  67. /* L4 PER */
  68. static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  69. .name = "l4_per",
  70. .class = &l4_hwmod_class,
  71. .flags = HWMOD_NO_IDLEST,
  72. };
  73. /* L4 WKUP */
  74. static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  75. .name = "l4_wkup",
  76. .class = &l4_hwmod_class,
  77. .flags = HWMOD_NO_IDLEST,
  78. };
  79. /* L4 SEC */
  80. static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  81. .name = "l4_sec",
  82. .class = &l4_hwmod_class,
  83. .flags = HWMOD_NO_IDLEST,
  84. };
  85. /* MPU */
  86. static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
  87. { .name = "pmu", .irq = 3 + OMAP_INTC_START },
  88. { .irq = -1 }
  89. };
  90. static struct omap_hwmod omap3xxx_mpu_hwmod = {
  91. .name = "mpu",
  92. .mpu_irqs = omap3xxx_mpu_irqs,
  93. .class = &mpu_hwmod_class,
  94. .main_clk = "arm_fck",
  95. };
  96. /* IVA2 (IVA2) */
  97. static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
  98. { .name = "logic", .rst_shift = 0, .st_shift = 8 },
  99. { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
  100. { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
  101. };
  102. static struct omap_hwmod omap3xxx_iva_hwmod = {
  103. .name = "iva",
  104. .class = &iva_hwmod_class,
  105. .clkdm_name = "iva2_clkdm",
  106. .rst_lines = omap3xxx_iva_resets,
  107. .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
  108. .main_clk = "iva2_ck",
  109. .prcm = {
  110. .omap2 = {
  111. .module_offs = OMAP3430_IVA2_MOD,
  112. .prcm_reg_id = 1,
  113. .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
  114. .idlest_reg_id = 1,
  115. .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
  116. }
  117. },
  118. };
  119. /*
  120. * 'debugss' class
  121. * debug and emulation sub system
  122. */
  123. static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
  124. .name = "debugss",
  125. };
  126. /* debugss */
  127. static struct omap_hwmod omap3xxx_debugss_hwmod = {
  128. .name = "debugss",
  129. .class = &omap3xxx_debugss_hwmod_class,
  130. .clkdm_name = "emu_clkdm",
  131. .main_clk = "emu_src_ck",
  132. .flags = HWMOD_NO_IDLEST,
  133. };
  134. /* timer class */
  135. static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
  136. .rev_offs = 0x0000,
  137. .sysc_offs = 0x0010,
  138. .syss_offs = 0x0014,
  139. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  140. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  141. SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
  142. SYSS_HAS_RESET_STATUS),
  143. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  144. .clockact = CLOCKACT_TEST_ICLK,
  145. .sysc_fields = &omap_hwmod_sysc_type1,
  146. };
  147. static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
  148. .name = "timer",
  149. .sysc = &omap3xxx_timer_sysc,
  150. };
  151. /* secure timers dev attribute */
  152. static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
  153. .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
  154. };
  155. /* always-on timers dev attribute */
  156. static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
  157. .timer_capability = OMAP_TIMER_ALWON,
  158. };
  159. /* pwm timers dev attribute */
  160. static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
  161. .timer_capability = OMAP_TIMER_HAS_PWM,
  162. };
  163. /* timers with DSP interrupt dev attribute */
  164. static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
  165. .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
  166. };
  167. /* pwm timers with DSP interrupt dev attribute */
  168. static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
  169. .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
  170. };
  171. /* timer1 */
  172. static struct omap_hwmod omap3xxx_timer1_hwmod = {
  173. .name = "timer1",
  174. .mpu_irqs = omap2_timer1_mpu_irqs,
  175. .main_clk = "gpt1_fck",
  176. .prcm = {
  177. .omap2 = {
  178. .prcm_reg_id = 1,
  179. .module_bit = OMAP3430_EN_GPT1_SHIFT,
  180. .module_offs = WKUP_MOD,
  181. .idlest_reg_id = 1,
  182. .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
  183. },
  184. },
  185. .dev_attr = &capability_alwon_dev_attr,
  186. .class = &omap3xxx_timer_hwmod_class,
  187. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  188. };
  189. /* timer2 */
  190. static struct omap_hwmod omap3xxx_timer2_hwmod = {
  191. .name = "timer2",
  192. .mpu_irqs = omap2_timer2_mpu_irqs,
  193. .main_clk = "gpt2_fck",
  194. .prcm = {
  195. .omap2 = {
  196. .prcm_reg_id = 1,
  197. .module_bit = OMAP3430_EN_GPT2_SHIFT,
  198. .module_offs = OMAP3430_PER_MOD,
  199. .idlest_reg_id = 1,
  200. .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
  201. },
  202. },
  203. .class = &omap3xxx_timer_hwmod_class,
  204. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  205. };
  206. /* timer3 */
  207. static struct omap_hwmod omap3xxx_timer3_hwmod = {
  208. .name = "timer3",
  209. .mpu_irqs = omap2_timer3_mpu_irqs,
  210. .main_clk = "gpt3_fck",
  211. .prcm = {
  212. .omap2 = {
  213. .prcm_reg_id = 1,
  214. .module_bit = OMAP3430_EN_GPT3_SHIFT,
  215. .module_offs = OMAP3430_PER_MOD,
  216. .idlest_reg_id = 1,
  217. .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
  218. },
  219. },
  220. .class = &omap3xxx_timer_hwmod_class,
  221. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  222. };
  223. /* timer4 */
  224. static struct omap_hwmod omap3xxx_timer4_hwmod = {
  225. .name = "timer4",
  226. .mpu_irqs = omap2_timer4_mpu_irqs,
  227. .main_clk = "gpt4_fck",
  228. .prcm = {
  229. .omap2 = {
  230. .prcm_reg_id = 1,
  231. .module_bit = OMAP3430_EN_GPT4_SHIFT,
  232. .module_offs = OMAP3430_PER_MOD,
  233. .idlest_reg_id = 1,
  234. .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
  235. },
  236. },
  237. .class = &omap3xxx_timer_hwmod_class,
  238. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  239. };
  240. /* timer5 */
  241. static struct omap_hwmod omap3xxx_timer5_hwmod = {
  242. .name = "timer5",
  243. .mpu_irqs = omap2_timer5_mpu_irqs,
  244. .main_clk = "gpt5_fck",
  245. .prcm = {
  246. .omap2 = {
  247. .prcm_reg_id = 1,
  248. .module_bit = OMAP3430_EN_GPT5_SHIFT,
  249. .module_offs = OMAP3430_PER_MOD,
  250. .idlest_reg_id = 1,
  251. .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
  252. },
  253. },
  254. .dev_attr = &capability_dsp_dev_attr,
  255. .class = &omap3xxx_timer_hwmod_class,
  256. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  257. };
  258. /* timer6 */
  259. static struct omap_hwmod omap3xxx_timer6_hwmod = {
  260. .name = "timer6",
  261. .mpu_irqs = omap2_timer6_mpu_irqs,
  262. .main_clk = "gpt6_fck",
  263. .prcm = {
  264. .omap2 = {
  265. .prcm_reg_id = 1,
  266. .module_bit = OMAP3430_EN_GPT6_SHIFT,
  267. .module_offs = OMAP3430_PER_MOD,
  268. .idlest_reg_id = 1,
  269. .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
  270. },
  271. },
  272. .dev_attr = &capability_dsp_dev_attr,
  273. .class = &omap3xxx_timer_hwmod_class,
  274. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  275. };
  276. /* timer7 */
  277. static struct omap_hwmod omap3xxx_timer7_hwmod = {
  278. .name = "timer7",
  279. .mpu_irqs = omap2_timer7_mpu_irqs,
  280. .main_clk = "gpt7_fck",
  281. .prcm = {
  282. .omap2 = {
  283. .prcm_reg_id = 1,
  284. .module_bit = OMAP3430_EN_GPT7_SHIFT,
  285. .module_offs = OMAP3430_PER_MOD,
  286. .idlest_reg_id = 1,
  287. .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
  288. },
  289. },
  290. .dev_attr = &capability_dsp_dev_attr,
  291. .class = &omap3xxx_timer_hwmod_class,
  292. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  293. };
  294. /* timer8 */
  295. static struct omap_hwmod omap3xxx_timer8_hwmod = {
  296. .name = "timer8",
  297. .mpu_irqs = omap2_timer8_mpu_irqs,
  298. .main_clk = "gpt8_fck",
  299. .prcm = {
  300. .omap2 = {
  301. .prcm_reg_id = 1,
  302. .module_bit = OMAP3430_EN_GPT8_SHIFT,
  303. .module_offs = OMAP3430_PER_MOD,
  304. .idlest_reg_id = 1,
  305. .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
  306. },
  307. },
  308. .dev_attr = &capability_dsp_pwm_dev_attr,
  309. .class = &omap3xxx_timer_hwmod_class,
  310. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  311. };
  312. /* timer9 */
  313. static struct omap_hwmod omap3xxx_timer9_hwmod = {
  314. .name = "timer9",
  315. .mpu_irqs = omap2_timer9_mpu_irqs,
  316. .main_clk = "gpt9_fck",
  317. .prcm = {
  318. .omap2 = {
  319. .prcm_reg_id = 1,
  320. .module_bit = OMAP3430_EN_GPT9_SHIFT,
  321. .module_offs = OMAP3430_PER_MOD,
  322. .idlest_reg_id = 1,
  323. .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
  324. },
  325. },
  326. .dev_attr = &capability_pwm_dev_attr,
  327. .class = &omap3xxx_timer_hwmod_class,
  328. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  329. };
  330. /* timer10 */
  331. static struct omap_hwmod omap3xxx_timer10_hwmod = {
  332. .name = "timer10",
  333. .mpu_irqs = omap2_timer10_mpu_irqs,
  334. .main_clk = "gpt10_fck",
  335. .prcm = {
  336. .omap2 = {
  337. .prcm_reg_id = 1,
  338. .module_bit = OMAP3430_EN_GPT10_SHIFT,
  339. .module_offs = CORE_MOD,
  340. .idlest_reg_id = 1,
  341. .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
  342. },
  343. },
  344. .dev_attr = &capability_pwm_dev_attr,
  345. .class = &omap3xxx_timer_hwmod_class,
  346. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  347. };
  348. /* timer11 */
  349. static struct omap_hwmod omap3xxx_timer11_hwmod = {
  350. .name = "timer11",
  351. .mpu_irqs = omap2_timer11_mpu_irqs,
  352. .main_clk = "gpt11_fck",
  353. .prcm = {
  354. .omap2 = {
  355. .prcm_reg_id = 1,
  356. .module_bit = OMAP3430_EN_GPT11_SHIFT,
  357. .module_offs = CORE_MOD,
  358. .idlest_reg_id = 1,
  359. .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
  360. },
  361. },
  362. .dev_attr = &capability_pwm_dev_attr,
  363. .class = &omap3xxx_timer_hwmod_class,
  364. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  365. };
  366. /* timer12 */
  367. static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
  368. { .irq = 95 + OMAP_INTC_START, },
  369. { .irq = -1 },
  370. };
  371. static struct omap_hwmod omap3xxx_timer12_hwmod = {
  372. .name = "timer12",
  373. .mpu_irqs = omap3xxx_timer12_mpu_irqs,
  374. .main_clk = "gpt12_fck",
  375. .prcm = {
  376. .omap2 = {
  377. .prcm_reg_id = 1,
  378. .module_bit = OMAP3430_EN_GPT12_SHIFT,
  379. .module_offs = WKUP_MOD,
  380. .idlest_reg_id = 1,
  381. .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
  382. },
  383. },
  384. .dev_attr = &capability_secure_dev_attr,
  385. .class = &omap3xxx_timer_hwmod_class,
  386. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  387. };
  388. /*
  389. * 'wd_timer' class
  390. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  391. * overflow condition
  392. */
  393. static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
  394. .rev_offs = 0x0000,
  395. .sysc_offs = 0x0010,
  396. .syss_offs = 0x0014,
  397. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
  398. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  399. SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  400. SYSS_HAS_RESET_STATUS),
  401. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  402. .sysc_fields = &omap_hwmod_sysc_type1,
  403. };
  404. /* I2C common */
  405. static struct omap_hwmod_class_sysconfig i2c_sysc = {
  406. .rev_offs = 0x00,
  407. .sysc_offs = 0x20,
  408. .syss_offs = 0x10,
  409. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  410. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  411. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  412. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  413. .clockact = CLOCKACT_TEST_ICLK,
  414. .sysc_fields = &omap_hwmod_sysc_type1,
  415. };
  416. static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
  417. .name = "wd_timer",
  418. .sysc = &omap3xxx_wd_timer_sysc,
  419. .pre_shutdown = &omap2_wd_timer_disable,
  420. .reset = &omap2_wd_timer_reset,
  421. };
  422. static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
  423. .name = "wd_timer2",
  424. .class = &omap3xxx_wd_timer_hwmod_class,
  425. .main_clk = "wdt2_fck",
  426. .prcm = {
  427. .omap2 = {
  428. .prcm_reg_id = 1,
  429. .module_bit = OMAP3430_EN_WDT2_SHIFT,
  430. .module_offs = WKUP_MOD,
  431. .idlest_reg_id = 1,
  432. .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
  433. },
  434. },
  435. /*
  436. * XXX: Use software supervised mode, HW supervised smartidle seems to
  437. * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
  438. */
  439. .flags = HWMOD_SWSUP_SIDLE,
  440. };
  441. /* UART1 */
  442. static struct omap_hwmod omap3xxx_uart1_hwmod = {
  443. .name = "uart1",
  444. .mpu_irqs = omap2_uart1_mpu_irqs,
  445. .sdma_reqs = omap2_uart1_sdma_reqs,
  446. .main_clk = "uart1_fck",
  447. .prcm = {
  448. .omap2 = {
  449. .module_offs = CORE_MOD,
  450. .prcm_reg_id = 1,
  451. .module_bit = OMAP3430_EN_UART1_SHIFT,
  452. .idlest_reg_id = 1,
  453. .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
  454. },
  455. },
  456. .class = &omap2_uart_class,
  457. };
  458. /* UART2 */
  459. static struct omap_hwmod omap3xxx_uart2_hwmod = {
  460. .name = "uart2",
  461. .mpu_irqs = omap2_uart2_mpu_irqs,
  462. .sdma_reqs = omap2_uart2_sdma_reqs,
  463. .main_clk = "uart2_fck",
  464. .prcm = {
  465. .omap2 = {
  466. .module_offs = CORE_MOD,
  467. .prcm_reg_id = 1,
  468. .module_bit = OMAP3430_EN_UART2_SHIFT,
  469. .idlest_reg_id = 1,
  470. .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
  471. },
  472. },
  473. .class = &omap2_uart_class,
  474. };
  475. /* UART3 */
  476. static struct omap_hwmod omap3xxx_uart3_hwmod = {
  477. .name = "uart3",
  478. .mpu_irqs = omap2_uart3_mpu_irqs,
  479. .sdma_reqs = omap2_uart3_sdma_reqs,
  480. .main_clk = "uart3_fck",
  481. .prcm = {
  482. .omap2 = {
  483. .module_offs = OMAP3430_PER_MOD,
  484. .prcm_reg_id = 1,
  485. .module_bit = OMAP3430_EN_UART3_SHIFT,
  486. .idlest_reg_id = 1,
  487. .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
  488. },
  489. },
  490. .class = &omap2_uart_class,
  491. };
  492. /* UART4 */
  493. static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
  494. { .irq = 80 + OMAP_INTC_START, },
  495. { .irq = -1 },
  496. };
  497. static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
  498. { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
  499. { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
  500. { .dma_req = -1 }
  501. };
  502. static struct omap_hwmod omap36xx_uart4_hwmod = {
  503. .name = "uart4",
  504. .mpu_irqs = uart4_mpu_irqs,
  505. .sdma_reqs = uart4_sdma_reqs,
  506. .main_clk = "uart4_fck",
  507. .prcm = {
  508. .omap2 = {
  509. .module_offs = OMAP3430_PER_MOD,
  510. .prcm_reg_id = 1,
  511. .module_bit = OMAP3630_EN_UART4_SHIFT,
  512. .idlest_reg_id = 1,
  513. .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
  514. },
  515. },
  516. .class = &omap2_uart_class,
  517. };
  518. static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
  519. { .irq = 84 + OMAP_INTC_START, },
  520. { .irq = -1 },
  521. };
  522. static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
  523. { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
  524. { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
  525. { .dma_req = -1 }
  526. };
  527. /*
  528. * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
  529. * uart2_fck being enabled. So we add uart1_fck as an optional clock,
  530. * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
  531. * should not be needed. The functional clock structure of the AM35xx
  532. * UART4 is extremely unclear and opaque; it is unclear what the role
  533. * of uart1/2_fck is for the UART4. Any clarification from either
  534. * empirical testing or the AM3505/3517 hardware designers would be
  535. * most welcome.
  536. */
  537. static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
  538. { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
  539. };
  540. static struct omap_hwmod am35xx_uart4_hwmod = {
  541. .name = "uart4",
  542. .mpu_irqs = am35xx_uart4_mpu_irqs,
  543. .sdma_reqs = am35xx_uart4_sdma_reqs,
  544. .main_clk = "uart4_fck",
  545. .prcm = {
  546. .omap2 = {
  547. .module_offs = CORE_MOD,
  548. .prcm_reg_id = 1,
  549. .module_bit = AM35XX_EN_UART4_SHIFT,
  550. .idlest_reg_id = 1,
  551. .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
  552. },
  553. },
  554. .opt_clks = am35xx_uart4_opt_clks,
  555. .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
  556. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  557. .class = &omap2_uart_class,
  558. };
  559. static struct omap_hwmod_class i2c_class = {
  560. .name = "i2c",
  561. .sysc = &i2c_sysc,
  562. .rev = OMAP_I2C_IP_VERSION_1,
  563. .reset = &omap_i2c_reset,
  564. };
  565. static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
  566. { .name = "dispc", .dma_req = 5 },
  567. { .name = "dsi1", .dma_req = 74 },
  568. { .dma_req = -1 }
  569. };
  570. /* dss */
  571. static struct omap_hwmod_opt_clk dss_opt_clks[] = {
  572. /*
  573. * The DSS HW needs all DSS clocks enabled during reset. The dss_core
  574. * driver does not use these clocks.
  575. */
  576. { .role = "sys_clk", .clk = "dss2_alwon_fck" },
  577. { .role = "tv_clk", .clk = "dss_tv_fck" },
  578. /* required only on OMAP3430 */
  579. { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
  580. };
  581. static struct omap_hwmod omap3430es1_dss_core_hwmod = {
  582. .name = "dss_core",
  583. .class = &omap2_dss_hwmod_class,
  584. .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
  585. .sdma_reqs = omap3xxx_dss_sdma_chs,
  586. .prcm = {
  587. .omap2 = {
  588. .prcm_reg_id = 1,
  589. .module_bit = OMAP3430_EN_DSS1_SHIFT,
  590. .module_offs = OMAP3430_DSS_MOD,
  591. .idlest_reg_id = 1,
  592. .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
  593. },
  594. },
  595. .opt_clks = dss_opt_clks,
  596. .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
  597. .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  598. };
  599. static struct omap_hwmod omap3xxx_dss_core_hwmod = {
  600. .name = "dss_core",
  601. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  602. .class = &omap2_dss_hwmod_class,
  603. .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
  604. .sdma_reqs = omap3xxx_dss_sdma_chs,
  605. .prcm = {
  606. .omap2 = {
  607. .prcm_reg_id = 1,
  608. .module_bit = OMAP3430_EN_DSS1_SHIFT,
  609. .module_offs = OMAP3430_DSS_MOD,
  610. .idlest_reg_id = 1,
  611. .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
  612. .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
  613. },
  614. },
  615. .opt_clks = dss_opt_clks,
  616. .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
  617. };
  618. /*
  619. * 'dispc' class
  620. * display controller
  621. */
  622. static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
  623. .rev_offs = 0x0000,
  624. .sysc_offs = 0x0010,
  625. .syss_offs = 0x0014,
  626. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  627. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  628. SYSC_HAS_ENAWAKEUP),
  629. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  630. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  631. .sysc_fields = &omap_hwmod_sysc_type1,
  632. };
  633. static struct omap_hwmod_class omap3_dispc_hwmod_class = {
  634. .name = "dispc",
  635. .sysc = &omap3_dispc_sysc,
  636. };
  637. static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
  638. .name = "dss_dispc",
  639. .class = &omap3_dispc_hwmod_class,
  640. .mpu_irqs = omap2_dispc_irqs,
  641. .main_clk = "dss1_alwon_fck",
  642. .prcm = {
  643. .omap2 = {
  644. .prcm_reg_id = 1,
  645. .module_bit = OMAP3430_EN_DSS1_SHIFT,
  646. .module_offs = OMAP3430_DSS_MOD,
  647. },
  648. },
  649. .flags = HWMOD_NO_IDLEST,
  650. .dev_attr = &omap2_3_dss_dispc_dev_attr
  651. };
  652. /*
  653. * 'dsi' class
  654. * display serial interface controller
  655. */
  656. static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
  657. .name = "dsi",
  658. };
  659. static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
  660. { .irq = 25 + OMAP_INTC_START, },
  661. { .irq = -1 },
  662. };
  663. /* dss_dsi1 */
  664. static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
  665. { .role = "sys_clk", .clk = "dss2_alwon_fck" },
  666. };
  667. static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
  668. .name = "dss_dsi1",
  669. .class = &omap3xxx_dsi_hwmod_class,
  670. .mpu_irqs = omap3xxx_dsi1_irqs,
  671. .main_clk = "dss1_alwon_fck",
  672. .prcm = {
  673. .omap2 = {
  674. .prcm_reg_id = 1,
  675. .module_bit = OMAP3430_EN_DSS1_SHIFT,
  676. .module_offs = OMAP3430_DSS_MOD,
  677. },
  678. },
  679. .opt_clks = dss_dsi1_opt_clks,
  680. .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
  681. .flags = HWMOD_NO_IDLEST,
  682. };
  683. static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
  684. { .role = "ick", .clk = "dss_ick" },
  685. };
  686. static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
  687. .name = "dss_rfbi",
  688. .class = &omap2_rfbi_hwmod_class,
  689. .main_clk = "dss1_alwon_fck",
  690. .prcm = {
  691. .omap2 = {
  692. .prcm_reg_id = 1,
  693. .module_bit = OMAP3430_EN_DSS1_SHIFT,
  694. .module_offs = OMAP3430_DSS_MOD,
  695. },
  696. },
  697. .opt_clks = dss_rfbi_opt_clks,
  698. .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
  699. .flags = HWMOD_NO_IDLEST,
  700. };
  701. static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
  702. /* required only on OMAP3430 */
  703. { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
  704. };
  705. static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
  706. .name = "dss_venc",
  707. .class = &omap2_venc_hwmod_class,
  708. .main_clk = "dss_tv_fck",
  709. .prcm = {
  710. .omap2 = {
  711. .prcm_reg_id = 1,
  712. .module_bit = OMAP3430_EN_DSS1_SHIFT,
  713. .module_offs = OMAP3430_DSS_MOD,
  714. },
  715. },
  716. .opt_clks = dss_venc_opt_clks,
  717. .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
  718. .flags = HWMOD_NO_IDLEST,
  719. };
  720. /* I2C1 */
  721. static struct omap_i2c_dev_attr i2c1_dev_attr = {
  722. .fifo_depth = 8, /* bytes */
  723. .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
  724. OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
  725. OMAP_I2C_FLAG_BUS_SHIFT_2,
  726. };
  727. static struct omap_hwmod omap3xxx_i2c1_hwmod = {
  728. .name = "i2c1",
  729. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  730. .mpu_irqs = omap2_i2c1_mpu_irqs,
  731. .sdma_reqs = omap2_i2c1_sdma_reqs,
  732. .main_clk = "i2c1_fck",
  733. .prcm = {
  734. .omap2 = {
  735. .module_offs = CORE_MOD,
  736. .prcm_reg_id = 1,
  737. .module_bit = OMAP3430_EN_I2C1_SHIFT,
  738. .idlest_reg_id = 1,
  739. .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
  740. },
  741. },
  742. .class = &i2c_class,
  743. .dev_attr = &i2c1_dev_attr,
  744. };
  745. /* I2C2 */
  746. static struct omap_i2c_dev_attr i2c2_dev_attr = {
  747. .fifo_depth = 8, /* bytes */
  748. .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
  749. OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
  750. OMAP_I2C_FLAG_BUS_SHIFT_2,
  751. };
  752. static struct omap_hwmod omap3xxx_i2c2_hwmod = {
  753. .name = "i2c2",
  754. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  755. .mpu_irqs = omap2_i2c2_mpu_irqs,
  756. .sdma_reqs = omap2_i2c2_sdma_reqs,
  757. .main_clk = "i2c2_fck",
  758. .prcm = {
  759. .omap2 = {
  760. .module_offs = CORE_MOD,
  761. .prcm_reg_id = 1,
  762. .module_bit = OMAP3430_EN_I2C2_SHIFT,
  763. .idlest_reg_id = 1,
  764. .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
  765. },
  766. },
  767. .class = &i2c_class,
  768. .dev_attr = &i2c2_dev_attr,
  769. };
  770. /* I2C3 */
  771. static struct omap_i2c_dev_attr i2c3_dev_attr = {
  772. .fifo_depth = 64, /* bytes */
  773. .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
  774. OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
  775. OMAP_I2C_FLAG_BUS_SHIFT_2,
  776. };
  777. static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
  778. { .irq = 61 + OMAP_INTC_START, },
  779. { .irq = -1 },
  780. };
  781. static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
  782. { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
  783. { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
  784. { .dma_req = -1 }
  785. };
  786. static struct omap_hwmod omap3xxx_i2c3_hwmod = {
  787. .name = "i2c3",
  788. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  789. .mpu_irqs = i2c3_mpu_irqs,
  790. .sdma_reqs = i2c3_sdma_reqs,
  791. .main_clk = "i2c3_fck",
  792. .prcm = {
  793. .omap2 = {
  794. .module_offs = CORE_MOD,
  795. .prcm_reg_id = 1,
  796. .module_bit = OMAP3430_EN_I2C3_SHIFT,
  797. .idlest_reg_id = 1,
  798. .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
  799. },
  800. },
  801. .class = &i2c_class,
  802. .dev_attr = &i2c3_dev_attr,
  803. };
  804. /*
  805. * 'gpio' class
  806. * general purpose io module
  807. */
  808. static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
  809. .rev_offs = 0x0000,
  810. .sysc_offs = 0x0010,
  811. .syss_offs = 0x0014,
  812. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  813. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  814. SYSS_HAS_RESET_STATUS),
  815. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  816. .sysc_fields = &omap_hwmod_sysc_type1,
  817. };
  818. static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
  819. .name = "gpio",
  820. .sysc = &omap3xxx_gpio_sysc,
  821. .rev = 1,
  822. };
  823. /* gpio_dev_attr */
  824. static struct omap_gpio_dev_attr gpio_dev_attr = {
  825. .bank_width = 32,
  826. .dbck_flag = true,
  827. };
  828. /* gpio1 */
  829. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  830. { .role = "dbclk", .clk = "gpio1_dbck", },
  831. };
  832. static struct omap_hwmod omap3xxx_gpio1_hwmod = {
  833. .name = "gpio1",
  834. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  835. .mpu_irqs = omap2_gpio1_irqs,
  836. .main_clk = "gpio1_ick",
  837. .opt_clks = gpio1_opt_clks,
  838. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  839. .prcm = {
  840. .omap2 = {
  841. .prcm_reg_id = 1,
  842. .module_bit = OMAP3430_EN_GPIO1_SHIFT,
  843. .module_offs = WKUP_MOD,
  844. .idlest_reg_id = 1,
  845. .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
  846. },
  847. },
  848. .class = &omap3xxx_gpio_hwmod_class,
  849. .dev_attr = &gpio_dev_attr,
  850. };
  851. /* gpio2 */
  852. static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
  853. { .role = "dbclk", .clk = "gpio2_dbck", },
  854. };
  855. static struct omap_hwmod omap3xxx_gpio2_hwmod = {
  856. .name = "gpio2",
  857. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  858. .mpu_irqs = omap2_gpio2_irqs,
  859. .main_clk = "gpio2_ick",
  860. .opt_clks = gpio2_opt_clks,
  861. .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  862. .prcm = {
  863. .omap2 = {
  864. .prcm_reg_id = 1,
  865. .module_bit = OMAP3430_EN_GPIO2_SHIFT,
  866. .module_offs = OMAP3430_PER_MOD,
  867. .idlest_reg_id = 1,
  868. .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
  869. },
  870. },
  871. .class = &omap3xxx_gpio_hwmod_class,
  872. .dev_attr = &gpio_dev_attr,
  873. };
  874. /* gpio3 */
  875. static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
  876. { .role = "dbclk", .clk = "gpio3_dbck", },
  877. };
  878. static struct omap_hwmod omap3xxx_gpio3_hwmod = {
  879. .name = "gpio3",
  880. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  881. .mpu_irqs = omap2_gpio3_irqs,
  882. .main_clk = "gpio3_ick",
  883. .opt_clks = gpio3_opt_clks,
  884. .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  885. .prcm = {
  886. .omap2 = {
  887. .prcm_reg_id = 1,
  888. .module_bit = OMAP3430_EN_GPIO3_SHIFT,
  889. .module_offs = OMAP3430_PER_MOD,
  890. .idlest_reg_id = 1,
  891. .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
  892. },
  893. },
  894. .class = &omap3xxx_gpio_hwmod_class,
  895. .dev_attr = &gpio_dev_attr,
  896. };
  897. /* gpio4 */
  898. static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
  899. { .role = "dbclk", .clk = "gpio4_dbck", },
  900. };
  901. static struct omap_hwmod omap3xxx_gpio4_hwmod = {
  902. .name = "gpio4",
  903. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  904. .mpu_irqs = omap2_gpio4_irqs,
  905. .main_clk = "gpio4_ick",
  906. .opt_clks = gpio4_opt_clks,
  907. .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
  908. .prcm = {
  909. .omap2 = {
  910. .prcm_reg_id = 1,
  911. .module_bit = OMAP3430_EN_GPIO4_SHIFT,
  912. .module_offs = OMAP3430_PER_MOD,
  913. .idlest_reg_id = 1,
  914. .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
  915. },
  916. },
  917. .class = &omap3xxx_gpio_hwmod_class,
  918. .dev_attr = &gpio_dev_attr,
  919. };
  920. /* gpio5 */
  921. static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
  922. { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
  923. { .irq = -1 },
  924. };
  925. static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
  926. { .role = "dbclk", .clk = "gpio5_dbck", },
  927. };
  928. static struct omap_hwmod omap3xxx_gpio5_hwmod = {
  929. .name = "gpio5",
  930. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  931. .mpu_irqs = omap3xxx_gpio5_irqs,
  932. .main_clk = "gpio5_ick",
  933. .opt_clks = gpio5_opt_clks,
  934. .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
  935. .prcm = {
  936. .omap2 = {
  937. .prcm_reg_id = 1,
  938. .module_bit = OMAP3430_EN_GPIO5_SHIFT,
  939. .module_offs = OMAP3430_PER_MOD,
  940. .idlest_reg_id = 1,
  941. .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
  942. },
  943. },
  944. .class = &omap3xxx_gpio_hwmod_class,
  945. .dev_attr = &gpio_dev_attr,
  946. };
  947. /* gpio6 */
  948. static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
  949. { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
  950. { .irq = -1 },
  951. };
  952. static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
  953. { .role = "dbclk", .clk = "gpio6_dbck", },
  954. };
  955. static struct omap_hwmod omap3xxx_gpio6_hwmod = {
  956. .name = "gpio6",
  957. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  958. .mpu_irqs = omap3xxx_gpio6_irqs,
  959. .main_clk = "gpio6_ick",
  960. .opt_clks = gpio6_opt_clks,
  961. .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
  962. .prcm = {
  963. .omap2 = {
  964. .prcm_reg_id = 1,
  965. .module_bit = OMAP3430_EN_GPIO6_SHIFT,
  966. .module_offs = OMAP3430_PER_MOD,
  967. .idlest_reg_id = 1,
  968. .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
  969. },
  970. },
  971. .class = &omap3xxx_gpio_hwmod_class,
  972. .dev_attr = &gpio_dev_attr,
  973. };
  974. /* dma attributes */
  975. static struct omap_dma_dev_attr dma_dev_attr = {
  976. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  977. IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
  978. .lch_count = 32,
  979. };
  980. static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
  981. .rev_offs = 0x0000,
  982. .sysc_offs = 0x002c,
  983. .syss_offs = 0x0028,
  984. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  985. SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  986. SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
  987. SYSS_HAS_RESET_STATUS),
  988. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  989. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  990. .sysc_fields = &omap_hwmod_sysc_type1,
  991. };
  992. static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
  993. .name = "dma",
  994. .sysc = &omap3xxx_dma_sysc,
  995. };
  996. /* dma_system */
  997. static struct omap_hwmod omap3xxx_dma_system_hwmod = {
  998. .name = "dma",
  999. .class = &omap3xxx_dma_hwmod_class,
  1000. .mpu_irqs = omap2_dma_system_irqs,
  1001. .main_clk = "core_l3_ick",
  1002. .prcm = {
  1003. .omap2 = {
  1004. .module_offs = CORE_MOD,
  1005. .prcm_reg_id = 1,
  1006. .module_bit = OMAP3430_ST_SDMA_SHIFT,
  1007. .idlest_reg_id = 1,
  1008. .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
  1009. },
  1010. },
  1011. .dev_attr = &dma_dev_attr,
  1012. .flags = HWMOD_NO_IDLEST,
  1013. };
  1014. /*
  1015. * 'mcbsp' class
  1016. * multi channel buffered serial port controller
  1017. */
  1018. static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
  1019. .sysc_offs = 0x008c,
  1020. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
  1021. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1022. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1023. .sysc_fields = &omap_hwmod_sysc_type1,
  1024. .clockact = 0x2,
  1025. };
  1026. static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
  1027. .name = "mcbsp",
  1028. .sysc = &omap3xxx_mcbsp_sysc,
  1029. .rev = MCBSP_CONFIG_TYPE3,
  1030. };
  1031. /* McBSP functional clock mapping */
  1032. static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
  1033. { .role = "pad_fck", .clk = "mcbsp_clks" },
  1034. { .role = "prcm_fck", .clk = "core_96m_fck" },
  1035. };
  1036. static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
  1037. { .role = "pad_fck", .clk = "mcbsp_clks" },
  1038. { .role = "prcm_fck", .clk = "per_96m_fck" },
  1039. };
  1040. /* mcbsp1 */
  1041. static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
  1042. { .name = "common", .irq = 16 + OMAP_INTC_START, },
  1043. { .name = "tx", .irq = 59 + OMAP_INTC_START, },
  1044. { .name = "rx", .irq = 60 + OMAP_INTC_START, },
  1045. { .irq = -1 },
  1046. };
  1047. static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
  1048. .name = "mcbsp1",
  1049. .class = &omap3xxx_mcbsp_hwmod_class,
  1050. .mpu_irqs = omap3xxx_mcbsp1_irqs,
  1051. .sdma_reqs = omap2_mcbsp1_sdma_reqs,
  1052. .main_clk = "mcbsp1_fck",
  1053. .prcm = {
  1054. .omap2 = {
  1055. .prcm_reg_id = 1,
  1056. .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1057. .module_offs = CORE_MOD,
  1058. .idlest_reg_id = 1,
  1059. .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
  1060. },
  1061. },
  1062. .opt_clks = mcbsp15_opt_clks,
  1063. .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
  1064. };
  1065. /* mcbsp2 */
  1066. static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
  1067. { .name = "common", .irq = 17 + OMAP_INTC_START, },
  1068. { .name = "tx", .irq = 62 + OMAP_INTC_START, },
  1069. { .name = "rx", .irq = 63 + OMAP_INTC_START, },
  1070. { .irq = -1 },
  1071. };
  1072. static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
  1073. .sidetone = "mcbsp2_sidetone",
  1074. };
  1075. static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
  1076. .name = "mcbsp2",
  1077. .class = &omap3xxx_mcbsp_hwmod_class,
  1078. .mpu_irqs = omap3xxx_mcbsp2_irqs,
  1079. .sdma_reqs = omap2_mcbsp2_sdma_reqs,
  1080. .main_clk = "mcbsp2_fck",
  1081. .prcm = {
  1082. .omap2 = {
  1083. .prcm_reg_id = 1,
  1084. .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
  1085. .module_offs = OMAP3430_PER_MOD,
  1086. .idlest_reg_id = 1,
  1087. .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
  1088. },
  1089. },
  1090. .opt_clks = mcbsp234_opt_clks,
  1091. .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
  1092. .dev_attr = &omap34xx_mcbsp2_dev_attr,
  1093. };
  1094. /* mcbsp3 */
  1095. static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
  1096. { .name = "common", .irq = 22 + OMAP_INTC_START, },
  1097. { .name = "tx", .irq = 89 + OMAP_INTC_START, },
  1098. { .name = "rx", .irq = 90 + OMAP_INTC_START, },
  1099. { .irq = -1 },
  1100. };
  1101. static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
  1102. .sidetone = "mcbsp3_sidetone",
  1103. };
  1104. static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
  1105. .name = "mcbsp3",
  1106. .class = &omap3xxx_mcbsp_hwmod_class,
  1107. .mpu_irqs = omap3xxx_mcbsp3_irqs,
  1108. .sdma_reqs = omap2_mcbsp3_sdma_reqs,
  1109. .main_clk = "mcbsp3_fck",
  1110. .prcm = {
  1111. .omap2 = {
  1112. .prcm_reg_id = 1,
  1113. .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
  1114. .module_offs = OMAP3430_PER_MOD,
  1115. .idlest_reg_id = 1,
  1116. .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
  1117. },
  1118. },
  1119. .opt_clks = mcbsp234_opt_clks,
  1120. .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
  1121. .dev_attr = &omap34xx_mcbsp3_dev_attr,
  1122. };
  1123. /* mcbsp4 */
  1124. static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
  1125. { .name = "common", .irq = 23 + OMAP_INTC_START, },
  1126. { .name = "tx", .irq = 54 + OMAP_INTC_START, },
  1127. { .name = "rx", .irq = 55 + OMAP_INTC_START, },
  1128. { .irq = -1 },
  1129. };
  1130. static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
  1131. { .name = "rx", .dma_req = 20 },
  1132. { .name = "tx", .dma_req = 19 },
  1133. { .dma_req = -1 }
  1134. };
  1135. static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
  1136. .name = "mcbsp4",
  1137. .class = &omap3xxx_mcbsp_hwmod_class,
  1138. .mpu_irqs = omap3xxx_mcbsp4_irqs,
  1139. .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
  1140. .main_clk = "mcbsp4_fck",
  1141. .prcm = {
  1142. .omap2 = {
  1143. .prcm_reg_id = 1,
  1144. .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
  1145. .module_offs = OMAP3430_PER_MOD,
  1146. .idlest_reg_id = 1,
  1147. .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
  1148. },
  1149. },
  1150. .opt_clks = mcbsp234_opt_clks,
  1151. .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
  1152. };
  1153. /* mcbsp5 */
  1154. static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
  1155. { .name = "common", .irq = 27 + OMAP_INTC_START, },
  1156. { .name = "tx", .irq = 81 + OMAP_INTC_START, },
  1157. { .name = "rx", .irq = 82 + OMAP_INTC_START, },
  1158. { .irq = -1 },
  1159. };
  1160. static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
  1161. { .name = "rx", .dma_req = 22 },
  1162. { .name = "tx", .dma_req = 21 },
  1163. { .dma_req = -1 }
  1164. };
  1165. static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
  1166. .name = "mcbsp5",
  1167. .class = &omap3xxx_mcbsp_hwmod_class,
  1168. .mpu_irqs = omap3xxx_mcbsp5_irqs,
  1169. .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
  1170. .main_clk = "mcbsp5_fck",
  1171. .prcm = {
  1172. .omap2 = {
  1173. .prcm_reg_id = 1,
  1174. .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1175. .module_offs = CORE_MOD,
  1176. .idlest_reg_id = 1,
  1177. .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
  1178. },
  1179. },
  1180. .opt_clks = mcbsp15_opt_clks,
  1181. .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
  1182. };
  1183. /* 'mcbsp sidetone' class */
  1184. static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
  1185. .sysc_offs = 0x0010,
  1186. .sysc_flags = SYSC_HAS_AUTOIDLE,
  1187. .sysc_fields = &omap_hwmod_sysc_type1,
  1188. };
  1189. static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
  1190. .name = "mcbsp_sidetone",
  1191. .sysc = &omap3xxx_mcbsp_sidetone_sysc,
  1192. };
  1193. /* mcbsp2_sidetone */
  1194. static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
  1195. { .name = "irq", .irq = 4 + OMAP_INTC_START, },
  1196. { .irq = -1 },
  1197. };
  1198. static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
  1199. .name = "mcbsp2_sidetone",
  1200. .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
  1201. .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
  1202. .main_clk = "mcbsp2_fck",
  1203. .prcm = {
  1204. .omap2 = {
  1205. .prcm_reg_id = 1,
  1206. .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
  1207. .module_offs = OMAP3430_PER_MOD,
  1208. .idlest_reg_id = 1,
  1209. .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
  1210. },
  1211. },
  1212. };
  1213. /* mcbsp3_sidetone */
  1214. static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
  1215. { .name = "irq", .irq = 5 + OMAP_INTC_START, },
  1216. { .irq = -1 },
  1217. };
  1218. static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
  1219. .name = "mcbsp3_sidetone",
  1220. .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
  1221. .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
  1222. .main_clk = "mcbsp3_fck",
  1223. .prcm = {
  1224. .omap2 = {
  1225. .prcm_reg_id = 1,
  1226. .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
  1227. .module_offs = OMAP3430_PER_MOD,
  1228. .idlest_reg_id = 1,
  1229. .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
  1230. },
  1231. },
  1232. };
  1233. /* SR common */
  1234. static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
  1235. .clkact_shift = 20,
  1236. };
  1237. static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
  1238. .sysc_offs = 0x24,
  1239. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
  1240. .clockact = CLOCKACT_TEST_ICLK,
  1241. .sysc_fields = &omap34xx_sr_sysc_fields,
  1242. };
  1243. static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
  1244. .name = "smartreflex",
  1245. .sysc = &omap34xx_sr_sysc,
  1246. .rev = 1,
  1247. };
  1248. static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
  1249. .sidle_shift = 24,
  1250. .enwkup_shift = 26,
  1251. };
  1252. static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
  1253. .sysc_offs = 0x38,
  1254. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1255. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
  1256. SYSC_NO_CACHE),
  1257. .sysc_fields = &omap36xx_sr_sysc_fields,
  1258. };
  1259. static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
  1260. .name = "smartreflex",
  1261. .sysc = &omap36xx_sr_sysc,
  1262. .rev = 2,
  1263. };
  1264. /* SR1 */
  1265. static struct omap_smartreflex_dev_attr sr1_dev_attr = {
  1266. .sensor_voltdm_name = "mpu_iva",
  1267. };
  1268. static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
  1269. { .irq = 18 + OMAP_INTC_START, },
  1270. { .irq = -1 },
  1271. };
  1272. static struct omap_hwmod omap34xx_sr1_hwmod = {
  1273. .name = "smartreflex_mpu_iva",
  1274. .class = &omap34xx_smartreflex_hwmod_class,
  1275. .main_clk = "sr1_fck",
  1276. .prcm = {
  1277. .omap2 = {
  1278. .prcm_reg_id = 1,
  1279. .module_bit = OMAP3430_EN_SR1_SHIFT,
  1280. .module_offs = WKUP_MOD,
  1281. .idlest_reg_id = 1,
  1282. .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
  1283. },
  1284. },
  1285. .dev_attr = &sr1_dev_attr,
  1286. .mpu_irqs = omap3_smartreflex_mpu_irqs,
  1287. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  1288. };
  1289. static struct omap_hwmod omap36xx_sr1_hwmod = {
  1290. .name = "smartreflex_mpu_iva",
  1291. .class = &omap36xx_smartreflex_hwmod_class,
  1292. .main_clk = "sr1_fck",
  1293. .prcm = {
  1294. .omap2 = {
  1295. .prcm_reg_id = 1,
  1296. .module_bit = OMAP3430_EN_SR1_SHIFT,
  1297. .module_offs = WKUP_MOD,
  1298. .idlest_reg_id = 1,
  1299. .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
  1300. },
  1301. },
  1302. .dev_attr = &sr1_dev_attr,
  1303. .mpu_irqs = omap3_smartreflex_mpu_irqs,
  1304. };
  1305. /* SR2 */
  1306. static struct omap_smartreflex_dev_attr sr2_dev_attr = {
  1307. .sensor_voltdm_name = "core",
  1308. };
  1309. static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
  1310. { .irq = 19 + OMAP_INTC_START, },
  1311. { .irq = -1 },
  1312. };
  1313. static struct omap_hwmod omap34xx_sr2_hwmod = {
  1314. .name = "smartreflex_core",
  1315. .class = &omap34xx_smartreflex_hwmod_class,
  1316. .main_clk = "sr2_fck",
  1317. .prcm = {
  1318. .omap2 = {
  1319. .prcm_reg_id = 1,
  1320. .module_bit = OMAP3430_EN_SR2_SHIFT,
  1321. .module_offs = WKUP_MOD,
  1322. .idlest_reg_id = 1,
  1323. .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
  1324. },
  1325. },
  1326. .dev_attr = &sr2_dev_attr,
  1327. .mpu_irqs = omap3_smartreflex_core_irqs,
  1328. .flags = HWMOD_SET_DEFAULT_CLOCKACT,
  1329. };
  1330. static struct omap_hwmod omap36xx_sr2_hwmod = {
  1331. .name = "smartreflex_core",
  1332. .class = &omap36xx_smartreflex_hwmod_class,
  1333. .main_clk = "sr2_fck",
  1334. .prcm = {
  1335. .omap2 = {
  1336. .prcm_reg_id = 1,
  1337. .module_bit = OMAP3430_EN_SR2_SHIFT,
  1338. .module_offs = WKUP_MOD,
  1339. .idlest_reg_id = 1,
  1340. .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
  1341. },
  1342. },
  1343. .dev_attr = &sr2_dev_attr,
  1344. .mpu_irqs = omap3_smartreflex_core_irqs,
  1345. };
  1346. /*
  1347. * 'mailbox' class
  1348. * mailbox module allowing communication between the on-chip processors
  1349. * using a queued mailbox-interrupt mechanism.
  1350. */
  1351. static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
  1352. .rev_offs = 0x000,
  1353. .sysc_offs = 0x010,
  1354. .syss_offs = 0x014,
  1355. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1356. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1357. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1358. .sysc_fields = &omap_hwmod_sysc_type1,
  1359. };
  1360. static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
  1361. .name = "mailbox",
  1362. .sysc = &omap3xxx_mailbox_sysc,
  1363. };
  1364. static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
  1365. { .irq = 26 + OMAP_INTC_START, },
  1366. { .irq = -1 },
  1367. };
  1368. static struct omap_hwmod omap3xxx_mailbox_hwmod = {
  1369. .name = "mailbox",
  1370. .class = &omap3xxx_mailbox_hwmod_class,
  1371. .mpu_irqs = omap3xxx_mailbox_irqs,
  1372. .main_clk = "mailboxes_ick",
  1373. .prcm = {
  1374. .omap2 = {
  1375. .prcm_reg_id = 1,
  1376. .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
  1377. .module_offs = CORE_MOD,
  1378. .idlest_reg_id = 1,
  1379. .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
  1380. },
  1381. },
  1382. };
  1383. /*
  1384. * 'mcspi' class
  1385. * multichannel serial port interface (mcspi) / master/slave synchronous serial
  1386. * bus
  1387. */
  1388. static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
  1389. .rev_offs = 0x0000,
  1390. .sysc_offs = 0x0010,
  1391. .syss_offs = 0x0014,
  1392. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1393. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1394. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  1395. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1396. .sysc_fields = &omap_hwmod_sysc_type1,
  1397. };
  1398. static struct omap_hwmod_class omap34xx_mcspi_class = {
  1399. .name = "mcspi",
  1400. .sysc = &omap34xx_mcspi_sysc,
  1401. .rev = OMAP3_MCSPI_REV,
  1402. };
  1403. /* mcspi1 */
  1404. static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
  1405. .num_chipselect = 4,
  1406. };
  1407. static struct omap_hwmod omap34xx_mcspi1 = {
  1408. .name = "mcspi1",
  1409. .mpu_irqs = omap2_mcspi1_mpu_irqs,
  1410. .sdma_reqs = omap2_mcspi1_sdma_reqs,
  1411. .main_clk = "mcspi1_fck",
  1412. .prcm = {
  1413. .omap2 = {
  1414. .module_offs = CORE_MOD,
  1415. .prcm_reg_id = 1,
  1416. .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1417. .idlest_reg_id = 1,
  1418. .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
  1419. },
  1420. },
  1421. .class = &omap34xx_mcspi_class,
  1422. .dev_attr = &omap_mcspi1_dev_attr,
  1423. };
  1424. /* mcspi2 */
  1425. static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
  1426. .num_chipselect = 2,
  1427. };
  1428. static struct omap_hwmod omap34xx_mcspi2 = {
  1429. .name = "mcspi2",
  1430. .mpu_irqs = omap2_mcspi2_mpu_irqs,
  1431. .sdma_reqs = omap2_mcspi2_sdma_reqs,
  1432. .main_clk = "mcspi2_fck",
  1433. .prcm = {
  1434. .omap2 = {
  1435. .module_offs = CORE_MOD,
  1436. .prcm_reg_id = 1,
  1437. .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1438. .idlest_reg_id = 1,
  1439. .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
  1440. },
  1441. },
  1442. .class = &omap34xx_mcspi_class,
  1443. .dev_attr = &omap_mcspi2_dev_attr,
  1444. };
  1445. /* mcspi3 */
  1446. static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
  1447. { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
  1448. { .irq = -1 },
  1449. };
  1450. static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
  1451. { .name = "tx0", .dma_req = 15 },
  1452. { .name = "rx0", .dma_req = 16 },
  1453. { .name = "tx1", .dma_req = 23 },
  1454. { .name = "rx1", .dma_req = 24 },
  1455. { .dma_req = -1 }
  1456. };
  1457. static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
  1458. .num_chipselect = 2,
  1459. };
  1460. static struct omap_hwmod omap34xx_mcspi3 = {
  1461. .name = "mcspi3",
  1462. .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
  1463. .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
  1464. .main_clk = "mcspi3_fck",
  1465. .prcm = {
  1466. .omap2 = {
  1467. .module_offs = CORE_MOD,
  1468. .prcm_reg_id = 1,
  1469. .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1470. .idlest_reg_id = 1,
  1471. .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
  1472. },
  1473. },
  1474. .class = &omap34xx_mcspi_class,
  1475. .dev_attr = &omap_mcspi3_dev_attr,
  1476. };
  1477. /* mcspi4 */
  1478. static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
  1479. { .name = "irq", .irq = 48 + OMAP_INTC_START, },
  1480. { .irq = -1 },
  1481. };
  1482. static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
  1483. { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
  1484. { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
  1485. { .dma_req = -1 }
  1486. };
  1487. static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
  1488. .num_chipselect = 1,
  1489. };
  1490. static struct omap_hwmod omap34xx_mcspi4 = {
  1491. .name = "mcspi4",
  1492. .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
  1493. .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
  1494. .main_clk = "mcspi4_fck",
  1495. .prcm = {
  1496. .omap2 = {
  1497. .module_offs = CORE_MOD,
  1498. .prcm_reg_id = 1,
  1499. .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1500. .idlest_reg_id = 1,
  1501. .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
  1502. },
  1503. },
  1504. .class = &omap34xx_mcspi_class,
  1505. .dev_attr = &omap_mcspi4_dev_attr,
  1506. };
  1507. /* usbhsotg */
  1508. static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
  1509. .rev_offs = 0x0400,
  1510. .sysc_offs = 0x0404,
  1511. .syss_offs = 0x0408,
  1512. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
  1513. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1514. SYSC_HAS_AUTOIDLE),
  1515. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1516. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1517. .sysc_fields = &omap_hwmod_sysc_type1,
  1518. };
  1519. static struct omap_hwmod_class usbotg_class = {
  1520. .name = "usbotg",
  1521. .sysc = &omap3xxx_usbhsotg_sysc,
  1522. };
  1523. /* usb_otg_hs */
  1524. static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
  1525. { .name = "mc", .irq = 92 + OMAP_INTC_START, },
  1526. { .name = "dma", .irq = 93 + OMAP_INTC_START, },
  1527. { .irq = -1 },
  1528. };
  1529. static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
  1530. .name = "usb_otg_hs",
  1531. .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
  1532. .main_clk = "hsotgusb_ick",
  1533. .prcm = {
  1534. .omap2 = {
  1535. .prcm_reg_id = 1,
  1536. .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1537. .module_offs = CORE_MOD,
  1538. .idlest_reg_id = 1,
  1539. .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
  1540. .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
  1541. },
  1542. },
  1543. .class = &usbotg_class,
  1544. /*
  1545. * Erratum ID: i479 idle_req / idle_ack mechanism potentially
  1546. * broken when autoidle is enabled
  1547. * workaround is to disable the autoidle bit at module level.
  1548. */
  1549. .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
  1550. | HWMOD_SWSUP_MSTANDBY,
  1551. };
  1552. /* usb_otg_hs */
  1553. static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
  1554. { .name = "mc", .irq = 71 + OMAP_INTC_START, },
  1555. { .irq = -1 },
  1556. };
  1557. static struct omap_hwmod_class am35xx_usbotg_class = {
  1558. .name = "am35xx_usbotg",
  1559. };
  1560. static struct omap_hwmod am35xx_usbhsotg_hwmod = {
  1561. .name = "am35x_otg_hs",
  1562. .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
  1563. .main_clk = "hsotgusb_fck",
  1564. .class = &am35xx_usbotg_class,
  1565. .flags = HWMOD_NO_IDLEST,
  1566. };
  1567. /* MMC/SD/SDIO common */
  1568. static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
  1569. .rev_offs = 0x1fc,
  1570. .sysc_offs = 0x10,
  1571. .syss_offs = 0x14,
  1572. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1573. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1574. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  1575. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1576. .sysc_fields = &omap_hwmod_sysc_type1,
  1577. };
  1578. static struct omap_hwmod_class omap34xx_mmc_class = {
  1579. .name = "mmc",
  1580. .sysc = &omap34xx_mmc_sysc,
  1581. };
  1582. /* MMC/SD/SDIO1 */
  1583. static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
  1584. { .irq = 83 + OMAP_INTC_START, },
  1585. { .irq = -1 },
  1586. };
  1587. static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
  1588. { .name = "tx", .dma_req = 61, },
  1589. { .name = "rx", .dma_req = 62, },
  1590. { .dma_req = -1 }
  1591. };
  1592. static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
  1593. { .role = "dbck", .clk = "omap_32k_fck", },
  1594. };
  1595. static struct omap_mmc_dev_attr mmc1_dev_attr = {
  1596. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1597. };
  1598. /* See 35xx errata 2.1.1.128 in SPRZ278F */
  1599. static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
  1600. .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
  1601. OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
  1602. };
  1603. static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
  1604. .name = "mmc1",
  1605. .mpu_irqs = omap34xx_mmc1_mpu_irqs,
  1606. .sdma_reqs = omap34xx_mmc1_sdma_reqs,
  1607. .opt_clks = omap34xx_mmc1_opt_clks,
  1608. .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
  1609. .main_clk = "mmchs1_fck",
  1610. .prcm = {
  1611. .omap2 = {
  1612. .module_offs = CORE_MOD,
  1613. .prcm_reg_id = 1,
  1614. .module_bit = OMAP3430_EN_MMC1_SHIFT,
  1615. .idlest_reg_id = 1,
  1616. .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
  1617. },
  1618. },
  1619. .dev_attr = &mmc1_pre_es3_dev_attr,
  1620. .class = &omap34xx_mmc_class,
  1621. };
  1622. static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
  1623. .name = "mmc1",
  1624. .mpu_irqs = omap34xx_mmc1_mpu_irqs,
  1625. .sdma_reqs = omap34xx_mmc1_sdma_reqs,
  1626. .opt_clks = omap34xx_mmc1_opt_clks,
  1627. .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
  1628. .main_clk = "mmchs1_fck",
  1629. .prcm = {
  1630. .omap2 = {
  1631. .module_offs = CORE_MOD,
  1632. .prcm_reg_id = 1,
  1633. .module_bit = OMAP3430_EN_MMC1_SHIFT,
  1634. .idlest_reg_id = 1,
  1635. .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
  1636. },
  1637. },
  1638. .dev_attr = &mmc1_dev_attr,
  1639. .class = &omap34xx_mmc_class,
  1640. };
  1641. /* MMC/SD/SDIO2 */
  1642. static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
  1643. { .irq = 86 + OMAP_INTC_START, },
  1644. { .irq = -1 },
  1645. };
  1646. static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
  1647. { .name = "tx", .dma_req = 47, },
  1648. { .name = "rx", .dma_req = 48, },
  1649. { .dma_req = -1 }
  1650. };
  1651. static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
  1652. { .role = "dbck", .clk = "omap_32k_fck", },
  1653. };
  1654. /* See 35xx errata 2.1.1.128 in SPRZ278F */
  1655. static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
  1656. .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
  1657. };
  1658. static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
  1659. .name = "mmc2",
  1660. .mpu_irqs = omap34xx_mmc2_mpu_irqs,
  1661. .sdma_reqs = omap34xx_mmc2_sdma_reqs,
  1662. .opt_clks = omap34xx_mmc2_opt_clks,
  1663. .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
  1664. .main_clk = "mmchs2_fck",
  1665. .prcm = {
  1666. .omap2 = {
  1667. .module_offs = CORE_MOD,
  1668. .prcm_reg_id = 1,
  1669. .module_bit = OMAP3430_EN_MMC2_SHIFT,
  1670. .idlest_reg_id = 1,
  1671. .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
  1672. },
  1673. },
  1674. .dev_attr = &mmc2_pre_es3_dev_attr,
  1675. .class = &omap34xx_mmc_class,
  1676. };
  1677. static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
  1678. .name = "mmc2",
  1679. .mpu_irqs = omap34xx_mmc2_mpu_irqs,
  1680. .sdma_reqs = omap34xx_mmc2_sdma_reqs,
  1681. .opt_clks = omap34xx_mmc2_opt_clks,
  1682. .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
  1683. .main_clk = "mmchs2_fck",
  1684. .prcm = {
  1685. .omap2 = {
  1686. .module_offs = CORE_MOD,
  1687. .prcm_reg_id = 1,
  1688. .module_bit = OMAP3430_EN_MMC2_SHIFT,
  1689. .idlest_reg_id = 1,
  1690. .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
  1691. },
  1692. },
  1693. .class = &omap34xx_mmc_class,
  1694. };
  1695. /* MMC/SD/SDIO3 */
  1696. static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
  1697. { .irq = 94 + OMAP_INTC_START, },
  1698. { .irq = -1 },
  1699. };
  1700. static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
  1701. { .name = "tx", .dma_req = 77, },
  1702. { .name = "rx", .dma_req = 78, },
  1703. { .dma_req = -1 }
  1704. };
  1705. static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
  1706. { .role = "dbck", .clk = "omap_32k_fck", },
  1707. };
  1708. static struct omap_hwmod omap3xxx_mmc3_hwmod = {
  1709. .name = "mmc3",
  1710. .mpu_irqs = omap34xx_mmc3_mpu_irqs,
  1711. .sdma_reqs = omap34xx_mmc3_sdma_reqs,
  1712. .opt_clks = omap34xx_mmc3_opt_clks,
  1713. .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
  1714. .main_clk = "mmchs3_fck",
  1715. .prcm = {
  1716. .omap2 = {
  1717. .prcm_reg_id = 1,
  1718. .module_bit = OMAP3430_EN_MMC3_SHIFT,
  1719. .idlest_reg_id = 1,
  1720. .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
  1721. },
  1722. },
  1723. .class = &omap34xx_mmc_class,
  1724. };
  1725. /*
  1726. * 'usb_host_hs' class
  1727. * high-speed multi-port usb host controller
  1728. */
  1729. static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
  1730. .rev_offs = 0x0000,
  1731. .sysc_offs = 0x0010,
  1732. .syss_offs = 0x0014,
  1733. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  1734. SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
  1735. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  1736. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1737. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  1738. .sysc_fields = &omap_hwmod_sysc_type1,
  1739. };
  1740. static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
  1741. .name = "usb_host_hs",
  1742. .sysc = &omap3xxx_usb_host_hs_sysc,
  1743. };
  1744. static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
  1745. { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
  1746. };
  1747. static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
  1748. { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
  1749. { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
  1750. { .irq = -1 },
  1751. };
  1752. static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
  1753. .name = "usb_host_hs",
  1754. .class = &omap3xxx_usb_host_hs_hwmod_class,
  1755. .clkdm_name = "l3_init_clkdm",
  1756. .mpu_irqs = omap3xxx_usb_host_hs_irqs,
  1757. .main_clk = "usbhost_48m_fck",
  1758. .prcm = {
  1759. .omap2 = {
  1760. .module_offs = OMAP3430ES2_USBHOST_MOD,
  1761. .prcm_reg_id = 1,
  1762. .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
  1763. .idlest_reg_id = 1,
  1764. .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
  1765. .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
  1766. },
  1767. },
  1768. .opt_clks = omap3xxx_usb_host_hs_opt_clks,
  1769. .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
  1770. /*
  1771. * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
  1772. * id: i660
  1773. *
  1774. * Description:
  1775. * In the following configuration :
  1776. * - USBHOST module is set to smart-idle mode
  1777. * - PRCM asserts idle_req to the USBHOST module ( This typically
  1778. * happens when the system is going to a low power mode : all ports
  1779. * have been suspended, the master part of the USBHOST module has
  1780. * entered the standby state, and SW has cut the functional clocks)
  1781. * - an USBHOST interrupt occurs before the module is able to answer
  1782. * idle_ack, typically a remote wakeup IRQ.
  1783. * Then the USB HOST module will enter a deadlock situation where it
  1784. * is no more accessible nor functional.
  1785. *
  1786. * Workaround:
  1787. * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
  1788. */
  1789. /*
  1790. * Errata: USB host EHCI may stall when entering smart-standby mode
  1791. * Id: i571
  1792. *
  1793. * Description:
  1794. * When the USBHOST module is set to smart-standby mode, and when it is
  1795. * ready to enter the standby state (i.e. all ports are suspended and
  1796. * all attached devices are in suspend mode), then it can wrongly assert
  1797. * the Mstandby signal too early while there are still some residual OCP
  1798. * transactions ongoing. If this condition occurs, the internal state
  1799. * machine may go to an undefined state and the USB link may be stuck
  1800. * upon the next resume.
  1801. *
  1802. * Workaround:
  1803. * Don't use smart standby; use only force standby,
  1804. * hence HWMOD_SWSUP_MSTANDBY
  1805. */
  1806. /*
  1807. * During system boot; If the hwmod framework resets the module
  1808. * the module will have smart idle settings; which can lead to deadlock
  1809. * (above Errata Id:i660); so, dont reset the module during boot;
  1810. * Use HWMOD_INIT_NO_RESET.
  1811. */
  1812. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
  1813. HWMOD_INIT_NO_RESET,
  1814. };
  1815. /*
  1816. * 'usb_tll_hs' class
  1817. * usb_tll_hs module is the adapter on the usb_host_hs ports
  1818. */
  1819. static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
  1820. .rev_offs = 0x0000,
  1821. .sysc_offs = 0x0010,
  1822. .syss_offs = 0x0014,
  1823. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1824. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  1825. SYSC_HAS_AUTOIDLE),
  1826. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1827. .sysc_fields = &omap_hwmod_sysc_type1,
  1828. };
  1829. static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
  1830. .name = "usb_tll_hs",
  1831. .sysc = &omap3xxx_usb_tll_hs_sysc,
  1832. };
  1833. static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
  1834. { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
  1835. { .irq = -1 },
  1836. };
  1837. static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
  1838. .name = "usb_tll_hs",
  1839. .class = &omap3xxx_usb_tll_hs_hwmod_class,
  1840. .clkdm_name = "l3_init_clkdm",
  1841. .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
  1842. .main_clk = "usbtll_fck",
  1843. .prcm = {
  1844. .omap2 = {
  1845. .module_offs = CORE_MOD,
  1846. .prcm_reg_id = 3,
  1847. .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  1848. .idlest_reg_id = 3,
  1849. .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
  1850. },
  1851. },
  1852. };
  1853. static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
  1854. .name = "hdq1w",
  1855. .mpu_irqs = omap2_hdq1w_mpu_irqs,
  1856. .main_clk = "hdq_fck",
  1857. .prcm = {
  1858. .omap2 = {
  1859. .module_offs = CORE_MOD,
  1860. .prcm_reg_id = 1,
  1861. .module_bit = OMAP3430_EN_HDQ_SHIFT,
  1862. .idlest_reg_id = 1,
  1863. .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
  1864. },
  1865. },
  1866. .class = &omap2_hdq1w_class,
  1867. };
  1868. /* SAD2D */
  1869. static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
  1870. { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
  1871. { .name = "rst_modem_sw", .rst_shift = 1 },
  1872. };
  1873. static struct omap_hwmod_class omap3xxx_sad2d_class = {
  1874. .name = "sad2d",
  1875. };
  1876. static struct omap_hwmod omap3xxx_sad2d_hwmod = {
  1877. .name = "sad2d",
  1878. .rst_lines = omap3xxx_sad2d_resets,
  1879. .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
  1880. .main_clk = "sad2d_ick",
  1881. .prcm = {
  1882. .omap2 = {
  1883. .module_offs = CORE_MOD,
  1884. .prcm_reg_id = 1,
  1885. .module_bit = OMAP3430_EN_SAD2D_SHIFT,
  1886. .idlest_reg_id = 1,
  1887. .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
  1888. },
  1889. },
  1890. .class = &omap3xxx_sad2d_class,
  1891. };
  1892. /*
  1893. * '32K sync counter' class
  1894. * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
  1895. */
  1896. static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
  1897. .rev_offs = 0x0000,
  1898. .sysc_offs = 0x0004,
  1899. .sysc_flags = SYSC_HAS_SIDLEMODE,
  1900. .idlemodes = (SIDLE_FORCE | SIDLE_NO),
  1901. .sysc_fields = &omap_hwmod_sysc_type1,
  1902. };
  1903. static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
  1904. .name = "counter",
  1905. .sysc = &omap3xxx_counter_sysc,
  1906. };
  1907. static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
  1908. .name = "counter_32k",
  1909. .class = &omap3xxx_counter_hwmod_class,
  1910. .clkdm_name = "wkup_clkdm",
  1911. .flags = HWMOD_SWSUP_SIDLE,
  1912. .main_clk = "wkup_32k_fck",
  1913. .prcm = {
  1914. .omap2 = {
  1915. .module_offs = WKUP_MOD,
  1916. .prcm_reg_id = 1,
  1917. .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
  1918. .idlest_reg_id = 1,
  1919. .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
  1920. },
  1921. },
  1922. };
  1923. /*
  1924. * 'gpmc' class
  1925. * general purpose memory controller
  1926. */
  1927. static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
  1928. .rev_offs = 0x0000,
  1929. .sysc_offs = 0x0010,
  1930. .syss_offs = 0x0014,
  1931. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
  1932. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1933. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1934. .sysc_fields = &omap_hwmod_sysc_type1,
  1935. };
  1936. static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
  1937. .name = "gpmc",
  1938. .sysc = &omap3xxx_gpmc_sysc,
  1939. };
  1940. static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
  1941. { .irq = 20 },
  1942. { .irq = -1 }
  1943. };
  1944. static struct omap_hwmod omap3xxx_gpmc_hwmod = {
  1945. .name = "gpmc",
  1946. .class = &omap3xxx_gpmc_hwmod_class,
  1947. .clkdm_name = "core_l3_clkdm",
  1948. .mpu_irqs = omap3xxx_gpmc_irqs,
  1949. .main_clk = "gpmc_fck",
  1950. /*
  1951. * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
  1952. * block. It is not being added due to any known bugs with
  1953. * resetting the GPMC IP block, but rather because any timings
  1954. * set by the bootloader are not being correctly programmed by
  1955. * the kernel from the board file or DT data.
  1956. * HWMOD_INIT_NO_RESET should be removed ASAP.
  1957. */
  1958. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
  1959. HWMOD_NO_IDLEST),
  1960. };
  1961. /*
  1962. * interfaces
  1963. */
  1964. /* L3 -> L4_CORE interface */
  1965. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  1966. .master = &omap3xxx_l3_main_hwmod,
  1967. .slave = &omap3xxx_l4_core_hwmod,
  1968. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1969. };
  1970. /* L3 -> L4_PER interface */
  1971. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  1972. .master = &omap3xxx_l3_main_hwmod,
  1973. .slave = &omap3xxx_l4_per_hwmod,
  1974. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1975. };
  1976. static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
  1977. {
  1978. .pa_start = 0x68000000,
  1979. .pa_end = 0x6800ffff,
  1980. .flags = ADDR_TYPE_RT,
  1981. },
  1982. { }
  1983. };
  1984. /* MPU -> L3 interface */
  1985. static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  1986. .master = &omap3xxx_mpu_hwmod,
  1987. .slave = &omap3xxx_l3_main_hwmod,
  1988. .addr = omap3xxx_l3_main_addrs,
  1989. .user = OCP_USER_MPU,
  1990. };
  1991. static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
  1992. {
  1993. .pa_start = 0x54000000,
  1994. .pa_end = 0x547fffff,
  1995. .flags = ADDR_TYPE_RT,
  1996. },
  1997. { }
  1998. };
  1999. /* l3 -> debugss */
  2000. static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
  2001. .master = &omap3xxx_l3_main_hwmod,
  2002. .slave = &omap3xxx_debugss_hwmod,
  2003. .addr = omap3xxx_l4_emu_addrs,
  2004. .user = OCP_USER_MPU,
  2005. };
  2006. /* DSS -> l3 */
  2007. static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
  2008. .master = &omap3430es1_dss_core_hwmod,
  2009. .slave = &omap3xxx_l3_main_hwmod,
  2010. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2011. };
  2012. static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
  2013. .master = &omap3xxx_dss_core_hwmod,
  2014. .slave = &omap3xxx_l3_main_hwmod,
  2015. .fw = {
  2016. .omap2 = {
  2017. .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
  2018. .flags = OMAP_FIREWALL_L3,
  2019. }
  2020. },
  2021. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2022. };
  2023. /* l3_core -> usbhsotg interface */
  2024. static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
  2025. .master = &omap3xxx_usbhsotg_hwmod,
  2026. .slave = &omap3xxx_l3_main_hwmod,
  2027. .clk = "core_l3_ick",
  2028. .user = OCP_USER_MPU,
  2029. };
  2030. /* l3_core -> am35xx_usbhsotg interface */
  2031. static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
  2032. .master = &am35xx_usbhsotg_hwmod,
  2033. .slave = &omap3xxx_l3_main_hwmod,
  2034. .clk = "hsotgusb_ick",
  2035. .user = OCP_USER_MPU,
  2036. };
  2037. /* l3_core -> sad2d interface */
  2038. static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
  2039. .master = &omap3xxx_sad2d_hwmod,
  2040. .slave = &omap3xxx_l3_main_hwmod,
  2041. .clk = "core_l3_ick",
  2042. .user = OCP_USER_MPU,
  2043. };
  2044. /* L4_CORE -> L4_WKUP interface */
  2045. static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
  2046. .master = &omap3xxx_l4_core_hwmod,
  2047. .slave = &omap3xxx_l4_wkup_hwmod,
  2048. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2049. };
  2050. /* L4 CORE -> MMC1 interface */
  2051. static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
  2052. .master = &omap3xxx_l4_core_hwmod,
  2053. .slave = &omap3xxx_pre_es3_mmc1_hwmod,
  2054. .clk = "mmchs1_ick",
  2055. .addr = omap2430_mmc1_addr_space,
  2056. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2057. .flags = OMAP_FIREWALL_L4
  2058. };
  2059. static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
  2060. .master = &omap3xxx_l4_core_hwmod,
  2061. .slave = &omap3xxx_es3plus_mmc1_hwmod,
  2062. .clk = "mmchs1_ick",
  2063. .addr = omap2430_mmc1_addr_space,
  2064. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2065. .flags = OMAP_FIREWALL_L4
  2066. };
  2067. /* L4 CORE -> MMC2 interface */
  2068. static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
  2069. .master = &omap3xxx_l4_core_hwmod,
  2070. .slave = &omap3xxx_pre_es3_mmc2_hwmod,
  2071. .clk = "mmchs2_ick",
  2072. .addr = omap2430_mmc2_addr_space,
  2073. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2074. .flags = OMAP_FIREWALL_L4
  2075. };
  2076. static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
  2077. .master = &omap3xxx_l4_core_hwmod,
  2078. .slave = &omap3xxx_es3plus_mmc2_hwmod,
  2079. .clk = "mmchs2_ick",
  2080. .addr = omap2430_mmc2_addr_space,
  2081. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2082. .flags = OMAP_FIREWALL_L4
  2083. };
  2084. /* L4 CORE -> MMC3 interface */
  2085. static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
  2086. {
  2087. .pa_start = 0x480ad000,
  2088. .pa_end = 0x480ad1ff,
  2089. .flags = ADDR_TYPE_RT,
  2090. },
  2091. { }
  2092. };
  2093. static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
  2094. .master = &omap3xxx_l4_core_hwmod,
  2095. .slave = &omap3xxx_mmc3_hwmod,
  2096. .clk = "mmchs3_ick",
  2097. .addr = omap3xxx_mmc3_addr_space,
  2098. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2099. .flags = OMAP_FIREWALL_L4
  2100. };
  2101. /* L4 CORE -> UART1 interface */
  2102. static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
  2103. {
  2104. .pa_start = OMAP3_UART1_BASE,
  2105. .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
  2106. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  2107. },
  2108. { }
  2109. };
  2110. static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
  2111. .master = &omap3xxx_l4_core_hwmod,
  2112. .slave = &omap3xxx_uart1_hwmod,
  2113. .clk = "uart1_ick",
  2114. .addr = omap3xxx_uart1_addr_space,
  2115. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2116. };
  2117. /* L4 CORE -> UART2 interface */
  2118. static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
  2119. {
  2120. .pa_start = OMAP3_UART2_BASE,
  2121. .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
  2122. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  2123. },
  2124. { }
  2125. };
  2126. static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
  2127. .master = &omap3xxx_l4_core_hwmod,
  2128. .slave = &omap3xxx_uart2_hwmod,
  2129. .clk = "uart2_ick",
  2130. .addr = omap3xxx_uart2_addr_space,
  2131. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2132. };
  2133. /* L4 PER -> UART3 interface */
  2134. static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
  2135. {
  2136. .pa_start = OMAP3_UART3_BASE,
  2137. .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
  2138. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  2139. },
  2140. { }
  2141. };
  2142. static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
  2143. .master = &omap3xxx_l4_per_hwmod,
  2144. .slave = &omap3xxx_uart3_hwmod,
  2145. .clk = "uart3_ick",
  2146. .addr = omap3xxx_uart3_addr_space,
  2147. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2148. };
  2149. /* L4 PER -> UART4 interface */
  2150. static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
  2151. {
  2152. .pa_start = OMAP3_UART4_BASE,
  2153. .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
  2154. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  2155. },
  2156. { }
  2157. };
  2158. static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
  2159. .master = &omap3xxx_l4_per_hwmod,
  2160. .slave = &omap36xx_uart4_hwmod,
  2161. .clk = "uart4_ick",
  2162. .addr = omap36xx_uart4_addr_space,
  2163. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2164. };
  2165. /* AM35xx: L4 CORE -> UART4 interface */
  2166. static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
  2167. {
  2168. .pa_start = OMAP3_UART4_AM35XX_BASE,
  2169. .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
  2170. .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  2171. },
  2172. { }
  2173. };
  2174. static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
  2175. .master = &omap3xxx_l4_core_hwmod,
  2176. .slave = &am35xx_uart4_hwmod,
  2177. .clk = "uart4_ick",
  2178. .addr = am35xx_uart4_addr_space,
  2179. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2180. };
  2181. /* L4 CORE -> I2C1 interface */
  2182. static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
  2183. .master = &omap3xxx_l4_core_hwmod,
  2184. .slave = &omap3xxx_i2c1_hwmod,
  2185. .clk = "i2c1_ick",
  2186. .addr = omap2_i2c1_addr_space,
  2187. .fw = {
  2188. .omap2 = {
  2189. .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
  2190. .l4_prot_group = 7,
  2191. .flags = OMAP_FIREWALL_L4,
  2192. }
  2193. },
  2194. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2195. };
  2196. /* L4 CORE -> I2C2 interface */
  2197. static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
  2198. .master = &omap3xxx_l4_core_hwmod,
  2199. .slave = &omap3xxx_i2c2_hwmod,
  2200. .clk = "i2c2_ick",
  2201. .addr = omap2_i2c2_addr_space,
  2202. .fw = {
  2203. .omap2 = {
  2204. .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
  2205. .l4_prot_group = 7,
  2206. .flags = OMAP_FIREWALL_L4,
  2207. }
  2208. },
  2209. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2210. };
  2211. /* L4 CORE -> I2C3 interface */
  2212. static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
  2213. {
  2214. .pa_start = 0x48060000,
  2215. .pa_end = 0x48060000 + SZ_128 - 1,
  2216. .flags = ADDR_TYPE_RT,
  2217. },
  2218. { }
  2219. };
  2220. static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
  2221. .master = &omap3xxx_l4_core_hwmod,
  2222. .slave = &omap3xxx_i2c3_hwmod,
  2223. .clk = "i2c3_ick",
  2224. .addr = omap3xxx_i2c3_addr_space,
  2225. .fw = {
  2226. .omap2 = {
  2227. .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
  2228. .l4_prot_group = 7,
  2229. .flags = OMAP_FIREWALL_L4,
  2230. }
  2231. },
  2232. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2233. };
  2234. /* L4 CORE -> SR1 interface */
  2235. static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
  2236. {
  2237. .pa_start = OMAP34XX_SR1_BASE,
  2238. .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
  2239. .flags = ADDR_TYPE_RT,
  2240. },
  2241. { }
  2242. };
  2243. static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
  2244. .master = &omap3xxx_l4_core_hwmod,
  2245. .slave = &omap34xx_sr1_hwmod,
  2246. .clk = "sr_l4_ick",
  2247. .addr = omap3_sr1_addr_space,
  2248. .user = OCP_USER_MPU,
  2249. };
  2250. static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
  2251. .master = &omap3xxx_l4_core_hwmod,
  2252. .slave = &omap36xx_sr1_hwmod,
  2253. .clk = "sr_l4_ick",
  2254. .addr = omap3_sr1_addr_space,
  2255. .user = OCP_USER_MPU,
  2256. };
  2257. /* L4 CORE -> SR1 interface */
  2258. static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
  2259. {
  2260. .pa_start = OMAP34XX_SR2_BASE,
  2261. .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
  2262. .flags = ADDR_TYPE_RT,
  2263. },
  2264. { }
  2265. };
  2266. static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
  2267. .master = &omap3xxx_l4_core_hwmod,
  2268. .slave = &omap34xx_sr2_hwmod,
  2269. .clk = "sr_l4_ick",
  2270. .addr = omap3_sr2_addr_space,
  2271. .user = OCP_USER_MPU,
  2272. };
  2273. static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
  2274. .master = &omap3xxx_l4_core_hwmod,
  2275. .slave = &omap36xx_sr2_hwmod,
  2276. .clk = "sr_l4_ick",
  2277. .addr = omap3_sr2_addr_space,
  2278. .user = OCP_USER_MPU,
  2279. };
  2280. static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
  2281. {
  2282. .pa_start = OMAP34XX_HSUSB_OTG_BASE,
  2283. .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
  2284. .flags = ADDR_TYPE_RT
  2285. },
  2286. { }
  2287. };
  2288. /* l4_core -> usbhsotg */
  2289. static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
  2290. .master = &omap3xxx_l4_core_hwmod,
  2291. .slave = &omap3xxx_usbhsotg_hwmod,
  2292. .clk = "l4_ick",
  2293. .addr = omap3xxx_usbhsotg_addrs,
  2294. .user = OCP_USER_MPU,
  2295. };
  2296. static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
  2297. {
  2298. .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
  2299. .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
  2300. .flags = ADDR_TYPE_RT
  2301. },
  2302. { }
  2303. };
  2304. /* l4_core -> usbhsotg */
  2305. static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
  2306. .master = &omap3xxx_l4_core_hwmod,
  2307. .slave = &am35xx_usbhsotg_hwmod,
  2308. .clk = "hsotgusb_ick",
  2309. .addr = am35xx_usbhsotg_addrs,
  2310. .user = OCP_USER_MPU,
  2311. };
  2312. /* L4_WKUP -> L4_SEC interface */
  2313. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
  2314. .master = &omap3xxx_l4_wkup_hwmod,
  2315. .slave = &omap3xxx_l4_sec_hwmod,
  2316. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2317. };
  2318. /* IVA2 <- L3 interface */
  2319. static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
  2320. .master = &omap3xxx_l3_main_hwmod,
  2321. .slave = &omap3xxx_iva_hwmod,
  2322. .clk = "core_l3_ick",
  2323. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2324. };
  2325. static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
  2326. {
  2327. .pa_start = 0x48318000,
  2328. .pa_end = 0x48318000 + SZ_1K - 1,
  2329. .flags = ADDR_TYPE_RT
  2330. },
  2331. { }
  2332. };
  2333. /* l4_wkup -> timer1 */
  2334. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
  2335. .master = &omap3xxx_l4_wkup_hwmod,
  2336. .slave = &omap3xxx_timer1_hwmod,
  2337. .clk = "gpt1_ick",
  2338. .addr = omap3xxx_timer1_addrs,
  2339. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2340. };
  2341. static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
  2342. {
  2343. .pa_start = 0x49032000,
  2344. .pa_end = 0x49032000 + SZ_1K - 1,
  2345. .flags = ADDR_TYPE_RT
  2346. },
  2347. { }
  2348. };
  2349. /* l4_per -> timer2 */
  2350. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
  2351. .master = &omap3xxx_l4_per_hwmod,
  2352. .slave = &omap3xxx_timer2_hwmod,
  2353. .clk = "gpt2_ick",
  2354. .addr = omap3xxx_timer2_addrs,
  2355. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2356. };
  2357. static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
  2358. {
  2359. .pa_start = 0x49034000,
  2360. .pa_end = 0x49034000 + SZ_1K - 1,
  2361. .flags = ADDR_TYPE_RT
  2362. },
  2363. { }
  2364. };
  2365. /* l4_per -> timer3 */
  2366. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
  2367. .master = &omap3xxx_l4_per_hwmod,
  2368. .slave = &omap3xxx_timer3_hwmod,
  2369. .clk = "gpt3_ick",
  2370. .addr = omap3xxx_timer3_addrs,
  2371. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2372. };
  2373. static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
  2374. {
  2375. .pa_start = 0x49036000,
  2376. .pa_end = 0x49036000 + SZ_1K - 1,
  2377. .flags = ADDR_TYPE_RT
  2378. },
  2379. { }
  2380. };
  2381. /* l4_per -> timer4 */
  2382. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
  2383. .master = &omap3xxx_l4_per_hwmod,
  2384. .slave = &omap3xxx_timer4_hwmod,
  2385. .clk = "gpt4_ick",
  2386. .addr = omap3xxx_timer4_addrs,
  2387. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2388. };
  2389. static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
  2390. {
  2391. .pa_start = 0x49038000,
  2392. .pa_end = 0x49038000 + SZ_1K - 1,
  2393. .flags = ADDR_TYPE_RT
  2394. },
  2395. { }
  2396. };
  2397. /* l4_per -> timer5 */
  2398. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
  2399. .master = &omap3xxx_l4_per_hwmod,
  2400. .slave = &omap3xxx_timer5_hwmod,
  2401. .clk = "gpt5_ick",
  2402. .addr = omap3xxx_timer5_addrs,
  2403. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2404. };
  2405. static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
  2406. {
  2407. .pa_start = 0x4903A000,
  2408. .pa_end = 0x4903A000 + SZ_1K - 1,
  2409. .flags = ADDR_TYPE_RT
  2410. },
  2411. { }
  2412. };
  2413. /* l4_per -> timer6 */
  2414. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
  2415. .master = &omap3xxx_l4_per_hwmod,
  2416. .slave = &omap3xxx_timer6_hwmod,
  2417. .clk = "gpt6_ick",
  2418. .addr = omap3xxx_timer6_addrs,
  2419. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2420. };
  2421. static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
  2422. {
  2423. .pa_start = 0x4903C000,
  2424. .pa_end = 0x4903C000 + SZ_1K - 1,
  2425. .flags = ADDR_TYPE_RT
  2426. },
  2427. { }
  2428. };
  2429. /* l4_per -> timer7 */
  2430. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
  2431. .master = &omap3xxx_l4_per_hwmod,
  2432. .slave = &omap3xxx_timer7_hwmod,
  2433. .clk = "gpt7_ick",
  2434. .addr = omap3xxx_timer7_addrs,
  2435. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2436. };
  2437. static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
  2438. {
  2439. .pa_start = 0x4903E000,
  2440. .pa_end = 0x4903E000 + SZ_1K - 1,
  2441. .flags = ADDR_TYPE_RT
  2442. },
  2443. { }
  2444. };
  2445. /* l4_per -> timer8 */
  2446. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
  2447. .master = &omap3xxx_l4_per_hwmod,
  2448. .slave = &omap3xxx_timer8_hwmod,
  2449. .clk = "gpt8_ick",
  2450. .addr = omap3xxx_timer8_addrs,
  2451. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2452. };
  2453. static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
  2454. {
  2455. .pa_start = 0x49040000,
  2456. .pa_end = 0x49040000 + SZ_1K - 1,
  2457. .flags = ADDR_TYPE_RT
  2458. },
  2459. { }
  2460. };
  2461. /* l4_per -> timer9 */
  2462. static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
  2463. .master = &omap3xxx_l4_per_hwmod,
  2464. .slave = &omap3xxx_timer9_hwmod,
  2465. .clk = "gpt9_ick",
  2466. .addr = omap3xxx_timer9_addrs,
  2467. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2468. };
  2469. /* l4_core -> timer10 */
  2470. static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
  2471. .master = &omap3xxx_l4_core_hwmod,
  2472. .slave = &omap3xxx_timer10_hwmod,
  2473. .clk = "gpt10_ick",
  2474. .addr = omap2_timer10_addrs,
  2475. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2476. };
  2477. /* l4_core -> timer11 */
  2478. static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
  2479. .master = &omap3xxx_l4_core_hwmod,
  2480. .slave = &omap3xxx_timer11_hwmod,
  2481. .clk = "gpt11_ick",
  2482. .addr = omap2_timer11_addrs,
  2483. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2484. };
  2485. static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
  2486. {
  2487. .pa_start = 0x48304000,
  2488. .pa_end = 0x48304000 + SZ_1K - 1,
  2489. .flags = ADDR_TYPE_RT
  2490. },
  2491. { }
  2492. };
  2493. /* l4_core -> timer12 */
  2494. static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
  2495. .master = &omap3xxx_l4_sec_hwmod,
  2496. .slave = &omap3xxx_timer12_hwmod,
  2497. .clk = "gpt12_ick",
  2498. .addr = omap3xxx_timer12_addrs,
  2499. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2500. };
  2501. /* l4_wkup -> wd_timer2 */
  2502. static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
  2503. {
  2504. .pa_start = 0x48314000,
  2505. .pa_end = 0x4831407f,
  2506. .flags = ADDR_TYPE_RT
  2507. },
  2508. { }
  2509. };
  2510. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
  2511. .master = &omap3xxx_l4_wkup_hwmod,
  2512. .slave = &omap3xxx_wd_timer2_hwmod,
  2513. .clk = "wdt2_ick",
  2514. .addr = omap3xxx_wd_timer2_addrs,
  2515. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2516. };
  2517. /* l4_core -> dss */
  2518. static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
  2519. .master = &omap3xxx_l4_core_hwmod,
  2520. .slave = &omap3430es1_dss_core_hwmod,
  2521. .clk = "dss_ick",
  2522. .addr = omap2_dss_addrs,
  2523. .fw = {
  2524. .omap2 = {
  2525. .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
  2526. .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
  2527. .flags = OMAP_FIREWALL_L4,
  2528. }
  2529. },
  2530. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2531. };
  2532. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
  2533. .master = &omap3xxx_l4_core_hwmod,
  2534. .slave = &omap3xxx_dss_core_hwmod,
  2535. .clk = "dss_ick",
  2536. .addr = omap2_dss_addrs,
  2537. .fw = {
  2538. .omap2 = {
  2539. .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
  2540. .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
  2541. .flags = OMAP_FIREWALL_L4,
  2542. }
  2543. },
  2544. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2545. };
  2546. /* l4_core -> dss_dispc */
  2547. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
  2548. .master = &omap3xxx_l4_core_hwmod,
  2549. .slave = &omap3xxx_dss_dispc_hwmod,
  2550. .clk = "dss_ick",
  2551. .addr = omap2_dss_dispc_addrs,
  2552. .fw = {
  2553. .omap2 = {
  2554. .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
  2555. .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
  2556. .flags = OMAP_FIREWALL_L4,
  2557. }
  2558. },
  2559. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2560. };
  2561. static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
  2562. {
  2563. .pa_start = 0x4804FC00,
  2564. .pa_end = 0x4804FFFF,
  2565. .flags = ADDR_TYPE_RT
  2566. },
  2567. { }
  2568. };
  2569. /* l4_core -> dss_dsi1 */
  2570. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
  2571. .master = &omap3xxx_l4_core_hwmod,
  2572. .slave = &omap3xxx_dss_dsi1_hwmod,
  2573. .clk = "dss_ick",
  2574. .addr = omap3xxx_dss_dsi1_addrs,
  2575. .fw = {
  2576. .omap2 = {
  2577. .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
  2578. .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
  2579. .flags = OMAP_FIREWALL_L4,
  2580. }
  2581. },
  2582. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2583. };
  2584. /* l4_core -> dss_rfbi */
  2585. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
  2586. .master = &omap3xxx_l4_core_hwmod,
  2587. .slave = &omap3xxx_dss_rfbi_hwmod,
  2588. .clk = "dss_ick",
  2589. .addr = omap2_dss_rfbi_addrs,
  2590. .fw = {
  2591. .omap2 = {
  2592. .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
  2593. .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
  2594. .flags = OMAP_FIREWALL_L4,
  2595. }
  2596. },
  2597. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2598. };
  2599. /* l4_core -> dss_venc */
  2600. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
  2601. .master = &omap3xxx_l4_core_hwmod,
  2602. .slave = &omap3xxx_dss_venc_hwmod,
  2603. .clk = "dss_ick",
  2604. .addr = omap2_dss_venc_addrs,
  2605. .fw = {
  2606. .omap2 = {
  2607. .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
  2608. .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
  2609. .flags = OMAP_FIREWALL_L4,
  2610. }
  2611. },
  2612. .flags = OCPIF_SWSUP_IDLE,
  2613. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2614. };
  2615. /* l4_wkup -> gpio1 */
  2616. static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
  2617. {
  2618. .pa_start = 0x48310000,
  2619. .pa_end = 0x483101ff,
  2620. .flags = ADDR_TYPE_RT
  2621. },
  2622. { }
  2623. };
  2624. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
  2625. .master = &omap3xxx_l4_wkup_hwmod,
  2626. .slave = &omap3xxx_gpio1_hwmod,
  2627. .addr = omap3xxx_gpio1_addrs,
  2628. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2629. };
  2630. /* l4_per -> gpio2 */
  2631. static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
  2632. {
  2633. .pa_start = 0x49050000,
  2634. .pa_end = 0x490501ff,
  2635. .flags = ADDR_TYPE_RT
  2636. },
  2637. { }
  2638. };
  2639. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
  2640. .master = &omap3xxx_l4_per_hwmod,
  2641. .slave = &omap3xxx_gpio2_hwmod,
  2642. .addr = omap3xxx_gpio2_addrs,
  2643. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2644. };
  2645. /* l4_per -> gpio3 */
  2646. static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
  2647. {
  2648. .pa_start = 0x49052000,
  2649. .pa_end = 0x490521ff,
  2650. .flags = ADDR_TYPE_RT
  2651. },
  2652. { }
  2653. };
  2654. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
  2655. .master = &omap3xxx_l4_per_hwmod,
  2656. .slave = &omap3xxx_gpio3_hwmod,
  2657. .addr = omap3xxx_gpio3_addrs,
  2658. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2659. };
  2660. /*
  2661. * 'mmu' class
  2662. * The memory management unit performs virtual to physical address translation
  2663. * for its requestors.
  2664. */
  2665. static struct omap_hwmod_class_sysconfig mmu_sysc = {
  2666. .rev_offs = 0x000,
  2667. .sysc_offs = 0x010,
  2668. .syss_offs = 0x014,
  2669. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  2670. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  2671. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  2672. .sysc_fields = &omap_hwmod_sysc_type1,
  2673. };
  2674. static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
  2675. .name = "mmu",
  2676. .sysc = &mmu_sysc,
  2677. };
  2678. /* mmu isp */
  2679. static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
  2680. .da_start = 0x0,
  2681. .da_end = 0xfffff000,
  2682. .nr_tlb_entries = 8,
  2683. };
  2684. static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
  2685. static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
  2686. { .irq = 24 },
  2687. { .irq = -1 }
  2688. };
  2689. static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
  2690. {
  2691. .pa_start = 0x480bd400,
  2692. .pa_end = 0x480bd47f,
  2693. .flags = ADDR_TYPE_RT,
  2694. },
  2695. { }
  2696. };
  2697. /* l4_core -> mmu isp */
  2698. static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
  2699. .master = &omap3xxx_l4_core_hwmod,
  2700. .slave = &omap3xxx_mmu_isp_hwmod,
  2701. .addr = omap3xxx_mmu_isp_addrs,
  2702. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2703. };
  2704. static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
  2705. .name = "mmu_isp",
  2706. .class = &omap3xxx_mmu_hwmod_class,
  2707. .mpu_irqs = omap3xxx_mmu_isp_irqs,
  2708. .main_clk = "cam_ick",
  2709. .dev_attr = &mmu_isp_dev_attr,
  2710. .flags = HWMOD_NO_IDLEST,
  2711. };
  2712. #ifdef CONFIG_OMAP_IOMMU_IVA2
  2713. /* mmu iva */
  2714. static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
  2715. .da_start = 0x11000000,
  2716. .da_end = 0xfffff000,
  2717. .nr_tlb_entries = 32,
  2718. };
  2719. static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
  2720. static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
  2721. { .irq = 28 },
  2722. { .irq = -1 }
  2723. };
  2724. static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
  2725. { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
  2726. };
  2727. static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
  2728. {
  2729. .pa_start = 0x5d000000,
  2730. .pa_end = 0x5d00007f,
  2731. .flags = ADDR_TYPE_RT,
  2732. },
  2733. { }
  2734. };
  2735. /* l3_main -> iva mmu */
  2736. static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
  2737. .master = &omap3xxx_l3_main_hwmod,
  2738. .slave = &omap3xxx_mmu_iva_hwmod,
  2739. .addr = omap3xxx_mmu_iva_addrs,
  2740. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2741. };
  2742. static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
  2743. .name = "mmu_iva",
  2744. .class = &omap3xxx_mmu_hwmod_class,
  2745. .mpu_irqs = omap3xxx_mmu_iva_irqs,
  2746. .rst_lines = omap3xxx_mmu_iva_resets,
  2747. .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
  2748. .main_clk = "iva2_ck",
  2749. .prcm = {
  2750. .omap2 = {
  2751. .module_offs = OMAP3430_IVA2_MOD,
  2752. },
  2753. },
  2754. .dev_attr = &mmu_iva_dev_attr,
  2755. .flags = HWMOD_NO_IDLEST,
  2756. };
  2757. #endif
  2758. /* l4_per -> gpio4 */
  2759. static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
  2760. {
  2761. .pa_start = 0x49054000,
  2762. .pa_end = 0x490541ff,
  2763. .flags = ADDR_TYPE_RT
  2764. },
  2765. { }
  2766. };
  2767. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
  2768. .master = &omap3xxx_l4_per_hwmod,
  2769. .slave = &omap3xxx_gpio4_hwmod,
  2770. .addr = omap3xxx_gpio4_addrs,
  2771. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2772. };
  2773. /* l4_per -> gpio5 */
  2774. static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
  2775. {
  2776. .pa_start = 0x49056000,
  2777. .pa_end = 0x490561ff,
  2778. .flags = ADDR_TYPE_RT
  2779. },
  2780. { }
  2781. };
  2782. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
  2783. .master = &omap3xxx_l4_per_hwmod,
  2784. .slave = &omap3xxx_gpio5_hwmod,
  2785. .addr = omap3xxx_gpio5_addrs,
  2786. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2787. };
  2788. /* l4_per -> gpio6 */
  2789. static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
  2790. {
  2791. .pa_start = 0x49058000,
  2792. .pa_end = 0x490581ff,
  2793. .flags = ADDR_TYPE_RT
  2794. },
  2795. { }
  2796. };
  2797. static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
  2798. .master = &omap3xxx_l4_per_hwmod,
  2799. .slave = &omap3xxx_gpio6_hwmod,
  2800. .addr = omap3xxx_gpio6_addrs,
  2801. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2802. };
  2803. /* dma_system -> L3 */
  2804. static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
  2805. .master = &omap3xxx_dma_system_hwmod,
  2806. .slave = &omap3xxx_l3_main_hwmod,
  2807. .clk = "core_l3_ick",
  2808. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2809. };
  2810. static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
  2811. {
  2812. .pa_start = 0x48056000,
  2813. .pa_end = 0x48056fff,
  2814. .flags = ADDR_TYPE_RT
  2815. },
  2816. { }
  2817. };
  2818. /* l4_cfg -> dma_system */
  2819. static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
  2820. .master = &omap3xxx_l4_core_hwmod,
  2821. .slave = &omap3xxx_dma_system_hwmod,
  2822. .clk = "core_l4_ick",
  2823. .addr = omap3xxx_dma_system_addrs,
  2824. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2825. };
  2826. static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
  2827. {
  2828. .name = "mpu",
  2829. .pa_start = 0x48074000,
  2830. .pa_end = 0x480740ff,
  2831. .flags = ADDR_TYPE_RT
  2832. },
  2833. { }
  2834. };
  2835. /* l4_core -> mcbsp1 */
  2836. static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
  2837. .master = &omap3xxx_l4_core_hwmod,
  2838. .slave = &omap3xxx_mcbsp1_hwmod,
  2839. .clk = "mcbsp1_ick",
  2840. .addr = omap3xxx_mcbsp1_addrs,
  2841. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2842. };
  2843. static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
  2844. {
  2845. .name = "mpu",
  2846. .pa_start = 0x49022000,
  2847. .pa_end = 0x490220ff,
  2848. .flags = ADDR_TYPE_RT
  2849. },
  2850. { }
  2851. };
  2852. /* l4_per -> mcbsp2 */
  2853. static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
  2854. .master = &omap3xxx_l4_per_hwmod,
  2855. .slave = &omap3xxx_mcbsp2_hwmod,
  2856. .clk = "mcbsp2_ick",
  2857. .addr = omap3xxx_mcbsp2_addrs,
  2858. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2859. };
  2860. static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
  2861. {
  2862. .name = "mpu",
  2863. .pa_start = 0x49024000,
  2864. .pa_end = 0x490240ff,
  2865. .flags = ADDR_TYPE_RT
  2866. },
  2867. { }
  2868. };
  2869. /* l4_per -> mcbsp3 */
  2870. static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
  2871. .master = &omap3xxx_l4_per_hwmod,
  2872. .slave = &omap3xxx_mcbsp3_hwmod,
  2873. .clk = "mcbsp3_ick",
  2874. .addr = omap3xxx_mcbsp3_addrs,
  2875. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2876. };
  2877. static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
  2878. {
  2879. .name = "mpu",
  2880. .pa_start = 0x49026000,
  2881. .pa_end = 0x490260ff,
  2882. .flags = ADDR_TYPE_RT
  2883. },
  2884. { }
  2885. };
  2886. /* l4_per -> mcbsp4 */
  2887. static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
  2888. .master = &omap3xxx_l4_per_hwmod,
  2889. .slave = &omap3xxx_mcbsp4_hwmod,
  2890. .clk = "mcbsp4_ick",
  2891. .addr = omap3xxx_mcbsp4_addrs,
  2892. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2893. };
  2894. static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
  2895. {
  2896. .name = "mpu",
  2897. .pa_start = 0x48096000,
  2898. .pa_end = 0x480960ff,
  2899. .flags = ADDR_TYPE_RT
  2900. },
  2901. { }
  2902. };
  2903. /* l4_core -> mcbsp5 */
  2904. static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
  2905. .master = &omap3xxx_l4_core_hwmod,
  2906. .slave = &omap3xxx_mcbsp5_hwmod,
  2907. .clk = "mcbsp5_ick",
  2908. .addr = omap3xxx_mcbsp5_addrs,
  2909. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2910. };
  2911. static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
  2912. {
  2913. .name = "sidetone",
  2914. .pa_start = 0x49028000,
  2915. .pa_end = 0x490280ff,
  2916. .flags = ADDR_TYPE_RT
  2917. },
  2918. { }
  2919. };
  2920. /* l4_per -> mcbsp2_sidetone */
  2921. static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
  2922. .master = &omap3xxx_l4_per_hwmod,
  2923. .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
  2924. .clk = "mcbsp2_ick",
  2925. .addr = omap3xxx_mcbsp2_sidetone_addrs,
  2926. .user = OCP_USER_MPU,
  2927. };
  2928. static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
  2929. {
  2930. .name = "sidetone",
  2931. .pa_start = 0x4902A000,
  2932. .pa_end = 0x4902A0ff,
  2933. .flags = ADDR_TYPE_RT
  2934. },
  2935. { }
  2936. };
  2937. /* l4_per -> mcbsp3_sidetone */
  2938. static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
  2939. .master = &omap3xxx_l4_per_hwmod,
  2940. .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
  2941. .clk = "mcbsp3_ick",
  2942. .addr = omap3xxx_mcbsp3_sidetone_addrs,
  2943. .user = OCP_USER_MPU,
  2944. };
  2945. static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
  2946. {
  2947. .pa_start = 0x48094000,
  2948. .pa_end = 0x480941ff,
  2949. .flags = ADDR_TYPE_RT,
  2950. },
  2951. { }
  2952. };
  2953. /* l4_core -> mailbox */
  2954. static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
  2955. .master = &omap3xxx_l4_core_hwmod,
  2956. .slave = &omap3xxx_mailbox_hwmod,
  2957. .addr = omap3xxx_mailbox_addrs,
  2958. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2959. };
  2960. /* l4 core -> mcspi1 interface */
  2961. static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
  2962. .master = &omap3xxx_l4_core_hwmod,
  2963. .slave = &omap34xx_mcspi1,
  2964. .clk = "mcspi1_ick",
  2965. .addr = omap2_mcspi1_addr_space,
  2966. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2967. };
  2968. /* l4 core -> mcspi2 interface */
  2969. static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
  2970. .master = &omap3xxx_l4_core_hwmod,
  2971. .slave = &omap34xx_mcspi2,
  2972. .clk = "mcspi2_ick",
  2973. .addr = omap2_mcspi2_addr_space,
  2974. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2975. };
  2976. /* l4 core -> mcspi3 interface */
  2977. static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
  2978. .master = &omap3xxx_l4_core_hwmod,
  2979. .slave = &omap34xx_mcspi3,
  2980. .clk = "mcspi3_ick",
  2981. .addr = omap2430_mcspi3_addr_space,
  2982. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2983. };
  2984. /* l4 core -> mcspi4 interface */
  2985. static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
  2986. {
  2987. .pa_start = 0x480ba000,
  2988. .pa_end = 0x480ba0ff,
  2989. .flags = ADDR_TYPE_RT,
  2990. },
  2991. { }
  2992. };
  2993. static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
  2994. .master = &omap3xxx_l4_core_hwmod,
  2995. .slave = &omap34xx_mcspi4,
  2996. .clk = "mcspi4_ick",
  2997. .addr = omap34xx_mcspi4_addr_space,
  2998. .user = OCP_USER_MPU | OCP_USER_SDMA,
  2999. };
  3000. static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
  3001. .master = &omap3xxx_usb_host_hs_hwmod,
  3002. .slave = &omap3xxx_l3_main_hwmod,
  3003. .clk = "core_l3_ick",
  3004. .user = OCP_USER_MPU,
  3005. };
  3006. static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
  3007. {
  3008. .name = "uhh",
  3009. .pa_start = 0x48064000,
  3010. .pa_end = 0x480643ff,
  3011. .flags = ADDR_TYPE_RT
  3012. },
  3013. {
  3014. .name = "ohci",
  3015. .pa_start = 0x48064400,
  3016. .pa_end = 0x480647ff,
  3017. },
  3018. {
  3019. .name = "ehci",
  3020. .pa_start = 0x48064800,
  3021. .pa_end = 0x48064cff,
  3022. },
  3023. {}
  3024. };
  3025. static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
  3026. .master = &omap3xxx_l4_core_hwmod,
  3027. .slave = &omap3xxx_usb_host_hs_hwmod,
  3028. .clk = "usbhost_ick",
  3029. .addr = omap3xxx_usb_host_hs_addrs,
  3030. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3031. };
  3032. static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
  3033. {
  3034. .name = "tll",
  3035. .pa_start = 0x48062000,
  3036. .pa_end = 0x48062fff,
  3037. .flags = ADDR_TYPE_RT
  3038. },
  3039. {}
  3040. };
  3041. static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
  3042. .master = &omap3xxx_l4_core_hwmod,
  3043. .slave = &omap3xxx_usb_tll_hs_hwmod,
  3044. .clk = "usbtll_ick",
  3045. .addr = omap3xxx_usb_tll_hs_addrs,
  3046. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3047. };
  3048. /* l4_core -> hdq1w interface */
  3049. static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
  3050. .master = &omap3xxx_l4_core_hwmod,
  3051. .slave = &omap3xxx_hdq1w_hwmod,
  3052. .clk = "hdq_ick",
  3053. .addr = omap2_hdq1w_addr_space,
  3054. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3055. .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
  3056. };
  3057. /* l4_wkup -> 32ksync_counter */
  3058. static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
  3059. {
  3060. .pa_start = 0x48320000,
  3061. .pa_end = 0x4832001f,
  3062. .flags = ADDR_TYPE_RT
  3063. },
  3064. { }
  3065. };
  3066. static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
  3067. {
  3068. .pa_start = 0x6e000000,
  3069. .pa_end = 0x6e000fff,
  3070. .flags = ADDR_TYPE_RT
  3071. },
  3072. { }
  3073. };
  3074. static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
  3075. .master = &omap3xxx_l4_wkup_hwmod,
  3076. .slave = &omap3xxx_counter_32k_hwmod,
  3077. .clk = "omap_32ksync_ick",
  3078. .addr = omap3xxx_counter_32k_addrs,
  3079. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3080. };
  3081. /* am35xx has Davinci MDIO & EMAC */
  3082. static struct omap_hwmod_class am35xx_mdio_class = {
  3083. .name = "davinci_mdio",
  3084. };
  3085. static struct omap_hwmod am35xx_mdio_hwmod = {
  3086. .name = "davinci_mdio",
  3087. .class = &am35xx_mdio_class,
  3088. .flags = HWMOD_NO_IDLEST,
  3089. };
  3090. /*
  3091. * XXX Should be connected to an IPSS hwmod, not the L3 directly;
  3092. * but this will probably require some additional hwmod core support,
  3093. * so is left as a future to-do item.
  3094. */
  3095. static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
  3096. .master = &am35xx_mdio_hwmod,
  3097. .slave = &omap3xxx_l3_main_hwmod,
  3098. .clk = "emac_fck",
  3099. .user = OCP_USER_MPU,
  3100. };
  3101. static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
  3102. {
  3103. .pa_start = AM35XX_IPSS_MDIO_BASE,
  3104. .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
  3105. .flags = ADDR_TYPE_RT,
  3106. },
  3107. { }
  3108. };
  3109. /* l4_core -> davinci mdio */
  3110. /*
  3111. * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
  3112. * but this will probably require some additional hwmod core support,
  3113. * so is left as a future to-do item.
  3114. */
  3115. static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
  3116. .master = &omap3xxx_l4_core_hwmod,
  3117. .slave = &am35xx_mdio_hwmod,
  3118. .clk = "emac_fck",
  3119. .addr = am35xx_mdio_addrs,
  3120. .user = OCP_USER_MPU,
  3121. };
  3122. static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
  3123. { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
  3124. { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
  3125. { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
  3126. { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
  3127. { .irq = -1 },
  3128. };
  3129. static struct omap_hwmod_class am35xx_emac_class = {
  3130. .name = "davinci_emac",
  3131. };
  3132. static struct omap_hwmod am35xx_emac_hwmod = {
  3133. .name = "davinci_emac",
  3134. .mpu_irqs = am35xx_emac_mpu_irqs,
  3135. .class = &am35xx_emac_class,
  3136. .flags = HWMOD_NO_IDLEST,
  3137. };
  3138. /* l3_core -> davinci emac interface */
  3139. /*
  3140. * XXX Should be connected to an IPSS hwmod, not the L3 directly;
  3141. * but this will probably require some additional hwmod core support,
  3142. * so is left as a future to-do item.
  3143. */
  3144. static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
  3145. .master = &am35xx_emac_hwmod,
  3146. .slave = &omap3xxx_l3_main_hwmod,
  3147. .clk = "emac_ick",
  3148. .user = OCP_USER_MPU,
  3149. };
  3150. static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
  3151. {
  3152. .pa_start = AM35XX_IPSS_EMAC_BASE,
  3153. .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
  3154. .flags = ADDR_TYPE_RT,
  3155. },
  3156. { }
  3157. };
  3158. /* l4_core -> davinci emac */
  3159. /*
  3160. * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
  3161. * but this will probably require some additional hwmod core support,
  3162. * so is left as a future to-do item.
  3163. */
  3164. static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
  3165. .master = &omap3xxx_l4_core_hwmod,
  3166. .slave = &am35xx_emac_hwmod,
  3167. .clk = "emac_ick",
  3168. .addr = am35xx_emac_addrs,
  3169. .user = OCP_USER_MPU,
  3170. };
  3171. static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
  3172. .master = &omap3xxx_l3_main_hwmod,
  3173. .slave = &omap3xxx_gpmc_hwmod,
  3174. .clk = "core_l3_ick",
  3175. .addr = omap3xxx_gpmc_addrs,
  3176. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3177. };
  3178. static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
  3179. &omap3xxx_l3_main__l4_core,
  3180. &omap3xxx_l3_main__l4_per,
  3181. &omap3xxx_mpu__l3_main,
  3182. &omap3xxx_l3_main__l4_debugss,
  3183. &omap3xxx_l4_core__l4_wkup,
  3184. &omap3xxx_l4_core__mmc3,
  3185. &omap3_l4_core__uart1,
  3186. &omap3_l4_core__uart2,
  3187. &omap3_l4_per__uart3,
  3188. &omap3_l4_core__i2c1,
  3189. &omap3_l4_core__i2c2,
  3190. &omap3_l4_core__i2c3,
  3191. &omap3xxx_l4_wkup__l4_sec,
  3192. &omap3xxx_l4_wkup__timer1,
  3193. &omap3xxx_l4_per__timer2,
  3194. &omap3xxx_l4_per__timer3,
  3195. &omap3xxx_l4_per__timer4,
  3196. &omap3xxx_l4_per__timer5,
  3197. &omap3xxx_l4_per__timer6,
  3198. &omap3xxx_l4_per__timer7,
  3199. &omap3xxx_l4_per__timer8,
  3200. &omap3xxx_l4_per__timer9,
  3201. &omap3xxx_l4_core__timer10,
  3202. &omap3xxx_l4_core__timer11,
  3203. &omap3xxx_l4_wkup__wd_timer2,
  3204. &omap3xxx_l4_wkup__gpio1,
  3205. &omap3xxx_l4_per__gpio2,
  3206. &omap3xxx_l4_per__gpio3,
  3207. &omap3xxx_l4_per__gpio4,
  3208. &omap3xxx_l4_per__gpio5,
  3209. &omap3xxx_l4_per__gpio6,
  3210. &omap3xxx_dma_system__l3,
  3211. &omap3xxx_l4_core__dma_system,
  3212. &omap3xxx_l4_core__mcbsp1,
  3213. &omap3xxx_l4_per__mcbsp2,
  3214. &omap3xxx_l4_per__mcbsp3,
  3215. &omap3xxx_l4_per__mcbsp4,
  3216. &omap3xxx_l4_core__mcbsp5,
  3217. &omap3xxx_l4_per__mcbsp2_sidetone,
  3218. &omap3xxx_l4_per__mcbsp3_sidetone,
  3219. &omap34xx_l4_core__mcspi1,
  3220. &omap34xx_l4_core__mcspi2,
  3221. &omap34xx_l4_core__mcspi3,
  3222. &omap34xx_l4_core__mcspi4,
  3223. &omap3xxx_l4_wkup__counter_32k,
  3224. &omap3xxx_l3_main__gpmc,
  3225. NULL,
  3226. };
  3227. /* GP-only hwmod links */
  3228. static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
  3229. &omap3xxx_l4_sec__timer12,
  3230. NULL
  3231. };
  3232. /* 3430ES1-only hwmod links */
  3233. static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
  3234. &omap3430es1_dss__l3,
  3235. &omap3430es1_l4_core__dss,
  3236. NULL
  3237. };
  3238. /* 3430ES2+-only hwmod links */
  3239. static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
  3240. &omap3xxx_dss__l3,
  3241. &omap3xxx_l4_core__dss,
  3242. &omap3xxx_usbhsotg__l3,
  3243. &omap3xxx_l4_core__usbhsotg,
  3244. &omap3xxx_usb_host_hs__l3_main_2,
  3245. &omap3xxx_l4_core__usb_host_hs,
  3246. &omap3xxx_l4_core__usb_tll_hs,
  3247. NULL
  3248. };
  3249. /* <= 3430ES3-only hwmod links */
  3250. static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
  3251. &omap3xxx_l4_core__pre_es3_mmc1,
  3252. &omap3xxx_l4_core__pre_es3_mmc2,
  3253. NULL
  3254. };
  3255. /* 3430ES3+-only hwmod links */
  3256. static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
  3257. &omap3xxx_l4_core__es3plus_mmc1,
  3258. &omap3xxx_l4_core__es3plus_mmc2,
  3259. NULL
  3260. };
  3261. /* 34xx-only hwmod links (all ES revisions) */
  3262. static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
  3263. &omap3xxx_l3__iva,
  3264. &omap34xx_l4_core__sr1,
  3265. &omap34xx_l4_core__sr2,
  3266. &omap3xxx_l4_core__mailbox,
  3267. &omap3xxx_l4_core__hdq1w,
  3268. &omap3xxx_sad2d__l3,
  3269. &omap3xxx_l4_core__mmu_isp,
  3270. #ifdef CONFIG_OMAP_IOMMU_IVA2
  3271. &omap3xxx_l3_main__mmu_iva,
  3272. #endif
  3273. NULL
  3274. };
  3275. /* 36xx-only hwmod links (all ES revisions) */
  3276. static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
  3277. &omap3xxx_l3__iva,
  3278. &omap36xx_l4_per__uart4,
  3279. &omap3xxx_dss__l3,
  3280. &omap3xxx_l4_core__dss,
  3281. &omap36xx_l4_core__sr1,
  3282. &omap36xx_l4_core__sr2,
  3283. &omap3xxx_usbhsotg__l3,
  3284. &omap3xxx_l4_core__usbhsotg,
  3285. &omap3xxx_l4_core__mailbox,
  3286. &omap3xxx_usb_host_hs__l3_main_2,
  3287. &omap3xxx_l4_core__usb_host_hs,
  3288. &omap3xxx_l4_core__usb_tll_hs,
  3289. &omap3xxx_l4_core__es3plus_mmc1,
  3290. &omap3xxx_l4_core__es3plus_mmc2,
  3291. &omap3xxx_l4_core__hdq1w,
  3292. &omap3xxx_sad2d__l3,
  3293. &omap3xxx_l4_core__mmu_isp,
  3294. #ifdef CONFIG_OMAP_IOMMU_IVA2
  3295. &omap3xxx_l3_main__mmu_iva,
  3296. #endif
  3297. NULL
  3298. };
  3299. static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
  3300. &omap3xxx_dss__l3,
  3301. &omap3xxx_l4_core__dss,
  3302. &am35xx_usbhsotg__l3,
  3303. &am35xx_l4_core__usbhsotg,
  3304. &am35xx_l4_core__uart4,
  3305. &omap3xxx_usb_host_hs__l3_main_2,
  3306. &omap3xxx_l4_core__usb_host_hs,
  3307. &omap3xxx_l4_core__usb_tll_hs,
  3308. &omap3xxx_l4_core__es3plus_mmc1,
  3309. &omap3xxx_l4_core__es3plus_mmc2,
  3310. &omap3xxx_l4_core__hdq1w,
  3311. &am35xx_mdio__l3,
  3312. &am35xx_l4_core__mdio,
  3313. &am35xx_emac__l3,
  3314. &am35xx_l4_core__emac,
  3315. NULL
  3316. };
  3317. static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
  3318. &omap3xxx_l4_core__dss_dispc,
  3319. &omap3xxx_l4_core__dss_dsi1,
  3320. &omap3xxx_l4_core__dss_rfbi,
  3321. &omap3xxx_l4_core__dss_venc,
  3322. NULL
  3323. };
  3324. int __init omap3xxx_hwmod_init(void)
  3325. {
  3326. int r;
  3327. struct omap_hwmod_ocp_if **h = NULL;
  3328. unsigned int rev;
  3329. omap_hwmod_init();
  3330. /* Register hwmod links common to all OMAP3 */
  3331. r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
  3332. if (r < 0)
  3333. return r;
  3334. /* Register GP-only hwmod links. */
  3335. if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
  3336. r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
  3337. if (r < 0)
  3338. return r;
  3339. }
  3340. rev = omap_rev();
  3341. /*
  3342. * Register hwmod links common to individual OMAP3 families, all
  3343. * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
  3344. * All possible revisions should be included in this conditional.
  3345. */
  3346. if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
  3347. rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
  3348. rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
  3349. h = omap34xx_hwmod_ocp_ifs;
  3350. } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
  3351. h = am35xx_hwmod_ocp_ifs;
  3352. } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
  3353. rev == OMAP3630_REV_ES1_2) {
  3354. h = omap36xx_hwmod_ocp_ifs;
  3355. } else {
  3356. WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
  3357. return -EINVAL;
  3358. }
  3359. r = omap_hwmod_register_links(h);
  3360. if (r < 0)
  3361. return r;
  3362. /*
  3363. * Register hwmod links specific to certain ES levels of a
  3364. * particular family of silicon (e.g., 34xx ES1.0)
  3365. */
  3366. h = NULL;
  3367. if (rev == OMAP3430_REV_ES1_0) {
  3368. h = omap3430es1_hwmod_ocp_ifs;
  3369. } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
  3370. rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
  3371. rev == OMAP3430_REV_ES3_1_2) {
  3372. h = omap3430es2plus_hwmod_ocp_ifs;
  3373. }
  3374. if (h) {
  3375. r = omap_hwmod_register_links(h);
  3376. if (r < 0)
  3377. return r;
  3378. }
  3379. h = NULL;
  3380. if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
  3381. rev == OMAP3430_REV_ES2_1) {
  3382. h = omap3430_pre_es3_hwmod_ocp_ifs;
  3383. } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
  3384. rev == OMAP3430_REV_ES3_1_2) {
  3385. h = omap3430_es3plus_hwmod_ocp_ifs;
  3386. }
  3387. if (h)
  3388. r = omap_hwmod_register_links(h);
  3389. if (r < 0)
  3390. return r;
  3391. /*
  3392. * DSS code presumes that dss_core hwmod is handled first,
  3393. * _before_ any other DSS related hwmods so register common
  3394. * DSS hwmod links last to ensure that dss_core is already
  3395. * registered. Otherwise some change things may happen, for
  3396. * ex. if dispc is handled before dss_core and DSS is enabled
  3397. * in bootloader DISPC will be reset with outputs enabled
  3398. * which sometimes leads to unrecoverable L3 error. XXX The
  3399. * long-term fix to this is to ensure hwmods are set up in
  3400. * dependency order in the hwmod core code.
  3401. */
  3402. r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
  3403. return r;
  3404. }