netxen_nic_init.c 38 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. #if 0
  52. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  53. unsigned long off, int *data)
  54. {
  55. void __iomem *addr = pci_base_offset(adapter, off);
  56. writel(*data, addr);
  57. }
  58. #endif /* 0 */
  59. static void crb_addr_transform_setup(void)
  60. {
  61. crb_addr_transform(XDMA);
  62. crb_addr_transform(TIMR);
  63. crb_addr_transform(SRE);
  64. crb_addr_transform(SQN3);
  65. crb_addr_transform(SQN2);
  66. crb_addr_transform(SQN1);
  67. crb_addr_transform(SQN0);
  68. crb_addr_transform(SQS3);
  69. crb_addr_transform(SQS2);
  70. crb_addr_transform(SQS1);
  71. crb_addr_transform(SQS0);
  72. crb_addr_transform(RPMX7);
  73. crb_addr_transform(RPMX6);
  74. crb_addr_transform(RPMX5);
  75. crb_addr_transform(RPMX4);
  76. crb_addr_transform(RPMX3);
  77. crb_addr_transform(RPMX2);
  78. crb_addr_transform(RPMX1);
  79. crb_addr_transform(RPMX0);
  80. crb_addr_transform(ROMUSB);
  81. crb_addr_transform(SN);
  82. crb_addr_transform(QMN);
  83. crb_addr_transform(QMS);
  84. crb_addr_transform(PGNI);
  85. crb_addr_transform(PGND);
  86. crb_addr_transform(PGN3);
  87. crb_addr_transform(PGN2);
  88. crb_addr_transform(PGN1);
  89. crb_addr_transform(PGN0);
  90. crb_addr_transform(PGSI);
  91. crb_addr_transform(PGSD);
  92. crb_addr_transform(PGS3);
  93. crb_addr_transform(PGS2);
  94. crb_addr_transform(PGS1);
  95. crb_addr_transform(PGS0);
  96. crb_addr_transform(PS);
  97. crb_addr_transform(PH);
  98. crb_addr_transform(NIU);
  99. crb_addr_transform(I2Q);
  100. crb_addr_transform(EG);
  101. crb_addr_transform(MN);
  102. crb_addr_transform(MS);
  103. crb_addr_transform(CAS2);
  104. crb_addr_transform(CAS1);
  105. crb_addr_transform(CAS0);
  106. crb_addr_transform(CAM);
  107. crb_addr_transform(C2C1);
  108. crb_addr_transform(C2C0);
  109. crb_addr_transform(SMB);
  110. crb_addr_transform(OCM0);
  111. crb_addr_transform(I2C0);
  112. }
  113. int netxen_init_firmware(struct netxen_adapter *adapter)
  114. {
  115. u32 state = 0, loops = 0, err = 0;
  116. /* Window 1 call */
  117. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  118. if (state == PHAN_INITIALIZE_ACK)
  119. return 0;
  120. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  121. msleep(1);
  122. /* Window 1 call */
  123. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  124. loops++;
  125. }
  126. if (loops >= 2000) {
  127. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  128. state);
  129. err = -EIO;
  130. return err;
  131. }
  132. /* Window 1 call */
  133. adapter->pci_write_normalize(adapter,
  134. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  135. adapter->pci_write_normalize(adapter,
  136. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  137. adapter->pci_write_normalize(adapter,
  138. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  139. adapter->pci_write_normalize(adapter,
  140. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  141. return err;
  142. }
  143. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  144. {
  145. struct netxen_recv_context *recv_ctx;
  146. struct nx_host_rds_ring *rds_ring;
  147. struct netxen_rx_buffer *rx_buf;
  148. int i, ctxid, ring;
  149. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  150. recv_ctx = &adapter->recv_ctx[ctxid];
  151. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  152. rds_ring = &recv_ctx->rds_rings[ring];
  153. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  154. rx_buf = &(rds_ring->rx_buf_arr[i]);
  155. if (rx_buf->state == NETXEN_BUFFER_FREE)
  156. continue;
  157. pci_unmap_single(adapter->pdev,
  158. rx_buf->dma,
  159. rds_ring->dma_size,
  160. PCI_DMA_FROMDEVICE);
  161. if (rx_buf->skb != NULL)
  162. dev_kfree_skb_any(rx_buf->skb);
  163. }
  164. }
  165. }
  166. }
  167. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  168. {
  169. struct netxen_cmd_buffer *cmd_buf;
  170. struct netxen_skb_frag *buffrag;
  171. int i, j;
  172. cmd_buf = adapter->cmd_buf_arr;
  173. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  174. buffrag = cmd_buf->frag_array;
  175. if (buffrag->dma) {
  176. pci_unmap_single(adapter->pdev, buffrag->dma,
  177. buffrag->length, PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. for (j = 0; j < cmd_buf->frag_count; j++) {
  181. buffrag++;
  182. if (buffrag->dma) {
  183. pci_unmap_page(adapter->pdev, buffrag->dma,
  184. buffrag->length,
  185. PCI_DMA_TODEVICE);
  186. buffrag->dma = 0ULL;
  187. }
  188. }
  189. /* Free the skb we received in netxen_nic_xmit_frame */
  190. if (cmd_buf->skb) {
  191. dev_kfree_skb_any(cmd_buf->skb);
  192. cmd_buf->skb = NULL;
  193. }
  194. cmd_buf++;
  195. }
  196. }
  197. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  198. {
  199. struct netxen_recv_context *recv_ctx;
  200. struct nx_host_rds_ring *rds_ring;
  201. int ctx, ring;
  202. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  203. recv_ctx = &adapter->recv_ctx[ctx];
  204. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  205. rds_ring = &recv_ctx->rds_rings[ring];
  206. if (rds_ring->rx_buf_arr) {
  207. vfree(rds_ring->rx_buf_arr);
  208. rds_ring->rx_buf_arr = NULL;
  209. }
  210. }
  211. }
  212. if (adapter->cmd_buf_arr)
  213. vfree(adapter->cmd_buf_arr);
  214. return;
  215. }
  216. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  217. {
  218. struct netxen_recv_context *recv_ctx;
  219. struct nx_host_rds_ring *rds_ring;
  220. struct netxen_rx_buffer *rx_buf;
  221. int ctx, ring, i, num_rx_bufs;
  222. struct netxen_cmd_buffer *cmd_buf_arr;
  223. struct net_device *netdev = adapter->netdev;
  224. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  225. if (cmd_buf_arr == NULL) {
  226. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  227. netdev->name);
  228. return -ENOMEM;
  229. }
  230. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  231. adapter->cmd_buf_arr = cmd_buf_arr;
  232. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  233. recv_ctx = &adapter->recv_ctx[ctx];
  234. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  235. rds_ring = &recv_ctx->rds_rings[ring];
  236. switch (RCV_DESC_TYPE(ring)) {
  237. case RCV_DESC_NORMAL:
  238. rds_ring->max_rx_desc_count =
  239. adapter->max_rx_desc_count;
  240. rds_ring->flags = RCV_DESC_NORMAL;
  241. rds_ring->dma_size = RX_DMA_MAP_LEN;
  242. rds_ring->skb_size = MAX_RX_BUFFER_LENGTH;
  243. break;
  244. case RCV_DESC_JUMBO:
  245. rds_ring->max_rx_desc_count =
  246. adapter->max_jumbo_rx_desc_count;
  247. rds_ring->flags = RCV_DESC_JUMBO;
  248. rds_ring->dma_size = RX_JUMBO_DMA_MAP_LEN;
  249. rds_ring->skb_size =
  250. MAX_RX_JUMBO_BUFFER_LENGTH;
  251. break;
  252. case RCV_RING_LRO:
  253. rds_ring->max_rx_desc_count =
  254. adapter->max_lro_rx_desc_count;
  255. rds_ring->flags = RCV_DESC_LRO;
  256. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  257. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  258. break;
  259. }
  260. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  261. vmalloc(RCV_BUFFSIZE);
  262. if (rds_ring->rx_buf_arr == NULL) {
  263. printk(KERN_ERR "%s: Failed to allocate "
  264. "rx buffer ring %d\n",
  265. netdev->name, ring);
  266. /* free whatever was already allocated */
  267. goto err_out;
  268. }
  269. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  270. rds_ring->begin_alloc = 0;
  271. /*
  272. * Now go through all of them, set reference handles
  273. * and put them in the queues.
  274. */
  275. num_rx_bufs = rds_ring->max_rx_desc_count;
  276. rx_buf = rds_ring->rx_buf_arr;
  277. for (i = 0; i < num_rx_bufs; i++) {
  278. rx_buf->ref_handle = i;
  279. rx_buf->state = NETXEN_BUFFER_FREE;
  280. rx_buf++;
  281. }
  282. }
  283. }
  284. return 0;
  285. err_out:
  286. netxen_free_sw_resources(adapter);
  287. return -ENOMEM;
  288. }
  289. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  290. {
  291. switch (adapter->ahw.board_type) {
  292. case NETXEN_NIC_GBE:
  293. adapter->enable_phy_interrupts =
  294. netxen_niu_gbe_enable_phy_interrupts;
  295. adapter->disable_phy_interrupts =
  296. netxen_niu_gbe_disable_phy_interrupts;
  297. adapter->macaddr_set = netxen_niu_macaddr_set;
  298. adapter->set_mtu = netxen_nic_set_mtu_gb;
  299. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  300. adapter->phy_read = netxen_niu_gbe_phy_read;
  301. adapter->phy_write = netxen_niu_gbe_phy_write;
  302. adapter->init_niu = netxen_nic_init_niu_gb;
  303. adapter->stop_port = netxen_niu_disable_gbe_port;
  304. break;
  305. case NETXEN_NIC_XGBE:
  306. adapter->enable_phy_interrupts =
  307. netxen_niu_xgbe_enable_phy_interrupts;
  308. adapter->disable_phy_interrupts =
  309. netxen_niu_xgbe_disable_phy_interrupts;
  310. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  311. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  312. adapter->init_port = netxen_niu_xg_init_port;
  313. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  314. adapter->stop_port = netxen_niu_disable_xg_port;
  315. break;
  316. default:
  317. break;
  318. }
  319. }
  320. /*
  321. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  322. * address to external PCI CRB address.
  323. */
  324. static u32 netxen_decode_crb_addr(u32 addr)
  325. {
  326. int i;
  327. u32 base_addr, offset, pci_base;
  328. crb_addr_transform_setup();
  329. pci_base = NETXEN_ADDR_ERROR;
  330. base_addr = addr & 0xfff00000;
  331. offset = addr & 0x000fffff;
  332. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  333. if (crb_addr_xform[i] == base_addr) {
  334. pci_base = i << 20;
  335. break;
  336. }
  337. }
  338. if (pci_base == NETXEN_ADDR_ERROR)
  339. return pci_base;
  340. else
  341. return (pci_base + offset);
  342. }
  343. static long rom_max_timeout = 100;
  344. static long rom_lock_timeout = 10000;
  345. #if 0
  346. static long rom_write_timeout = 700;
  347. #endif
  348. static int rom_lock(struct netxen_adapter *adapter)
  349. {
  350. int iter;
  351. u32 done = 0;
  352. int timeout = 0;
  353. while (!done) {
  354. /* acquire semaphore2 from PCI HW block */
  355. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  356. &done);
  357. if (done == 1)
  358. break;
  359. if (timeout >= rom_lock_timeout)
  360. return -EIO;
  361. timeout++;
  362. /*
  363. * Yield CPU
  364. */
  365. if (!in_atomic())
  366. schedule();
  367. else {
  368. for (iter = 0; iter < 20; iter++)
  369. cpu_relax(); /*This a nop instr on i386 */
  370. }
  371. }
  372. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  373. return 0;
  374. }
  375. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  376. {
  377. long timeout = 0;
  378. long done = 0;
  379. while (done == 0) {
  380. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  381. done &= 2;
  382. timeout++;
  383. if (timeout >= rom_max_timeout) {
  384. printk("Timeout reached waiting for rom done");
  385. return -EIO;
  386. }
  387. }
  388. return 0;
  389. }
  390. #if 0
  391. static int netxen_rom_wren(struct netxen_adapter *adapter)
  392. {
  393. /* Set write enable latch in ROM status register */
  394. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  395. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  396. M25P_INSTR_WREN);
  397. if (netxen_wait_rom_done(adapter)) {
  398. return -1;
  399. }
  400. return 0;
  401. }
  402. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  403. unsigned int addr)
  404. {
  405. unsigned int data = 0xdeaddead;
  406. data = netxen_nic_reg_read(adapter, addr);
  407. return data;
  408. }
  409. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  410. {
  411. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  412. M25P_INSTR_RDSR);
  413. if (netxen_wait_rom_done(adapter)) {
  414. return -1;
  415. }
  416. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  417. }
  418. #endif
  419. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  420. {
  421. u32 val;
  422. /* release semaphore2 */
  423. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  424. }
  425. #if 0
  426. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  427. {
  428. long timeout = 0;
  429. long wip = 1;
  430. int val;
  431. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  432. while (wip != 0) {
  433. val = netxen_do_rom_rdsr(adapter);
  434. wip = val & 1;
  435. timeout++;
  436. if (timeout > rom_max_timeout) {
  437. return -1;
  438. }
  439. }
  440. return 0;
  441. }
  442. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  443. int data)
  444. {
  445. if (netxen_rom_wren(adapter)) {
  446. return -1;
  447. }
  448. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  449. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  450. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  451. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  452. M25P_INSTR_PP);
  453. if (netxen_wait_rom_done(adapter)) {
  454. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  455. return -1;
  456. }
  457. return netxen_rom_wip_poll(adapter);
  458. }
  459. #endif
  460. static int do_rom_fast_read(struct netxen_adapter *adapter,
  461. int addr, int *valp)
  462. {
  463. cond_resched();
  464. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  465. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  466. udelay(100); /* prevent bursting on CRB */
  467. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  468. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  469. if (netxen_wait_rom_done(adapter)) {
  470. printk("Error waiting for rom done\n");
  471. return -EIO;
  472. }
  473. /* reset abyte_cnt and dummy_byte_cnt */
  474. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  475. udelay(100); /* prevent bursting on CRB */
  476. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  477. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  478. return 0;
  479. }
  480. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  481. u8 *bytes, size_t size)
  482. {
  483. int addridx;
  484. int ret = 0;
  485. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  486. int v;
  487. ret = do_rom_fast_read(adapter, addridx, &v);
  488. if (ret != 0)
  489. break;
  490. *(__le32 *)bytes = cpu_to_le32(v);
  491. bytes += 4;
  492. }
  493. return ret;
  494. }
  495. int
  496. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  497. u8 *bytes, size_t size)
  498. {
  499. int ret;
  500. ret = rom_lock(adapter);
  501. if (ret < 0)
  502. return ret;
  503. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  504. netxen_rom_unlock(adapter);
  505. return ret;
  506. }
  507. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  508. {
  509. int ret;
  510. if (rom_lock(adapter) != 0)
  511. return -EIO;
  512. ret = do_rom_fast_read(adapter, addr, valp);
  513. netxen_rom_unlock(adapter);
  514. return ret;
  515. }
  516. #if 0
  517. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  518. {
  519. int ret = 0;
  520. if (rom_lock(adapter) != 0) {
  521. return -1;
  522. }
  523. ret = do_rom_fast_write(adapter, addr, data);
  524. netxen_rom_unlock(adapter);
  525. return ret;
  526. }
  527. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  528. int addr, u8 *bytes, size_t size)
  529. {
  530. int addridx = addr;
  531. int ret = 0;
  532. while (addridx < (addr + size)) {
  533. int last_attempt = 0;
  534. int timeout = 0;
  535. int data;
  536. data = le32_to_cpu((*(__le32*)bytes));
  537. ret = do_rom_fast_write(adapter, addridx, data);
  538. if (ret < 0)
  539. return ret;
  540. while(1) {
  541. int data1;
  542. ret = do_rom_fast_read(adapter, addridx, &data1);
  543. if (ret < 0)
  544. return ret;
  545. if (data1 == data)
  546. break;
  547. if (timeout++ >= rom_write_timeout) {
  548. if (last_attempt++ < 4) {
  549. ret = do_rom_fast_write(adapter,
  550. addridx, data);
  551. if (ret < 0)
  552. return ret;
  553. }
  554. else {
  555. printk(KERN_INFO "Data write did not "
  556. "succeed at address 0x%x\n", addridx);
  557. break;
  558. }
  559. }
  560. }
  561. bytes += 4;
  562. addridx += 4;
  563. }
  564. return ret;
  565. }
  566. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  567. u8 *bytes, size_t size)
  568. {
  569. int ret = 0;
  570. ret = rom_lock(adapter);
  571. if (ret < 0)
  572. return ret;
  573. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  574. netxen_rom_unlock(adapter);
  575. return ret;
  576. }
  577. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  578. {
  579. int ret;
  580. ret = netxen_rom_wren(adapter);
  581. if (ret < 0)
  582. return ret;
  583. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  584. netxen_crb_writelit_adapter(adapter,
  585. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  586. ret = netxen_wait_rom_done(adapter);
  587. if (ret < 0)
  588. return ret;
  589. return netxen_rom_wip_poll(adapter);
  590. }
  591. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  592. {
  593. int ret;
  594. ret = rom_lock(adapter);
  595. if (ret < 0)
  596. return ret;
  597. ret = netxen_do_rom_rdsr(adapter);
  598. netxen_rom_unlock(adapter);
  599. return ret;
  600. }
  601. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  602. {
  603. int ret = FLASH_SUCCESS;
  604. int val;
  605. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  606. if (!buffer)
  607. return -ENOMEM;
  608. /* unlock sector 63 */
  609. val = netxen_rom_rdsr(adapter);
  610. val = val & 0xe3;
  611. ret = netxen_rom_wrsr(adapter, val);
  612. if (ret != FLASH_SUCCESS)
  613. goto out_kfree;
  614. ret = netxen_rom_wip_poll(adapter);
  615. if (ret != FLASH_SUCCESS)
  616. goto out_kfree;
  617. /* copy sector 0 to sector 63 */
  618. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  619. buffer, NETXEN_FLASH_SECTOR_SIZE);
  620. if (ret != FLASH_SUCCESS)
  621. goto out_kfree;
  622. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  623. buffer, NETXEN_FLASH_SECTOR_SIZE);
  624. if (ret != FLASH_SUCCESS)
  625. goto out_kfree;
  626. /* lock sector 63 */
  627. val = netxen_rom_rdsr(adapter);
  628. if (!(val & 0x8)) {
  629. val |= (0x1 << 2);
  630. /* lock sector 63 */
  631. if (netxen_rom_wrsr(adapter, val) == 0) {
  632. ret = netxen_rom_wip_poll(adapter);
  633. if (ret != FLASH_SUCCESS)
  634. goto out_kfree;
  635. /* lock SR writes */
  636. ret = netxen_rom_wip_poll(adapter);
  637. if (ret != FLASH_SUCCESS)
  638. goto out_kfree;
  639. }
  640. }
  641. out_kfree:
  642. kfree(buffer);
  643. return ret;
  644. }
  645. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  646. {
  647. netxen_rom_wren(adapter);
  648. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  649. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  650. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  651. M25P_INSTR_SE);
  652. if (netxen_wait_rom_done(adapter)) {
  653. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  654. return -1;
  655. }
  656. return netxen_rom_wip_poll(adapter);
  657. }
  658. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  659. {
  660. int i;
  661. int val;
  662. int count = 0, erased_errors = 0;
  663. int range;
  664. range = (addr == NETXEN_USER_START) ?
  665. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  666. for (i = addr; i < range; i += 4) {
  667. netxen_rom_fast_read(adapter, i, &val);
  668. if (val != 0xffffffff)
  669. erased_errors++;
  670. count++;
  671. }
  672. if (erased_errors)
  673. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  674. "for sector address: %x\n", erased_errors, count, addr);
  675. }
  676. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  677. {
  678. int ret = 0;
  679. if (rom_lock(adapter) != 0) {
  680. return -1;
  681. }
  682. ret = netxen_do_rom_se(adapter, addr);
  683. netxen_rom_unlock(adapter);
  684. msleep(30);
  685. check_erased_flash(adapter, addr);
  686. return ret;
  687. }
  688. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  689. int start, int end)
  690. {
  691. int ret = FLASH_SUCCESS;
  692. int i;
  693. for (i = start; i < end; i++) {
  694. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  695. if (ret)
  696. break;
  697. ret = netxen_rom_wip_poll(adapter);
  698. if (ret < 0)
  699. return ret;
  700. }
  701. return ret;
  702. }
  703. int
  704. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  705. {
  706. int ret = FLASH_SUCCESS;
  707. int start, end;
  708. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  709. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  710. ret = netxen_flash_erase_sections(adapter, start, end);
  711. return ret;
  712. }
  713. int
  714. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  715. {
  716. int ret = FLASH_SUCCESS;
  717. int start, end;
  718. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  719. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  720. ret = netxen_flash_erase_sections(adapter, start, end);
  721. return ret;
  722. }
  723. void netxen_halt_pegs(struct netxen_adapter *adapter)
  724. {
  725. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  726. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  727. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  728. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  729. }
  730. int netxen_flash_unlock(struct netxen_adapter *adapter)
  731. {
  732. int ret = 0;
  733. ret = netxen_rom_wrsr(adapter, 0);
  734. if (ret < 0)
  735. return ret;
  736. ret = netxen_rom_wren(adapter);
  737. if (ret < 0)
  738. return ret;
  739. return ret;
  740. }
  741. #endif /* 0 */
  742. #define NETXEN_BOARDTYPE 0x4008
  743. #define NETXEN_BOARDNUM 0x400c
  744. #define NETXEN_CHIPNUM 0x4010
  745. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  746. {
  747. int addr, val;
  748. int i, init_delay = 0;
  749. struct crb_addr_pair *buf;
  750. unsigned offset, n;
  751. u32 off;
  752. /* resetall */
  753. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  754. 0xffffffff);
  755. if (verbose) {
  756. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  757. printk("P2 ROM board type: 0x%08x\n", val);
  758. else
  759. printk("Could not read board type\n");
  760. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  761. printk("P2 ROM board num: 0x%08x\n", val);
  762. else
  763. printk("Could not read board number\n");
  764. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  765. printk("P2 ROM chip num: 0x%08x\n", val);
  766. else
  767. printk("Could not read chip number\n");
  768. }
  769. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  770. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  771. (n != 0xcafecafeUL) ||
  772. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  773. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  774. "n: %08x\n", netxen_nic_driver_name, n);
  775. return -EIO;
  776. }
  777. offset = n & 0xffffU;
  778. n = (n >> 16) & 0xffffU;
  779. } else {
  780. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  781. !(n & 0x80000000)) {
  782. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  783. "n: %08x\n", netxen_nic_driver_name, n);
  784. return -EIO;
  785. }
  786. offset = 1;
  787. n &= ~0x80000000;
  788. }
  789. if (n < 1024) {
  790. if (verbose)
  791. printk(KERN_DEBUG "%s: %d CRB init values found"
  792. " in ROM.\n", netxen_nic_driver_name, n);
  793. } else {
  794. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  795. " initialized.\n", __func__, n);
  796. return -EIO;
  797. }
  798. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  799. if (buf == NULL) {
  800. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  801. netxen_nic_driver_name);
  802. return -ENOMEM;
  803. }
  804. for (i = 0; i < n; i++) {
  805. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  806. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0)
  807. return -EIO;
  808. buf[i].addr = addr;
  809. buf[i].data = val;
  810. if (verbose)
  811. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  812. netxen_nic_driver_name,
  813. (u32)netxen_decode_crb_addr(addr), val);
  814. }
  815. for (i = 0; i < n; i++) {
  816. off = netxen_decode_crb_addr(buf[i].addr);
  817. if (off == NETXEN_ADDR_ERROR) {
  818. printk(KERN_ERR"CRB init value out of range %x\n",
  819. buf[i].addr);
  820. continue;
  821. }
  822. off += NETXEN_PCI_CRBSPACE;
  823. /* skipping cold reboot MAGIC */
  824. if (off == NETXEN_CAM_RAM(0x1fc))
  825. continue;
  826. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  827. /* do not reset PCI */
  828. if (off == (ROMUSB_GLB + 0xbc))
  829. continue;
  830. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  831. buf[i].data = 0x1020;
  832. /* skip the function enable register */
  833. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  834. continue;
  835. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  836. continue;
  837. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  838. continue;
  839. }
  840. if (off == NETXEN_ADDR_ERROR) {
  841. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  842. netxen_nic_driver_name, buf[i].addr);
  843. continue;
  844. }
  845. /* After writing this register, HW needs time for CRB */
  846. /* to quiet down (else crb_window returns 0xffffffff) */
  847. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  848. init_delay = 1;
  849. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  850. /* hold xdma in reset also */
  851. buf[i].data = NETXEN_NIC_XDMA_RESET;
  852. }
  853. }
  854. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  855. if (init_delay == 1) {
  856. msleep(1000);
  857. init_delay = 0;
  858. }
  859. msleep(1);
  860. }
  861. kfree(buf);
  862. /* disable_peg_cache_all */
  863. /* unreset_net_cache */
  864. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  865. adapter->hw_read_wx(adapter,
  866. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  867. netxen_crb_writelit_adapter(adapter,
  868. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  869. }
  870. /* p2dn replyCount */
  871. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  872. /* disable_peg_cache 0 */
  873. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  874. /* disable_peg_cache 1 */
  875. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  876. /* peg_clr_all */
  877. /* peg_clr 0 */
  878. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  879. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  880. /* peg_clr 1 */
  881. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  882. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  883. /* peg_clr 2 */
  884. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  885. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  886. /* peg_clr 3 */
  887. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  888. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  889. return 0;
  890. }
  891. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  892. {
  893. uint64_t addr;
  894. uint32_t hi;
  895. uint32_t lo;
  896. adapter->dummy_dma.addr =
  897. pci_alloc_consistent(adapter->pdev,
  898. NETXEN_HOST_DUMMY_DMA_SIZE,
  899. &adapter->dummy_dma.phys_addr);
  900. if (adapter->dummy_dma.addr == NULL) {
  901. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  902. __func__);
  903. return -ENOMEM;
  904. }
  905. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  906. hi = (addr >> 32) & 0xffffffff;
  907. lo = addr & 0xffffffff;
  908. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  909. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  910. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  911. uint32_t temp = 0;
  912. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  913. }
  914. return 0;
  915. }
  916. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  917. {
  918. int i;
  919. if (adapter->dummy_dma.addr) {
  920. i = 100;
  921. do {
  922. if (dma_watchdog_shutdown_request(adapter) == 1)
  923. break;
  924. msleep(50);
  925. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  926. break;
  927. } while (--i);
  928. if (i) {
  929. pci_free_consistent(adapter->pdev,
  930. NETXEN_HOST_DUMMY_DMA_SIZE,
  931. adapter->dummy_dma.addr,
  932. adapter->dummy_dma.phys_addr);
  933. adapter->dummy_dma.addr = NULL;
  934. } else {
  935. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  936. adapter->netdev->name);
  937. }
  938. }
  939. }
  940. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  941. {
  942. u32 val = 0;
  943. int retries = 60;
  944. if (!pegtune_val) {
  945. do {
  946. val = adapter->pci_read_normalize(adapter,
  947. CRB_CMDPEG_STATE);
  948. if (val == PHAN_INITIALIZE_COMPLETE ||
  949. val == PHAN_INITIALIZE_ACK)
  950. return 0;
  951. msleep(500);
  952. } while (--retries);
  953. if (!retries) {
  954. pegtune_val = adapter->pci_read_normalize(adapter,
  955. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  956. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  957. "pegtune_val=%x\n", pegtune_val);
  958. return -1;
  959. }
  960. }
  961. return 0;
  962. }
  963. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  964. {
  965. u32 val = 0;
  966. int retries = 2000;
  967. do {
  968. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  969. if (val == PHAN_PEG_RCV_INITIALIZED)
  970. return 0;
  971. msleep(10);
  972. } while (--retries);
  973. if (!retries) {
  974. printk(KERN_ERR "Receive Peg initialization not "
  975. "complete, state: 0x%x.\n", val);
  976. return -EIO;
  977. }
  978. return 0;
  979. }
  980. /*
  981. * netxen_process_rcv() send the received packet to the protocol stack.
  982. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  983. * invoke the routine to send more rx buffers to the Phantom...
  984. */
  985. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  986. struct status_desc *desc)
  987. {
  988. struct pci_dev *pdev = adapter->pdev;
  989. struct net_device *netdev = adapter->netdev;
  990. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  991. int index = netxen_get_sts_refhandle(sts_data);
  992. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  993. struct netxen_rx_buffer *buffer;
  994. struct sk_buff *skb;
  995. u32 length = netxen_get_sts_totallength(sts_data);
  996. u32 desc_ctx;
  997. struct nx_host_rds_ring *rds_ring;
  998. int ret;
  999. desc_ctx = netxen_get_sts_type(sts_data);
  1000. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  1001. printk("%s: %s Bad Rcv descriptor ring\n",
  1002. netxen_nic_driver_name, netdev->name);
  1003. return;
  1004. }
  1005. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  1006. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  1007. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  1008. index, rds_ring->max_rx_desc_count);
  1009. return;
  1010. }
  1011. buffer = &rds_ring->rx_buf_arr[index];
  1012. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1013. buffer->lro_current_frags++;
  1014. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  1015. buffer->lro_expected_frags =
  1016. netxen_get_sts_desc_lro_cnt(desc);
  1017. buffer->lro_length = length;
  1018. }
  1019. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  1020. if (buffer->lro_expected_frags != 0) {
  1021. printk("LRO: (refhandle:%x) recv frag. "
  1022. "wait for last. flags: %x expected:%d "
  1023. "have:%d\n", index,
  1024. netxen_get_sts_desc_lro_last_frag(desc),
  1025. buffer->lro_expected_frags,
  1026. buffer->lro_current_frags);
  1027. }
  1028. return;
  1029. }
  1030. }
  1031. pci_unmap_single(pdev, buffer->dma, rds_ring->dma_size,
  1032. PCI_DMA_FROMDEVICE);
  1033. skb = (struct sk_buff *)buffer->skb;
  1034. if (likely(adapter->rx_csum &&
  1035. netxen_get_sts_status(sts_data) == STATUS_CKSUM_OK)) {
  1036. adapter->stats.csummed++;
  1037. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1038. } else
  1039. skb->ip_summed = CHECKSUM_NONE;
  1040. skb->dev = netdev;
  1041. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1042. /* True length was only available on the last pkt */
  1043. skb_put(skb, buffer->lro_length);
  1044. } else {
  1045. skb_put(skb, length);
  1046. }
  1047. skb->protocol = eth_type_trans(skb, netdev);
  1048. ret = netif_receive_skb(skb);
  1049. netdev->last_rx = jiffies;
  1050. /*
  1051. * We just consumed one buffer so post a buffer.
  1052. */
  1053. buffer->skb = NULL;
  1054. buffer->state = NETXEN_BUFFER_FREE;
  1055. buffer->lro_current_frags = 0;
  1056. buffer->lro_expected_frags = 0;
  1057. adapter->stats.no_rcv++;
  1058. adapter->stats.rxbytes += length;
  1059. }
  1060. /* Process Receive status ring */
  1061. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1062. {
  1063. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1064. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1065. struct status_desc *desc; /* used to read status desc here */
  1066. u32 consumer = recv_ctx->status_rx_consumer;
  1067. int count = 0, ring;
  1068. while (count < max) {
  1069. desc = &desc_head[consumer];
  1070. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1071. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1072. netxen_get_sts_owner(desc));
  1073. break;
  1074. }
  1075. netxen_process_rcv(adapter, ctxid, desc);
  1076. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1077. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1078. count++;
  1079. }
  1080. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  1081. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1082. /* update the consumer index in phantom */
  1083. if (count) {
  1084. recv_ctx->status_rx_consumer = consumer;
  1085. /* Window = 1 */
  1086. adapter->pci_write_normalize(adapter,
  1087. recv_ctx->crb_sts_consumer, consumer);
  1088. }
  1089. return count;
  1090. }
  1091. /* Process Command status ring */
  1092. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1093. {
  1094. u32 last_consumer, consumer;
  1095. int count = 0, i;
  1096. struct netxen_cmd_buffer *buffer;
  1097. struct pci_dev *pdev = adapter->pdev;
  1098. struct net_device *netdev = adapter->netdev;
  1099. struct netxen_skb_frag *frag;
  1100. int done = 0;
  1101. last_consumer = adapter->last_cmd_consumer;
  1102. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1103. while (last_consumer != consumer) {
  1104. buffer = &adapter->cmd_buf_arr[last_consumer];
  1105. if (buffer->skb) {
  1106. frag = &buffer->frag_array[0];
  1107. pci_unmap_single(pdev, frag->dma, frag->length,
  1108. PCI_DMA_TODEVICE);
  1109. frag->dma = 0ULL;
  1110. for (i = 1; i < buffer->frag_count; i++) {
  1111. frag++; /* Get the next frag */
  1112. pci_unmap_page(pdev, frag->dma, frag->length,
  1113. PCI_DMA_TODEVICE);
  1114. frag->dma = 0ULL;
  1115. }
  1116. adapter->stats.xmitfinished++;
  1117. dev_kfree_skb_any(buffer->skb);
  1118. buffer->skb = NULL;
  1119. }
  1120. last_consumer = get_next_index(last_consumer,
  1121. adapter->max_tx_desc_count);
  1122. if (++count >= MAX_STATUS_HANDLE)
  1123. break;
  1124. }
  1125. if (count) {
  1126. adapter->last_cmd_consumer = last_consumer;
  1127. smp_mb();
  1128. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1129. netif_tx_lock(netdev);
  1130. netif_wake_queue(netdev);
  1131. smp_mb();
  1132. netif_tx_unlock(netdev);
  1133. }
  1134. }
  1135. /*
  1136. * If everything is freed up to consumer then check if the ring is full
  1137. * If the ring is full then check if more needs to be freed and
  1138. * schedule the call back again.
  1139. *
  1140. * This happens when there are 2 CPUs. One could be freeing and the
  1141. * other filling it. If the ring is full when we get out of here and
  1142. * the card has already interrupted the host then the host can miss the
  1143. * interrupt.
  1144. *
  1145. * There is still a possible race condition and the host could miss an
  1146. * interrupt. The card has to take care of this.
  1147. */
  1148. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1149. done = (last_consumer == consumer);
  1150. return (done);
  1151. }
  1152. /*
  1153. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1154. */
  1155. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1156. {
  1157. struct pci_dev *pdev = adapter->pdev;
  1158. struct sk_buff *skb;
  1159. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1160. struct nx_host_rds_ring *rds_ring = NULL;
  1161. uint producer;
  1162. struct rcv_desc *pdesc;
  1163. struct netxen_rx_buffer *buffer;
  1164. int count = 0;
  1165. int index = 0;
  1166. netxen_ctx_msg msg = 0;
  1167. dma_addr_t dma;
  1168. rds_ring = &recv_ctx->rds_rings[ringid];
  1169. producer = rds_ring->producer;
  1170. index = rds_ring->begin_alloc;
  1171. buffer = &rds_ring->rx_buf_arr[index];
  1172. /* We can start writing rx descriptors into the phantom memory. */
  1173. while (buffer->state == NETXEN_BUFFER_FREE) {
  1174. skb = dev_alloc_skb(rds_ring->skb_size);
  1175. if (unlikely(!skb)) {
  1176. /*
  1177. * TODO
  1178. * We need to schedule the posting of buffers to the pegs.
  1179. */
  1180. rds_ring->begin_alloc = index;
  1181. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1182. " allocated only %d buffers\n", count);
  1183. break;
  1184. }
  1185. count++; /* now there should be no failure */
  1186. pdesc = &rds_ring->desc_head[producer];
  1187. #if defined(XGB_DEBUG)
  1188. *(unsigned long *)(skb->head) = 0xc0debabe;
  1189. if (skb_is_nonlinear(skb)) {
  1190. printk("Allocated SKB @%p is nonlinear\n");
  1191. }
  1192. #endif
  1193. skb_reserve(skb, 2);
  1194. /* This will be setup when we receive the
  1195. * buffer after it has been filled FSL TBD TBD
  1196. * skb->dev = netdev;
  1197. */
  1198. dma = pci_map_single(pdev, skb->data, rds_ring->dma_size,
  1199. PCI_DMA_FROMDEVICE);
  1200. pdesc->addr_buffer = cpu_to_le64(dma);
  1201. buffer->skb = skb;
  1202. buffer->state = NETXEN_BUFFER_BUSY;
  1203. buffer->dma = dma;
  1204. /* make a rcv descriptor */
  1205. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1206. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1207. DPRINTK(INFO, "done writing descripter\n");
  1208. producer =
  1209. get_next_index(producer, rds_ring->max_rx_desc_count);
  1210. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1211. buffer = &rds_ring->rx_buf_arr[index];
  1212. }
  1213. /* if we did allocate buffers, then write the count to Phantom */
  1214. if (count) {
  1215. rds_ring->begin_alloc = index;
  1216. rds_ring->producer = producer;
  1217. /* Window = 1 */
  1218. adapter->pci_write_normalize(adapter,
  1219. rds_ring->crb_rcv_producer,
  1220. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1221. if (adapter->fw_major < 4) {
  1222. /*
  1223. * Write a doorbell msg to tell phanmon of change in
  1224. * receive ring producer
  1225. * Only for firmware version < 4.0.0
  1226. */
  1227. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1228. netxen_set_msg_privid(msg);
  1229. netxen_set_msg_count(msg,
  1230. ((producer -
  1231. 1) & (rds_ring->
  1232. max_rx_desc_count - 1)));
  1233. netxen_set_msg_ctxid(msg, adapter->portnum);
  1234. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1235. writel(msg,
  1236. DB_NORMALIZE(adapter,
  1237. NETXEN_RCV_PRODUCER_OFFSET));
  1238. }
  1239. }
  1240. }
  1241. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1242. uint32_t ctx, uint32_t ringid)
  1243. {
  1244. struct pci_dev *pdev = adapter->pdev;
  1245. struct sk_buff *skb;
  1246. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1247. struct nx_host_rds_ring *rds_ring = NULL;
  1248. u32 producer;
  1249. struct rcv_desc *pdesc;
  1250. struct netxen_rx_buffer *buffer;
  1251. int count = 0;
  1252. int index = 0;
  1253. rds_ring = &recv_ctx->rds_rings[ringid];
  1254. producer = rds_ring->producer;
  1255. index = rds_ring->begin_alloc;
  1256. buffer = &rds_ring->rx_buf_arr[index];
  1257. /* We can start writing rx descriptors into the phantom memory. */
  1258. while (buffer->state == NETXEN_BUFFER_FREE) {
  1259. skb = dev_alloc_skb(rds_ring->skb_size);
  1260. if (unlikely(!skb)) {
  1261. /*
  1262. * We need to schedule the posting of buffers to the pegs.
  1263. */
  1264. rds_ring->begin_alloc = index;
  1265. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1266. " allocated only %d buffers\n", count);
  1267. break;
  1268. }
  1269. count++; /* now there should be no failure */
  1270. pdesc = &rds_ring->desc_head[producer];
  1271. skb_reserve(skb, 2);
  1272. /*
  1273. * This will be setup when we receive the
  1274. * buffer after it has been filled
  1275. * skb->dev = netdev;
  1276. */
  1277. buffer->skb = skb;
  1278. buffer->state = NETXEN_BUFFER_BUSY;
  1279. buffer->dma = pci_map_single(pdev, skb->data,
  1280. rds_ring->dma_size,
  1281. PCI_DMA_FROMDEVICE);
  1282. /* make a rcv descriptor */
  1283. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1284. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1285. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1286. producer =
  1287. get_next_index(producer, rds_ring->max_rx_desc_count);
  1288. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1289. buffer = &rds_ring->rx_buf_arr[index];
  1290. }
  1291. /* if we did allocate buffers, then write the count to Phantom */
  1292. if (count) {
  1293. rds_ring->begin_alloc = index;
  1294. rds_ring->producer = producer;
  1295. /* Window = 1 */
  1296. adapter->pci_write_normalize(adapter,
  1297. rds_ring->crb_rcv_producer,
  1298. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1299. wmb();
  1300. }
  1301. }
  1302. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1303. {
  1304. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1305. return;
  1306. }