tlb.c 22 KB

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  1. /*
  2. * TLB Management (flush/create/diagnostics) for ARC700
  3. *
  4. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * vineetg: Aug 2011
  11. * -Reintroduce duplicate PD fixup - some customer chips still have the issue
  12. *
  13. * vineetg: May 2011
  14. * -No need to flush_cache_page( ) for each call to update_mmu_cache()
  15. * some of the LMBench tests improved amazingly
  16. * = page-fault thrice as fast (75 usec to 28 usec)
  17. * = mmap twice as fast (9.6 msec to 4.6 msec),
  18. * = fork (5.3 msec to 3.7 msec)
  19. *
  20. * vineetg: April 2011 :
  21. * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
  22. * helps avoid a shift when preparing PD0 from PTE
  23. *
  24. * vineetg: April 2011 : Preparing for MMU V3
  25. * -MMU v2/v3 BCRs decoded differently
  26. * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
  27. * -tlb_entry_erase( ) can be void
  28. * -local_flush_tlb_range( ):
  29. * = need not "ceil" @end
  30. * = walks MMU only if range spans < 32 entries, as opposed to 256
  31. *
  32. * Vineetg: Sept 10th 2008
  33. * -Changes related to MMU v2 (Rel 4.8)
  34. *
  35. * Vineetg: Aug 29th 2008
  36. * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
  37. * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
  38. * it fails. Thus need to load it with ANY valid value before invoking
  39. * TLBIVUTLB cmd
  40. *
  41. * Vineetg: Aug 21th 2008:
  42. * -Reduced the duration of IRQ lockouts in TLB Flush routines
  43. * -Multiple copies of TLB erase code seperated into a "single" function
  44. * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
  45. * in interrupt-safe region.
  46. *
  47. * Vineetg: April 23rd Bug #93131
  48. * Problem: tlb_flush_kernel_range() doesnt do anything if the range to
  49. * flush is more than the size of TLB itself.
  50. *
  51. * Rahul Trivedi : Codito Technologies 2004
  52. */
  53. #include <linux/module.h>
  54. #include <linux/bug.h>
  55. #include <asm/arcregs.h>
  56. #include <asm/setup.h>
  57. #include <asm/mmu_context.h>
  58. #include <asm/mmu.h>
  59. /* Need for ARC MMU v2
  60. *
  61. * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
  62. * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
  63. * map into same set, there would be contention for the 2 ways causing severe
  64. * Thrashing.
  65. *
  66. * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
  67. * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
  68. * Given this, the thrasing problem should never happen because once the 3
  69. * J-TLB entries are created (even though 3rd will knock out one of the prev
  70. * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
  71. *
  72. * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
  73. * This is a simple design for keeping them in sync. So what do we do?
  74. * The solution which James came up was pretty neat. It utilised the assoc
  75. * of uTLBs by not invalidating always but only when absolutely necessary.
  76. *
  77. * - Existing TLB commands work as before
  78. * - New command (TLBWriteNI) for TLB write without clearing uTLBs
  79. * - New command (TLBIVUTLB) to invalidate uTLBs.
  80. *
  81. * The uTLBs need only be invalidated when pages are being removed from the
  82. * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
  83. * as a result of a miss, the removed entry is still allowed to exist in the
  84. * uTLBs as it is still valid and present in the OS page table. This allows the
  85. * full associativity of the uTLBs to hide the limited associativity of the main
  86. * TLB.
  87. *
  88. * During a miss handler, the new "TLBWriteNI" command is used to load
  89. * entries without clearing the uTLBs.
  90. *
  91. * When the OS page table is updated, TLB entries that may be associated with a
  92. * removed page are removed (flushed) from the TLB using TLBWrite. In this
  93. * circumstance, the uTLBs must also be cleared. This is done by using the
  94. * existing TLBWrite command. An explicit IVUTLB is also required for those
  95. * corner cases when TLBWrite was not executed at all because the corresp
  96. * J-TLB entry got evicted/replaced.
  97. */
  98. /* A copy of the ASID from the PID reg is kept in asid_cache */
  99. int asid_cache = FIRST_ASID;
  100. /* ASID to mm struct mapping. We have one extra entry corresponding to
  101. * NO_ASID to save us a compare when clearing the mm entry for old asid
  102. * see get_new_mmu_context (asm-arc/mmu_context.h)
  103. */
  104. struct mm_struct *asid_mm_map[NUM_ASID + 1];
  105. /*
  106. * Utility Routine to erase a J-TLB entry
  107. * Caller needs to setup Index Reg (manually or via getIndex)
  108. */
  109. static inline void __tlb_entry_erase(void)
  110. {
  111. write_aux_reg(ARC_REG_TLBPD1, 0);
  112. write_aux_reg(ARC_REG_TLBPD0, 0);
  113. write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
  114. }
  115. static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
  116. {
  117. unsigned int idx;
  118. write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
  119. write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
  120. idx = read_aux_reg(ARC_REG_TLBINDEX);
  121. return idx;
  122. }
  123. static void tlb_entry_erase(unsigned int vaddr_n_asid)
  124. {
  125. unsigned int idx;
  126. /* Locate the TLB entry for this vaddr + ASID */
  127. idx = tlb_entry_lkup(vaddr_n_asid);
  128. /* No error means entry found, zero it out */
  129. if (likely(!(idx & TLB_LKUP_ERR))) {
  130. __tlb_entry_erase();
  131. } else {
  132. /* Duplicate entry error */
  133. WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
  134. vaddr_n_asid);
  135. }
  136. }
  137. /****************************************************************************
  138. * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
  139. *
  140. * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
  141. *
  142. * utlb_invalidate ( )
  143. * -For v2 MMU calls Flush uTLB Cmd
  144. * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
  145. * This is because in v1 TLBWrite itself invalidate uTLBs
  146. ***************************************************************************/
  147. static void utlb_invalidate(void)
  148. {
  149. #if (CONFIG_ARC_MMU_VER >= 2)
  150. #if (CONFIG_ARC_MMU_VER == 2)
  151. /* MMU v2 introduced the uTLB Flush command.
  152. * There was however an obscure hardware bug, where uTLB flush would
  153. * fail when a prior probe for J-TLB (both totally unrelated) would
  154. * return lkup err - because the entry didnt exist in MMU.
  155. * The Workround was to set Index reg with some valid value, prior to
  156. * flush. This was fixed in MMU v3 hence not needed any more
  157. */
  158. unsigned int idx;
  159. /* make sure INDEX Reg is valid */
  160. idx = read_aux_reg(ARC_REG_TLBINDEX);
  161. /* If not write some dummy val */
  162. if (unlikely(idx & TLB_LKUP_ERR))
  163. write_aux_reg(ARC_REG_TLBINDEX, 0xa);
  164. #endif
  165. write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
  166. #endif
  167. }
  168. static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
  169. {
  170. unsigned int idx;
  171. /*
  172. * First verify if entry for this vaddr+ASID already exists
  173. * This also sets up PD0 (vaddr, ASID..) for final commit
  174. */
  175. idx = tlb_entry_lkup(pd0);
  176. /*
  177. * If Not already present get a free slot from MMU.
  178. * Otherwise, Probe would have located the entry and set INDEX Reg
  179. * with existing location. This will cause Write CMD to over-write
  180. * existing entry with new PD0 and PD1
  181. */
  182. if (likely(idx & TLB_LKUP_ERR))
  183. write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
  184. /* setup the other half of TLB entry (pfn, rwx..) */
  185. write_aux_reg(ARC_REG_TLBPD1, pd1);
  186. /*
  187. * Commit the Entry to MMU
  188. * It doesnt sound safe to use the TLBWriteNI cmd here
  189. * which doesn't flush uTLBs. I'd rather be safe than sorry.
  190. */
  191. write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
  192. }
  193. /*
  194. * Un-conditionally (without lookup) erase the entire MMU contents
  195. */
  196. noinline void local_flush_tlb_all(void)
  197. {
  198. unsigned long flags;
  199. unsigned int entry;
  200. struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
  201. local_irq_save(flags);
  202. /* Load PD0 and PD1 with template for a Blank Entry */
  203. write_aux_reg(ARC_REG_TLBPD1, 0);
  204. write_aux_reg(ARC_REG_TLBPD0, 0);
  205. for (entry = 0; entry < mmu->num_tlb; entry++) {
  206. /* write this entry to the TLB */
  207. write_aux_reg(ARC_REG_TLBINDEX, entry);
  208. write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
  209. }
  210. utlb_invalidate();
  211. local_irq_restore(flags);
  212. }
  213. /*
  214. * Flush the entrie MM for userland. The fastest way is to move to Next ASID
  215. */
  216. noinline void local_flush_tlb_mm(struct mm_struct *mm)
  217. {
  218. /*
  219. * Small optimisation courtesy IA64
  220. * flush_mm called during fork,exit,munmap etc, multiple times as well.
  221. * Only for fork( ) do we need to move parent to a new MMU ctxt,
  222. * all other cases are NOPs, hence this check.
  223. */
  224. if (atomic_read(&mm->mm_users) == 0)
  225. return;
  226. /*
  227. * Workaround for Android weirdism:
  228. * A binder VMA could end up in a task such that vma->mm != tsk->mm
  229. * old code would cause h/w - s/w ASID to get out of sync
  230. */
  231. if (current->mm != mm)
  232. destroy_context(mm);
  233. else
  234. get_new_mmu_context(mm);
  235. }
  236. /*
  237. * Flush a Range of TLB entries for userland.
  238. * @start is inclusive, while @end is exclusive
  239. * Difference between this and Kernel Range Flush is
  240. * -Here the fastest way (if range is too large) is to move to next ASID
  241. * without doing any explicit Shootdown
  242. * -In case of kernel Flush, entry has to be shot down explictly
  243. */
  244. void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
  245. unsigned long end)
  246. {
  247. unsigned long flags;
  248. unsigned int asid;
  249. /* If range @start to @end is more than 32 TLB entries deep,
  250. * its better to move to a new ASID rather than searching for
  251. * individual entries and then shooting them down
  252. *
  253. * The calc above is rough, doesn't account for unaligned parts,
  254. * since this is heuristics based anyways
  255. */
  256. if (unlikely((end - start) >= PAGE_SIZE * 32)) {
  257. local_flush_tlb_mm(vma->vm_mm);
  258. return;
  259. }
  260. /*
  261. * @start moved to page start: this alone suffices for checking
  262. * loop end condition below, w/o need for aligning @end to end
  263. * e.g. 2000 to 4001 will anyhow loop twice
  264. */
  265. start &= PAGE_MASK;
  266. local_irq_save(flags);
  267. asid = vma->vm_mm->context.asid;
  268. if (asid != NO_ASID) {
  269. while (start < end) {
  270. tlb_entry_erase(start | (asid & 0xff));
  271. start += PAGE_SIZE;
  272. }
  273. }
  274. utlb_invalidate();
  275. local_irq_restore(flags);
  276. }
  277. /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
  278. * @start, @end interpreted as kvaddr
  279. * Interestingly, shared TLB entries can also be flushed using just
  280. * @start,@end alone (interpreted as user vaddr), although technically SASID
  281. * is also needed. However our smart TLbProbe lookup takes care of that.
  282. */
  283. void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
  284. {
  285. unsigned long flags;
  286. /* exactly same as above, except for TLB entry not taking ASID */
  287. if (unlikely((end - start) >= PAGE_SIZE * 32)) {
  288. local_flush_tlb_all();
  289. return;
  290. }
  291. start &= PAGE_MASK;
  292. local_irq_save(flags);
  293. while (start < end) {
  294. tlb_entry_erase(start);
  295. start += PAGE_SIZE;
  296. }
  297. utlb_invalidate();
  298. local_irq_restore(flags);
  299. }
  300. /*
  301. * Delete TLB entry in MMU for a given page (??? address)
  302. * NOTE One TLB entry contains translation for single PAGE
  303. */
  304. void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
  305. {
  306. unsigned long flags;
  307. /* Note that it is critical that interrupts are DISABLED between
  308. * checking the ASID and using it flush the TLB entry
  309. */
  310. local_irq_save(flags);
  311. if (vma->vm_mm->context.asid != NO_ASID) {
  312. tlb_entry_erase((page & PAGE_MASK) |
  313. (vma->vm_mm->context.asid & 0xff));
  314. utlb_invalidate();
  315. }
  316. local_irq_restore(flags);
  317. }
  318. /*
  319. * Routine to create a TLB entry
  320. */
  321. void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
  322. {
  323. unsigned long flags;
  324. unsigned int asid_or_sasid, rwx;
  325. unsigned long pd0, pd1;
  326. /*
  327. * create_tlb() assumes that current->mm == vma->mm, since
  328. * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
  329. * -completes the lazy write to SASID reg (again valid for curr tsk)
  330. *
  331. * Removing the assumption involves
  332. * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
  333. * -Fix the TLB paranoid debug code to not trigger false negatives.
  334. * -More importantly it makes this handler inconsistent with fast-path
  335. * TLB Refill handler which always deals with "current"
  336. *
  337. * Lets see the use cases when current->mm != vma->mm and we land here
  338. * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
  339. * Here VM wants to pre-install a TLB entry for user stack while
  340. * current->mm still points to pre-execve mm (hence the condition).
  341. * However the stack vaddr is soon relocated (randomization) and
  342. * move_page_tables() tries to undo that TLB entry.
  343. * Thus not creating TLB entry is not any worse.
  344. *
  345. * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
  346. * breakpoint in debugged task. Not creating a TLB now is not
  347. * performance critical.
  348. *
  349. * Both the cases above are not good enough for code churn.
  350. */
  351. if (current->active_mm != vma->vm_mm)
  352. return;
  353. local_irq_save(flags);
  354. tlb_paranoid_check(vma->vm_mm->context.asid, address);
  355. address &= PAGE_MASK;
  356. /* update this PTE credentials */
  357. pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
  358. /* Create HW TLB(PD0,PD1) from PTE */
  359. /* ASID for this task */
  360. asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
  361. pd0 = address | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
  362. /*
  363. * ARC MMU provides fully orthogonal access bits for K/U mode,
  364. * however Linux only saves 1 set to save PTE real-estate
  365. * Here we convert 3 PTE bits into 6 MMU bits:
  366. * -Kernel only entries have Kr Kw Kx 0 0 0
  367. * -User entries have mirrored K and U bits
  368. */
  369. rwx = pte_val(*ptep) & PTE_BITS_RWX;
  370. if (pte_val(*ptep) & _PAGE_GLOBAL)
  371. rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
  372. else
  373. rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
  374. pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
  375. tlb_entry_insert(pd0, pd1);
  376. local_irq_restore(flags);
  377. }
  378. /*
  379. * Called at the end of pagefault, for a userspace mapped page
  380. * -pre-install the corresponding TLB entry into MMU
  381. * -Finalize the delayed D-cache flush of kernel mapping of page due to
  382. * flush_dcache_page(), copy_user_page()
  383. *
  384. * Note that flush (when done) involves both WBACK - so physical page is
  385. * in sync as well as INV - so any non-congruent aliases don't remain
  386. */
  387. void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
  388. pte_t *ptep)
  389. {
  390. unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
  391. unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
  392. struct page *page = pfn_to_page(pte_pfn(*ptep));
  393. create_tlb(vma, vaddr, ptep);
  394. if (page == ZERO_PAGE(0)) {
  395. return;
  396. }
  397. /*
  398. * Exec page : Independent of aliasing/page-color considerations,
  399. * since icache doesn't snoop dcache on ARC, any dirty
  400. * K-mapping of a code page needs to be wback+inv so that
  401. * icache fetch by userspace sees code correctly.
  402. * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
  403. * so userspace sees the right data.
  404. * (Avoids the flush for Non-exec + congruent mapping case)
  405. */
  406. if ((vma->vm_flags & VM_EXEC) ||
  407. addr_not_cache_congruent(paddr, vaddr)) {
  408. int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
  409. if (dirty) {
  410. /* wback + inv dcache lines */
  411. __flush_dcache_page(paddr, paddr);
  412. /* invalidate any existing icache lines */
  413. if (vma->vm_flags & VM_EXEC)
  414. __inv_icache_page(paddr, vaddr);
  415. }
  416. }
  417. }
  418. /* Read the Cache Build Confuration Registers, Decode them and save into
  419. * the cpuinfo structure for later use.
  420. * No Validation is done here, simply read/convert the BCRs
  421. */
  422. void read_decode_mmu_bcr(void)
  423. {
  424. struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
  425. unsigned int tmp;
  426. struct bcr_mmu_1_2 {
  427. #ifdef CONFIG_CPU_BIG_ENDIAN
  428. unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
  429. #else
  430. unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
  431. #endif
  432. } *mmu2;
  433. struct bcr_mmu_3 {
  434. #ifdef CONFIG_CPU_BIG_ENDIAN
  435. unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
  436. u_itlb:4, u_dtlb:4;
  437. #else
  438. unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
  439. ways:4, ver:8;
  440. #endif
  441. } *mmu3;
  442. tmp = read_aux_reg(ARC_REG_MMU_BCR);
  443. mmu->ver = (tmp >> 24);
  444. if (mmu->ver <= 2) {
  445. mmu2 = (struct bcr_mmu_1_2 *)&tmp;
  446. mmu->pg_sz = PAGE_SIZE;
  447. mmu->sets = 1 << mmu2->sets;
  448. mmu->ways = 1 << mmu2->ways;
  449. mmu->u_dtlb = mmu2->u_dtlb;
  450. mmu->u_itlb = mmu2->u_itlb;
  451. } else {
  452. mmu3 = (struct bcr_mmu_3 *)&tmp;
  453. mmu->pg_sz = 512 << mmu3->pg_sz;
  454. mmu->sets = 1 << mmu3->sets;
  455. mmu->ways = 1 << mmu3->ways;
  456. mmu->u_dtlb = mmu3->u_dtlb;
  457. mmu->u_itlb = mmu3->u_itlb;
  458. }
  459. mmu->num_tlb = mmu->sets * mmu->ways;
  460. }
  461. char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
  462. {
  463. int n = 0;
  464. struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
  465. n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ",
  466. p_mmu->ver, TO_KB(p_mmu->pg_sz));
  467. n += scnprintf(buf + n, len - n,
  468. "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
  469. p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
  470. p_mmu->u_dtlb, p_mmu->u_itlb,
  471. IS_ENABLED(CONFIG_ARC_MMU_SASID) ? "SASID" : "");
  472. return buf;
  473. }
  474. void arc_mmu_init(void)
  475. {
  476. char str[256];
  477. struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
  478. printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
  479. /* For efficiency sake, kernel is compile time built for a MMU ver
  480. * This must match the hardware it is running on.
  481. * Linux built for MMU V2, if run on MMU V1 will break down because V1
  482. * hardware doesn't understand cmds such as WriteNI, or IVUTLB
  483. * On the other hand, Linux built for V1 if run on MMU V2 will do
  484. * un-needed workarounds to prevent memcpy thrashing.
  485. * Similarly MMU V3 has new features which won't work on older MMU
  486. */
  487. if (mmu->ver != CONFIG_ARC_MMU_VER) {
  488. panic("MMU ver %d doesn't match kernel built for %d...\n",
  489. mmu->ver, CONFIG_ARC_MMU_VER);
  490. }
  491. if (mmu->pg_sz != PAGE_SIZE)
  492. panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
  493. /*
  494. * ASID mgmt data structures are compile time init
  495. * asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
  496. */
  497. local_flush_tlb_all();
  498. /* Enable the MMU */
  499. write_aux_reg(ARC_REG_PID, MMU_ENABLE);
  500. /* In smp we use this reg for interrupt 1 scratch */
  501. #ifndef CONFIG_SMP
  502. /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
  503. write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
  504. #endif
  505. }
  506. /*
  507. * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
  508. * The mapping is Column-first.
  509. * --------------------- -----------
  510. * |way0|way1|way2|way3| |way0|way1|
  511. * --------------------- -----------
  512. * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
  513. * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
  514. * ~ ~ ~ ~
  515. * [set127] | 508| 509| 510| 511| | 254| 255|
  516. * --------------------- -----------
  517. * For normal operations we don't(must not) care how above works since
  518. * MMU cmd getIndex(vaddr) abstracts that out.
  519. * However for walking WAYS of a SET, we need to know this
  520. */
  521. #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
  522. /* Handling of Duplicate PD (TLB entry) in MMU.
  523. * -Could be due to buggy customer tapeouts or obscure kernel bugs
  524. * -MMU complaints not at the time of duplicate PD installation, but at the
  525. * time of lookup matching multiple ways.
  526. * -Ideally these should never happen - but if they do - workaround by deleting
  527. * the duplicate one.
  528. * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
  529. */
  530. volatile int dup_pd_verbose = 1;/* Be slient abt it or complain (default) */
  531. void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
  532. struct pt_regs *regs)
  533. {
  534. int set, way, n;
  535. unsigned int pd0[4], pd1[4]; /* assume max 4 ways */
  536. unsigned long flags, is_valid;
  537. struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
  538. local_irq_save(flags);
  539. /* re-enable the MMU */
  540. write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
  541. /* loop thru all sets of TLB */
  542. for (set = 0; set < mmu->sets; set++) {
  543. /* read out all the ways of current set */
  544. for (way = 0, is_valid = 0; way < mmu->ways; way++) {
  545. write_aux_reg(ARC_REG_TLBINDEX,
  546. SET_WAY_TO_IDX(mmu, set, way));
  547. write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
  548. pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
  549. pd1[way] = read_aux_reg(ARC_REG_TLBPD1);
  550. is_valid |= pd0[way] & _PAGE_PRESENT;
  551. }
  552. /* If all the WAYS in SET are empty, skip to next SET */
  553. if (!is_valid)
  554. continue;
  555. /* Scan the set for duplicate ways: needs a nested loop */
  556. for (way = 0; way < mmu->ways; way++) {
  557. if (!pd0[way])
  558. continue;
  559. for (n = way + 1; n < mmu->ways; n++) {
  560. if ((pd0[way] & PAGE_MASK) ==
  561. (pd0[n] & PAGE_MASK)) {
  562. if (dup_pd_verbose) {
  563. pr_info("Duplicate PD's @"
  564. "[%d:%d]/[%d:%d]\n",
  565. set, way, set, n);
  566. pr_info("TLBPD0[%u]: %08x\n",
  567. way, pd0[way]);
  568. }
  569. /*
  570. * clear entry @way and not @n. This is
  571. * critical to our optimised loop
  572. */
  573. pd0[way] = pd1[way] = 0;
  574. write_aux_reg(ARC_REG_TLBINDEX,
  575. SET_WAY_TO_IDX(mmu, set, way));
  576. __tlb_entry_erase();
  577. }
  578. }
  579. }
  580. }
  581. local_irq_restore(flags);
  582. }
  583. /***********************************************************************
  584. * Diagnostic Routines
  585. * -Called from Low Level TLB Hanlders if things don;t look good
  586. **********************************************************************/
  587. #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
  588. /*
  589. * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
  590. * don't match
  591. */
  592. void print_asid_mismatch(int is_fast_path)
  593. {
  594. int pid_sw, pid_hw;
  595. pid_sw = current->active_mm->context.asid;
  596. pid_hw = read_aux_reg(ARC_REG_PID) & 0xff;
  597. pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
  598. is_fast_path ? "Fast" : "Slow", pid_sw, pid_hw);
  599. __asm__ __volatile__("flag 1");
  600. }
  601. void tlb_paranoid_check(unsigned int pid_sw, unsigned long addr)
  602. {
  603. unsigned int pid_hw;
  604. pid_hw = read_aux_reg(ARC_REG_PID) & 0xff;
  605. if (addr < 0x70000000 && ((pid_hw != pid_sw) || (pid_sw == NO_ASID)))
  606. print_asid_mismatch(0);
  607. }
  608. #endif