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- * Samsung's usb phy transceiver
- The Samsung's phy transceiver is used for controlling usb phy for
- s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
- across Samsung SOCs.
- TODO: Adding the PHY binding with controller(s) according to the under
- developement generic PHY driver.
- Required properties:
- Exynos4210:
- - compatible : should be "samsung,exynos4210-usbphy"
- - reg : base physical address of the phy registers and length of memory mapped
- region.
- Exynos5250:
- - compatible : should be "samsung,exynos5250-usbphy"
- - reg : base physical address of the phy registers and length of memory mapped
- region.
- Optional properties:
- - #address-cells: should be '1' when usbphy node has a child node with 'reg'
- property.
- - #size-cells: should be '1' when usbphy node has a child node with 'reg'
- property.
- - ranges: allows valid translation between child's address space and parent's
- address space.
- - The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
- interface for usb-phy. It should provide the following information required by
- usb-phy controller to control phy.
- - reg : base physical address of PHY_CONTROL registers.
- The size of this register is the total sum of size of all PHY_CONTROL
- registers that the SoC has. For example, the size will be
- '0x4' in case we have only one PHY_CONTROL register (e.g.
- OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
- and, '0x8' in case we have two PHY_CONTROL registers (e.g.
- USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
- and so on.
- Example:
- - Exynos4210
- usbphy@125B0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "samsung,exynos4210-usbphy";
- reg = <0x125B0000 0x100>;
- ranges;
- usbphy-sys {
- /* USB device and host PHY_CONTROL registers */
- reg = <0x10020704 0x8>;
- };
- };
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