integrator_ap.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-integrator/integrator_ap.c
  3. *
  4. * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/types.h>
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/list.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/slab.h>
  26. #include <linux/string.h>
  27. #include <linux/syscore_ops.h>
  28. #include <linux/amba/bus.h>
  29. #include <linux/amba/kmi.h>
  30. #include <linux/clocksource.h>
  31. #include <linux/clockchips.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <video/vga.h>
  36. #include <mach/hardware.h>
  37. #include <mach/platform.h>
  38. #include <asm/hardware/arm_timer.h>
  39. #include <asm/irq.h>
  40. #include <asm/setup.h>
  41. #include <asm/param.h> /* HZ */
  42. #include <asm/mach-types.h>
  43. #include <mach/lm.h>
  44. #include <asm/mach/arch.h>
  45. #include <asm/mach/irq.h>
  46. #include <asm/mach/map.h>
  47. #include <asm/mach/time.h>
  48. #include <plat/fpga-irq.h>
  49. #include "common.h"
  50. /*
  51. * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  52. * is the (PA >> 12).
  53. *
  54. * Setup a VA for the Integrator interrupt controller (for header #0,
  55. * just for now).
  56. */
  57. #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
  58. #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
  59. #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
  60. #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
  61. /*
  62. * Logical Physical
  63. * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
  64. * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
  65. * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
  66. * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
  67. * ef000000 Cache flush
  68. * f1000000 10000000 Core module registers
  69. * f1100000 11000000 System controller registers
  70. * f1200000 12000000 EBI registers
  71. * f1300000 13000000 Counter/Timer
  72. * f1400000 14000000 Interrupt controller
  73. * f1600000 16000000 UART 0
  74. * f1700000 17000000 UART 1
  75. * f1a00000 1a000000 Debug LEDs
  76. * f1b00000 1b000000 GPIO
  77. */
  78. static struct map_desc ap_io_desc[] __initdata = {
  79. {
  80. .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  81. .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  82. .length = SZ_4K,
  83. .type = MT_DEVICE
  84. }, {
  85. .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
  86. .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
  87. .length = SZ_4K,
  88. .type = MT_DEVICE
  89. }, {
  90. .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  91. .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  92. .length = SZ_4K,
  93. .type = MT_DEVICE
  94. }, {
  95. .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
  96. .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
  97. .length = SZ_4K,
  98. .type = MT_DEVICE
  99. }, {
  100. .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
  101. .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
  102. .length = SZ_4K,
  103. .type = MT_DEVICE
  104. }, {
  105. .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
  106. .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
  107. .length = SZ_4K,
  108. .type = MT_DEVICE
  109. }, {
  110. .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
  111. .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
  112. .length = SZ_4K,
  113. .type = MT_DEVICE
  114. }, {
  115. .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
  116. .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
  117. .length = SZ_4K,
  118. .type = MT_DEVICE
  119. }, {
  120. .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
  121. .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
  122. .length = SZ_4K,
  123. .type = MT_DEVICE
  124. }, {
  125. .virtual = PCI_MEMORY_VADDR,
  126. .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
  127. .length = SZ_16M,
  128. .type = MT_DEVICE
  129. }, {
  130. .virtual = PCI_CONFIG_VADDR,
  131. .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
  132. .length = SZ_16M,
  133. .type = MT_DEVICE
  134. }, {
  135. .virtual = PCI_V3_VADDR,
  136. .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
  137. .length = SZ_64K,
  138. .type = MT_DEVICE
  139. }, {
  140. .virtual = PCI_IO_VADDR,
  141. .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
  142. .length = SZ_64K,
  143. .type = MT_DEVICE
  144. }
  145. };
  146. static void __init ap_map_io(void)
  147. {
  148. iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
  149. vga_base = PCI_MEMORY_VADDR;
  150. }
  151. #define INTEGRATOR_SC_VALID_INT 0x003fffff
  152. static struct fpga_irq_data sc_irq_data = {
  153. .base = VA_IC_BASE,
  154. .irq_start = 0,
  155. .chip.name = "SC",
  156. };
  157. static void __init ap_init_irq(void)
  158. {
  159. /* Disable all interrupts initially. */
  160. /* Do the core module ones */
  161. writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
  162. /* do the header card stuff next */
  163. writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
  164. writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
  165. fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
  166. }
  167. #ifdef CONFIG_PM
  168. static unsigned long ic_irq_enable;
  169. static int irq_suspend(void)
  170. {
  171. ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
  172. return 0;
  173. }
  174. static void irq_resume(void)
  175. {
  176. /* disable all irq sources */
  177. writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
  178. writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
  179. writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
  180. writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
  181. }
  182. #else
  183. #define irq_suspend NULL
  184. #define irq_resume NULL
  185. #endif
  186. static struct syscore_ops irq_syscore_ops = {
  187. .suspend = irq_suspend,
  188. .resume = irq_resume,
  189. };
  190. static int __init irq_syscore_init(void)
  191. {
  192. register_syscore_ops(&irq_syscore_ops);
  193. return 0;
  194. }
  195. device_initcall(irq_syscore_init);
  196. /*
  197. * Flash handling.
  198. */
  199. #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
  200. #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
  201. #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
  202. #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
  203. static int ap_flash_init(struct platform_device *dev)
  204. {
  205. u32 tmp;
  206. writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
  207. tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
  208. writel(tmp, EBI_CSR1);
  209. if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
  210. writel(0xa05f, EBI_LOCK);
  211. writel(tmp, EBI_CSR1);
  212. writel(0, EBI_LOCK);
  213. }
  214. return 0;
  215. }
  216. static void ap_flash_exit(struct platform_device *dev)
  217. {
  218. u32 tmp;
  219. writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
  220. tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
  221. writel(tmp, EBI_CSR1);
  222. if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
  223. writel(0xa05f, EBI_LOCK);
  224. writel(tmp, EBI_CSR1);
  225. writel(0, EBI_LOCK);
  226. }
  227. }
  228. static void ap_flash_set_vpp(struct platform_device *pdev, int on)
  229. {
  230. void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
  231. writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
  232. }
  233. static struct physmap_flash_data ap_flash_data = {
  234. .width = 4,
  235. .init = ap_flash_init,
  236. .exit = ap_flash_exit,
  237. .set_vpp = ap_flash_set_vpp,
  238. };
  239. static struct resource cfi_flash_resource = {
  240. .start = INTEGRATOR_FLASH_BASE,
  241. .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
  242. .flags = IORESOURCE_MEM,
  243. };
  244. static struct platform_device cfi_flash_device = {
  245. .name = "physmap-flash",
  246. .id = 0,
  247. .dev = {
  248. .platform_data = &ap_flash_data,
  249. },
  250. .num_resources = 1,
  251. .resource = &cfi_flash_resource,
  252. };
  253. static void __init ap_init(void)
  254. {
  255. unsigned long sc_dec;
  256. int i;
  257. platform_device_register(&cfi_flash_device);
  258. sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
  259. for (i = 0; i < 4; i++) {
  260. struct lm_device *lmdev;
  261. if ((sc_dec & (16 << i)) == 0)
  262. continue;
  263. lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
  264. if (!lmdev)
  265. continue;
  266. lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
  267. lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
  268. lmdev->resource.flags = IORESOURCE_MEM;
  269. lmdev->irq = IRQ_AP_EXPINT0 + i;
  270. lmdev->id = i;
  271. lm_device_register(lmdev);
  272. }
  273. }
  274. /*
  275. * Where is the timer (VA)?
  276. */
  277. #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
  278. #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
  279. #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
  280. /*
  281. * How long is the timer interval?
  282. */
  283. #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
  284. #if TIMER_INTERVAL >= 0x100000
  285. #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
  286. #elif TIMER_INTERVAL >= 0x10000
  287. #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
  288. #else
  289. #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
  290. #endif
  291. static unsigned long timer_reload;
  292. static void integrator_clocksource_init(u32 khz)
  293. {
  294. void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
  295. u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
  296. if (khz >= 1500) {
  297. khz /= 16;
  298. ctrl |= TIMER_CTRL_DIV16;
  299. }
  300. writel(0xffff, base + TIMER_LOAD);
  301. writel(ctrl, base + TIMER_CTRL);
  302. clocksource_mmio_init(base + TIMER_VALUE, "timer2",
  303. khz * 1000, 200, 16, clocksource_mmio_readl_down);
  304. }
  305. static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
  306. /*
  307. * IRQ handler for the timer
  308. */
  309. static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
  310. {
  311. struct clock_event_device *evt = dev_id;
  312. /* clear the interrupt */
  313. writel(1, clkevt_base + TIMER_INTCLR);
  314. evt->event_handler(evt);
  315. return IRQ_HANDLED;
  316. }
  317. static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
  318. {
  319. u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
  320. BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
  321. if (mode == CLOCK_EVT_MODE_PERIODIC) {
  322. writel(ctrl, clkevt_base + TIMER_CTRL);
  323. writel(timer_reload, clkevt_base + TIMER_LOAD);
  324. ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
  325. }
  326. writel(ctrl, clkevt_base + TIMER_CTRL);
  327. }
  328. static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
  329. {
  330. unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
  331. writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
  332. writel(next, clkevt_base + TIMER_LOAD);
  333. writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
  334. return 0;
  335. }
  336. static struct clock_event_device integrator_clockevent = {
  337. .name = "timer1",
  338. .shift = 34,
  339. .features = CLOCK_EVT_FEAT_PERIODIC,
  340. .set_mode = clkevt_set_mode,
  341. .set_next_event = clkevt_set_next_event,
  342. .rating = 300,
  343. .cpumask = cpu_all_mask,
  344. };
  345. static struct irqaction integrator_timer_irq = {
  346. .name = "timer",
  347. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  348. .handler = integrator_timer_interrupt,
  349. .dev_id = &integrator_clockevent,
  350. };
  351. static void integrator_clockevent_init(u32 khz)
  352. {
  353. struct clock_event_device *evt = &integrator_clockevent;
  354. unsigned int ctrl = 0;
  355. if (khz * 1000 > 0x100000 * HZ) {
  356. khz /= 256;
  357. ctrl |= TIMER_CTRL_DIV256;
  358. } else if (khz * 1000 > 0x10000 * HZ) {
  359. khz /= 16;
  360. ctrl |= TIMER_CTRL_DIV16;
  361. }
  362. timer_reload = khz * 1000 / HZ;
  363. writel(ctrl, clkevt_base + TIMER_CTRL);
  364. evt->irq = IRQ_TIMERINT1;
  365. evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
  366. evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
  367. evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
  368. setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
  369. clockevents_register_device(evt);
  370. }
  371. /*
  372. * Set up timer(s).
  373. */
  374. static void __init ap_init_timer(void)
  375. {
  376. u32 khz = TICKS_PER_uSEC * 1000;
  377. writel(0, TIMER0_VA_BASE + TIMER_CTRL);
  378. writel(0, TIMER1_VA_BASE + TIMER_CTRL);
  379. writel(0, TIMER2_VA_BASE + TIMER_CTRL);
  380. integrator_clocksource_init(khz);
  381. integrator_clockevent_init(khz);
  382. }
  383. static struct sys_timer ap_timer = {
  384. .init = ap_init_timer,
  385. };
  386. MACHINE_START(INTEGRATOR, "ARM-Integrator")
  387. /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
  388. .boot_params = 0x00000100,
  389. .reserve = integrator_reserve,
  390. .map_io = ap_map_io,
  391. .init_early = integrator_init_early,
  392. .init_irq = ap_init_irq,
  393. .timer = &ap_timer,
  394. .init_machine = ap_init,
  395. MACHINE_END