at91_adc.c 19 KB

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  1. /*
  2. * Driver for the ADC present in the Atmel AT91 evaluation boards.
  3. *
  4. * Copyright 2011 Free Electrons
  5. *
  6. * Licensed under the GPLv2 or later.
  7. */
  8. #include <linux/bitmap.h>
  9. #include <linux/bitops.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/jiffies.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/sched.h>
  21. #include <linux/slab.h>
  22. #include <linux/wait.h>
  23. #include <linux/platform_data/at91_adc.h>
  24. #include <linux/iio/iio.h>
  25. #include <linux/iio/buffer.h>
  26. #include <linux/iio/trigger.h>
  27. #include <linux/iio/trigger_consumer.h>
  28. #include <linux/iio/triggered_buffer.h>
  29. #include <mach/at91_adc.h>
  30. #define AT91_ADC_CHAN(st, ch) \
  31. (st->registers->channel_base + (ch * 4))
  32. #define at91_adc_readl(st, reg) \
  33. (readl_relaxed(st->reg_base + reg))
  34. #define at91_adc_writel(st, reg, val) \
  35. (writel_relaxed(val, st->reg_base + reg))
  36. struct at91_adc_state {
  37. struct clk *adc_clk;
  38. u16 *buffer;
  39. unsigned long channels_mask;
  40. struct clk *clk;
  41. bool done;
  42. int irq;
  43. u16 last_value;
  44. struct mutex lock;
  45. u8 num_channels;
  46. void __iomem *reg_base;
  47. struct at91_adc_reg_desc *registers;
  48. u8 startup_time;
  49. struct iio_trigger **trig;
  50. struct at91_adc_trigger *trigger_list;
  51. u32 trigger_number;
  52. bool use_external;
  53. u32 vref_mv;
  54. u32 res; /* resolution used for convertions */
  55. bool low_res; /* the resolution corresponds to the lowest one */
  56. wait_queue_head_t wq_data_avail;
  57. };
  58. static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
  59. {
  60. struct iio_poll_func *pf = p;
  61. struct iio_dev *idev = pf->indio_dev;
  62. struct at91_adc_state *st = iio_priv(idev);
  63. int i, j = 0;
  64. for (i = 0; i < idev->masklength; i++) {
  65. if (!test_bit(i, idev->active_scan_mask))
  66. continue;
  67. st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
  68. j++;
  69. }
  70. if (idev->scan_timestamp) {
  71. s64 *timestamp = (s64 *)((u8 *)st->buffer +
  72. ALIGN(j, sizeof(s64)));
  73. *timestamp = pf->timestamp;
  74. }
  75. iio_push_to_buffers(idev, (u8 *)st->buffer);
  76. iio_trigger_notify_done(idev->trig);
  77. /* Needed to ACK the DRDY interruption */
  78. at91_adc_readl(st, AT91_ADC_LCDR);
  79. enable_irq(st->irq);
  80. return IRQ_HANDLED;
  81. }
  82. static irqreturn_t at91_adc_eoc_trigger(int irq, void *private)
  83. {
  84. struct iio_dev *idev = private;
  85. struct at91_adc_state *st = iio_priv(idev);
  86. u32 status = at91_adc_readl(st, st->registers->status_register);
  87. if (!(status & st->registers->drdy_mask))
  88. return IRQ_HANDLED;
  89. if (iio_buffer_enabled(idev)) {
  90. disable_irq_nosync(irq);
  91. iio_trigger_poll(idev->trig, iio_get_time_ns());
  92. } else {
  93. st->last_value = at91_adc_readl(st, AT91_ADC_LCDR);
  94. st->done = true;
  95. wake_up_interruptible(&st->wq_data_avail);
  96. }
  97. return IRQ_HANDLED;
  98. }
  99. static int at91_adc_channel_init(struct iio_dev *idev)
  100. {
  101. struct at91_adc_state *st = iio_priv(idev);
  102. struct iio_chan_spec *chan_array, *timestamp;
  103. int bit, idx = 0;
  104. idev->num_channels = bitmap_weight(&st->channels_mask,
  105. st->num_channels) + 1;
  106. chan_array = devm_kzalloc(&idev->dev,
  107. ((idev->num_channels + 1) *
  108. sizeof(struct iio_chan_spec)),
  109. GFP_KERNEL);
  110. if (!chan_array)
  111. return -ENOMEM;
  112. for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
  113. struct iio_chan_spec *chan = chan_array + idx;
  114. chan->type = IIO_VOLTAGE;
  115. chan->indexed = 1;
  116. chan->channel = bit;
  117. chan->scan_index = idx;
  118. chan->scan_type.sign = 'u';
  119. chan->scan_type.realbits = st->res;
  120. chan->scan_type.storagebits = 16;
  121. chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
  122. chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  123. idx++;
  124. }
  125. timestamp = chan_array + idx;
  126. timestamp->type = IIO_TIMESTAMP;
  127. timestamp->channel = -1;
  128. timestamp->scan_index = idx;
  129. timestamp->scan_type.sign = 's';
  130. timestamp->scan_type.realbits = 64;
  131. timestamp->scan_type.storagebits = 64;
  132. idev->channels = chan_array;
  133. return idev->num_channels;
  134. }
  135. static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
  136. struct at91_adc_trigger *triggers,
  137. const char *trigger_name)
  138. {
  139. struct at91_adc_state *st = iio_priv(idev);
  140. u8 value = 0;
  141. int i;
  142. for (i = 0; i < st->trigger_number; i++) {
  143. char *name = kasprintf(GFP_KERNEL,
  144. "%s-dev%d-%s",
  145. idev->name,
  146. idev->id,
  147. triggers[i].name);
  148. if (!name)
  149. return -ENOMEM;
  150. if (strcmp(trigger_name, name) == 0) {
  151. value = triggers[i].value;
  152. kfree(name);
  153. break;
  154. }
  155. kfree(name);
  156. }
  157. return value;
  158. }
  159. static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
  160. {
  161. struct iio_dev *idev = iio_trigger_get_drvdata(trig);
  162. struct at91_adc_state *st = iio_priv(idev);
  163. struct iio_buffer *buffer = idev->buffer;
  164. struct at91_adc_reg_desc *reg = st->registers;
  165. u32 status = at91_adc_readl(st, reg->trigger_register);
  166. u8 value;
  167. u8 bit;
  168. value = at91_adc_get_trigger_value_by_name(idev,
  169. st->trigger_list,
  170. idev->trig->name);
  171. if (value == 0)
  172. return -EINVAL;
  173. if (state) {
  174. st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
  175. if (st->buffer == NULL)
  176. return -ENOMEM;
  177. at91_adc_writel(st, reg->trigger_register,
  178. status | value);
  179. for_each_set_bit(bit, buffer->scan_mask,
  180. st->num_channels) {
  181. struct iio_chan_spec const *chan = idev->channels + bit;
  182. at91_adc_writel(st, AT91_ADC_CHER,
  183. AT91_ADC_CH(chan->channel));
  184. }
  185. at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
  186. } else {
  187. at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
  188. at91_adc_writel(st, reg->trigger_register,
  189. status & ~value);
  190. for_each_set_bit(bit, buffer->scan_mask,
  191. st->num_channels) {
  192. struct iio_chan_spec const *chan = idev->channels + bit;
  193. at91_adc_writel(st, AT91_ADC_CHDR,
  194. AT91_ADC_CH(chan->channel));
  195. }
  196. kfree(st->buffer);
  197. }
  198. return 0;
  199. }
  200. static const struct iio_trigger_ops at91_adc_trigger_ops = {
  201. .owner = THIS_MODULE,
  202. .set_trigger_state = &at91_adc_configure_trigger,
  203. };
  204. static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
  205. struct at91_adc_trigger *trigger)
  206. {
  207. struct iio_trigger *trig;
  208. int ret;
  209. trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
  210. idev->id, trigger->name);
  211. if (trig == NULL)
  212. return NULL;
  213. trig->dev.parent = idev->dev.parent;
  214. iio_trigger_set_drvdata(trig, idev);
  215. trig->ops = &at91_adc_trigger_ops;
  216. ret = iio_trigger_register(trig);
  217. if (ret)
  218. return NULL;
  219. return trig;
  220. }
  221. static int at91_adc_trigger_init(struct iio_dev *idev)
  222. {
  223. struct at91_adc_state *st = iio_priv(idev);
  224. int i, ret;
  225. st->trig = devm_kzalloc(&idev->dev,
  226. st->trigger_number * sizeof(st->trig),
  227. GFP_KERNEL);
  228. if (st->trig == NULL) {
  229. ret = -ENOMEM;
  230. goto error_ret;
  231. }
  232. for (i = 0; i < st->trigger_number; i++) {
  233. if (st->trigger_list[i].is_external && !(st->use_external))
  234. continue;
  235. st->trig[i] = at91_adc_allocate_trigger(idev,
  236. st->trigger_list + i);
  237. if (st->trig[i] == NULL) {
  238. dev_err(&idev->dev,
  239. "Could not allocate trigger %d\n", i);
  240. ret = -ENOMEM;
  241. goto error_trigger;
  242. }
  243. }
  244. return 0;
  245. error_trigger:
  246. for (i--; i >= 0; i--) {
  247. iio_trigger_unregister(st->trig[i]);
  248. iio_trigger_free(st->trig[i]);
  249. }
  250. error_ret:
  251. return ret;
  252. }
  253. static void at91_adc_trigger_remove(struct iio_dev *idev)
  254. {
  255. struct at91_adc_state *st = iio_priv(idev);
  256. int i;
  257. for (i = 0; i < st->trigger_number; i++) {
  258. iio_trigger_unregister(st->trig[i]);
  259. iio_trigger_free(st->trig[i]);
  260. }
  261. }
  262. static int at91_adc_buffer_init(struct iio_dev *idev)
  263. {
  264. return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
  265. &at91_adc_trigger_handler, NULL);
  266. }
  267. static void at91_adc_buffer_remove(struct iio_dev *idev)
  268. {
  269. iio_triggered_buffer_cleanup(idev);
  270. }
  271. static int at91_adc_read_raw(struct iio_dev *idev,
  272. struct iio_chan_spec const *chan,
  273. int *val, int *val2, long mask)
  274. {
  275. struct at91_adc_state *st = iio_priv(idev);
  276. int ret;
  277. switch (mask) {
  278. case IIO_CHAN_INFO_RAW:
  279. mutex_lock(&st->lock);
  280. at91_adc_writel(st, AT91_ADC_CHER,
  281. AT91_ADC_CH(chan->channel));
  282. at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask);
  283. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
  284. ret = wait_event_interruptible_timeout(st->wq_data_avail,
  285. st->done,
  286. msecs_to_jiffies(1000));
  287. if (ret == 0)
  288. ret = -ETIMEDOUT;
  289. if (ret < 0) {
  290. mutex_unlock(&st->lock);
  291. return ret;
  292. }
  293. *val = st->last_value;
  294. at91_adc_writel(st, AT91_ADC_CHDR,
  295. AT91_ADC_CH(chan->channel));
  296. at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask);
  297. st->last_value = 0;
  298. st->done = false;
  299. mutex_unlock(&st->lock);
  300. return IIO_VAL_INT;
  301. case IIO_CHAN_INFO_SCALE:
  302. *val = (st->vref_mv * 1000) >> chan->scan_type.realbits;
  303. *val2 = 0;
  304. return IIO_VAL_INT_PLUS_MICRO;
  305. default:
  306. break;
  307. }
  308. return -EINVAL;
  309. }
  310. static int at91_adc_of_get_resolution(struct at91_adc_state *st,
  311. struct platform_device *pdev)
  312. {
  313. struct iio_dev *idev = iio_priv_to_dev(st);
  314. struct device_node *np = pdev->dev.of_node;
  315. int count, i, ret = 0;
  316. char *res_name, *s;
  317. u32 *resolutions;
  318. count = of_property_count_strings(np, "atmel,adc-res-names");
  319. if (count < 2) {
  320. dev_err(&idev->dev, "You must specified at least two resolution names for "
  321. "adc-res-names property in the DT\n");
  322. return count;
  323. }
  324. resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL);
  325. if (!resolutions)
  326. return -ENOMEM;
  327. if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
  328. dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
  329. ret = -ENODEV;
  330. goto ret;
  331. }
  332. if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
  333. res_name = "highres";
  334. for (i = 0; i < count; i++) {
  335. if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
  336. continue;
  337. if (strcmp(res_name, s))
  338. continue;
  339. st->res = resolutions[i];
  340. if (!strcmp(res_name, "lowres"))
  341. st->low_res = true;
  342. else
  343. st->low_res = false;
  344. dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
  345. goto ret;
  346. }
  347. dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
  348. ret:
  349. kfree(resolutions);
  350. return ret;
  351. }
  352. static int at91_adc_probe_dt(struct at91_adc_state *st,
  353. struct platform_device *pdev)
  354. {
  355. struct iio_dev *idev = iio_priv_to_dev(st);
  356. struct device_node *node = pdev->dev.of_node;
  357. struct device_node *trig_node;
  358. int i = 0, ret;
  359. u32 prop;
  360. if (!node)
  361. return -EINVAL;
  362. st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
  363. if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
  364. dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
  365. ret = -EINVAL;
  366. goto error_ret;
  367. }
  368. st->channels_mask = prop;
  369. if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) {
  370. dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n");
  371. ret = -EINVAL;
  372. goto error_ret;
  373. }
  374. st->num_channels = prop;
  375. if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
  376. dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
  377. ret = -EINVAL;
  378. goto error_ret;
  379. }
  380. st->startup_time = prop;
  381. if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
  382. dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
  383. ret = -EINVAL;
  384. goto error_ret;
  385. }
  386. st->vref_mv = prop;
  387. ret = at91_adc_of_get_resolution(st, pdev);
  388. if (ret)
  389. goto error_ret;
  390. st->registers = devm_kzalloc(&idev->dev,
  391. sizeof(struct at91_adc_reg_desc),
  392. GFP_KERNEL);
  393. if (!st->registers) {
  394. dev_err(&idev->dev, "Could not allocate register memory.\n");
  395. ret = -ENOMEM;
  396. goto error_ret;
  397. }
  398. if (of_property_read_u32(node, "atmel,adc-channel-base", &prop)) {
  399. dev_err(&idev->dev, "Missing adc-channel-base property in the DT.\n");
  400. ret = -EINVAL;
  401. goto error_ret;
  402. }
  403. st->registers->channel_base = prop;
  404. if (of_property_read_u32(node, "atmel,adc-drdy-mask", &prop)) {
  405. dev_err(&idev->dev, "Missing adc-drdy-mask property in the DT.\n");
  406. ret = -EINVAL;
  407. goto error_ret;
  408. }
  409. st->registers->drdy_mask = prop;
  410. if (of_property_read_u32(node, "atmel,adc-status-register", &prop)) {
  411. dev_err(&idev->dev, "Missing adc-status-register property in the DT.\n");
  412. ret = -EINVAL;
  413. goto error_ret;
  414. }
  415. st->registers->status_register = prop;
  416. if (of_property_read_u32(node, "atmel,adc-trigger-register", &prop)) {
  417. dev_err(&idev->dev, "Missing adc-trigger-register property in the DT.\n");
  418. ret = -EINVAL;
  419. goto error_ret;
  420. }
  421. st->registers->trigger_register = prop;
  422. st->trigger_number = of_get_child_count(node);
  423. st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
  424. sizeof(struct at91_adc_trigger),
  425. GFP_KERNEL);
  426. if (!st->trigger_list) {
  427. dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
  428. ret = -ENOMEM;
  429. goto error_ret;
  430. }
  431. for_each_child_of_node(node, trig_node) {
  432. struct at91_adc_trigger *trig = st->trigger_list + i;
  433. const char *name;
  434. if (of_property_read_string(trig_node, "trigger-name", &name)) {
  435. dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
  436. ret = -EINVAL;
  437. goto error_ret;
  438. }
  439. trig->name = name;
  440. if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
  441. dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
  442. ret = -EINVAL;
  443. goto error_ret;
  444. }
  445. trig->value = prop;
  446. trig->is_external = of_property_read_bool(trig_node, "trigger-external");
  447. i++;
  448. }
  449. return 0;
  450. error_ret:
  451. return ret;
  452. }
  453. static int at91_adc_probe_pdata(struct at91_adc_state *st,
  454. struct platform_device *pdev)
  455. {
  456. struct at91_adc_data *pdata = pdev->dev.platform_data;
  457. if (!pdata)
  458. return -EINVAL;
  459. st->use_external = pdata->use_external_triggers;
  460. st->vref_mv = pdata->vref;
  461. st->channels_mask = pdata->channels_used;
  462. st->num_channels = pdata->num_channels;
  463. st->startup_time = pdata->startup_time;
  464. st->trigger_number = pdata->trigger_number;
  465. st->trigger_list = pdata->trigger_list;
  466. st->registers = pdata->registers;
  467. return 0;
  468. }
  469. static const struct iio_info at91_adc_info = {
  470. .driver_module = THIS_MODULE,
  471. .read_raw = &at91_adc_read_raw,
  472. };
  473. static int at91_adc_probe(struct platform_device *pdev)
  474. {
  475. unsigned int prsc, mstrclk, ticks, adc_clk;
  476. int ret;
  477. struct iio_dev *idev;
  478. struct at91_adc_state *st;
  479. struct resource *res;
  480. idev = iio_device_alloc(sizeof(struct at91_adc_state));
  481. if (idev == NULL) {
  482. ret = -ENOMEM;
  483. goto error_ret;
  484. }
  485. st = iio_priv(idev);
  486. if (pdev->dev.of_node)
  487. ret = at91_adc_probe_dt(st, pdev);
  488. else
  489. ret = at91_adc_probe_pdata(st, pdev);
  490. if (ret) {
  491. dev_err(&pdev->dev, "No platform data available.\n");
  492. ret = -EINVAL;
  493. goto error_free_device;
  494. }
  495. platform_set_drvdata(pdev, idev);
  496. idev->dev.parent = &pdev->dev;
  497. idev->name = dev_name(&pdev->dev);
  498. idev->modes = INDIO_DIRECT_MODE;
  499. idev->info = &at91_adc_info;
  500. st->irq = platform_get_irq(pdev, 0);
  501. if (st->irq < 0) {
  502. dev_err(&pdev->dev, "No IRQ ID is designated\n");
  503. ret = -ENODEV;
  504. goto error_free_device;
  505. }
  506. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  507. st->reg_base = devm_ioremap_resource(&pdev->dev, res);
  508. if (IS_ERR(st->reg_base)) {
  509. ret = PTR_ERR(st->reg_base);
  510. goto error_free_device;
  511. }
  512. /*
  513. * Disable all IRQs before setting up the handler
  514. */
  515. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
  516. at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
  517. ret = request_irq(st->irq,
  518. at91_adc_eoc_trigger,
  519. 0,
  520. pdev->dev.driver->name,
  521. idev);
  522. if (ret) {
  523. dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
  524. goto error_free_device;
  525. }
  526. st->clk = devm_clk_get(&pdev->dev, "adc_clk");
  527. if (IS_ERR(st->clk)) {
  528. dev_err(&pdev->dev, "Failed to get the clock.\n");
  529. ret = PTR_ERR(st->clk);
  530. goto error_free_irq;
  531. }
  532. ret = clk_prepare_enable(st->clk);
  533. if (ret) {
  534. dev_err(&pdev->dev,
  535. "Could not prepare or enable the clock.\n");
  536. goto error_free_irq;
  537. }
  538. st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
  539. if (IS_ERR(st->adc_clk)) {
  540. dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
  541. ret = PTR_ERR(st->adc_clk);
  542. goto error_disable_clk;
  543. }
  544. ret = clk_prepare_enable(st->adc_clk);
  545. if (ret) {
  546. dev_err(&pdev->dev,
  547. "Could not prepare or enable the ADC clock.\n");
  548. goto error_disable_clk;
  549. }
  550. /*
  551. * Prescaler rate computation using the formula from the Atmel's
  552. * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
  553. * specified by the electrical characteristics of the board.
  554. */
  555. mstrclk = clk_get_rate(st->clk);
  556. adc_clk = clk_get_rate(st->adc_clk);
  557. prsc = (mstrclk / (2 * adc_clk)) - 1;
  558. if (!st->startup_time) {
  559. dev_err(&pdev->dev, "No startup time available.\n");
  560. ret = -EINVAL;
  561. goto error_disable_adc_clk;
  562. }
  563. /*
  564. * Number of ticks needed to cover the startup time of the ADC as
  565. * defined in the electrical characteristics of the board, divided by 8.
  566. * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
  567. */
  568. ticks = round_up((st->startup_time * adc_clk /
  569. 1000000) - 1, 8) / 8;
  570. if (st->low_res)
  571. at91_adc_writel(st, AT91_ADC_MR,
  572. AT91_ADC_LOWRES |
  573. (AT91_ADC_PRESCAL_(prsc) & AT91_ADC_PRESCAL) |
  574. (AT91_ADC_STARTUP_(ticks) & AT91_ADC_STARTUP));
  575. else
  576. at91_adc_writel(st, AT91_ADC_MR,
  577. (AT91_ADC_PRESCAL_(prsc) & AT91_ADC_PRESCAL) |
  578. (AT91_ADC_STARTUP_(ticks) & AT91_ADC_STARTUP));
  579. /* Setup the ADC channels available on the board */
  580. ret = at91_adc_channel_init(idev);
  581. if (ret < 0) {
  582. dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
  583. goto error_disable_adc_clk;
  584. }
  585. init_waitqueue_head(&st->wq_data_avail);
  586. mutex_init(&st->lock);
  587. ret = at91_adc_buffer_init(idev);
  588. if (ret < 0) {
  589. dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
  590. goto error_disable_adc_clk;
  591. }
  592. ret = at91_adc_trigger_init(idev);
  593. if (ret < 0) {
  594. dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
  595. goto error_unregister_buffer;
  596. }
  597. ret = iio_device_register(idev);
  598. if (ret < 0) {
  599. dev_err(&pdev->dev, "Couldn't register the device.\n");
  600. goto error_remove_triggers;
  601. }
  602. return 0;
  603. error_remove_triggers:
  604. at91_adc_trigger_remove(idev);
  605. error_unregister_buffer:
  606. at91_adc_buffer_remove(idev);
  607. error_disable_adc_clk:
  608. clk_disable_unprepare(st->adc_clk);
  609. error_disable_clk:
  610. clk_disable_unprepare(st->clk);
  611. error_free_irq:
  612. free_irq(st->irq, idev);
  613. error_free_device:
  614. iio_device_free(idev);
  615. error_ret:
  616. return ret;
  617. }
  618. static int at91_adc_remove(struct platform_device *pdev)
  619. {
  620. struct iio_dev *idev = platform_get_drvdata(pdev);
  621. struct at91_adc_state *st = iio_priv(idev);
  622. iio_device_unregister(idev);
  623. at91_adc_trigger_remove(idev);
  624. at91_adc_buffer_remove(idev);
  625. clk_disable_unprepare(st->adc_clk);
  626. clk_disable_unprepare(st->clk);
  627. free_irq(st->irq, idev);
  628. iio_device_free(idev);
  629. return 0;
  630. }
  631. static const struct of_device_id at91_adc_dt_ids[] = {
  632. { .compatible = "atmel,at91sam9260-adc" },
  633. {},
  634. };
  635. MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
  636. static struct platform_driver at91_adc_driver = {
  637. .probe = at91_adc_probe,
  638. .remove = at91_adc_remove,
  639. .driver = {
  640. .name = "at91_adc",
  641. .of_match_table = of_match_ptr(at91_adc_dt_ids),
  642. },
  643. };
  644. module_platform_driver(at91_adc_driver);
  645. MODULE_LICENSE("GPL");
  646. MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
  647. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");