iwl-agn.c 87 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. priv->cfg->ops->smgmt->clear_station_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->cmd[index]->meta, mapping),
  366. pci_unmap_len(&txq->cmd[index]->meta, len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Misc. internal state and helper functions
  424. *
  425. ******************************************************************************/
  426. #define MAX_UCODE_BEACON_INTERVAL 4096
  427. static u16 iwl_adjust_beacon_interval(u16 beacon_val)
  428. {
  429. u16 new_val = 0;
  430. u16 beacon_factor = 0;
  431. beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  432. / MAX_UCODE_BEACON_INTERVAL;
  433. new_val = beacon_val / beacon_factor;
  434. if (!new_val)
  435. new_val = MAX_UCODE_BEACON_INTERVAL;
  436. return new_val;
  437. }
  438. static void iwl_setup_rxon_timing(struct iwl_priv *priv)
  439. {
  440. u64 tsf;
  441. s32 interval_tm, rem;
  442. unsigned long flags;
  443. struct ieee80211_conf *conf = NULL;
  444. u16 beacon_int = 0;
  445. conf = ieee80211_get_hw_conf(priv->hw);
  446. spin_lock_irqsave(&priv->lock, flags);
  447. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  448. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  449. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  450. beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
  451. priv->rxon_timing.atim_window = 0;
  452. } else {
  453. beacon_int = iwl_adjust_beacon_interval(
  454. priv->vif->bss_conf.beacon_int);
  455. /* TODO: we need to get atim_window from upper stack
  456. * for now we set to 0 */
  457. priv->rxon_timing.atim_window = 0;
  458. }
  459. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  460. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  461. interval_tm = beacon_int * 1024;
  462. rem = do_div(tsf, interval_tm);
  463. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  464. spin_unlock_irqrestore(&priv->lock, flags);
  465. IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
  466. le16_to_cpu(priv->rxon_timing.beacon_interval),
  467. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  468. le16_to_cpu(priv->rxon_timing.atim_window));
  469. }
  470. /******************************************************************************
  471. *
  472. * Generic RX handler implementations
  473. *
  474. ******************************************************************************/
  475. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  476. struct iwl_rx_mem_buffer *rxb)
  477. {
  478. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  479. struct iwl_alive_resp *palive;
  480. struct delayed_work *pwork;
  481. palive = &pkt->u.alive_frame;
  482. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  483. "0x%01X 0x%01X\n",
  484. palive->is_valid, palive->ver_type,
  485. palive->ver_subtype);
  486. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  487. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  488. memcpy(&priv->card_alive_init,
  489. &pkt->u.alive_frame,
  490. sizeof(struct iwl_init_alive_resp));
  491. pwork = &priv->init_alive_start;
  492. } else {
  493. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  494. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  495. sizeof(struct iwl_alive_resp));
  496. pwork = &priv->alive_start;
  497. }
  498. /* We delay the ALIVE response by 5ms to
  499. * give the HW RF Kill time to activate... */
  500. if (palive->is_valid == UCODE_VALID_OK)
  501. queue_delayed_work(priv->workqueue, pwork,
  502. msecs_to_jiffies(5));
  503. else
  504. IWL_WARN(priv, "uCode did not respond OK.\n");
  505. }
  506. static void iwl_bg_beacon_update(struct work_struct *work)
  507. {
  508. struct iwl_priv *priv =
  509. container_of(work, struct iwl_priv, beacon_update);
  510. struct sk_buff *beacon;
  511. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  512. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  513. if (!beacon) {
  514. IWL_ERR(priv, "update beacon failed\n");
  515. return;
  516. }
  517. mutex_lock(&priv->mutex);
  518. /* new beacon skb is allocated every time; dispose previous.*/
  519. if (priv->ibss_beacon)
  520. dev_kfree_skb(priv->ibss_beacon);
  521. priv->ibss_beacon = beacon;
  522. mutex_unlock(&priv->mutex);
  523. iwl_send_beacon_cmd(priv);
  524. }
  525. /**
  526. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  527. *
  528. * This callback is provided in order to send a statistics request.
  529. *
  530. * This timer function is continually reset to execute within
  531. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  532. * was received. We need to ensure we receive the statistics in order
  533. * to update the temperature used for calibrating the TXPOWER.
  534. */
  535. static void iwl_bg_statistics_periodic(unsigned long data)
  536. {
  537. struct iwl_priv *priv = (struct iwl_priv *)data;
  538. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  539. return;
  540. /* dont send host command if rf-kill is on */
  541. if (!iwl_is_ready_rf(priv))
  542. return;
  543. iwl_send_statistics_request(priv, CMD_ASYNC);
  544. }
  545. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  546. struct iwl_rx_mem_buffer *rxb)
  547. {
  548. #ifdef CONFIG_IWLWIFI_DEBUG
  549. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  550. struct iwl4965_beacon_notif *beacon =
  551. (struct iwl4965_beacon_notif *)pkt->u.raw;
  552. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  553. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  554. "tsf %d %d rate %d\n",
  555. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  556. beacon->beacon_notify_hdr.failure_frame,
  557. le32_to_cpu(beacon->ibss_mgr_status),
  558. le32_to_cpu(beacon->high_tsf),
  559. le32_to_cpu(beacon->low_tsf), rate);
  560. #endif
  561. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  562. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  563. queue_work(priv->workqueue, &priv->beacon_update);
  564. }
  565. /* Handle notification from uCode that card's power state is changing
  566. * due to software, hardware, or critical temperature RFKILL */
  567. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  568. struct iwl_rx_mem_buffer *rxb)
  569. {
  570. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  571. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  572. unsigned long status = priv->status;
  573. unsigned long reg_flags;
  574. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  575. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  576. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  577. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  578. RF_CARD_DISABLED)) {
  579. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  580. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  581. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  582. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  583. if (!(flags & RXON_CARD_DISABLED)) {
  584. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  585. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  586. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  587. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  588. }
  589. if (flags & RF_CARD_DISABLED) {
  590. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  591. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  592. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  593. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  594. if (!iwl_grab_nic_access(priv))
  595. iwl_release_nic_access(priv);
  596. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  597. }
  598. }
  599. if (flags & HW_CARD_DISABLED)
  600. set_bit(STATUS_RF_KILL_HW, &priv->status);
  601. else
  602. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  603. if (flags & SW_CARD_DISABLED)
  604. set_bit(STATUS_RF_KILL_SW, &priv->status);
  605. else
  606. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  607. if (!(flags & RXON_CARD_DISABLED))
  608. iwl_scan_cancel(priv);
  609. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  610. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  611. (test_bit(STATUS_RF_KILL_SW, &status) !=
  612. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  613. queue_work(priv->workqueue, &priv->rf_kill);
  614. else
  615. wake_up_interruptible(&priv->wait_command_queue);
  616. }
  617. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  618. {
  619. if (src == IWL_PWR_SRC_VAUX) {
  620. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  621. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  622. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  623. ~APMG_PS_CTRL_MSK_PWR_SRC);
  624. } else {
  625. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  626. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  627. ~APMG_PS_CTRL_MSK_PWR_SRC);
  628. }
  629. return 0;
  630. }
  631. /**
  632. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  633. *
  634. * Setup the RX handlers for each of the reply types sent from the uCode
  635. * to the host.
  636. *
  637. * This function chains into the hardware specific files for them to setup
  638. * any hardware specific handlers as well.
  639. */
  640. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  641. {
  642. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  643. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  644. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  645. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  646. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  647. iwl_rx_pm_debug_statistics_notif;
  648. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  649. /*
  650. * The same handler is used for both the REPLY to a discrete
  651. * statistics request from the host as well as for the periodic
  652. * statistics notifications (after received beacons) from the uCode.
  653. */
  654. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  655. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  656. iwl_setup_spectrum_handlers(priv);
  657. iwl_setup_rx_scan_handlers(priv);
  658. /* status change handler */
  659. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  660. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  661. iwl_rx_missed_beacon_notif;
  662. /* Rx handlers */
  663. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  664. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  665. /* block ack */
  666. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  667. /* Set up hardware specific Rx handlers */
  668. priv->cfg->ops->lib->rx_handler_setup(priv);
  669. }
  670. /**
  671. * iwl_rx_handle - Main entry function for receiving responses from uCode
  672. *
  673. * Uses the priv->rx_handlers callback function array to invoke
  674. * the appropriate handlers, including command responses,
  675. * frame-received notifications, and other notifications.
  676. */
  677. void iwl_rx_handle(struct iwl_priv *priv)
  678. {
  679. struct iwl_rx_mem_buffer *rxb;
  680. struct iwl_rx_packet *pkt;
  681. struct iwl_rx_queue *rxq = &priv->rxq;
  682. u32 r, i;
  683. int reclaim;
  684. unsigned long flags;
  685. u8 fill_rx = 0;
  686. u32 count = 8;
  687. int total_empty;
  688. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  689. * buffer that the driver may process (last buffer filled by ucode). */
  690. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  691. i = rxq->read;
  692. /* Rx interrupt, but nothing sent from uCode */
  693. if (i == r)
  694. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  695. /* calculate total frames need to be restock after handling RX */
  696. total_empty = r - priv->rxq.write_actual;
  697. if (total_empty < 0)
  698. total_empty += RX_QUEUE_SIZE;
  699. if (total_empty > (RX_QUEUE_SIZE / 2))
  700. fill_rx = 1;
  701. while (i != r) {
  702. rxb = rxq->queue[i];
  703. /* If an RXB doesn't have a Rx queue slot associated with it,
  704. * then a bug has been introduced in the queue refilling
  705. * routines -- catch it here */
  706. BUG_ON(rxb == NULL);
  707. rxq->queue[i] = NULL;
  708. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  709. priv->hw_params.rx_buf_size + 256,
  710. PCI_DMA_FROMDEVICE);
  711. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  712. /* Reclaim a command buffer only if this packet is a response
  713. * to a (driver-originated) command.
  714. * If the packet (e.g. Rx frame) originated from uCode,
  715. * there is no command buffer to reclaim.
  716. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  717. * but apparently a few don't get set; catch them here. */
  718. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  719. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  720. (pkt->hdr.cmd != REPLY_RX) &&
  721. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  722. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  723. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  724. (pkt->hdr.cmd != REPLY_TX);
  725. /* Based on type of command response or notification,
  726. * handle those that need handling via function in
  727. * rx_handlers table. See iwl_setup_rx_handlers() */
  728. if (priv->rx_handlers[pkt->hdr.cmd]) {
  729. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  730. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  731. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  732. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  733. } else {
  734. /* No handling needed */
  735. IWL_DEBUG_RX(priv,
  736. "r %d i %d No handler needed for %s, 0x%02x\n",
  737. r, i, get_cmd_string(pkt->hdr.cmd),
  738. pkt->hdr.cmd);
  739. }
  740. if (reclaim) {
  741. /* Invoke any callbacks, transfer the skb to caller, and
  742. * fire off the (possibly) blocking iwl_send_cmd()
  743. * as we reclaim the driver command queue */
  744. if (rxb && rxb->skb)
  745. iwl_tx_cmd_complete(priv, rxb);
  746. else
  747. IWL_WARN(priv, "Claim null rxb?\n");
  748. }
  749. /* For now we just don't re-use anything. We can tweak this
  750. * later to try and re-use notification packets and SKBs that
  751. * fail to Rx correctly */
  752. if (rxb->skb != NULL) {
  753. priv->alloc_rxb_skb--;
  754. dev_kfree_skb_any(rxb->skb);
  755. rxb->skb = NULL;
  756. }
  757. spin_lock_irqsave(&rxq->lock, flags);
  758. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  759. spin_unlock_irqrestore(&rxq->lock, flags);
  760. i = (i + 1) & RX_QUEUE_MASK;
  761. /* If there are a lot of unused frames,
  762. * restock the Rx queue so ucode wont assert. */
  763. if (fill_rx) {
  764. count++;
  765. if (count >= 8) {
  766. priv->rxq.read = i;
  767. iwl_rx_replenish_now(priv);
  768. count = 0;
  769. }
  770. }
  771. }
  772. /* Backtrack one entry */
  773. priv->rxq.read = i;
  774. if (fill_rx)
  775. iwl_rx_replenish_now(priv);
  776. else
  777. iwl_rx_queue_restock(priv);
  778. }
  779. /* call this function to flush any scheduled tasklet */
  780. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  781. {
  782. /* wait to make sure we flush pending tasklet*/
  783. synchronize_irq(priv->pci_dev->irq);
  784. tasklet_kill(&priv->irq_tasklet);
  785. }
  786. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  787. {
  788. u32 inta, handled = 0;
  789. u32 inta_fh;
  790. unsigned long flags;
  791. #ifdef CONFIG_IWLWIFI_DEBUG
  792. u32 inta_mask;
  793. #endif
  794. spin_lock_irqsave(&priv->lock, flags);
  795. /* Ack/clear/reset pending uCode interrupts.
  796. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  797. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  798. inta = iwl_read32(priv, CSR_INT);
  799. iwl_write32(priv, CSR_INT, inta);
  800. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  801. * Any new interrupts that happen after this, either while we're
  802. * in this tasklet, or later, will show up in next ISR/tasklet. */
  803. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  804. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  805. #ifdef CONFIG_IWLWIFI_DEBUG
  806. if (priv->debug_level & IWL_DL_ISR) {
  807. /* just for debug */
  808. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  809. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  810. inta, inta_mask, inta_fh);
  811. }
  812. #endif
  813. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  814. * atomic, make sure that inta covers all the interrupts that
  815. * we've discovered, even if FH interrupt came in just after
  816. * reading CSR_INT. */
  817. if (inta_fh & CSR49_FH_INT_RX_MASK)
  818. inta |= CSR_INT_BIT_FH_RX;
  819. if (inta_fh & CSR49_FH_INT_TX_MASK)
  820. inta |= CSR_INT_BIT_FH_TX;
  821. /* Now service all interrupt bits discovered above. */
  822. if (inta & CSR_INT_BIT_HW_ERR) {
  823. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  824. /* Tell the device to stop sending interrupts */
  825. iwl_disable_interrupts(priv);
  826. priv->isr_stats.hw++;
  827. iwl_irq_handle_error(priv);
  828. handled |= CSR_INT_BIT_HW_ERR;
  829. spin_unlock_irqrestore(&priv->lock, flags);
  830. return;
  831. }
  832. #ifdef CONFIG_IWLWIFI_DEBUG
  833. if (priv->debug_level & (IWL_DL_ISR)) {
  834. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  835. if (inta & CSR_INT_BIT_SCD) {
  836. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  837. "the frame/frames.\n");
  838. priv->isr_stats.sch++;
  839. }
  840. /* Alive notification via Rx interrupt will do the real work */
  841. if (inta & CSR_INT_BIT_ALIVE) {
  842. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  843. priv->isr_stats.alive++;
  844. }
  845. }
  846. #endif
  847. /* Safely ignore these bits for debug checks below */
  848. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  849. /* HW RF KILL switch toggled */
  850. if (inta & CSR_INT_BIT_RF_KILL) {
  851. int hw_rf_kill = 0;
  852. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  853. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  854. hw_rf_kill = 1;
  855. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  856. hw_rf_kill ? "disable radio" : "enable radio");
  857. priv->isr_stats.rfkill++;
  858. /* driver only loads ucode once setting the interface up.
  859. * the driver allows loading the ucode even if the radio
  860. * is killed. Hence update the killswitch state here. The
  861. * rfkill handler will care about restarting if needed.
  862. */
  863. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  864. if (hw_rf_kill)
  865. set_bit(STATUS_RF_KILL_HW, &priv->status);
  866. else
  867. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  868. queue_work(priv->workqueue, &priv->rf_kill);
  869. }
  870. handled |= CSR_INT_BIT_RF_KILL;
  871. }
  872. /* Chip got too hot and stopped itself */
  873. if (inta & CSR_INT_BIT_CT_KILL) {
  874. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  875. priv->isr_stats.ctkill++;
  876. handled |= CSR_INT_BIT_CT_KILL;
  877. }
  878. /* Error detected by uCode */
  879. if (inta & CSR_INT_BIT_SW_ERR) {
  880. IWL_ERR(priv, "Microcode SW error detected. "
  881. " Restarting 0x%X.\n", inta);
  882. priv->isr_stats.sw++;
  883. priv->isr_stats.sw_err = inta;
  884. iwl_irq_handle_error(priv);
  885. handled |= CSR_INT_BIT_SW_ERR;
  886. }
  887. /* uCode wakes up after power-down sleep */
  888. if (inta & CSR_INT_BIT_WAKEUP) {
  889. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  890. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  891. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  892. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  893. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  894. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  895. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  896. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  897. priv->isr_stats.wakeup++;
  898. handled |= CSR_INT_BIT_WAKEUP;
  899. }
  900. /* All uCode command responses, including Tx command responses,
  901. * Rx "responses" (frame-received notification), and other
  902. * notifications from uCode come through here*/
  903. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  904. iwl_rx_handle(priv);
  905. priv->isr_stats.rx++;
  906. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  907. }
  908. if (inta & CSR_INT_BIT_FH_TX) {
  909. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  910. priv->isr_stats.tx++;
  911. handled |= CSR_INT_BIT_FH_TX;
  912. /* FH finished to write, send event */
  913. priv->ucode_write_complete = 1;
  914. wake_up_interruptible(&priv->wait_command_queue);
  915. }
  916. if (inta & ~handled) {
  917. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  918. priv->isr_stats.unhandled++;
  919. }
  920. if (inta & ~CSR_INI_SET_MASK) {
  921. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  922. inta & ~CSR_INI_SET_MASK);
  923. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  924. }
  925. /* Re-enable all interrupts */
  926. /* only Re-enable if diabled by irq */
  927. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  928. iwl_enable_interrupts(priv);
  929. #ifdef CONFIG_IWLWIFI_DEBUG
  930. if (priv->debug_level & (IWL_DL_ISR)) {
  931. inta = iwl_read32(priv, CSR_INT);
  932. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  933. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  934. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  935. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  936. }
  937. #endif
  938. spin_unlock_irqrestore(&priv->lock, flags);
  939. }
  940. /* tasklet for iwlagn interrupt */
  941. static void iwl_irq_tasklet(struct iwl_priv *priv)
  942. {
  943. u32 inta = 0;
  944. u32 handled = 0;
  945. unsigned long flags;
  946. #ifdef CONFIG_IWLWIFI_DEBUG
  947. u32 inta_mask;
  948. #endif
  949. spin_lock_irqsave(&priv->lock, flags);
  950. /* Ack/clear/reset pending uCode interrupts.
  951. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  952. */
  953. iwl_write32(priv, CSR_INT, priv->inta);
  954. inta = priv->inta;
  955. #ifdef CONFIG_IWLWIFI_DEBUG
  956. if (priv->debug_level & IWL_DL_ISR) {
  957. /* just for debug */
  958. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  959. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  960. inta, inta_mask);
  961. }
  962. #endif
  963. /* saved interrupt in inta variable now we can reset priv->inta */
  964. priv->inta = 0;
  965. /* Now service all interrupt bits discovered above. */
  966. if (inta & CSR_INT_BIT_HW_ERR) {
  967. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  968. /* Tell the device to stop sending interrupts */
  969. iwl_disable_interrupts(priv);
  970. priv->isr_stats.hw++;
  971. iwl_irq_handle_error(priv);
  972. handled |= CSR_INT_BIT_HW_ERR;
  973. spin_unlock_irqrestore(&priv->lock, flags);
  974. return;
  975. }
  976. #ifdef CONFIG_IWLWIFI_DEBUG
  977. if (priv->debug_level & (IWL_DL_ISR)) {
  978. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  979. if (inta & CSR_INT_BIT_SCD) {
  980. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  981. "the frame/frames.\n");
  982. priv->isr_stats.sch++;
  983. }
  984. /* Alive notification via Rx interrupt will do the real work */
  985. if (inta & CSR_INT_BIT_ALIVE) {
  986. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  987. priv->isr_stats.alive++;
  988. }
  989. }
  990. #endif
  991. /* Safely ignore these bits for debug checks below */
  992. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  993. /* HW RF KILL switch toggled */
  994. if (inta & CSR_INT_BIT_RF_KILL) {
  995. int hw_rf_kill = 0;
  996. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  997. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  998. hw_rf_kill = 1;
  999. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  1000. hw_rf_kill ? "disable radio" : "enable radio");
  1001. priv->isr_stats.rfkill++;
  1002. /* driver only loads ucode once setting the interface up.
  1003. * the driver allows loading the ucode even if the radio
  1004. * is killed. Hence update the killswitch state here. The
  1005. * rfkill handler will care about restarting if needed.
  1006. */
  1007. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1008. if (hw_rf_kill)
  1009. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1010. else
  1011. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1012. queue_work(priv->workqueue, &priv->rf_kill);
  1013. }
  1014. handled |= CSR_INT_BIT_RF_KILL;
  1015. }
  1016. /* Chip got too hot and stopped itself */
  1017. if (inta & CSR_INT_BIT_CT_KILL) {
  1018. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1019. priv->isr_stats.ctkill++;
  1020. handled |= CSR_INT_BIT_CT_KILL;
  1021. }
  1022. /* Error detected by uCode */
  1023. if (inta & CSR_INT_BIT_SW_ERR) {
  1024. IWL_ERR(priv, "Microcode SW error detected. "
  1025. " Restarting 0x%X.\n", inta);
  1026. priv->isr_stats.sw++;
  1027. priv->isr_stats.sw_err = inta;
  1028. iwl_irq_handle_error(priv);
  1029. handled |= CSR_INT_BIT_SW_ERR;
  1030. }
  1031. /* uCode wakes up after power-down sleep */
  1032. if (inta & CSR_INT_BIT_WAKEUP) {
  1033. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1034. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1035. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  1036. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1037. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1038. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1039. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1040. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1041. priv->isr_stats.wakeup++;
  1042. handled |= CSR_INT_BIT_WAKEUP;
  1043. }
  1044. /* All uCode command responses, including Tx command responses,
  1045. * Rx "responses" (frame-received notification), and other
  1046. * notifications from uCode come through here*/
  1047. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1048. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1049. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_RX_MASK);
  1050. iwl_rx_handle(priv);
  1051. priv->isr_stats.rx++;
  1052. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1053. }
  1054. if (inta & CSR_INT_BIT_FH_TX) {
  1055. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1056. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1057. priv->isr_stats.tx++;
  1058. handled |= CSR_INT_BIT_FH_TX;
  1059. /* FH finished to write, send event */
  1060. priv->ucode_write_complete = 1;
  1061. wake_up_interruptible(&priv->wait_command_queue);
  1062. }
  1063. if (inta & ~handled) {
  1064. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1065. priv->isr_stats.unhandled++;
  1066. }
  1067. if (inta & ~CSR_INI_SET_MASK) {
  1068. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1069. inta & ~CSR_INI_SET_MASK);
  1070. }
  1071. /* Re-enable all interrupts */
  1072. /* only Re-enable if diabled by irq */
  1073. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1074. iwl_enable_interrupts(priv);
  1075. spin_unlock_irqrestore(&priv->lock, flags);
  1076. }
  1077. /******************************************************************************
  1078. *
  1079. * uCode download functions
  1080. *
  1081. ******************************************************************************/
  1082. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1083. {
  1084. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1085. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1086. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1087. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1088. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1089. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1090. }
  1091. static void iwl_nic_start(struct iwl_priv *priv)
  1092. {
  1093. /* Remove all resets to allow NIC to operate */
  1094. iwl_write32(priv, CSR_RESET, 0);
  1095. }
  1096. /**
  1097. * iwl_read_ucode - Read uCode images from disk file.
  1098. *
  1099. * Copy into buffers for card to fetch via bus-mastering
  1100. */
  1101. static int iwl_read_ucode(struct iwl_priv *priv)
  1102. {
  1103. struct iwl_ucode *ucode;
  1104. int ret = -EINVAL, index;
  1105. const struct firmware *ucode_raw;
  1106. const char *name_pre = priv->cfg->fw_name_pre;
  1107. const unsigned int api_max = priv->cfg->ucode_api_max;
  1108. const unsigned int api_min = priv->cfg->ucode_api_min;
  1109. char buf[25];
  1110. u8 *src;
  1111. size_t len;
  1112. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1113. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1114. * request_firmware() is synchronous, file is in memory on return. */
  1115. for (index = api_max; index >= api_min; index--) {
  1116. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1117. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1118. if (ret < 0) {
  1119. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1120. buf, ret);
  1121. if (ret == -ENOENT)
  1122. continue;
  1123. else
  1124. goto error;
  1125. } else {
  1126. if (index < api_max)
  1127. IWL_ERR(priv, "Loaded firmware %s, "
  1128. "which is deprecated. "
  1129. "Please use API v%u instead.\n",
  1130. buf, api_max);
  1131. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1132. buf, ucode_raw->size);
  1133. break;
  1134. }
  1135. }
  1136. if (ret < 0)
  1137. goto error;
  1138. /* Make sure that we got at least our header! */
  1139. if (ucode_raw->size < sizeof(*ucode)) {
  1140. IWL_ERR(priv, "File size way too small!\n");
  1141. ret = -EINVAL;
  1142. goto err_release;
  1143. }
  1144. /* Data from ucode file: header followed by uCode images */
  1145. ucode = (void *)ucode_raw->data;
  1146. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1147. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1148. inst_size = le32_to_cpu(ucode->inst_size);
  1149. data_size = le32_to_cpu(ucode->data_size);
  1150. init_size = le32_to_cpu(ucode->init_size);
  1151. init_data_size = le32_to_cpu(ucode->init_data_size);
  1152. boot_size = le32_to_cpu(ucode->boot_size);
  1153. /* api_ver should match the api version forming part of the
  1154. * firmware filename ... but we don't check for that and only rely
  1155. * on the API version read from firmware header from here on forward */
  1156. if (api_ver < api_min || api_ver > api_max) {
  1157. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1158. "Driver supports v%u, firmware is v%u.\n",
  1159. api_max, api_ver);
  1160. priv->ucode_ver = 0;
  1161. ret = -EINVAL;
  1162. goto err_release;
  1163. }
  1164. if (api_ver != api_max)
  1165. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1166. "got v%u. New firmware can be obtained "
  1167. "from http://www.intellinuxwireless.org.\n",
  1168. api_max, api_ver);
  1169. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1170. IWL_UCODE_MAJOR(priv->ucode_ver),
  1171. IWL_UCODE_MINOR(priv->ucode_ver),
  1172. IWL_UCODE_API(priv->ucode_ver),
  1173. IWL_UCODE_SERIAL(priv->ucode_ver));
  1174. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1175. priv->ucode_ver);
  1176. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1177. inst_size);
  1178. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1179. data_size);
  1180. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1181. init_size);
  1182. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1183. init_data_size);
  1184. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1185. boot_size);
  1186. /* Verify size of file vs. image size info in file's header */
  1187. if (ucode_raw->size < sizeof(*ucode) +
  1188. inst_size + data_size + init_size +
  1189. init_data_size + boot_size) {
  1190. IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
  1191. (int)ucode_raw->size);
  1192. ret = -EINVAL;
  1193. goto err_release;
  1194. }
  1195. /* Verify that uCode images will fit in card's SRAM */
  1196. if (inst_size > priv->hw_params.max_inst_size) {
  1197. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1198. inst_size);
  1199. ret = -EINVAL;
  1200. goto err_release;
  1201. }
  1202. if (data_size > priv->hw_params.max_data_size) {
  1203. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1204. data_size);
  1205. ret = -EINVAL;
  1206. goto err_release;
  1207. }
  1208. if (init_size > priv->hw_params.max_inst_size) {
  1209. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1210. init_size);
  1211. ret = -EINVAL;
  1212. goto err_release;
  1213. }
  1214. if (init_data_size > priv->hw_params.max_data_size) {
  1215. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1216. init_data_size);
  1217. ret = -EINVAL;
  1218. goto err_release;
  1219. }
  1220. if (boot_size > priv->hw_params.max_bsm_size) {
  1221. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1222. boot_size);
  1223. ret = -EINVAL;
  1224. goto err_release;
  1225. }
  1226. /* Allocate ucode buffers for card's bus-master loading ... */
  1227. /* Runtime instructions and 2 copies of data:
  1228. * 1) unmodified from disk
  1229. * 2) backup cache for save/restore during power-downs */
  1230. priv->ucode_code.len = inst_size;
  1231. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1232. priv->ucode_data.len = data_size;
  1233. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1234. priv->ucode_data_backup.len = data_size;
  1235. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1236. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1237. !priv->ucode_data_backup.v_addr)
  1238. goto err_pci_alloc;
  1239. /* Initialization instructions and data */
  1240. if (init_size && init_data_size) {
  1241. priv->ucode_init.len = init_size;
  1242. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1243. priv->ucode_init_data.len = init_data_size;
  1244. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1245. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1246. goto err_pci_alloc;
  1247. }
  1248. /* Bootstrap (instructions only, no data) */
  1249. if (boot_size) {
  1250. priv->ucode_boot.len = boot_size;
  1251. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1252. if (!priv->ucode_boot.v_addr)
  1253. goto err_pci_alloc;
  1254. }
  1255. /* Copy images into buffers for card's bus-master reads ... */
  1256. /* Runtime instructions (first block of data in file) */
  1257. src = &ucode->data[0];
  1258. len = priv->ucode_code.len;
  1259. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1260. memcpy(priv->ucode_code.v_addr, src, len);
  1261. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1262. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1263. /* Runtime data (2nd block)
  1264. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1265. src = &ucode->data[inst_size];
  1266. len = priv->ucode_data.len;
  1267. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1268. memcpy(priv->ucode_data.v_addr, src, len);
  1269. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1270. /* Initialization instructions (3rd block) */
  1271. if (init_size) {
  1272. src = &ucode->data[inst_size + data_size];
  1273. len = priv->ucode_init.len;
  1274. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1275. len);
  1276. memcpy(priv->ucode_init.v_addr, src, len);
  1277. }
  1278. /* Initialization data (4th block) */
  1279. if (init_data_size) {
  1280. src = &ucode->data[inst_size + data_size + init_size];
  1281. len = priv->ucode_init_data.len;
  1282. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1283. len);
  1284. memcpy(priv->ucode_init_data.v_addr, src, len);
  1285. }
  1286. /* Bootstrap instructions (5th block) */
  1287. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  1288. len = priv->ucode_boot.len;
  1289. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1290. memcpy(priv->ucode_boot.v_addr, src, len);
  1291. /* We have our copies now, allow OS release its copies */
  1292. release_firmware(ucode_raw);
  1293. return 0;
  1294. err_pci_alloc:
  1295. IWL_ERR(priv, "failed to allocate pci memory\n");
  1296. ret = -ENOMEM;
  1297. iwl_dealloc_ucode_pci(priv);
  1298. err_release:
  1299. release_firmware(ucode_raw);
  1300. error:
  1301. return ret;
  1302. }
  1303. /**
  1304. * iwl_alive_start - called after REPLY_ALIVE notification received
  1305. * from protocol/runtime uCode (initialization uCode's
  1306. * Alive gets handled by iwl_init_alive_start()).
  1307. */
  1308. static void iwl_alive_start(struct iwl_priv *priv)
  1309. {
  1310. int ret = 0;
  1311. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1312. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1313. /* We had an error bringing up the hardware, so take it
  1314. * all the way back down so we can try again */
  1315. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1316. goto restart;
  1317. }
  1318. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1319. * This is a paranoid check, because we would not have gotten the
  1320. * "runtime" alive if code weren't properly loaded. */
  1321. if (iwl_verify_ucode(priv)) {
  1322. /* Runtime instruction load was bad;
  1323. * take it all the way back down so we can try again */
  1324. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1325. goto restart;
  1326. }
  1327. priv->cfg->ops->smgmt->clear_station_table(priv);
  1328. ret = priv->cfg->ops->lib->alive_notify(priv);
  1329. if (ret) {
  1330. IWL_WARN(priv,
  1331. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1332. goto restart;
  1333. }
  1334. /* After the ALIVE response, we can send host commands to the uCode */
  1335. set_bit(STATUS_ALIVE, &priv->status);
  1336. if (iwl_is_rfkill(priv))
  1337. return;
  1338. ieee80211_wake_queues(priv->hw);
  1339. priv->active_rate = priv->rates_mask;
  1340. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1341. if (iwl_is_associated(priv)) {
  1342. struct iwl_rxon_cmd *active_rxon =
  1343. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1344. /* apply any changes in staging */
  1345. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1346. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1347. } else {
  1348. /* Initialize our rx_config data */
  1349. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1350. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1351. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1352. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1353. }
  1354. /* Configure Bluetooth device coexistence support */
  1355. iwl_send_bt_config(priv);
  1356. iwl_reset_run_time_calib(priv);
  1357. /* Configure the adapter for unassociated operation */
  1358. iwlcore_commit_rxon(priv);
  1359. /* At this point, the NIC is initialized and operational */
  1360. iwl_rf_kill_ct_config(priv);
  1361. iwl_leds_register(priv);
  1362. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1363. set_bit(STATUS_READY, &priv->status);
  1364. wake_up_interruptible(&priv->wait_command_queue);
  1365. iwl_power_update_mode(priv, 1);
  1366. /* reassociate for ADHOC mode */
  1367. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1368. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1369. priv->vif);
  1370. if (beacon)
  1371. iwl_mac_beacon_update(priv->hw, beacon);
  1372. }
  1373. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1374. iwl_set_mode(priv, priv->iw_mode);
  1375. return;
  1376. restart:
  1377. queue_work(priv->workqueue, &priv->restart);
  1378. }
  1379. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1380. static void __iwl_down(struct iwl_priv *priv)
  1381. {
  1382. unsigned long flags;
  1383. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1384. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1385. if (!exit_pending)
  1386. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1387. iwl_leds_unregister(priv);
  1388. priv->cfg->ops->smgmt->clear_station_table(priv);
  1389. /* Unblock any waiting calls */
  1390. wake_up_interruptible_all(&priv->wait_command_queue);
  1391. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1392. * exiting the module */
  1393. if (!exit_pending)
  1394. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1395. /* stop and reset the on-board processor */
  1396. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1397. /* tell the device to stop sending interrupts */
  1398. spin_lock_irqsave(&priv->lock, flags);
  1399. iwl_disable_interrupts(priv);
  1400. spin_unlock_irqrestore(&priv->lock, flags);
  1401. iwl_synchronize_irq(priv);
  1402. if (priv->mac80211_registered)
  1403. ieee80211_stop_queues(priv->hw);
  1404. /* If we have not previously called iwl_init() then
  1405. * clear all bits but the RF Kill bits and return */
  1406. if (!iwl_is_init(priv)) {
  1407. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1408. STATUS_RF_KILL_HW |
  1409. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1410. STATUS_RF_KILL_SW |
  1411. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1412. STATUS_GEO_CONFIGURED |
  1413. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1414. STATUS_EXIT_PENDING;
  1415. goto exit;
  1416. }
  1417. /* ...otherwise clear out all the status bits but the RF Kill
  1418. * bits and continue taking the NIC down. */
  1419. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1420. STATUS_RF_KILL_HW |
  1421. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1422. STATUS_RF_KILL_SW |
  1423. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1424. STATUS_GEO_CONFIGURED |
  1425. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1426. STATUS_FW_ERROR |
  1427. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1428. STATUS_EXIT_PENDING;
  1429. /* device going down, Stop using ICT table */
  1430. iwl_disable_ict(priv);
  1431. spin_lock_irqsave(&priv->lock, flags);
  1432. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1433. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1434. spin_unlock_irqrestore(&priv->lock, flags);
  1435. iwl_txq_ctx_stop(priv);
  1436. iwl_rxq_stop(priv);
  1437. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1438. APMG_CLK_VAL_DMA_CLK_RQT);
  1439. udelay(5);
  1440. /* FIXME: apm_ops.suspend(priv) */
  1441. if (exit_pending)
  1442. priv->cfg->ops->lib->apm_ops.stop(priv);
  1443. else
  1444. priv->cfg->ops->lib->apm_ops.reset(priv);
  1445. exit:
  1446. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1447. if (priv->ibss_beacon)
  1448. dev_kfree_skb(priv->ibss_beacon);
  1449. priv->ibss_beacon = NULL;
  1450. /* clear out any free frames */
  1451. iwl_clear_free_frames(priv);
  1452. }
  1453. static void iwl_down(struct iwl_priv *priv)
  1454. {
  1455. mutex_lock(&priv->mutex);
  1456. __iwl_down(priv);
  1457. mutex_unlock(&priv->mutex);
  1458. iwl_cancel_deferred_work(priv);
  1459. }
  1460. #define MAX_HW_RESTARTS 5
  1461. static int __iwl_up(struct iwl_priv *priv)
  1462. {
  1463. int i;
  1464. int ret;
  1465. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1466. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1467. return -EIO;
  1468. }
  1469. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1470. IWL_ERR(priv, "ucode not available for device bringup\n");
  1471. return -EIO;
  1472. }
  1473. /* If platform's RF_KILL switch is NOT set to KILL */
  1474. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1475. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1476. else
  1477. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1478. if (iwl_is_rfkill(priv)) {
  1479. iwl_enable_interrupts(priv);
  1480. IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
  1481. test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
  1482. return 0;
  1483. }
  1484. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1485. ret = iwl_hw_nic_init(priv);
  1486. if (ret) {
  1487. IWL_ERR(priv, "Unable to init nic\n");
  1488. return ret;
  1489. }
  1490. /* make sure rfkill handshake bits are cleared */
  1491. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1492. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1493. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1494. /* clear (again), then enable host interrupts */
  1495. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1496. /* enable dram interrupt */
  1497. iwl_reset_ict(priv);
  1498. iwl_enable_interrupts(priv);
  1499. /* really make sure rfkill handshake bits are cleared */
  1500. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1501. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1502. /* Copy original ucode data image from disk into backup cache.
  1503. * This will be used to initialize the on-board processor's
  1504. * data SRAM for a clean start when the runtime program first loads. */
  1505. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1506. priv->ucode_data.len);
  1507. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1508. priv->cfg->ops->smgmt->clear_station_table(priv);
  1509. /* load bootstrap state machine,
  1510. * load bootstrap program into processor's memory,
  1511. * prepare to load the "initialize" uCode */
  1512. ret = priv->cfg->ops->lib->load_ucode(priv);
  1513. if (ret) {
  1514. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1515. ret);
  1516. continue;
  1517. }
  1518. /* start card; "initialize" will load runtime ucode */
  1519. iwl_nic_start(priv);
  1520. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1521. return 0;
  1522. }
  1523. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1524. __iwl_down(priv);
  1525. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1526. /* tried to restart and config the device for as long as our
  1527. * patience could withstand */
  1528. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1529. return -EIO;
  1530. }
  1531. /*****************************************************************************
  1532. *
  1533. * Workqueue callbacks
  1534. *
  1535. *****************************************************************************/
  1536. static void iwl_bg_init_alive_start(struct work_struct *data)
  1537. {
  1538. struct iwl_priv *priv =
  1539. container_of(data, struct iwl_priv, init_alive_start.work);
  1540. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1541. return;
  1542. mutex_lock(&priv->mutex);
  1543. priv->cfg->ops->lib->init_alive_start(priv);
  1544. mutex_unlock(&priv->mutex);
  1545. }
  1546. static void iwl_bg_alive_start(struct work_struct *data)
  1547. {
  1548. struct iwl_priv *priv =
  1549. container_of(data, struct iwl_priv, alive_start.work);
  1550. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1551. return;
  1552. mutex_lock(&priv->mutex);
  1553. iwl_alive_start(priv);
  1554. mutex_unlock(&priv->mutex);
  1555. }
  1556. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1557. {
  1558. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1559. run_time_calib_work);
  1560. mutex_lock(&priv->mutex);
  1561. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1562. test_bit(STATUS_SCANNING, &priv->status)) {
  1563. mutex_unlock(&priv->mutex);
  1564. return;
  1565. }
  1566. if (priv->start_calib) {
  1567. iwl_chain_noise_calibration(priv, &priv->statistics);
  1568. iwl_sensitivity_calibration(priv, &priv->statistics);
  1569. }
  1570. mutex_unlock(&priv->mutex);
  1571. return;
  1572. }
  1573. static void iwl_bg_up(struct work_struct *data)
  1574. {
  1575. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1576. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1577. return;
  1578. mutex_lock(&priv->mutex);
  1579. __iwl_up(priv);
  1580. mutex_unlock(&priv->mutex);
  1581. iwl_rfkill_set_hw_state(priv);
  1582. }
  1583. static void iwl_bg_restart(struct work_struct *data)
  1584. {
  1585. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1586. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1587. return;
  1588. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1589. mutex_lock(&priv->mutex);
  1590. priv->vif = NULL;
  1591. priv->is_open = 0;
  1592. mutex_unlock(&priv->mutex);
  1593. iwl_down(priv);
  1594. ieee80211_restart_hw(priv->hw);
  1595. } else {
  1596. iwl_down(priv);
  1597. queue_work(priv->workqueue, &priv->up);
  1598. }
  1599. }
  1600. static void iwl_bg_rx_replenish(struct work_struct *data)
  1601. {
  1602. struct iwl_priv *priv =
  1603. container_of(data, struct iwl_priv, rx_replenish);
  1604. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1605. return;
  1606. mutex_lock(&priv->mutex);
  1607. iwl_rx_replenish(priv);
  1608. mutex_unlock(&priv->mutex);
  1609. }
  1610. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1611. void iwl_post_associate(struct iwl_priv *priv)
  1612. {
  1613. struct ieee80211_conf *conf = NULL;
  1614. int ret = 0;
  1615. unsigned long flags;
  1616. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1617. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1618. return;
  1619. }
  1620. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1621. priv->assoc_id, priv->active_rxon.bssid_addr);
  1622. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1623. return;
  1624. if (!priv->vif || !priv->is_open)
  1625. return;
  1626. iwl_scan_cancel_timeout(priv, 200);
  1627. conf = ieee80211_get_hw_conf(priv->hw);
  1628. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1629. iwlcore_commit_rxon(priv);
  1630. iwl_setup_rxon_timing(priv);
  1631. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1632. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1633. if (ret)
  1634. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1635. "Attempting to continue.\n");
  1636. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1637. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1638. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1639. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1640. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1641. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1642. priv->assoc_id, priv->beacon_int);
  1643. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1644. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1645. else
  1646. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1647. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1648. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1649. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1650. else
  1651. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1652. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1653. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1654. }
  1655. iwlcore_commit_rxon(priv);
  1656. switch (priv->iw_mode) {
  1657. case NL80211_IFTYPE_STATION:
  1658. break;
  1659. case NL80211_IFTYPE_ADHOC:
  1660. /* assume default assoc id */
  1661. priv->assoc_id = 1;
  1662. iwl_rxon_add_station(priv, priv->bssid, 0);
  1663. iwl_send_beacon_cmd(priv);
  1664. break;
  1665. default:
  1666. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1667. __func__, priv->iw_mode);
  1668. break;
  1669. }
  1670. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1671. priv->assoc_station_added = 1;
  1672. spin_lock_irqsave(&priv->lock, flags);
  1673. iwl_activate_qos(priv, 0);
  1674. spin_unlock_irqrestore(&priv->lock, flags);
  1675. /* the chain noise calibration will enabled PM upon completion
  1676. * If chain noise has already been run, then we need to enable
  1677. * power management here */
  1678. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1679. iwl_power_update_mode(priv, 0);
  1680. /* Enable Rx differential gain and sensitivity calibrations */
  1681. iwl_chain_noise_reset(priv);
  1682. priv->start_calib = 1;
  1683. }
  1684. /*****************************************************************************
  1685. *
  1686. * mac80211 entry point functions
  1687. *
  1688. *****************************************************************************/
  1689. #define UCODE_READY_TIMEOUT (4 * HZ)
  1690. static int iwl_mac_start(struct ieee80211_hw *hw)
  1691. {
  1692. struct iwl_priv *priv = hw->priv;
  1693. int ret;
  1694. IWL_DEBUG_MAC80211(priv, "enter\n");
  1695. /* we should be verifying the device is ready to be opened */
  1696. mutex_lock(&priv->mutex);
  1697. memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
  1698. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1699. * ucode filename and max sizes are card-specific. */
  1700. if (!priv->ucode_code.len) {
  1701. ret = iwl_read_ucode(priv);
  1702. if (ret) {
  1703. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1704. mutex_unlock(&priv->mutex);
  1705. return ret;
  1706. }
  1707. }
  1708. ret = __iwl_up(priv);
  1709. mutex_unlock(&priv->mutex);
  1710. iwl_rfkill_set_hw_state(priv);
  1711. if (ret)
  1712. return ret;
  1713. if (iwl_is_rfkill(priv))
  1714. goto out;
  1715. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1716. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1717. * mac80211 will not be run successfully. */
  1718. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1719. test_bit(STATUS_READY, &priv->status),
  1720. UCODE_READY_TIMEOUT);
  1721. if (!ret) {
  1722. if (!test_bit(STATUS_READY, &priv->status)) {
  1723. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1724. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1725. return -ETIMEDOUT;
  1726. }
  1727. }
  1728. out:
  1729. priv->is_open = 1;
  1730. IWL_DEBUG_MAC80211(priv, "leave\n");
  1731. return 0;
  1732. }
  1733. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1734. {
  1735. struct iwl_priv *priv = hw->priv;
  1736. IWL_DEBUG_MAC80211(priv, "enter\n");
  1737. if (!priv->is_open)
  1738. return;
  1739. priv->is_open = 0;
  1740. if (iwl_is_ready_rf(priv)) {
  1741. /* stop mac, cancel any scan request and clear
  1742. * RXON_FILTER_ASSOC_MSK BIT
  1743. */
  1744. mutex_lock(&priv->mutex);
  1745. iwl_scan_cancel_timeout(priv, 100);
  1746. mutex_unlock(&priv->mutex);
  1747. }
  1748. iwl_down(priv);
  1749. flush_workqueue(priv->workqueue);
  1750. /* enable interrupts again in order to receive rfkill changes */
  1751. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1752. iwl_enable_interrupts(priv);
  1753. IWL_DEBUG_MAC80211(priv, "leave\n");
  1754. }
  1755. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1756. {
  1757. struct iwl_priv *priv = hw->priv;
  1758. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1759. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1760. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1761. if (iwl_tx_skb(priv, skb))
  1762. dev_kfree_skb_any(skb);
  1763. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1764. return NETDEV_TX_OK;
  1765. }
  1766. void iwl_config_ap(struct iwl_priv *priv)
  1767. {
  1768. int ret = 0;
  1769. unsigned long flags;
  1770. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1771. return;
  1772. /* The following should be done only at AP bring up */
  1773. if (!iwl_is_associated(priv)) {
  1774. /* RXON - unassoc (to set timing command) */
  1775. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1776. iwlcore_commit_rxon(priv);
  1777. /* RXON Timing */
  1778. iwl_setup_rxon_timing(priv);
  1779. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1780. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1781. if (ret)
  1782. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1783. "Attempting to continue.\n");
  1784. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1785. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1786. /* FIXME: what should be the assoc_id for AP? */
  1787. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1788. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1789. priv->staging_rxon.flags |=
  1790. RXON_FLG_SHORT_PREAMBLE_MSK;
  1791. else
  1792. priv->staging_rxon.flags &=
  1793. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1794. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1795. if (priv->assoc_capability &
  1796. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1797. priv->staging_rxon.flags |=
  1798. RXON_FLG_SHORT_SLOT_MSK;
  1799. else
  1800. priv->staging_rxon.flags &=
  1801. ~RXON_FLG_SHORT_SLOT_MSK;
  1802. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1803. priv->staging_rxon.flags &=
  1804. ~RXON_FLG_SHORT_SLOT_MSK;
  1805. }
  1806. /* restore RXON assoc */
  1807. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1808. iwlcore_commit_rxon(priv);
  1809. spin_lock_irqsave(&priv->lock, flags);
  1810. iwl_activate_qos(priv, 1);
  1811. spin_unlock_irqrestore(&priv->lock, flags);
  1812. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1813. }
  1814. iwl_send_beacon_cmd(priv);
  1815. /* FIXME - we need to add code here to detect a totally new
  1816. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1817. * clear sta table, add BCAST sta... */
  1818. }
  1819. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1820. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1821. u32 iv32, u16 *phase1key)
  1822. {
  1823. struct iwl_priv *priv = hw->priv;
  1824. IWL_DEBUG_MAC80211(priv, "enter\n");
  1825. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1826. IWL_DEBUG_MAC80211(priv, "leave\n");
  1827. }
  1828. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1829. struct ieee80211_vif *vif,
  1830. struct ieee80211_sta *sta,
  1831. struct ieee80211_key_conf *key)
  1832. {
  1833. struct iwl_priv *priv = hw->priv;
  1834. const u8 *addr;
  1835. int ret;
  1836. u8 sta_id;
  1837. bool is_default_wep_key = false;
  1838. IWL_DEBUG_MAC80211(priv, "enter\n");
  1839. if (priv->hw_params.sw_crypto) {
  1840. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1841. return -EOPNOTSUPP;
  1842. }
  1843. addr = sta ? sta->addr : iwl_bcast_addr;
  1844. sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
  1845. if (sta_id == IWL_INVALID_STATION) {
  1846. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1847. addr);
  1848. return -EINVAL;
  1849. }
  1850. mutex_lock(&priv->mutex);
  1851. iwl_scan_cancel_timeout(priv, 100);
  1852. mutex_unlock(&priv->mutex);
  1853. /* If we are getting WEP group key and we didn't receive any key mapping
  1854. * so far, we are in legacy wep mode (group key only), otherwise we are
  1855. * in 1X mode.
  1856. * In legacy wep mode, we use another host command to the uCode */
  1857. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1858. priv->iw_mode != NL80211_IFTYPE_AP) {
  1859. if (cmd == SET_KEY)
  1860. is_default_wep_key = !priv->key_mapping_key;
  1861. else
  1862. is_default_wep_key =
  1863. (key->hw_key_idx == HW_KEY_DEFAULT);
  1864. }
  1865. switch (cmd) {
  1866. case SET_KEY:
  1867. if (is_default_wep_key)
  1868. ret = iwl_set_default_wep_key(priv, key);
  1869. else
  1870. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1871. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1872. break;
  1873. case DISABLE_KEY:
  1874. if (is_default_wep_key)
  1875. ret = iwl_remove_default_wep_key(priv, key);
  1876. else
  1877. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1878. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1879. break;
  1880. default:
  1881. ret = -EINVAL;
  1882. }
  1883. IWL_DEBUG_MAC80211(priv, "leave\n");
  1884. return ret;
  1885. }
  1886. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1887. enum ieee80211_ampdu_mlme_action action,
  1888. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1889. {
  1890. struct iwl_priv *priv = hw->priv;
  1891. int ret;
  1892. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1893. sta->addr, tid);
  1894. if (!(priv->cfg->sku & IWL_SKU_N))
  1895. return -EACCES;
  1896. switch (action) {
  1897. case IEEE80211_AMPDU_RX_START:
  1898. IWL_DEBUG_HT(priv, "start Rx\n");
  1899. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1900. case IEEE80211_AMPDU_RX_STOP:
  1901. IWL_DEBUG_HT(priv, "stop Rx\n");
  1902. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1903. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1904. return 0;
  1905. else
  1906. return ret;
  1907. case IEEE80211_AMPDU_TX_START:
  1908. IWL_DEBUG_HT(priv, "start Tx\n");
  1909. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1910. case IEEE80211_AMPDU_TX_STOP:
  1911. IWL_DEBUG_HT(priv, "stop Tx\n");
  1912. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1913. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1914. return 0;
  1915. else
  1916. return ret;
  1917. default:
  1918. IWL_DEBUG_HT(priv, "unknown\n");
  1919. return -EINVAL;
  1920. break;
  1921. }
  1922. return 0;
  1923. }
  1924. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1925. struct ieee80211_low_level_stats *stats)
  1926. {
  1927. struct iwl_priv *priv = hw->priv;
  1928. priv = hw->priv;
  1929. IWL_DEBUG_MAC80211(priv, "enter\n");
  1930. IWL_DEBUG_MAC80211(priv, "leave\n");
  1931. return 0;
  1932. }
  1933. /*****************************************************************************
  1934. *
  1935. * sysfs attributes
  1936. *
  1937. *****************************************************************************/
  1938. #ifdef CONFIG_IWLWIFI_DEBUG
  1939. /*
  1940. * The following adds a new attribute to the sysfs representation
  1941. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1942. * used for controlling the debug level.
  1943. *
  1944. * See the level definitions in iwl for details.
  1945. */
  1946. static ssize_t show_debug_level(struct device *d,
  1947. struct device_attribute *attr, char *buf)
  1948. {
  1949. struct iwl_priv *priv = dev_get_drvdata(d);
  1950. return sprintf(buf, "0x%08X\n", priv->debug_level);
  1951. }
  1952. static ssize_t store_debug_level(struct device *d,
  1953. struct device_attribute *attr,
  1954. const char *buf, size_t count)
  1955. {
  1956. struct iwl_priv *priv = dev_get_drvdata(d);
  1957. unsigned long val;
  1958. int ret;
  1959. ret = strict_strtoul(buf, 0, &val);
  1960. if (ret)
  1961. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1962. else
  1963. priv->debug_level = val;
  1964. return strnlen(buf, count);
  1965. }
  1966. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1967. show_debug_level, store_debug_level);
  1968. #endif /* CONFIG_IWLWIFI_DEBUG */
  1969. static ssize_t show_version(struct device *d,
  1970. struct device_attribute *attr, char *buf)
  1971. {
  1972. struct iwl_priv *priv = dev_get_drvdata(d);
  1973. struct iwl_alive_resp *palive = &priv->card_alive;
  1974. ssize_t pos = 0;
  1975. u16 eeprom_ver;
  1976. if (palive->is_valid)
  1977. pos += sprintf(buf + pos,
  1978. "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
  1979. "fw type: 0x%01X 0x%01X\n",
  1980. palive->ucode_major, palive->ucode_minor,
  1981. palive->sw_rev[0], palive->sw_rev[1],
  1982. palive->ver_type, palive->ver_subtype);
  1983. else
  1984. pos += sprintf(buf + pos, "fw not loaded\n");
  1985. if (priv->eeprom) {
  1986. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1987. pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
  1988. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1989. ? "OTP" : "EEPROM", eeprom_ver);
  1990. } else {
  1991. pos += sprintf(buf + pos, "EEPROM not initialzed\n");
  1992. }
  1993. return pos;
  1994. }
  1995. static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
  1996. static ssize_t show_temperature(struct device *d,
  1997. struct device_attribute *attr, char *buf)
  1998. {
  1999. struct iwl_priv *priv = dev_get_drvdata(d);
  2000. if (!iwl_is_alive(priv))
  2001. return -EAGAIN;
  2002. return sprintf(buf, "%d\n", priv->temperature);
  2003. }
  2004. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2005. static ssize_t show_tx_power(struct device *d,
  2006. struct device_attribute *attr, char *buf)
  2007. {
  2008. struct iwl_priv *priv = dev_get_drvdata(d);
  2009. if (!iwl_is_ready_rf(priv))
  2010. return sprintf(buf, "off\n");
  2011. else
  2012. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2013. }
  2014. static ssize_t store_tx_power(struct device *d,
  2015. struct device_attribute *attr,
  2016. const char *buf, size_t count)
  2017. {
  2018. struct iwl_priv *priv = dev_get_drvdata(d);
  2019. unsigned long val;
  2020. int ret;
  2021. ret = strict_strtoul(buf, 10, &val);
  2022. if (ret)
  2023. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2024. else
  2025. iwl_set_tx_power(priv, val, false);
  2026. return count;
  2027. }
  2028. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2029. static ssize_t show_flags(struct device *d,
  2030. struct device_attribute *attr, char *buf)
  2031. {
  2032. struct iwl_priv *priv = dev_get_drvdata(d);
  2033. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2034. }
  2035. static ssize_t store_flags(struct device *d,
  2036. struct device_attribute *attr,
  2037. const char *buf, size_t count)
  2038. {
  2039. struct iwl_priv *priv = dev_get_drvdata(d);
  2040. unsigned long val;
  2041. u32 flags;
  2042. int ret = strict_strtoul(buf, 0, &val);
  2043. if (ret)
  2044. return ret;
  2045. flags = (u32)val;
  2046. mutex_lock(&priv->mutex);
  2047. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2048. /* Cancel any currently running scans... */
  2049. if (iwl_scan_cancel_timeout(priv, 100))
  2050. IWL_WARN(priv, "Could not cancel scan.\n");
  2051. else {
  2052. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2053. priv->staging_rxon.flags = cpu_to_le32(flags);
  2054. iwlcore_commit_rxon(priv);
  2055. }
  2056. }
  2057. mutex_unlock(&priv->mutex);
  2058. return count;
  2059. }
  2060. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2061. static ssize_t show_filter_flags(struct device *d,
  2062. struct device_attribute *attr, char *buf)
  2063. {
  2064. struct iwl_priv *priv = dev_get_drvdata(d);
  2065. return sprintf(buf, "0x%04X\n",
  2066. le32_to_cpu(priv->active_rxon.filter_flags));
  2067. }
  2068. static ssize_t store_filter_flags(struct device *d,
  2069. struct device_attribute *attr,
  2070. const char *buf, size_t count)
  2071. {
  2072. struct iwl_priv *priv = dev_get_drvdata(d);
  2073. unsigned long val;
  2074. u32 filter_flags;
  2075. int ret = strict_strtoul(buf, 0, &val);
  2076. if (ret)
  2077. return ret;
  2078. filter_flags = (u32)val;
  2079. mutex_lock(&priv->mutex);
  2080. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2081. /* Cancel any currently running scans... */
  2082. if (iwl_scan_cancel_timeout(priv, 100))
  2083. IWL_WARN(priv, "Could not cancel scan.\n");
  2084. else {
  2085. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2086. "0x%04X\n", filter_flags);
  2087. priv->staging_rxon.filter_flags =
  2088. cpu_to_le32(filter_flags);
  2089. iwlcore_commit_rxon(priv);
  2090. }
  2091. }
  2092. mutex_unlock(&priv->mutex);
  2093. return count;
  2094. }
  2095. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2096. store_filter_flags);
  2097. static ssize_t store_power_level(struct device *d,
  2098. struct device_attribute *attr,
  2099. const char *buf, size_t count)
  2100. {
  2101. struct iwl_priv *priv = dev_get_drvdata(d);
  2102. int ret;
  2103. unsigned long mode;
  2104. mutex_lock(&priv->mutex);
  2105. ret = strict_strtoul(buf, 10, &mode);
  2106. if (ret)
  2107. goto out;
  2108. ret = iwl_power_set_user_mode(priv, mode);
  2109. if (ret) {
  2110. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  2111. goto out;
  2112. }
  2113. ret = count;
  2114. out:
  2115. mutex_unlock(&priv->mutex);
  2116. return ret;
  2117. }
  2118. static ssize_t show_power_level(struct device *d,
  2119. struct device_attribute *attr, char *buf)
  2120. {
  2121. struct iwl_priv *priv = dev_get_drvdata(d);
  2122. int mode = priv->power_data.user_power_setting;
  2123. int level = priv->power_data.power_mode;
  2124. char *p = buf;
  2125. p += sprintf(p, "INDEX:%d\t", level);
  2126. p += sprintf(p, "USER:%d\n", mode);
  2127. return p - buf + 1;
  2128. }
  2129. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2130. store_power_level);
  2131. static ssize_t show_qos(struct device *d,
  2132. struct device_attribute *attr, char *buf)
  2133. {
  2134. struct iwl_priv *priv = dev_get_drvdata(d);
  2135. char *p = buf;
  2136. int q;
  2137. for (q = 0; q < AC_NUM; q++) {
  2138. p += sprintf(p, "\tcw_min\tcw_max\taifsn\ttxop\n");
  2139. p += sprintf(p, "AC[%d]\t%u\t%u\t%u\t%u\n", q,
  2140. priv->qos_data.def_qos_parm.ac[q].cw_min,
  2141. priv->qos_data.def_qos_parm.ac[q].cw_max,
  2142. priv->qos_data.def_qos_parm.ac[q].aifsn,
  2143. priv->qos_data.def_qos_parm.ac[q].edca_txop);
  2144. }
  2145. return p - buf + 1;
  2146. }
  2147. static DEVICE_ATTR(qos, S_IRUGO, show_qos, NULL);
  2148. static ssize_t show_statistics(struct device *d,
  2149. struct device_attribute *attr, char *buf)
  2150. {
  2151. struct iwl_priv *priv = dev_get_drvdata(d);
  2152. u32 size = sizeof(struct iwl_notif_statistics);
  2153. u32 len = 0, ofs = 0;
  2154. u8 *data = (u8 *)&priv->statistics;
  2155. int rc = 0;
  2156. if (!iwl_is_alive(priv))
  2157. return -EAGAIN;
  2158. mutex_lock(&priv->mutex);
  2159. rc = iwl_send_statistics_request(priv, 0);
  2160. mutex_unlock(&priv->mutex);
  2161. if (rc) {
  2162. len = sprintf(buf,
  2163. "Error sending statistics request: 0x%08X\n", rc);
  2164. return len;
  2165. }
  2166. while (size && (PAGE_SIZE - len)) {
  2167. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2168. PAGE_SIZE - len, 1);
  2169. len = strlen(buf);
  2170. if (PAGE_SIZE - len)
  2171. buf[len++] = '\n';
  2172. ofs += 16;
  2173. size -= min(size, 16U);
  2174. }
  2175. return len;
  2176. }
  2177. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2178. /*****************************************************************************
  2179. *
  2180. * driver setup and teardown
  2181. *
  2182. *****************************************************************************/
  2183. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2184. {
  2185. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2186. init_waitqueue_head(&priv->wait_command_queue);
  2187. INIT_WORK(&priv->up, iwl_bg_up);
  2188. INIT_WORK(&priv->restart, iwl_bg_restart);
  2189. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2190. INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
  2191. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2192. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2193. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2194. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2195. iwl_setup_scan_deferred_work(priv);
  2196. if (priv->cfg->ops->lib->setup_deferred_work)
  2197. priv->cfg->ops->lib->setup_deferred_work(priv);
  2198. init_timer(&priv->statistics_periodic);
  2199. priv->statistics_periodic.data = (unsigned long)priv;
  2200. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2201. if (!priv->cfg->use_isr_legacy)
  2202. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2203. iwl_irq_tasklet, (unsigned long)priv);
  2204. else
  2205. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2206. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2207. }
  2208. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2209. {
  2210. if (priv->cfg->ops->lib->cancel_deferred_work)
  2211. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2212. cancel_delayed_work_sync(&priv->init_alive_start);
  2213. cancel_delayed_work(&priv->scan_check);
  2214. cancel_delayed_work(&priv->alive_start);
  2215. cancel_work_sync(&priv->beacon_update);
  2216. del_timer_sync(&priv->statistics_periodic);
  2217. }
  2218. static struct attribute *iwl_sysfs_entries[] = {
  2219. &dev_attr_flags.attr,
  2220. &dev_attr_filter_flags.attr,
  2221. &dev_attr_power_level.attr,
  2222. &dev_attr_statistics.attr,
  2223. &dev_attr_temperature.attr,
  2224. &dev_attr_tx_power.attr,
  2225. #ifdef CONFIG_IWLWIFI_DEBUG
  2226. &dev_attr_debug_level.attr,
  2227. #endif
  2228. &dev_attr_version.attr,
  2229. &dev_attr_qos.attr,
  2230. NULL
  2231. };
  2232. static struct attribute_group iwl_attribute_group = {
  2233. .name = NULL, /* put in device directory */
  2234. .attrs = iwl_sysfs_entries,
  2235. };
  2236. static struct ieee80211_ops iwl_hw_ops = {
  2237. .tx = iwl_mac_tx,
  2238. .start = iwl_mac_start,
  2239. .stop = iwl_mac_stop,
  2240. .add_interface = iwl_mac_add_interface,
  2241. .remove_interface = iwl_mac_remove_interface,
  2242. .config = iwl_mac_config,
  2243. .configure_filter = iwl_configure_filter,
  2244. .set_key = iwl_mac_set_key,
  2245. .update_tkip_key = iwl_mac_update_tkip_key,
  2246. .get_stats = iwl_mac_get_stats,
  2247. .get_tx_stats = iwl_mac_get_tx_stats,
  2248. .conf_tx = iwl_mac_conf_tx,
  2249. .reset_tsf = iwl_mac_reset_tsf,
  2250. .bss_info_changed = iwl_bss_info_changed,
  2251. .ampdu_action = iwl_mac_ampdu_action,
  2252. .hw_scan = iwl_mac_hw_scan
  2253. };
  2254. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2255. {
  2256. int err = 0;
  2257. struct iwl_priv *priv;
  2258. struct ieee80211_hw *hw;
  2259. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2260. unsigned long flags;
  2261. u16 pci_cmd;
  2262. /************************
  2263. * 1. Allocating HW data
  2264. ************************/
  2265. /* Disabling hardware scan means that mac80211 will perform scans
  2266. * "the hard way", rather than using device's scan. */
  2267. if (cfg->mod_params->disable_hw_scan) {
  2268. if (cfg->mod_params->debug & IWL_DL_INFO)
  2269. dev_printk(KERN_DEBUG, &(pdev->dev),
  2270. "Disabling hw_scan\n");
  2271. iwl_hw_ops.hw_scan = NULL;
  2272. }
  2273. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2274. if (!hw) {
  2275. err = -ENOMEM;
  2276. goto out;
  2277. }
  2278. priv = hw->priv;
  2279. /* At this point both hw and priv are allocated. */
  2280. SET_IEEE80211_DEV(hw, &pdev->dev);
  2281. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2282. priv->cfg = cfg;
  2283. priv->pci_dev = pdev;
  2284. #ifdef CONFIG_IWLWIFI_DEBUG
  2285. priv->debug_level = priv->cfg->mod_params->debug;
  2286. atomic_set(&priv->restrict_refcnt, 0);
  2287. #endif
  2288. /**************************
  2289. * 2. Initializing PCI bus
  2290. **************************/
  2291. if (pci_enable_device(pdev)) {
  2292. err = -ENODEV;
  2293. goto out_ieee80211_free_hw;
  2294. }
  2295. pci_set_master(pdev);
  2296. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2297. if (!err)
  2298. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2299. if (err) {
  2300. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2301. if (!err)
  2302. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2303. /* both attempts failed: */
  2304. if (err) {
  2305. IWL_WARN(priv, "No suitable DMA available.\n");
  2306. goto out_pci_disable_device;
  2307. }
  2308. }
  2309. err = pci_request_regions(pdev, DRV_NAME);
  2310. if (err)
  2311. goto out_pci_disable_device;
  2312. pci_set_drvdata(pdev, priv);
  2313. /***********************
  2314. * 3. Read REV register
  2315. ***********************/
  2316. priv->hw_base = pci_iomap(pdev, 0, 0);
  2317. if (!priv->hw_base) {
  2318. err = -ENODEV;
  2319. goto out_pci_release_regions;
  2320. }
  2321. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2322. (unsigned long long) pci_resource_len(pdev, 0));
  2323. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2324. /* this spin lock will be used in apm_ops.init and EEPROM access
  2325. * we should init now
  2326. */
  2327. spin_lock_init(&priv->reg_lock);
  2328. iwl_hw_detect(priv);
  2329. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2330. priv->cfg->name, priv->hw_rev);
  2331. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2332. * PCI Tx retries from interfering with C3 CPU state */
  2333. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2334. /* amp init */
  2335. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2336. if (err < 0) {
  2337. IWL_ERR(priv, "Failed to init APMG\n");
  2338. goto out_iounmap;
  2339. }
  2340. /*****************
  2341. * 4. Read EEPROM
  2342. *****************/
  2343. /* Read the EEPROM */
  2344. err = iwl_eeprom_init(priv);
  2345. if (err) {
  2346. IWL_ERR(priv, "Unable to init EEPROM\n");
  2347. goto out_iounmap;
  2348. }
  2349. err = iwl_eeprom_check_version(priv);
  2350. if (err)
  2351. goto out_free_eeprom;
  2352. /* extract MAC Address */
  2353. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2354. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2355. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2356. /************************
  2357. * 5. Setup HW constants
  2358. ************************/
  2359. if (iwl_set_hw_params(priv)) {
  2360. IWL_ERR(priv, "failed to set hw parameters\n");
  2361. goto out_free_eeprom;
  2362. }
  2363. /*******************
  2364. * 6. Setup priv
  2365. *******************/
  2366. err = iwl_init_drv(priv);
  2367. if (err)
  2368. goto out_free_eeprom;
  2369. /* At this point both hw and priv are initialized. */
  2370. /********************
  2371. * 7. Setup services
  2372. ********************/
  2373. spin_lock_irqsave(&priv->lock, flags);
  2374. iwl_disable_interrupts(priv);
  2375. spin_unlock_irqrestore(&priv->lock, flags);
  2376. pci_enable_msi(priv->pci_dev);
  2377. iwl_alloc_isr_ict(priv);
  2378. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2379. IRQF_SHARED, DRV_NAME, priv);
  2380. if (err) {
  2381. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2382. goto out_disable_msi;
  2383. }
  2384. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2385. if (err) {
  2386. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2387. goto out_free_irq;
  2388. }
  2389. iwl_setup_deferred_work(priv);
  2390. iwl_setup_rx_handlers(priv);
  2391. /**********************************
  2392. * 8. Setup and register mac80211
  2393. **********************************/
  2394. /* enable interrupts if needed: hw bug w/a */
  2395. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2396. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2397. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2398. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2399. }
  2400. iwl_enable_interrupts(priv);
  2401. err = iwl_setup_mac(priv);
  2402. if (err)
  2403. goto out_remove_sysfs;
  2404. err = iwl_dbgfs_register(priv, DRV_NAME);
  2405. if (err)
  2406. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2407. /* If platform's RF_KILL switch is NOT set to KILL */
  2408. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2409. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2410. else
  2411. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2412. err = iwl_rfkill_init(priv);
  2413. if (err)
  2414. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  2415. "Ignoring error: %d\n", err);
  2416. else
  2417. iwl_rfkill_set_hw_state(priv);
  2418. iwl_power_initialize(priv);
  2419. return 0;
  2420. out_remove_sysfs:
  2421. destroy_workqueue(priv->workqueue);
  2422. priv->workqueue = NULL;
  2423. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2424. out_free_irq:
  2425. free_irq(priv->pci_dev->irq, priv);
  2426. iwl_free_isr_ict(priv);
  2427. out_disable_msi:
  2428. pci_disable_msi(priv->pci_dev);
  2429. iwl_uninit_drv(priv);
  2430. out_free_eeprom:
  2431. iwl_eeprom_free(priv);
  2432. out_iounmap:
  2433. pci_iounmap(pdev, priv->hw_base);
  2434. out_pci_release_regions:
  2435. pci_set_drvdata(pdev, NULL);
  2436. pci_release_regions(pdev);
  2437. out_pci_disable_device:
  2438. pci_disable_device(pdev);
  2439. out_ieee80211_free_hw:
  2440. ieee80211_free_hw(priv->hw);
  2441. out:
  2442. return err;
  2443. }
  2444. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2445. {
  2446. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2447. unsigned long flags;
  2448. if (!priv)
  2449. return;
  2450. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2451. iwl_dbgfs_unregister(priv);
  2452. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2453. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2454. * to be called and iwl_down since we are removing the device
  2455. * we need to set STATUS_EXIT_PENDING bit.
  2456. */
  2457. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2458. if (priv->mac80211_registered) {
  2459. ieee80211_unregister_hw(priv->hw);
  2460. priv->mac80211_registered = 0;
  2461. } else {
  2462. iwl_down(priv);
  2463. }
  2464. /* make sure we flush any pending irq or
  2465. * tasklet for the driver
  2466. */
  2467. spin_lock_irqsave(&priv->lock, flags);
  2468. iwl_disable_interrupts(priv);
  2469. spin_unlock_irqrestore(&priv->lock, flags);
  2470. iwl_synchronize_irq(priv);
  2471. iwl_rfkill_unregister(priv);
  2472. iwl_dealloc_ucode_pci(priv);
  2473. if (priv->rxq.bd)
  2474. iwl_rx_queue_free(priv, &priv->rxq);
  2475. iwl_hw_txq_ctx_free(priv);
  2476. priv->cfg->ops->smgmt->clear_station_table(priv);
  2477. iwl_eeprom_free(priv);
  2478. /*netif_stop_queue(dev); */
  2479. flush_workqueue(priv->workqueue);
  2480. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2481. * priv->workqueue... so we can't take down the workqueue
  2482. * until now... */
  2483. destroy_workqueue(priv->workqueue);
  2484. priv->workqueue = NULL;
  2485. free_irq(priv->pci_dev->irq, priv);
  2486. pci_disable_msi(priv->pci_dev);
  2487. pci_iounmap(pdev, priv->hw_base);
  2488. pci_release_regions(pdev);
  2489. pci_disable_device(pdev);
  2490. pci_set_drvdata(pdev, NULL);
  2491. iwl_uninit_drv(priv);
  2492. iwl_free_isr_ict(priv);
  2493. if (priv->ibss_beacon)
  2494. dev_kfree_skb(priv->ibss_beacon);
  2495. ieee80211_free_hw(priv->hw);
  2496. }
  2497. /*****************************************************************************
  2498. *
  2499. * driver and module entry point
  2500. *
  2501. *****************************************************************************/
  2502. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2503. static struct pci_device_id iwl_hw_card_ids[] = {
  2504. #ifdef CONFIG_IWL4965
  2505. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2506. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2507. #endif /* CONFIG_IWL4965 */
  2508. #ifdef CONFIG_IWL5000
  2509. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2510. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2511. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2512. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2513. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2514. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2515. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2516. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2517. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2518. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2519. /* 5350 WiFi/WiMax */
  2520. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2521. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2522. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2523. /* 5150 Wifi/WiMax */
  2524. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2525. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2526. /* 6000/6050 Series */
  2527. {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
  2528. {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
  2529. {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
  2530. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2531. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2532. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2533. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2534. {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2535. {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2536. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2537. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2538. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2539. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2540. /* 1000 Series WiFi */
  2541. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2542. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2543. #endif /* CONFIG_IWL5000 */
  2544. {0}
  2545. };
  2546. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2547. static struct pci_driver iwl_driver = {
  2548. .name = DRV_NAME,
  2549. .id_table = iwl_hw_card_ids,
  2550. .probe = iwl_pci_probe,
  2551. .remove = __devexit_p(iwl_pci_remove),
  2552. #ifdef CONFIG_PM
  2553. .suspend = iwl_pci_suspend,
  2554. .resume = iwl_pci_resume,
  2555. #endif
  2556. };
  2557. static int __init iwl_init(void)
  2558. {
  2559. int ret;
  2560. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2561. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2562. ret = iwlagn_rate_control_register();
  2563. if (ret) {
  2564. printk(KERN_ERR DRV_NAME
  2565. "Unable to register rate control algorithm: %d\n", ret);
  2566. return ret;
  2567. }
  2568. ret = pci_register_driver(&iwl_driver);
  2569. if (ret) {
  2570. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2571. goto error_register;
  2572. }
  2573. return ret;
  2574. error_register:
  2575. iwlagn_rate_control_unregister();
  2576. return ret;
  2577. }
  2578. static void __exit iwl_exit(void)
  2579. {
  2580. pci_unregister_driver(&iwl_driver);
  2581. iwlagn_rate_control_unregister();
  2582. }
  2583. module_exit(iwl_exit);
  2584. module_init(iwl_init);