cpsw.txt 2.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394
  1. TI SoC Ethernet Switch Controller Device Tree Bindings
  2. ------------------------------------------------------
  3. Required properties:
  4. - compatible : Should be "ti,cpsw"
  5. - reg : physical base address and size of the cpsw
  6. registers map
  7. - interrupts : property with a value describing the interrupt
  8. number
  9. - interrupt-parent : The parent interrupt controller
  10. - cpdma_channels : Specifies number of channels in CPDMA
  11. - ale_entries : Specifies No of entries ALE can hold
  12. - bd_ram_size : Specifies internal descriptor RAM size
  13. - rx_descs : Specifies number of Rx descriptors
  14. - mac_control : Specifies Default MAC control register content
  15. for the specific platform
  16. - slaves : Specifies number for slaves
  17. - cpts_active_slave : Specifies the slave to use for time stamping
  18. - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds
  19. - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds
  20. Optional properties:
  21. - ti,hwmods : Must be "cpgmac0"
  22. - no_bd_ram : Must be 0 or 1
  23. - dual_emac : Specifies Switch to act as Dual EMAC
  24. Slave Properties:
  25. Required properties:
  26. - phy_id : Specifies slave phy id
  27. - mac-address : Specifies slave MAC address
  28. Optional properties:
  29. - dual_emac_res_vlan : Specifies VID to be used to segregate the ports
  30. Note: "ti,hwmods" field is used to fetch the base address and irq
  31. resources from TI, omap hwmod data base during device registration.
  32. Future plan is to migrate hwmod data base contents into device tree
  33. blob so that, all the required data will be used from device tree dts
  34. file.
  35. Examples:
  36. mac: ethernet@4A100000 {
  37. compatible = "ti,cpsw";
  38. reg = <0x4A100000 0x1000>;
  39. interrupts = <55 0x4>;
  40. interrupt-parent = <&intc>;
  41. cpdma_channels = <8>;
  42. ale_entries = <1024>;
  43. bd_ram_size = <0x2000>;
  44. no_bd_ram = <0>;
  45. rx_descs = <64>;
  46. mac_control = <0x20>;
  47. slaves = <2>;
  48. cpts_active_slave = <0>;
  49. cpts_clock_mult = <0x80000000>;
  50. cpts_clock_shift = <29>;
  51. cpsw_emac0: slave@0 {
  52. phy_id = <&davinci_mdio>, <0>;
  53. /* Filled in by U-Boot */
  54. mac-address = [ 00 00 00 00 00 00 ];
  55. };
  56. cpsw_emac1: slave@1 {
  57. phy_id = <&davinci_mdio>, <1>;
  58. /* Filled in by U-Boot */
  59. mac-address = [ 00 00 00 00 00 00 ];
  60. };
  61. };
  62. (or)
  63. mac: ethernet@4A100000 {
  64. compatible = "ti,cpsw";
  65. ti,hwmods = "cpgmac0";
  66. cpdma_channels = <8>;
  67. ale_entries = <1024>;
  68. bd_ram_size = <0x2000>;
  69. no_bd_ram = <0>;
  70. rx_descs = <64>;
  71. mac_control = <0x20>;
  72. slaves = <2>;
  73. cpts_active_slave = <0>;
  74. cpts_clock_mult = <0x80000000>;
  75. cpts_clock_shift = <29>;
  76. cpsw_emac0: slave@0 {
  77. phy_id = <&davinci_mdio>, <0>;
  78. /* Filled in by U-Boot */
  79. mac-address = [ 00 00 00 00 00 00 ];
  80. };
  81. cpsw_emac1: slave@1 {
  82. phy_id = <&davinci_mdio>, <1>;
  83. /* Filled in by U-Boot */
  84. mac-address = [ 00 00 00 00 00 00 ];
  85. };
  86. };