cpuidle.c 4.4 KB

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  1. /*
  2. * CPU idle for DaVinci SoCs
  3. *
  4. * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
  5. *
  6. * Derived from Marvell Kirkwood CPU idle code
  7. * (arch/arm/mach-kirkwood/cpuidle.c)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/cpuidle.h>
  17. #include <linux/io.h>
  18. #include <asm/proc-fns.h>
  19. #include <mach/cpuidle.h>
  20. #include <mach/memory.h>
  21. #define DAVINCI_CPUIDLE_MAX_STATES 2
  22. struct davinci_ops {
  23. void (*enter) (u32 flags);
  24. void (*exit) (u32 flags);
  25. u32 flags;
  26. };
  27. /* fields in davinci_ops.flags */
  28. #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
  29. static struct cpuidle_driver davinci_idle_driver = {
  30. .name = "cpuidle-davinci",
  31. .owner = THIS_MODULE,
  32. };
  33. static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
  34. static void __iomem *ddr2_reg_base;
  35. static void davinci_save_ddr_power(int enter, bool pdown)
  36. {
  37. u32 val;
  38. val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
  39. if (enter) {
  40. if (pdown)
  41. val |= DDR2_SRPD_BIT;
  42. else
  43. val &= ~DDR2_SRPD_BIT;
  44. val |= DDR2_LPMODEN_BIT;
  45. } else {
  46. val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
  47. }
  48. __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
  49. }
  50. static void davinci_c2state_enter(u32 flags)
  51. {
  52. davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  53. }
  54. static void davinci_c2state_exit(u32 flags)
  55. {
  56. davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  57. }
  58. static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
  59. [1] = {
  60. .enter = davinci_c2state_enter,
  61. .exit = davinci_c2state_exit,
  62. },
  63. };
  64. /* Actual code that puts the SoC in different idle states */
  65. static int davinci_enter_idle(struct cpuidle_device *dev,
  66. struct cpuidle_driver *drv,
  67. int index)
  68. {
  69. struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
  70. struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
  71. struct timeval before, after;
  72. int idle_time;
  73. local_irq_disable();
  74. do_gettimeofday(&before);
  75. if (ops && ops->enter)
  76. ops->enter(ops->flags);
  77. /* Wait for interrupt state */
  78. cpu_do_idle();
  79. if (ops && ops->exit)
  80. ops->exit(ops->flags);
  81. do_gettimeofday(&after);
  82. local_irq_enable();
  83. idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
  84. (after.tv_usec - before.tv_usec);
  85. dev->last_residency = idle_time;
  86. return index;
  87. }
  88. static int __init davinci_cpuidle_probe(struct platform_device *pdev)
  89. {
  90. int ret;
  91. struct cpuidle_device *device;
  92. struct cpuidle_driver *driver = &davinci_idle_driver;
  93. struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
  94. device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
  95. if (!pdata) {
  96. dev_err(&pdev->dev, "cannot get platform data\n");
  97. return -ENOENT;
  98. }
  99. ddr2_reg_base = pdata->ddr2_ctlr_base;
  100. /* Wait for interrupt state */
  101. driver->states[0].enter = davinci_enter_idle;
  102. driver->states[0].exit_latency = 1;
  103. driver->states[0].target_residency = 10000;
  104. driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
  105. strcpy(driver->states[0].name, "WFI");
  106. strcpy(driver->states[0].desc, "Wait for interrupt");
  107. /* Wait for interrupt and DDR self refresh state */
  108. driver->states[1].enter = davinci_enter_idle;
  109. driver->states[1].exit_latency = 10;
  110. driver->states[1].target_residency = 10000;
  111. driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
  112. strcpy(driver->states[1].name, "DDR SR");
  113. strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
  114. if (pdata->ddr2_pdown)
  115. davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
  116. cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
  117. device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
  118. driver->state_count = DAVINCI_CPUIDLE_MAX_STATES;
  119. ret = cpuidle_register_driver(&davinci_idle_driver);
  120. if (ret) {
  121. dev_err(&pdev->dev, "failed to register driver\n");
  122. return ret;
  123. }
  124. ret = cpuidle_register_device(device);
  125. if (ret) {
  126. dev_err(&pdev->dev, "failed to register device\n");
  127. cpuidle_unregister_driver(&davinci_idle_driver);
  128. return ret;
  129. }
  130. return 0;
  131. }
  132. static struct platform_driver davinci_cpuidle_driver = {
  133. .driver = {
  134. .name = "cpuidle-davinci",
  135. .owner = THIS_MODULE,
  136. },
  137. };
  138. static int __init davinci_cpuidle_init(void)
  139. {
  140. return platform_driver_probe(&davinci_cpuidle_driver,
  141. davinci_cpuidle_probe);
  142. }
  143. device_initcall(davinci_cpuidle_init);