main.c 104 KB

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  1. /*
  2. *
  3. * Broadcom B43legacy wireless driver
  4. *
  5. * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
  7. * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  8. * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11. *
  12. * Some parts of the code in this file are derived from the ipw2200
  13. * driver Copyright(c) 2003 - 2004 Intel Corporation.
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; see the file COPYING. If not, write to
  26. * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27. * Boston, MA 02110-1301, USA.
  28. *
  29. */
  30. #include <linux/delay.h>
  31. #include <linux/init.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/if_arp.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/version.h>
  36. #include <linux/firmware.h>
  37. #include <linux/wireless.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/dst.h>
  42. #include <asm/unaligned.h>
  43. #include "b43legacy.h"
  44. #include "main.h"
  45. #include "debugfs.h"
  46. #include "phy.h"
  47. #include "dma.h"
  48. #include "pio.h"
  49. #include "sysfs.h"
  50. #include "xmit.h"
  51. #include "radio.h"
  52. MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_LICENSE("GPL");
  57. MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
  58. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  59. static int modparam_pio;
  60. module_param_named(pio, modparam_pio, int, 0444);
  61. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  62. #elif defined(CONFIG_B43LEGACY_DMA)
  63. # define modparam_pio 0
  64. #elif defined(CONFIG_B43LEGACY_PIO)
  65. # define modparam_pio 1
  66. #endif
  67. static int modparam_bad_frames_preempt;
  68. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  69. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  70. " Preemption");
  71. static char modparam_fwpostfix[16];
  72. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  73. MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  74. /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  75. static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  76. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  77. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  78. SSB_DEVTABLE_END
  79. };
  80. MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  81. /* Channel and ratetables are shared for all devices.
  82. * They can't be const, because ieee80211 puts some precalculated
  83. * data in there. This data is the same for all devices, so we don't
  84. * get concurrency issues */
  85. #define RATETAB_ENT(_rateid, _flags) \
  86. { \
  87. .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
  88. .hw_value = (_rateid), \
  89. .flags = (_flags), \
  90. }
  91. /*
  92. * NOTE: When changing this, sync with xmit.c's
  93. * b43legacy_plcp_get_bitrate_idx_* functions!
  94. */
  95. static struct ieee80211_rate __b43legacy_ratetable[] = {
  96. RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
  97. RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
  98. RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
  99. RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
  100. RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
  101. RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
  102. RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
  103. RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
  104. RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
  105. RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
  106. RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
  107. RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
  108. };
  109. #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
  110. #define b43legacy_b_ratetable_size 4
  111. #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
  112. #define b43legacy_g_ratetable_size 12
  113. #define CHANTAB_ENT(_chanid, _freq) \
  114. { \
  115. .center_freq = (_freq), \
  116. .hw_value = (_chanid), \
  117. }
  118. static struct ieee80211_channel b43legacy_bg_chantable[] = {
  119. CHANTAB_ENT(1, 2412),
  120. CHANTAB_ENT(2, 2417),
  121. CHANTAB_ENT(3, 2422),
  122. CHANTAB_ENT(4, 2427),
  123. CHANTAB_ENT(5, 2432),
  124. CHANTAB_ENT(6, 2437),
  125. CHANTAB_ENT(7, 2442),
  126. CHANTAB_ENT(8, 2447),
  127. CHANTAB_ENT(9, 2452),
  128. CHANTAB_ENT(10, 2457),
  129. CHANTAB_ENT(11, 2462),
  130. CHANTAB_ENT(12, 2467),
  131. CHANTAB_ENT(13, 2472),
  132. CHANTAB_ENT(14, 2484),
  133. };
  134. static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
  135. .channels = b43legacy_bg_chantable,
  136. .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
  137. .bitrates = b43legacy_b_ratetable,
  138. .n_bitrates = b43legacy_b_ratetable_size,
  139. };
  140. static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
  141. .channels = b43legacy_bg_chantable,
  142. .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
  143. .bitrates = b43legacy_g_ratetable,
  144. .n_bitrates = b43legacy_g_ratetable_size,
  145. };
  146. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
  147. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
  148. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
  149. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
  150. static int b43legacy_ratelimit(struct b43legacy_wl *wl)
  151. {
  152. if (!wl || !wl->current_dev)
  153. return 1;
  154. if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
  155. return 1;
  156. /* We are up and running.
  157. * Ratelimit the messages to avoid DoS over the net. */
  158. return net_ratelimit();
  159. }
  160. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  161. {
  162. va_list args;
  163. if (!b43legacy_ratelimit(wl))
  164. return;
  165. va_start(args, fmt);
  166. printk(KERN_INFO "b43legacy-%s: ",
  167. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  168. vprintk(fmt, args);
  169. va_end(args);
  170. }
  171. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  172. {
  173. va_list args;
  174. if (!b43legacy_ratelimit(wl))
  175. return;
  176. va_start(args, fmt);
  177. printk(KERN_ERR "b43legacy-%s ERROR: ",
  178. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  179. vprintk(fmt, args);
  180. va_end(args);
  181. }
  182. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  183. {
  184. va_list args;
  185. if (!b43legacy_ratelimit(wl))
  186. return;
  187. va_start(args, fmt);
  188. printk(KERN_WARNING "b43legacy-%s warning: ",
  189. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  190. vprintk(fmt, args);
  191. va_end(args);
  192. }
  193. #if B43legacy_DEBUG
  194. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  195. {
  196. va_list args;
  197. va_start(args, fmt);
  198. printk(KERN_DEBUG "b43legacy-%s debug: ",
  199. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  200. vprintk(fmt, args);
  201. va_end(args);
  202. }
  203. #endif /* DEBUG */
  204. static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
  205. u32 val)
  206. {
  207. u32 status;
  208. B43legacy_WARN_ON(offset % 4 != 0);
  209. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  210. if (status & B43legacy_MACCTL_BE)
  211. val = swab32(val);
  212. b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
  213. mmiowb();
  214. b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
  215. }
  216. static inline
  217. void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
  218. u16 routing, u16 offset)
  219. {
  220. u32 control;
  221. /* "offset" is the WORD offset. */
  222. control = routing;
  223. control <<= 16;
  224. control |= offset;
  225. b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
  226. }
  227. u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
  228. u16 routing, u16 offset)
  229. {
  230. u32 ret;
  231. if (routing == B43legacy_SHM_SHARED) {
  232. B43legacy_WARN_ON((offset & 0x0001) != 0);
  233. if (offset & 0x0003) {
  234. /* Unaligned access */
  235. b43legacy_shm_control_word(dev, routing, offset >> 2);
  236. ret = b43legacy_read16(dev,
  237. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  238. ret <<= 16;
  239. b43legacy_shm_control_word(dev, routing,
  240. (offset >> 2) + 1);
  241. ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  242. return ret;
  243. }
  244. offset >>= 2;
  245. }
  246. b43legacy_shm_control_word(dev, routing, offset);
  247. ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
  248. return ret;
  249. }
  250. u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
  251. u16 routing, u16 offset)
  252. {
  253. u16 ret;
  254. if (routing == B43legacy_SHM_SHARED) {
  255. B43legacy_WARN_ON((offset & 0x0001) != 0);
  256. if (offset & 0x0003) {
  257. /* Unaligned access */
  258. b43legacy_shm_control_word(dev, routing, offset >> 2);
  259. ret = b43legacy_read16(dev,
  260. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  261. return ret;
  262. }
  263. offset >>= 2;
  264. }
  265. b43legacy_shm_control_word(dev, routing, offset);
  266. ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  267. return ret;
  268. }
  269. void b43legacy_shm_write32(struct b43legacy_wldev *dev,
  270. u16 routing, u16 offset,
  271. u32 value)
  272. {
  273. if (routing == B43legacy_SHM_SHARED) {
  274. B43legacy_WARN_ON((offset & 0x0001) != 0);
  275. if (offset & 0x0003) {
  276. /* Unaligned access */
  277. b43legacy_shm_control_word(dev, routing, offset >> 2);
  278. mmiowb();
  279. b43legacy_write16(dev,
  280. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  281. (value >> 16) & 0xffff);
  282. mmiowb();
  283. b43legacy_shm_control_word(dev, routing,
  284. (offset >> 2) + 1);
  285. mmiowb();
  286. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
  287. value & 0xffff);
  288. return;
  289. }
  290. offset >>= 2;
  291. }
  292. b43legacy_shm_control_word(dev, routing, offset);
  293. mmiowb();
  294. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
  295. }
  296. void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
  297. u16 value)
  298. {
  299. if (routing == B43legacy_SHM_SHARED) {
  300. B43legacy_WARN_ON((offset & 0x0001) != 0);
  301. if (offset & 0x0003) {
  302. /* Unaligned access */
  303. b43legacy_shm_control_word(dev, routing, offset >> 2);
  304. mmiowb();
  305. b43legacy_write16(dev,
  306. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  307. value);
  308. return;
  309. }
  310. offset >>= 2;
  311. }
  312. b43legacy_shm_control_word(dev, routing, offset);
  313. mmiowb();
  314. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
  315. }
  316. /* Read HostFlags */
  317. u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
  318. {
  319. u32 ret;
  320. ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  321. B43legacy_SHM_SH_HOSTFHI);
  322. ret <<= 16;
  323. ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  324. B43legacy_SHM_SH_HOSTFLO);
  325. return ret;
  326. }
  327. /* Write HostFlags */
  328. void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
  329. {
  330. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  331. B43legacy_SHM_SH_HOSTFLO,
  332. (value & 0x0000FFFF));
  333. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  334. B43legacy_SHM_SH_HOSTFHI,
  335. ((value & 0xFFFF0000) >> 16));
  336. }
  337. void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
  338. {
  339. /* We need to be careful. As we read the TSF from multiple
  340. * registers, we should take care of register overflows.
  341. * In theory, the whole tsf read process should be atomic.
  342. * We try to be atomic here, by restaring the read process,
  343. * if any of the high registers changed (overflew).
  344. */
  345. if (dev->dev->id.revision >= 3) {
  346. u32 low;
  347. u32 high;
  348. u32 high2;
  349. do {
  350. high = b43legacy_read32(dev,
  351. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  352. low = b43legacy_read32(dev,
  353. B43legacy_MMIO_REV3PLUS_TSF_LOW);
  354. high2 = b43legacy_read32(dev,
  355. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  356. } while (unlikely(high != high2));
  357. *tsf = high;
  358. *tsf <<= 32;
  359. *tsf |= low;
  360. } else {
  361. u64 tmp;
  362. u16 v0;
  363. u16 v1;
  364. u16 v2;
  365. u16 v3;
  366. u16 test1;
  367. u16 test2;
  368. u16 test3;
  369. do {
  370. v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  371. v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  372. v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  373. v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
  374. test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  375. test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  376. test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  377. } while (v3 != test3 || v2 != test2 || v1 != test1);
  378. *tsf = v3;
  379. *tsf <<= 48;
  380. tmp = v2;
  381. tmp <<= 32;
  382. *tsf |= tmp;
  383. tmp = v1;
  384. tmp <<= 16;
  385. *tsf |= tmp;
  386. *tsf |= v0;
  387. }
  388. }
  389. static void b43legacy_time_lock(struct b43legacy_wldev *dev)
  390. {
  391. u32 status;
  392. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  393. status |= B43legacy_MACCTL_TBTTHOLD;
  394. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
  395. mmiowb();
  396. }
  397. static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
  398. {
  399. u32 status;
  400. status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  401. status &= ~B43legacy_MACCTL_TBTTHOLD;
  402. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
  403. }
  404. static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
  405. {
  406. /* Be careful with the in-progress timer.
  407. * First zero out the low register, so we have a full
  408. * register-overflow duration to complete the operation.
  409. */
  410. if (dev->dev->id.revision >= 3) {
  411. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  412. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  413. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
  414. mmiowb();
  415. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
  416. hi);
  417. mmiowb();
  418. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
  419. lo);
  420. } else {
  421. u16 v0 = (tsf & 0x000000000000FFFFULL);
  422. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  423. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  424. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  425. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
  426. mmiowb();
  427. b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
  428. mmiowb();
  429. b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
  430. mmiowb();
  431. b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
  432. mmiowb();
  433. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
  434. }
  435. }
  436. void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
  437. {
  438. b43legacy_time_lock(dev);
  439. b43legacy_tsf_write_locked(dev, tsf);
  440. b43legacy_time_unlock(dev);
  441. }
  442. static
  443. void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
  444. u16 offset, const u8 *mac)
  445. {
  446. static const u8 zero_addr[ETH_ALEN] = { 0 };
  447. u16 data;
  448. if (!mac)
  449. mac = zero_addr;
  450. offset |= 0x0020;
  451. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
  452. data = mac[0];
  453. data |= mac[1] << 8;
  454. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  455. data = mac[2];
  456. data |= mac[3] << 8;
  457. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  458. data = mac[4];
  459. data |= mac[5] << 8;
  460. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  461. }
  462. static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
  463. {
  464. static const u8 zero_addr[ETH_ALEN] = { 0 };
  465. const u8 *mac = dev->wl->mac_addr;
  466. const u8 *bssid = dev->wl->bssid;
  467. u8 mac_bssid[ETH_ALEN * 2];
  468. int i;
  469. u32 tmp;
  470. if (!bssid)
  471. bssid = zero_addr;
  472. if (!mac)
  473. mac = zero_addr;
  474. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
  475. memcpy(mac_bssid, mac, ETH_ALEN);
  476. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  477. /* Write our MAC address and BSSID to template ram */
  478. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  479. tmp = (u32)(mac_bssid[i + 0]);
  480. tmp |= (u32)(mac_bssid[i + 1]) << 8;
  481. tmp |= (u32)(mac_bssid[i + 2]) << 16;
  482. tmp |= (u32)(mac_bssid[i + 3]) << 24;
  483. b43legacy_ram_write(dev, 0x20 + i, tmp);
  484. b43legacy_ram_write(dev, 0x78 + i, tmp);
  485. b43legacy_ram_write(dev, 0x478 + i, tmp);
  486. }
  487. }
  488. static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
  489. {
  490. b43legacy_write_mac_bssid_templates(dev);
  491. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
  492. dev->wl->mac_addr);
  493. }
  494. static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
  495. u16 slot_time)
  496. {
  497. /* slot_time is in usec. */
  498. if (dev->phy.type != B43legacy_PHYTYPE_G)
  499. return;
  500. b43legacy_write16(dev, 0x684, 510 + slot_time);
  501. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
  502. slot_time);
  503. }
  504. static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
  505. {
  506. b43legacy_set_slot_time(dev, 9);
  507. dev->short_slot = 1;
  508. }
  509. static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
  510. {
  511. b43legacy_set_slot_time(dev, 20);
  512. dev->short_slot = 0;
  513. }
  514. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  515. * Returns the _previously_ enabled IRQ mask.
  516. */
  517. static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
  518. u32 mask)
  519. {
  520. u32 old_mask;
  521. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  522. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
  523. mask);
  524. return old_mask;
  525. }
  526. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  527. * Returns the _previously_ enabled IRQ mask.
  528. */
  529. static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
  530. u32 mask)
  531. {
  532. u32 old_mask;
  533. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  534. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  535. return old_mask;
  536. }
  537. /* Synchronize IRQ top- and bottom-half.
  538. * IRQs must be masked before calling this.
  539. * This must not be called with the irq_lock held.
  540. */
  541. static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
  542. {
  543. synchronize_irq(dev->dev->irq);
  544. tasklet_kill(&dev->isr_tasklet);
  545. }
  546. /* DummyTransmission function, as documented on
  547. * http://bcm-specs.sipsolutions.net/DummyTransmission
  548. */
  549. void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
  550. {
  551. struct b43legacy_phy *phy = &dev->phy;
  552. unsigned int i;
  553. unsigned int max_loop;
  554. u16 value;
  555. u32 buffer[5] = {
  556. 0x00000000,
  557. 0x00D40000,
  558. 0x00000000,
  559. 0x01000000,
  560. 0x00000000,
  561. };
  562. switch (phy->type) {
  563. case B43legacy_PHYTYPE_B:
  564. case B43legacy_PHYTYPE_G:
  565. max_loop = 0xFA;
  566. buffer[0] = 0x000B846E;
  567. break;
  568. default:
  569. B43legacy_BUG_ON(1);
  570. return;
  571. }
  572. for (i = 0; i < 5; i++)
  573. b43legacy_ram_write(dev, i * 4, buffer[i]);
  574. /* dummy read follows */
  575. b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  576. b43legacy_write16(dev, 0x0568, 0x0000);
  577. b43legacy_write16(dev, 0x07C0, 0x0000);
  578. b43legacy_write16(dev, 0x050C, 0x0000);
  579. b43legacy_write16(dev, 0x0508, 0x0000);
  580. b43legacy_write16(dev, 0x050A, 0x0000);
  581. b43legacy_write16(dev, 0x054C, 0x0000);
  582. b43legacy_write16(dev, 0x056A, 0x0014);
  583. b43legacy_write16(dev, 0x0568, 0x0826);
  584. b43legacy_write16(dev, 0x0500, 0x0000);
  585. b43legacy_write16(dev, 0x0502, 0x0030);
  586. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  587. b43legacy_radio_write16(dev, 0x0051, 0x0017);
  588. for (i = 0x00; i < max_loop; i++) {
  589. value = b43legacy_read16(dev, 0x050E);
  590. if (value & 0x0080)
  591. break;
  592. udelay(10);
  593. }
  594. for (i = 0x00; i < 0x0A; i++) {
  595. value = b43legacy_read16(dev, 0x050E);
  596. if (value & 0x0400)
  597. break;
  598. udelay(10);
  599. }
  600. for (i = 0x00; i < 0x0A; i++) {
  601. value = b43legacy_read16(dev, 0x0690);
  602. if (!(value & 0x0100))
  603. break;
  604. udelay(10);
  605. }
  606. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  607. b43legacy_radio_write16(dev, 0x0051, 0x0037);
  608. }
  609. /* Turn the Analog ON/OFF */
  610. static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
  611. {
  612. b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
  613. }
  614. void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
  615. {
  616. u32 tmslow;
  617. u32 macctl;
  618. flags |= B43legacy_TMSLOW_PHYCLKEN;
  619. flags |= B43legacy_TMSLOW_PHYRESET;
  620. ssb_device_enable(dev->dev, flags);
  621. msleep(2); /* Wait for the PLL to turn on. */
  622. /* Now take the PHY out of Reset again */
  623. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  624. tmslow |= SSB_TMSLOW_FGC;
  625. tmslow &= ~B43legacy_TMSLOW_PHYRESET;
  626. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  627. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  628. msleep(1);
  629. tmslow &= ~SSB_TMSLOW_FGC;
  630. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  631. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  632. msleep(1);
  633. /* Turn Analog ON */
  634. b43legacy_switch_analog(dev, 1);
  635. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  636. macctl &= ~B43legacy_MACCTL_GMODE;
  637. if (flags & B43legacy_TMSLOW_GMODE) {
  638. macctl |= B43legacy_MACCTL_GMODE;
  639. dev->phy.gmode = 1;
  640. } else
  641. dev->phy.gmode = 0;
  642. macctl |= B43legacy_MACCTL_IHR_ENABLED;
  643. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  644. }
  645. static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
  646. {
  647. u32 v0;
  648. u32 v1;
  649. u16 tmp;
  650. struct b43legacy_txstatus stat;
  651. while (1) {
  652. v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  653. if (!(v0 & 0x00000001))
  654. break;
  655. v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  656. stat.cookie = (v0 >> 16);
  657. stat.seq = (v1 & 0x0000FFFF);
  658. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  659. tmp = (v0 & 0x0000FFFF);
  660. stat.frame_count = ((tmp & 0xF000) >> 12);
  661. stat.rts_count = ((tmp & 0x0F00) >> 8);
  662. stat.supp_reason = ((tmp & 0x001C) >> 2);
  663. stat.pm_indicated = !!(tmp & 0x0080);
  664. stat.intermediate = !!(tmp & 0x0040);
  665. stat.for_ampdu = !!(tmp & 0x0020);
  666. stat.acked = !!(tmp & 0x0002);
  667. b43legacy_handle_txstatus(dev, &stat);
  668. }
  669. }
  670. static void drain_txstatus_queue(struct b43legacy_wldev *dev)
  671. {
  672. u32 dummy;
  673. if (dev->dev->id.revision < 5)
  674. return;
  675. /* Read all entries from the microcode TXstatus FIFO
  676. * and throw them away.
  677. */
  678. while (1) {
  679. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  680. if (!(dummy & 0x00000001))
  681. break;
  682. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  683. }
  684. }
  685. static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
  686. {
  687. u32 val = 0;
  688. val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
  689. val <<= 16;
  690. val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
  691. return val;
  692. }
  693. static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
  694. {
  695. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
  696. (jssi & 0x0000FFFF));
  697. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
  698. (jssi & 0xFFFF0000) >> 16);
  699. }
  700. static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
  701. {
  702. b43legacy_jssi_write(dev, 0x7F7F7F7F);
  703. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  704. b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
  705. | B43legacy_MACCMD_BGNOISE);
  706. B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
  707. dev->phy.channel);
  708. }
  709. static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
  710. {
  711. /* Top half of Link Quality calculation. */
  712. if (dev->noisecalc.calculation_running)
  713. return;
  714. dev->noisecalc.channel_at_start = dev->phy.channel;
  715. dev->noisecalc.calculation_running = 1;
  716. dev->noisecalc.nr_samples = 0;
  717. b43legacy_generate_noise_sample(dev);
  718. }
  719. static void handle_irq_noise(struct b43legacy_wldev *dev)
  720. {
  721. struct b43legacy_phy *phy = &dev->phy;
  722. u16 tmp;
  723. u8 noise[4];
  724. u8 i;
  725. u8 j;
  726. s32 average;
  727. /* Bottom half of Link Quality calculation. */
  728. B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
  729. if (dev->noisecalc.channel_at_start != phy->channel)
  730. goto drop_calculation;
  731. *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
  732. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  733. noise[2] == 0x7F || noise[3] == 0x7F)
  734. goto generate_new;
  735. /* Get the noise samples. */
  736. B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
  737. i = dev->noisecalc.nr_samples;
  738. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  739. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  740. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  741. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  742. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  743. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  744. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  745. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  746. dev->noisecalc.nr_samples++;
  747. if (dev->noisecalc.nr_samples == 8) {
  748. /* Calculate the Link Quality by the noise samples. */
  749. average = 0;
  750. for (i = 0; i < 8; i++) {
  751. for (j = 0; j < 4; j++)
  752. average += dev->noisecalc.samples[i][j];
  753. }
  754. average /= (8 * 4);
  755. average *= 125;
  756. average += 64;
  757. average /= 128;
  758. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  759. 0x40C);
  760. tmp = (tmp / 128) & 0x1F;
  761. if (tmp >= 8)
  762. average += 2;
  763. else
  764. average -= 25;
  765. if (tmp == 8)
  766. average -= 72;
  767. else
  768. average -= 48;
  769. dev->stats.link_noise = average;
  770. drop_calculation:
  771. dev->noisecalc.calculation_running = 0;
  772. return;
  773. }
  774. generate_new:
  775. b43legacy_generate_noise_sample(dev);
  776. }
  777. static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
  778. {
  779. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  780. /* TODO: PS TBTT */
  781. } else {
  782. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  783. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  784. }
  785. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  786. dev->dfq_valid = 1;
  787. }
  788. static void handle_irq_atim_end(struct b43legacy_wldev *dev)
  789. {
  790. if (dev->dfq_valid) {
  791. b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
  792. b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
  793. | B43legacy_MACCMD_DFQ_VALID);
  794. dev->dfq_valid = 0;
  795. }
  796. }
  797. static void handle_irq_pmq(struct b43legacy_wldev *dev)
  798. {
  799. u32 tmp;
  800. /* TODO: AP mode. */
  801. while (1) {
  802. tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
  803. if (!(tmp & 0x00000008))
  804. break;
  805. }
  806. /* 16bit write is odd, but correct. */
  807. b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
  808. }
  809. static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
  810. const u8 *data, u16 size,
  811. u16 ram_offset,
  812. u16 shm_size_offset, u8 rate)
  813. {
  814. u32 i;
  815. u32 tmp;
  816. struct b43legacy_plcp_hdr4 plcp;
  817. plcp.data = 0;
  818. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  819. b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  820. ram_offset += sizeof(u32);
  821. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  822. * So leave the first two bytes of the next write blank.
  823. */
  824. tmp = (u32)(data[0]) << 16;
  825. tmp |= (u32)(data[1]) << 24;
  826. b43legacy_ram_write(dev, ram_offset, tmp);
  827. ram_offset += sizeof(u32);
  828. for (i = 2; i < size; i += sizeof(u32)) {
  829. tmp = (u32)(data[i + 0]);
  830. if (i + 1 < size)
  831. tmp |= (u32)(data[i + 1]) << 8;
  832. if (i + 2 < size)
  833. tmp |= (u32)(data[i + 2]) << 16;
  834. if (i + 3 < size)
  835. tmp |= (u32)(data[i + 3]) << 24;
  836. b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
  837. }
  838. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
  839. size + sizeof(struct b43legacy_plcp_hdr6));
  840. }
  841. static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
  842. u16 ram_offset,
  843. u16 shm_size_offset, u8 rate)
  844. {
  845. unsigned int i, len, variable_len;
  846. const struct ieee80211_mgmt *bcn;
  847. const u8 *ie;
  848. bool tim_found = 0;
  849. bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
  850. len = min((size_t)dev->wl->current_beacon->len,
  851. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  852. b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
  853. shm_size_offset, rate);
  854. /* Find the position of the TIM and the DTIM_period value
  855. * and write them to SHM. */
  856. ie = bcn->u.beacon.variable;
  857. variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
  858. for (i = 0; i < variable_len - 2; ) {
  859. uint8_t ie_id, ie_len;
  860. ie_id = ie[i];
  861. ie_len = ie[i + 1];
  862. if (ie_id == 5) {
  863. u16 tim_position;
  864. u16 dtim_period;
  865. /* This is the TIM Information Element */
  866. /* Check whether the ie_len is in the beacon data range. */
  867. if (variable_len < ie_len + 2 + i)
  868. break;
  869. /* A valid TIM is at least 4 bytes long. */
  870. if (ie_len < 4)
  871. break;
  872. tim_found = 1;
  873. tim_position = sizeof(struct b43legacy_plcp_hdr6);
  874. tim_position += offsetof(struct ieee80211_mgmt,
  875. u.beacon.variable);
  876. tim_position += i;
  877. dtim_period = ie[i + 3];
  878. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  879. B43legacy_SHM_SH_TIMPOS, tim_position);
  880. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  881. B43legacy_SHM_SH_DTIMP, dtim_period);
  882. break;
  883. }
  884. i += ie_len + 2;
  885. }
  886. if (!tim_found) {
  887. b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
  888. "beacon template packet. AP or IBSS operation "
  889. "may be broken.\n");
  890. }
  891. }
  892. static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
  893. u16 shm_offset, u16 size,
  894. struct ieee80211_rate *rate)
  895. {
  896. struct b43legacy_plcp_hdr4 plcp;
  897. u32 tmp;
  898. __le16 dur;
  899. plcp.data = 0;
  900. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->bitrate);
  901. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  902. dev->wl->vif,
  903. size,
  904. rate);
  905. /* Write PLCP in two parts and timing for packet transfer */
  906. tmp = le32_to_cpu(plcp.data);
  907. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
  908. tmp & 0xFFFF);
  909. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
  910. tmp >> 16);
  911. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
  912. le16_to_cpu(dur));
  913. }
  914. /* Instead of using custom probe response template, this function
  915. * just patches custom beacon template by:
  916. * 1) Changing packet type
  917. * 2) Patching duration field
  918. * 3) Stripping TIM
  919. */
  920. static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
  921. u16 *dest_size,
  922. struct ieee80211_rate *rate)
  923. {
  924. const u8 *src_data;
  925. u8 *dest_data;
  926. u16 src_size, elem_size, src_pos, dest_pos;
  927. __le16 dur;
  928. struct ieee80211_hdr *hdr;
  929. size_t ie_start;
  930. src_size = dev->wl->current_beacon->len;
  931. src_data = (const u8 *)dev->wl->current_beacon->data;
  932. /* Get the start offset of the variable IEs in the packet. */
  933. ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
  934. B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
  935. u.beacon.variable));
  936. if (B43legacy_WARN_ON(src_size < ie_start))
  937. return NULL;
  938. dest_data = kmalloc(src_size, GFP_ATOMIC);
  939. if (unlikely(!dest_data))
  940. return NULL;
  941. /* Copy the static data and all Information Elements, except the TIM. */
  942. memcpy(dest_data, src_data, ie_start);
  943. src_pos = ie_start;
  944. dest_pos = ie_start;
  945. for ( ; src_pos < src_size - 2; src_pos += elem_size) {
  946. elem_size = src_data[src_pos + 1] + 2;
  947. if (src_data[src_pos] == 5) {
  948. /* This is the TIM. */
  949. continue;
  950. }
  951. memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
  952. dest_pos += elem_size;
  953. }
  954. *dest_size = dest_pos;
  955. hdr = (struct ieee80211_hdr *)dest_data;
  956. /* Set the frame control. */
  957. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  958. IEEE80211_STYPE_PROBE_RESP);
  959. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  960. dev->wl->vif,
  961. *dest_size,
  962. rate);
  963. hdr->duration_id = dur;
  964. return dest_data;
  965. }
  966. static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
  967. u16 ram_offset,
  968. u16 shm_size_offset,
  969. struct ieee80211_rate *rate)
  970. {
  971. const u8 *probe_resp_data;
  972. u16 size;
  973. size = dev->wl->current_beacon->len;
  974. probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
  975. if (unlikely(!probe_resp_data))
  976. return;
  977. /* Looks like PLCP headers plus packet timings are stored for
  978. * all possible basic rates
  979. */
  980. b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
  981. &b43legacy_b_ratetable[0]);
  982. b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
  983. &b43legacy_b_ratetable[1]);
  984. b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
  985. &b43legacy_b_ratetable[2]);
  986. b43legacy_write_probe_resp_plcp(dev, 0x350, size,
  987. &b43legacy_b_ratetable[3]);
  988. size = min((size_t)size,
  989. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  990. b43legacy_write_template_common(dev, probe_resp_data,
  991. size, ram_offset,
  992. shm_size_offset, rate->bitrate);
  993. kfree(probe_resp_data);
  994. }
  995. /* Asynchronously update the packet templates in template RAM.
  996. * Locking: Requires wl->irq_lock to be locked. */
  997. static void b43legacy_update_templates(struct b43legacy_wl *wl,
  998. struct sk_buff *beacon)
  999. {
  1000. /* This is the top half of the ansynchronous beacon update. The bottom
  1001. * half is the beacon IRQ. Beacon update must be asynchronous to avoid
  1002. * sending an invalid beacon. This can happen for example, if the
  1003. * firmware transmits a beacon while we are updating it. */
  1004. if (wl->current_beacon)
  1005. dev_kfree_skb_any(wl->current_beacon);
  1006. wl->current_beacon = beacon;
  1007. wl->beacon0_uploaded = 0;
  1008. wl->beacon1_uploaded = 0;
  1009. }
  1010. static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
  1011. const u8 *ssid, u8 ssid_len)
  1012. {
  1013. u32 tmp;
  1014. u16 i;
  1015. u16 len;
  1016. len = min((u16)ssid_len, (u16)0x100);
  1017. for (i = 0; i < len; i += sizeof(u32)) {
  1018. tmp = (u32)(ssid[i + 0]);
  1019. if (i + 1 < len)
  1020. tmp |= (u32)(ssid[i + 1]) << 8;
  1021. if (i + 2 < len)
  1022. tmp |= (u32)(ssid[i + 2]) << 16;
  1023. if (i + 3 < len)
  1024. tmp |= (u32)(ssid[i + 3]) << 24;
  1025. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
  1026. 0x380 + i, tmp);
  1027. }
  1028. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1029. 0x48, len);
  1030. }
  1031. static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
  1032. u16 beacon_int)
  1033. {
  1034. b43legacy_time_lock(dev);
  1035. if (dev->dev->id.revision >= 3)
  1036. b43legacy_write32(dev, 0x188, (beacon_int << 16));
  1037. else {
  1038. b43legacy_write16(dev, 0x606, (beacon_int >> 6));
  1039. b43legacy_write16(dev, 0x610, beacon_int);
  1040. }
  1041. b43legacy_time_unlock(dev);
  1042. }
  1043. static void handle_irq_beacon(struct b43legacy_wldev *dev)
  1044. {
  1045. struct b43legacy_wl *wl = dev->wl;
  1046. u32 cmd;
  1047. if (!b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1048. return;
  1049. /* This is the bottom half of the asynchronous beacon update. */
  1050. cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
  1051. if (!(cmd & B43legacy_MACCMD_BEACON0_VALID)) {
  1052. if (!wl->beacon0_uploaded) {
  1053. b43legacy_write_beacon_template(dev, 0x68,
  1054. B43legacy_SHM_SH_BTL0,
  1055. B43legacy_CCK_RATE_1MB);
  1056. b43legacy_write_probe_resp_template(dev, 0x268,
  1057. B43legacy_SHM_SH_PRTLEN,
  1058. &__b43legacy_ratetable[3]);
  1059. wl->beacon0_uploaded = 1;
  1060. }
  1061. cmd |= B43legacy_MACCMD_BEACON0_VALID;
  1062. }
  1063. if (!(cmd & B43legacy_MACCMD_BEACON1_VALID)) {
  1064. if (!wl->beacon1_uploaded) {
  1065. b43legacy_write_beacon_template(dev, 0x468,
  1066. B43legacy_SHM_SH_BTL1,
  1067. B43legacy_CCK_RATE_1MB);
  1068. wl->beacon1_uploaded = 1;
  1069. }
  1070. cmd |= B43legacy_MACCMD_BEACON1_VALID;
  1071. }
  1072. b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
  1073. }
  1074. static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
  1075. {
  1076. }
  1077. /* Interrupt handler bottom-half */
  1078. static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
  1079. {
  1080. u32 reason;
  1081. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1082. u32 merged_dma_reason = 0;
  1083. int i;
  1084. unsigned long flags;
  1085. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1086. B43legacy_WARN_ON(b43legacy_status(dev) <
  1087. B43legacy_STAT_INITIALIZED);
  1088. reason = dev->irq_reason;
  1089. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1090. dma_reason[i] = dev->dma_reason[i];
  1091. merged_dma_reason |= dma_reason[i];
  1092. }
  1093. if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
  1094. b43legacyerr(dev->wl, "MAC transmission error\n");
  1095. if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
  1096. b43legacyerr(dev->wl, "PHY transmission error\n");
  1097. rmb();
  1098. if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
  1099. b43legacyerr(dev->wl, "Too many PHY TX errors, "
  1100. "restarting the controller\n");
  1101. b43legacy_controller_restart(dev, "PHY TX errors");
  1102. }
  1103. }
  1104. if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
  1105. B43legacy_DMAIRQ_NONFATALMASK))) {
  1106. if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
  1107. b43legacyerr(dev->wl, "Fatal DMA error: "
  1108. "0x%08X, 0x%08X, 0x%08X, "
  1109. "0x%08X, 0x%08X, 0x%08X\n",
  1110. dma_reason[0], dma_reason[1],
  1111. dma_reason[2], dma_reason[3],
  1112. dma_reason[4], dma_reason[5]);
  1113. b43legacy_controller_restart(dev, "DMA error");
  1114. mmiowb();
  1115. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1116. return;
  1117. }
  1118. if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
  1119. b43legacyerr(dev->wl, "DMA error: "
  1120. "0x%08X, 0x%08X, 0x%08X, "
  1121. "0x%08X, 0x%08X, 0x%08X\n",
  1122. dma_reason[0], dma_reason[1],
  1123. dma_reason[2], dma_reason[3],
  1124. dma_reason[4], dma_reason[5]);
  1125. }
  1126. if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
  1127. handle_irq_ucode_debug(dev);
  1128. if (reason & B43legacy_IRQ_TBTT_INDI)
  1129. handle_irq_tbtt_indication(dev);
  1130. if (reason & B43legacy_IRQ_ATIM_END)
  1131. handle_irq_atim_end(dev);
  1132. if (reason & B43legacy_IRQ_BEACON)
  1133. handle_irq_beacon(dev);
  1134. if (reason & B43legacy_IRQ_PMQ)
  1135. handle_irq_pmq(dev);
  1136. if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
  1137. ;/*TODO*/
  1138. if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
  1139. handle_irq_noise(dev);
  1140. /* Check the DMA reason registers for received data. */
  1141. if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
  1142. if (b43legacy_using_pio(dev))
  1143. b43legacy_pio_rx(dev->pio.queue0);
  1144. else
  1145. b43legacy_dma_rx(dev->dma.rx_ring0);
  1146. }
  1147. B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
  1148. B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
  1149. if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
  1150. if (b43legacy_using_pio(dev))
  1151. b43legacy_pio_rx(dev->pio.queue3);
  1152. else
  1153. b43legacy_dma_rx(dev->dma.rx_ring3);
  1154. }
  1155. B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
  1156. B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
  1157. if (reason & B43legacy_IRQ_TX_OK)
  1158. handle_irq_transmit_status(dev);
  1159. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1160. mmiowb();
  1161. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1162. }
  1163. static void pio_irq_workaround(struct b43legacy_wldev *dev,
  1164. u16 base, int queueidx)
  1165. {
  1166. u16 rxctl;
  1167. rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
  1168. if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
  1169. dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
  1170. else
  1171. dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
  1172. }
  1173. static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
  1174. {
  1175. if (b43legacy_using_pio(dev) &&
  1176. (dev->dev->id.revision < 3) &&
  1177. (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
  1178. /* Apply a PIO specific workaround to the dma_reasons */
  1179. pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
  1180. pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
  1181. pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
  1182. pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
  1183. }
  1184. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
  1185. b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
  1186. dev->dma_reason[0]);
  1187. b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
  1188. dev->dma_reason[1]);
  1189. b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
  1190. dev->dma_reason[2]);
  1191. b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
  1192. dev->dma_reason[3]);
  1193. b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
  1194. dev->dma_reason[4]);
  1195. b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
  1196. dev->dma_reason[5]);
  1197. }
  1198. /* Interrupt handler top-half */
  1199. static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
  1200. {
  1201. irqreturn_t ret = IRQ_NONE;
  1202. struct b43legacy_wldev *dev = dev_id;
  1203. u32 reason;
  1204. if (!dev)
  1205. return IRQ_NONE;
  1206. spin_lock(&dev->wl->irq_lock);
  1207. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  1208. goto out;
  1209. reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1210. if (reason == 0xffffffff) /* shared IRQ */
  1211. goto out;
  1212. ret = IRQ_HANDLED;
  1213. reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  1214. if (!reason)
  1215. goto out;
  1216. dev->dma_reason[0] = b43legacy_read32(dev,
  1217. B43legacy_MMIO_DMA0_REASON)
  1218. & 0x0001DC00;
  1219. dev->dma_reason[1] = b43legacy_read32(dev,
  1220. B43legacy_MMIO_DMA1_REASON)
  1221. & 0x0000DC00;
  1222. dev->dma_reason[2] = b43legacy_read32(dev,
  1223. B43legacy_MMIO_DMA2_REASON)
  1224. & 0x0000DC00;
  1225. dev->dma_reason[3] = b43legacy_read32(dev,
  1226. B43legacy_MMIO_DMA3_REASON)
  1227. & 0x0001DC00;
  1228. dev->dma_reason[4] = b43legacy_read32(dev,
  1229. B43legacy_MMIO_DMA4_REASON)
  1230. & 0x0000DC00;
  1231. dev->dma_reason[5] = b43legacy_read32(dev,
  1232. B43legacy_MMIO_DMA5_REASON)
  1233. & 0x0000DC00;
  1234. b43legacy_interrupt_ack(dev, reason);
  1235. /* disable all IRQs. They are enabled again in the bottom half. */
  1236. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  1237. B43legacy_IRQ_ALL);
  1238. /* save the reason code and call our bottom half. */
  1239. dev->irq_reason = reason;
  1240. tasklet_schedule(&dev->isr_tasklet);
  1241. out:
  1242. mmiowb();
  1243. spin_unlock(&dev->wl->irq_lock);
  1244. return ret;
  1245. }
  1246. static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
  1247. {
  1248. release_firmware(dev->fw.ucode);
  1249. dev->fw.ucode = NULL;
  1250. release_firmware(dev->fw.pcm);
  1251. dev->fw.pcm = NULL;
  1252. release_firmware(dev->fw.initvals);
  1253. dev->fw.initvals = NULL;
  1254. release_firmware(dev->fw.initvals_band);
  1255. dev->fw.initvals_band = NULL;
  1256. }
  1257. static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
  1258. {
  1259. b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
  1260. "Drivers/b43#devicefirmware "
  1261. "and download the correct firmware (version 3).\n");
  1262. }
  1263. static int do_request_fw(struct b43legacy_wldev *dev,
  1264. const char *name,
  1265. const struct firmware **fw)
  1266. {
  1267. char path[sizeof(modparam_fwpostfix) + 32];
  1268. struct b43legacy_fw_header *hdr;
  1269. u32 size;
  1270. int err;
  1271. if (!name)
  1272. return 0;
  1273. snprintf(path, ARRAY_SIZE(path),
  1274. "b43legacy%s/%s.fw",
  1275. modparam_fwpostfix, name);
  1276. err = request_firmware(fw, path, dev->dev->dev);
  1277. if (err) {
  1278. b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
  1279. "or load failed.\n", path);
  1280. return err;
  1281. }
  1282. if ((*fw)->size < sizeof(struct b43legacy_fw_header))
  1283. goto err_format;
  1284. hdr = (struct b43legacy_fw_header *)((*fw)->data);
  1285. switch (hdr->type) {
  1286. case B43legacy_FW_TYPE_UCODE:
  1287. case B43legacy_FW_TYPE_PCM:
  1288. size = be32_to_cpu(hdr->size);
  1289. if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
  1290. goto err_format;
  1291. /* fallthrough */
  1292. case B43legacy_FW_TYPE_IV:
  1293. if (hdr->ver != 1)
  1294. goto err_format;
  1295. break;
  1296. default:
  1297. goto err_format;
  1298. }
  1299. return err;
  1300. err_format:
  1301. b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1302. return -EPROTO;
  1303. }
  1304. static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
  1305. {
  1306. struct b43legacy_firmware *fw = &dev->fw;
  1307. const u8 rev = dev->dev->id.revision;
  1308. const char *filename;
  1309. u32 tmshigh;
  1310. int err;
  1311. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1312. if (!fw->ucode) {
  1313. if (rev == 2)
  1314. filename = "ucode2";
  1315. else if (rev == 4)
  1316. filename = "ucode4";
  1317. else
  1318. filename = "ucode5";
  1319. err = do_request_fw(dev, filename, &fw->ucode);
  1320. if (err)
  1321. goto err_load;
  1322. }
  1323. if (!fw->pcm) {
  1324. if (rev < 5)
  1325. filename = "pcm4";
  1326. else
  1327. filename = "pcm5";
  1328. err = do_request_fw(dev, filename, &fw->pcm);
  1329. if (err)
  1330. goto err_load;
  1331. }
  1332. if (!fw->initvals) {
  1333. switch (dev->phy.type) {
  1334. case B43legacy_PHYTYPE_G:
  1335. if ((rev >= 5) && (rev <= 10))
  1336. filename = "b0g0initvals5";
  1337. else if (rev == 2 || rev == 4)
  1338. filename = "b0g0initvals2";
  1339. else
  1340. goto err_no_initvals;
  1341. break;
  1342. default:
  1343. goto err_no_initvals;
  1344. }
  1345. err = do_request_fw(dev, filename, &fw->initvals);
  1346. if (err)
  1347. goto err_load;
  1348. }
  1349. if (!fw->initvals_band) {
  1350. switch (dev->phy.type) {
  1351. case B43legacy_PHYTYPE_G:
  1352. if ((rev >= 5) && (rev <= 10))
  1353. filename = "b0g0bsinitvals5";
  1354. else if (rev >= 11)
  1355. filename = NULL;
  1356. else if (rev == 2 || rev == 4)
  1357. filename = NULL;
  1358. else
  1359. goto err_no_initvals;
  1360. break;
  1361. default:
  1362. goto err_no_initvals;
  1363. }
  1364. err = do_request_fw(dev, filename, &fw->initvals_band);
  1365. if (err)
  1366. goto err_load;
  1367. }
  1368. return 0;
  1369. err_load:
  1370. b43legacy_print_fw_helptext(dev->wl);
  1371. goto error;
  1372. err_no_initvals:
  1373. err = -ENODEV;
  1374. b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
  1375. "core rev %u\n", dev->phy.type, rev);
  1376. goto error;
  1377. error:
  1378. b43legacy_release_firmware(dev);
  1379. return err;
  1380. }
  1381. static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
  1382. {
  1383. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1384. const __be32 *data;
  1385. unsigned int i;
  1386. unsigned int len;
  1387. u16 fwrev;
  1388. u16 fwpatch;
  1389. u16 fwdate;
  1390. u16 fwtime;
  1391. u32 tmp, macctl;
  1392. int err = 0;
  1393. /* Jump the microcode PSM to offset 0 */
  1394. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1395. B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
  1396. macctl |= B43legacy_MACCTL_PSM_JMP0;
  1397. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1398. /* Zero out all microcode PSM registers and shared memory. */
  1399. for (i = 0; i < 64; i++)
  1400. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
  1401. for (i = 0; i < 4096; i += 2)
  1402. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
  1403. /* Upload Microcode. */
  1404. data = (__be32 *) (dev->fw.ucode->data + hdr_len);
  1405. len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
  1406. b43legacy_shm_control_word(dev,
  1407. B43legacy_SHM_UCODE |
  1408. B43legacy_SHM_AUTOINC_W,
  1409. 0x0000);
  1410. for (i = 0; i < len; i++) {
  1411. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1412. be32_to_cpu(data[i]));
  1413. udelay(10);
  1414. }
  1415. if (dev->fw.pcm) {
  1416. /* Upload PCM data. */
  1417. data = (__be32 *) (dev->fw.pcm->data + hdr_len);
  1418. len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
  1419. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
  1420. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
  1421. /* No need for autoinc bit in SHM_HW */
  1422. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
  1423. for (i = 0; i < len; i++) {
  1424. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1425. be32_to_cpu(data[i]));
  1426. udelay(10);
  1427. }
  1428. }
  1429. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1430. B43legacy_IRQ_ALL);
  1431. /* Start the microcode PSM */
  1432. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1433. macctl &= ~B43legacy_MACCTL_PSM_JMP0;
  1434. macctl |= B43legacy_MACCTL_PSM_RUN;
  1435. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1436. /* Wait for the microcode to load and respond */
  1437. i = 0;
  1438. while (1) {
  1439. tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1440. if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
  1441. break;
  1442. i++;
  1443. if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
  1444. b43legacyerr(dev->wl, "Microcode not responding\n");
  1445. b43legacy_print_fw_helptext(dev->wl);
  1446. err = -ENODEV;
  1447. goto error;
  1448. }
  1449. msleep_interruptible(50);
  1450. if (signal_pending(current)) {
  1451. err = -EINTR;
  1452. goto error;
  1453. }
  1454. }
  1455. /* dummy read follows */
  1456. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1457. /* Get and check the revisions. */
  1458. fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1459. B43legacy_SHM_SH_UCODEREV);
  1460. fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1461. B43legacy_SHM_SH_UCODEPATCH);
  1462. fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1463. B43legacy_SHM_SH_UCODEDATE);
  1464. fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1465. B43legacy_SHM_SH_UCODETIME);
  1466. if (fwrev > 0x128) {
  1467. b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
  1468. " Only firmware from binary drivers version 3.x"
  1469. " is supported. You must change your firmware"
  1470. " files.\n");
  1471. b43legacy_print_fw_helptext(dev->wl);
  1472. err = -EOPNOTSUPP;
  1473. goto error;
  1474. }
  1475. b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
  1476. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
  1477. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1478. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
  1479. fwtime & 0x1F);
  1480. dev->fw.rev = fwrev;
  1481. dev->fw.patch = fwpatch;
  1482. return 0;
  1483. error:
  1484. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1485. macctl &= ~B43legacy_MACCTL_PSM_RUN;
  1486. macctl |= B43legacy_MACCTL_PSM_JMP0;
  1487. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1488. return err;
  1489. }
  1490. static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
  1491. const struct b43legacy_iv *ivals,
  1492. size_t count,
  1493. size_t array_size)
  1494. {
  1495. const struct b43legacy_iv *iv;
  1496. u16 offset;
  1497. size_t i;
  1498. bool bit32;
  1499. BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
  1500. iv = ivals;
  1501. for (i = 0; i < count; i++) {
  1502. if (array_size < sizeof(iv->offset_size))
  1503. goto err_format;
  1504. array_size -= sizeof(iv->offset_size);
  1505. offset = be16_to_cpu(iv->offset_size);
  1506. bit32 = !!(offset & B43legacy_IV_32BIT);
  1507. offset &= B43legacy_IV_OFFSET_MASK;
  1508. if (offset >= 0x1000)
  1509. goto err_format;
  1510. if (bit32) {
  1511. u32 value;
  1512. if (array_size < sizeof(iv->data.d32))
  1513. goto err_format;
  1514. array_size -= sizeof(iv->data.d32);
  1515. value = be32_to_cpu(get_unaligned(&iv->data.d32));
  1516. b43legacy_write32(dev, offset, value);
  1517. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1518. sizeof(__be16) +
  1519. sizeof(__be32));
  1520. } else {
  1521. u16 value;
  1522. if (array_size < sizeof(iv->data.d16))
  1523. goto err_format;
  1524. array_size -= sizeof(iv->data.d16);
  1525. value = be16_to_cpu(iv->data.d16);
  1526. b43legacy_write16(dev, offset, value);
  1527. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1528. sizeof(__be16) +
  1529. sizeof(__be16));
  1530. }
  1531. }
  1532. if (array_size)
  1533. goto err_format;
  1534. return 0;
  1535. err_format:
  1536. b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
  1537. b43legacy_print_fw_helptext(dev->wl);
  1538. return -EPROTO;
  1539. }
  1540. static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
  1541. {
  1542. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1543. const struct b43legacy_fw_header *hdr;
  1544. struct b43legacy_firmware *fw = &dev->fw;
  1545. const struct b43legacy_iv *ivals;
  1546. size_t count;
  1547. int err;
  1548. hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
  1549. ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
  1550. count = be32_to_cpu(hdr->size);
  1551. err = b43legacy_write_initvals(dev, ivals, count,
  1552. fw->initvals->size - hdr_len);
  1553. if (err)
  1554. goto out;
  1555. if (fw->initvals_band) {
  1556. hdr = (const struct b43legacy_fw_header *)
  1557. (fw->initvals_band->data);
  1558. ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
  1559. + hdr_len);
  1560. count = be32_to_cpu(hdr->size);
  1561. err = b43legacy_write_initvals(dev, ivals, count,
  1562. fw->initvals_band->size - hdr_len);
  1563. if (err)
  1564. goto out;
  1565. }
  1566. out:
  1567. return err;
  1568. }
  1569. /* Initialize the GPIOs
  1570. * http://bcm-specs.sipsolutions.net/GPIO
  1571. */
  1572. static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
  1573. {
  1574. struct ssb_bus *bus = dev->dev->bus;
  1575. struct ssb_device *gpiodev, *pcidev = NULL;
  1576. u32 mask;
  1577. u32 set;
  1578. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1579. b43legacy_read32(dev,
  1580. B43legacy_MMIO_MACCTL)
  1581. & 0xFFFF3FFF);
  1582. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1583. b43legacy_read16(dev,
  1584. B43legacy_MMIO_GPIO_MASK)
  1585. | 0x000F);
  1586. mask = 0x0000001F;
  1587. set = 0x0000000F;
  1588. if (dev->dev->bus->chip_id == 0x4301) {
  1589. mask |= 0x0060;
  1590. set |= 0x0060;
  1591. }
  1592. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
  1593. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1594. b43legacy_read16(dev,
  1595. B43legacy_MMIO_GPIO_MASK)
  1596. | 0x0200);
  1597. mask |= 0x0200;
  1598. set |= 0x0200;
  1599. }
  1600. if (dev->dev->id.revision >= 2)
  1601. mask |= 0x0010; /* FIXME: This is redundant. */
  1602. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1603. pcidev = bus->pcicore.dev;
  1604. #endif
  1605. gpiodev = bus->chipco.dev ? : pcidev;
  1606. if (!gpiodev)
  1607. return 0;
  1608. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
  1609. (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
  1610. & mask) | set);
  1611. return 0;
  1612. }
  1613. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1614. static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
  1615. {
  1616. struct ssb_bus *bus = dev->dev->bus;
  1617. struct ssb_device *gpiodev, *pcidev = NULL;
  1618. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1619. pcidev = bus->pcicore.dev;
  1620. #endif
  1621. gpiodev = bus->chipco.dev ? : pcidev;
  1622. if (!gpiodev)
  1623. return;
  1624. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
  1625. }
  1626. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1627. void b43legacy_mac_enable(struct b43legacy_wldev *dev)
  1628. {
  1629. dev->mac_suspended--;
  1630. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1631. B43legacy_WARN_ON(irqs_disabled());
  1632. if (dev->mac_suspended == 0) {
  1633. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1634. b43legacy_read32(dev,
  1635. B43legacy_MMIO_MACCTL)
  1636. | B43legacy_MACCTL_ENABLED);
  1637. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1638. B43legacy_IRQ_MAC_SUSPENDED);
  1639. /* the next two are dummy reads */
  1640. b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1641. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1642. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  1643. /* Re-enable IRQs. */
  1644. spin_lock_irq(&dev->wl->irq_lock);
  1645. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1646. spin_unlock_irq(&dev->wl->irq_lock);
  1647. }
  1648. }
  1649. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1650. void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
  1651. {
  1652. int i;
  1653. u32 tmp;
  1654. might_sleep();
  1655. B43legacy_WARN_ON(irqs_disabled());
  1656. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1657. if (dev->mac_suspended == 0) {
  1658. /* Mask IRQs before suspending MAC. Otherwise
  1659. * the MAC stays busy and won't suspend. */
  1660. spin_lock_irq(&dev->wl->irq_lock);
  1661. tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  1662. spin_unlock_irq(&dev->wl->irq_lock);
  1663. b43legacy_synchronize_irq(dev);
  1664. dev->irq_savedstate = tmp;
  1665. b43legacy_power_saving_ctl_bits(dev, -1, 1);
  1666. b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
  1667. b43legacy_read32(dev,
  1668. B43legacy_MMIO_MACCTL)
  1669. & ~B43legacy_MACCTL_ENABLED);
  1670. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1671. for (i = 40; i; i--) {
  1672. tmp = b43legacy_read32(dev,
  1673. B43legacy_MMIO_GEN_IRQ_REASON);
  1674. if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
  1675. goto out;
  1676. msleep(1);
  1677. }
  1678. b43legacyerr(dev->wl, "MAC suspend failed\n");
  1679. }
  1680. out:
  1681. dev->mac_suspended++;
  1682. }
  1683. static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
  1684. {
  1685. struct b43legacy_wl *wl = dev->wl;
  1686. u32 ctl;
  1687. u16 cfp_pretbtt;
  1688. ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1689. /* Reset status to STA infrastructure mode. */
  1690. ctl &= ~B43legacy_MACCTL_AP;
  1691. ctl &= ~B43legacy_MACCTL_KEEP_CTL;
  1692. ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
  1693. ctl &= ~B43legacy_MACCTL_KEEP_BAD;
  1694. ctl &= ~B43legacy_MACCTL_PROMISC;
  1695. ctl &= ~B43legacy_MACCTL_BEACPROMISC;
  1696. ctl |= B43legacy_MACCTL_INFRA;
  1697. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1698. ctl |= B43legacy_MACCTL_AP;
  1699. else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
  1700. ctl &= ~B43legacy_MACCTL_INFRA;
  1701. if (wl->filter_flags & FIF_CONTROL)
  1702. ctl |= B43legacy_MACCTL_KEEP_CTL;
  1703. if (wl->filter_flags & FIF_FCSFAIL)
  1704. ctl |= B43legacy_MACCTL_KEEP_BAD;
  1705. if (wl->filter_flags & FIF_PLCPFAIL)
  1706. ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
  1707. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  1708. ctl |= B43legacy_MACCTL_PROMISC;
  1709. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  1710. ctl |= B43legacy_MACCTL_BEACPROMISC;
  1711. /* Workaround: On old hardware the HW-MAC-address-filter
  1712. * doesn't work properly, so always run promisc in filter
  1713. * it in software. */
  1714. if (dev->dev->id.revision <= 4)
  1715. ctl |= B43legacy_MACCTL_PROMISC;
  1716. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
  1717. cfp_pretbtt = 2;
  1718. if ((ctl & B43legacy_MACCTL_INFRA) &&
  1719. !(ctl & B43legacy_MACCTL_AP)) {
  1720. if (dev->dev->bus->chip_id == 0x4306 &&
  1721. dev->dev->bus->chip_rev == 3)
  1722. cfp_pretbtt = 100;
  1723. else
  1724. cfp_pretbtt = 50;
  1725. }
  1726. b43legacy_write16(dev, 0x612, cfp_pretbtt);
  1727. }
  1728. static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
  1729. u16 rate,
  1730. int is_ofdm)
  1731. {
  1732. u16 offset;
  1733. if (is_ofdm) {
  1734. offset = 0x480;
  1735. offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  1736. } else {
  1737. offset = 0x4C0;
  1738. offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  1739. }
  1740. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
  1741. b43legacy_shm_read16(dev,
  1742. B43legacy_SHM_SHARED, offset));
  1743. }
  1744. static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
  1745. {
  1746. switch (dev->phy.type) {
  1747. case B43legacy_PHYTYPE_G:
  1748. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
  1749. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
  1750. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
  1751. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
  1752. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
  1753. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
  1754. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
  1755. /* fallthrough */
  1756. case B43legacy_PHYTYPE_B:
  1757. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
  1758. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
  1759. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
  1760. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
  1761. break;
  1762. default:
  1763. B43legacy_BUG_ON(1);
  1764. }
  1765. }
  1766. /* Set the TX-Antenna for management frames sent by firmware. */
  1767. static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
  1768. int antenna)
  1769. {
  1770. u16 ant = 0;
  1771. u16 tmp;
  1772. switch (antenna) {
  1773. case B43legacy_ANTENNA0:
  1774. ant |= B43legacy_TX4_PHY_ANT0;
  1775. break;
  1776. case B43legacy_ANTENNA1:
  1777. ant |= B43legacy_TX4_PHY_ANT1;
  1778. break;
  1779. case B43legacy_ANTENNA_AUTO:
  1780. ant |= B43legacy_TX4_PHY_ANTLAST;
  1781. break;
  1782. default:
  1783. B43legacy_BUG_ON(1);
  1784. }
  1785. /* FIXME We also need to set the other flags of the PHY control
  1786. * field somewhere. */
  1787. /* For Beacons */
  1788. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1789. B43legacy_SHM_SH_BEACPHYCTL);
  1790. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1791. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1792. B43legacy_SHM_SH_BEACPHYCTL, tmp);
  1793. /* For ACK/CTS */
  1794. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1795. B43legacy_SHM_SH_ACKCTSPHYCTL);
  1796. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1797. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1798. B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
  1799. /* For Probe Resposes */
  1800. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1801. B43legacy_SHM_SH_PRPHYCTL);
  1802. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1803. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1804. B43legacy_SHM_SH_PRPHYCTL, tmp);
  1805. }
  1806. /* This is the opposite of b43legacy_chip_init() */
  1807. static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
  1808. {
  1809. b43legacy_radio_turn_off(dev, 1);
  1810. b43legacy_gpio_cleanup(dev);
  1811. /* firmware is released later */
  1812. }
  1813. /* Initialize the chip
  1814. * http://bcm-specs.sipsolutions.net/ChipInit
  1815. */
  1816. static int b43legacy_chip_init(struct b43legacy_wldev *dev)
  1817. {
  1818. struct b43legacy_phy *phy = &dev->phy;
  1819. int err;
  1820. int tmp;
  1821. u32 value32, macctl;
  1822. u16 value16;
  1823. /* Initialize the MAC control */
  1824. macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
  1825. if (dev->phy.gmode)
  1826. macctl |= B43legacy_MACCTL_GMODE;
  1827. macctl |= B43legacy_MACCTL_INFRA;
  1828. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  1829. err = b43legacy_request_firmware(dev);
  1830. if (err)
  1831. goto out;
  1832. err = b43legacy_upload_microcode(dev);
  1833. if (err)
  1834. goto out; /* firmware is released later */
  1835. err = b43legacy_gpio_init(dev);
  1836. if (err)
  1837. goto out; /* firmware is released later */
  1838. err = b43legacy_upload_initvals(dev);
  1839. if (err)
  1840. goto err_gpio_clean;
  1841. b43legacy_radio_turn_on(dev);
  1842. b43legacy_write16(dev, 0x03E6, 0x0000);
  1843. err = b43legacy_phy_init(dev);
  1844. if (err)
  1845. goto err_radio_off;
  1846. /* Select initial Interference Mitigation. */
  1847. tmp = phy->interfmode;
  1848. phy->interfmode = B43legacy_INTERFMODE_NONE;
  1849. b43legacy_radio_set_interference_mitigation(dev, tmp);
  1850. b43legacy_phy_set_antenna_diversity(dev);
  1851. b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
  1852. if (phy->type == B43legacy_PHYTYPE_B) {
  1853. value16 = b43legacy_read16(dev, 0x005E);
  1854. value16 |= 0x0004;
  1855. b43legacy_write16(dev, 0x005E, value16);
  1856. }
  1857. b43legacy_write32(dev, 0x0100, 0x01000000);
  1858. if (dev->dev->id.revision < 5)
  1859. b43legacy_write32(dev, 0x010C, 0x01000000);
  1860. value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1861. value32 &= ~B43legacy_MACCTL_INFRA;
  1862. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
  1863. value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1864. value32 |= B43legacy_MACCTL_INFRA;
  1865. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
  1866. if (b43legacy_using_pio(dev)) {
  1867. b43legacy_write32(dev, 0x0210, 0x00000100);
  1868. b43legacy_write32(dev, 0x0230, 0x00000100);
  1869. b43legacy_write32(dev, 0x0250, 0x00000100);
  1870. b43legacy_write32(dev, 0x0270, 0x00000100);
  1871. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
  1872. 0x0000);
  1873. }
  1874. /* Probe Response Timeout value */
  1875. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  1876. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
  1877. /* Initially set the wireless operation mode. */
  1878. b43legacy_adjust_opmode(dev);
  1879. if (dev->dev->id.revision < 3) {
  1880. b43legacy_write16(dev, 0x060E, 0x0000);
  1881. b43legacy_write16(dev, 0x0610, 0x8000);
  1882. b43legacy_write16(dev, 0x0604, 0x0000);
  1883. b43legacy_write16(dev, 0x0606, 0x0200);
  1884. } else {
  1885. b43legacy_write32(dev, 0x0188, 0x80000000);
  1886. b43legacy_write32(dev, 0x018C, 0x02000000);
  1887. }
  1888. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
  1889. b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  1890. b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  1891. b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  1892. b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  1893. b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  1894. b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  1895. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  1896. value32 |= 0x00100000;
  1897. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  1898. b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
  1899. dev->dev->bus->chipco.fast_pwrup_delay);
  1900. /* PHY TX errors counter. */
  1901. atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
  1902. B43legacy_WARN_ON(err != 0);
  1903. b43legacydbg(dev->wl, "Chip initialized\n");
  1904. out:
  1905. return err;
  1906. err_radio_off:
  1907. b43legacy_radio_turn_off(dev, 1);
  1908. err_gpio_clean:
  1909. b43legacy_gpio_cleanup(dev);
  1910. goto out;
  1911. }
  1912. static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
  1913. {
  1914. struct b43legacy_phy *phy = &dev->phy;
  1915. if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
  1916. return;
  1917. b43legacy_mac_suspend(dev);
  1918. b43legacy_phy_lo_g_measure(dev);
  1919. b43legacy_mac_enable(dev);
  1920. }
  1921. static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
  1922. {
  1923. b43legacy_phy_lo_mark_all_unused(dev);
  1924. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
  1925. b43legacy_mac_suspend(dev);
  1926. b43legacy_calc_nrssi_slope(dev);
  1927. b43legacy_mac_enable(dev);
  1928. }
  1929. }
  1930. static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
  1931. {
  1932. /* Update device statistics. */
  1933. b43legacy_calculate_link_quality(dev);
  1934. }
  1935. static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
  1936. {
  1937. b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
  1938. atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
  1939. wmb();
  1940. }
  1941. static void do_periodic_work(struct b43legacy_wldev *dev)
  1942. {
  1943. unsigned int state;
  1944. state = dev->periodic_state;
  1945. if (state % 8 == 0)
  1946. b43legacy_periodic_every120sec(dev);
  1947. if (state % 4 == 0)
  1948. b43legacy_periodic_every60sec(dev);
  1949. if (state % 2 == 0)
  1950. b43legacy_periodic_every30sec(dev);
  1951. b43legacy_periodic_every15sec(dev);
  1952. }
  1953. /* Periodic work locking policy:
  1954. * The whole periodic work handler is protected by
  1955. * wl->mutex. If another lock is needed somewhere in the
  1956. * pwork callchain, it's aquired in-place, where it's needed.
  1957. */
  1958. static void b43legacy_periodic_work_handler(struct work_struct *work)
  1959. {
  1960. struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
  1961. periodic_work.work);
  1962. struct b43legacy_wl *wl = dev->wl;
  1963. unsigned long delay;
  1964. mutex_lock(&wl->mutex);
  1965. if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
  1966. goto out;
  1967. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
  1968. goto out_requeue;
  1969. do_periodic_work(dev);
  1970. dev->periodic_state++;
  1971. out_requeue:
  1972. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
  1973. delay = msecs_to_jiffies(50);
  1974. else
  1975. delay = round_jiffies_relative(HZ * 15);
  1976. queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
  1977. out:
  1978. mutex_unlock(&wl->mutex);
  1979. }
  1980. static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
  1981. {
  1982. struct delayed_work *work = &dev->periodic_work;
  1983. dev->periodic_state = 0;
  1984. INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
  1985. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  1986. }
  1987. /* Validate access to the chip (SHM) */
  1988. static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
  1989. {
  1990. u32 value;
  1991. u32 shm_backup;
  1992. shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
  1993. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
  1994. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  1995. 0xAA5555AA)
  1996. goto error;
  1997. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
  1998. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  1999. 0x55AAAA55)
  2000. goto error;
  2001. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
  2002. value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2003. if ((value | B43legacy_MACCTL_GMODE) !=
  2004. (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
  2005. goto error;
  2006. value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  2007. if (value)
  2008. goto error;
  2009. return 0;
  2010. error:
  2011. b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
  2012. return -ENODEV;
  2013. }
  2014. static void b43legacy_security_init(struct b43legacy_wldev *dev)
  2015. {
  2016. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  2017. B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  2018. dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  2019. 0x0056);
  2020. /* KTP is a word address, but we address SHM bytewise.
  2021. * So multiply by two.
  2022. */
  2023. dev->ktp *= 2;
  2024. if (dev->dev->id.revision >= 5)
  2025. /* Number of RCMTA address slots */
  2026. b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
  2027. dev->max_nr_keys - 8);
  2028. }
  2029. static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
  2030. {
  2031. struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
  2032. unsigned long flags;
  2033. /* Don't take wl->mutex here, as it could deadlock with
  2034. * hwrng internal locking. It's not needed to take
  2035. * wl->mutex here, anyway. */
  2036. spin_lock_irqsave(&wl->irq_lock, flags);
  2037. *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
  2038. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2039. return (sizeof(u16));
  2040. }
  2041. static void b43legacy_rng_exit(struct b43legacy_wl *wl)
  2042. {
  2043. if (wl->rng_initialized)
  2044. hwrng_unregister(&wl->rng);
  2045. }
  2046. static int b43legacy_rng_init(struct b43legacy_wl *wl)
  2047. {
  2048. int err;
  2049. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2050. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2051. wl->rng.name = wl->rng_name;
  2052. wl->rng.data_read = b43legacy_rng_read;
  2053. wl->rng.priv = (unsigned long)wl;
  2054. wl->rng_initialized = 1;
  2055. err = hwrng_register(&wl->rng);
  2056. if (err) {
  2057. wl->rng_initialized = 0;
  2058. b43legacyerr(wl, "Failed to register the random "
  2059. "number generator (%d)\n", err);
  2060. }
  2061. return err;
  2062. }
  2063. static int b43legacy_op_tx(struct ieee80211_hw *hw,
  2064. struct sk_buff *skb,
  2065. struct ieee80211_tx_control *ctl)
  2066. {
  2067. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2068. struct b43legacy_wldev *dev = wl->current_dev;
  2069. int err = -ENODEV;
  2070. unsigned long flags;
  2071. if (unlikely(!dev))
  2072. goto out;
  2073. if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
  2074. goto out;
  2075. /* DMA-TX is done without a global lock. */
  2076. if (b43legacy_using_pio(dev)) {
  2077. spin_lock_irqsave(&wl->irq_lock, flags);
  2078. err = b43legacy_pio_tx(dev, skb, ctl);
  2079. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2080. } else
  2081. err = b43legacy_dma_tx(dev, skb, ctl);
  2082. out:
  2083. if (unlikely(err))
  2084. return NETDEV_TX_BUSY;
  2085. return NETDEV_TX_OK;
  2086. }
  2087. static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
  2088. int queue,
  2089. const struct ieee80211_tx_queue_params *params)
  2090. {
  2091. return 0;
  2092. }
  2093. static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
  2094. struct ieee80211_tx_queue_stats *stats)
  2095. {
  2096. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2097. struct b43legacy_wldev *dev = wl->current_dev;
  2098. unsigned long flags;
  2099. int err = -ENODEV;
  2100. if (!dev)
  2101. goto out;
  2102. spin_lock_irqsave(&wl->irq_lock, flags);
  2103. if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
  2104. if (b43legacy_using_pio(dev))
  2105. b43legacy_pio_get_tx_stats(dev, stats);
  2106. else
  2107. b43legacy_dma_get_tx_stats(dev, stats);
  2108. err = 0;
  2109. }
  2110. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2111. out:
  2112. return err;
  2113. }
  2114. static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
  2115. struct ieee80211_low_level_stats *stats)
  2116. {
  2117. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2118. unsigned long flags;
  2119. spin_lock_irqsave(&wl->irq_lock, flags);
  2120. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2121. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2122. return 0;
  2123. }
  2124. static const char *phymode_to_string(unsigned int phymode)
  2125. {
  2126. switch (phymode) {
  2127. case B43legacy_PHYMODE_B:
  2128. return "B";
  2129. case B43legacy_PHYMODE_G:
  2130. return "G";
  2131. default:
  2132. B43legacy_BUG_ON(1);
  2133. }
  2134. return "";
  2135. }
  2136. static int find_wldev_for_phymode(struct b43legacy_wl *wl,
  2137. unsigned int phymode,
  2138. struct b43legacy_wldev **dev,
  2139. bool *gmode)
  2140. {
  2141. struct b43legacy_wldev *d;
  2142. list_for_each_entry(d, &wl->devlist, list) {
  2143. if (d->phy.possible_phymodes & phymode) {
  2144. /* Ok, this device supports the PHY-mode.
  2145. * Set the gmode bit. */
  2146. *gmode = 1;
  2147. *dev = d;
  2148. return 0;
  2149. }
  2150. }
  2151. return -ESRCH;
  2152. }
  2153. static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
  2154. {
  2155. struct ssb_device *sdev = dev->dev;
  2156. u32 tmslow;
  2157. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2158. tmslow &= ~B43legacy_TMSLOW_GMODE;
  2159. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2160. tmslow |= SSB_TMSLOW_FGC;
  2161. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2162. msleep(1);
  2163. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2164. tmslow &= ~SSB_TMSLOW_FGC;
  2165. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2166. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2167. msleep(1);
  2168. }
  2169. /* Expects wl->mutex locked */
  2170. static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
  2171. unsigned int new_mode)
  2172. {
  2173. struct b43legacy_wldev *up_dev;
  2174. struct b43legacy_wldev *down_dev;
  2175. int err;
  2176. bool gmode = 0;
  2177. int prev_status;
  2178. err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
  2179. if (err) {
  2180. b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
  2181. phymode_to_string(new_mode));
  2182. return err;
  2183. }
  2184. if ((up_dev == wl->current_dev) &&
  2185. (!!wl->current_dev->phy.gmode == !!gmode))
  2186. /* This device is already running. */
  2187. return 0;
  2188. b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
  2189. phymode_to_string(new_mode));
  2190. down_dev = wl->current_dev;
  2191. prev_status = b43legacy_status(down_dev);
  2192. /* Shutdown the currently running core. */
  2193. if (prev_status >= B43legacy_STAT_STARTED)
  2194. b43legacy_wireless_core_stop(down_dev);
  2195. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2196. b43legacy_wireless_core_exit(down_dev);
  2197. if (down_dev != up_dev)
  2198. /* We switch to a different core, so we put PHY into
  2199. * RESET on the old core. */
  2200. b43legacy_put_phy_into_reset(down_dev);
  2201. /* Now start the new core. */
  2202. up_dev->phy.gmode = gmode;
  2203. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2204. err = b43legacy_wireless_core_init(up_dev);
  2205. if (err) {
  2206. b43legacyerr(wl, "Fatal: Could not initialize device"
  2207. " for newly selected %s-PHY mode\n",
  2208. phymode_to_string(new_mode));
  2209. goto init_failure;
  2210. }
  2211. }
  2212. if (prev_status >= B43legacy_STAT_STARTED) {
  2213. err = b43legacy_wireless_core_start(up_dev);
  2214. if (err) {
  2215. b43legacyerr(wl, "Fatal: Coult not start device for "
  2216. "newly selected %s-PHY mode\n",
  2217. phymode_to_string(new_mode));
  2218. b43legacy_wireless_core_exit(up_dev);
  2219. goto init_failure;
  2220. }
  2221. }
  2222. B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
  2223. b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
  2224. wl->current_dev = up_dev;
  2225. return 0;
  2226. init_failure:
  2227. /* Whoops, failed to init the new core. No core is operating now. */
  2228. wl->current_dev = NULL;
  2229. return err;
  2230. }
  2231. static int b43legacy_antenna_from_ieee80211(u8 antenna)
  2232. {
  2233. switch (antenna) {
  2234. case 0: /* default/diversity */
  2235. return B43legacy_ANTENNA_DEFAULT;
  2236. case 1: /* Antenna 0 */
  2237. return B43legacy_ANTENNA0;
  2238. case 2: /* Antenna 1 */
  2239. return B43legacy_ANTENNA1;
  2240. default:
  2241. return B43legacy_ANTENNA_DEFAULT;
  2242. }
  2243. }
  2244. static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
  2245. struct ieee80211_conf *conf)
  2246. {
  2247. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2248. struct b43legacy_wldev *dev;
  2249. struct b43legacy_phy *phy;
  2250. unsigned long flags;
  2251. unsigned int new_phymode = 0xFFFF;
  2252. int antenna_tx;
  2253. int antenna_rx;
  2254. int err = 0;
  2255. u32 savedirqs;
  2256. antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
  2257. antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
  2258. mutex_lock(&wl->mutex);
  2259. dev = wl->current_dev;
  2260. phy = &dev->phy;
  2261. /* Switch the PHY mode (if necessary). */
  2262. switch (conf->channel->band) {
  2263. case IEEE80211_BAND_2GHZ:
  2264. if (phy->type == B43legacy_PHYTYPE_B)
  2265. new_phymode = B43legacy_PHYMODE_B;
  2266. else
  2267. new_phymode = B43legacy_PHYMODE_G;
  2268. break;
  2269. default:
  2270. B43legacy_WARN_ON(1);
  2271. }
  2272. err = b43legacy_switch_phymode(wl, new_phymode);
  2273. if (err)
  2274. goto out_unlock_mutex;
  2275. /* Disable IRQs while reconfiguring the device.
  2276. * This makes it possible to drop the spinlock throughout
  2277. * the reconfiguration process. */
  2278. spin_lock_irqsave(&wl->irq_lock, flags);
  2279. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2280. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2281. goto out_unlock_mutex;
  2282. }
  2283. savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  2284. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2285. b43legacy_synchronize_irq(dev);
  2286. /* Switch to the requested channel.
  2287. * The firmware takes care of races with the TX handler. */
  2288. if (conf->channel->hw_value != phy->channel)
  2289. b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
  2290. /* Enable/Disable ShortSlot timing. */
  2291. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
  2292. != dev->short_slot) {
  2293. B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
  2294. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2295. b43legacy_short_slot_timing_enable(dev);
  2296. else
  2297. b43legacy_short_slot_timing_disable(dev);
  2298. }
  2299. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  2300. /* Adjust the desired TX power level. */
  2301. if (conf->power_level != 0) {
  2302. if (conf->power_level != phy->power_level) {
  2303. phy->power_level = conf->power_level;
  2304. b43legacy_phy_xmitpower(dev);
  2305. }
  2306. }
  2307. /* Antennas for RX and management frame TX. */
  2308. b43legacy_mgmtframe_txantenna(dev, antenna_tx);
  2309. /* Update templates for AP mode. */
  2310. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2311. b43legacy_set_beacon_int(dev, conf->beacon_int);
  2312. if (!!conf->radio_enabled != phy->radio_on) {
  2313. if (conf->radio_enabled) {
  2314. b43legacy_radio_turn_on(dev);
  2315. b43legacyinfo(dev->wl, "Radio turned on by software\n");
  2316. if (!dev->radio_hw_enable)
  2317. b43legacyinfo(dev->wl, "The hardware RF-kill"
  2318. " button still turns the radio"
  2319. " physically off. Press the"
  2320. " button to turn it on.\n");
  2321. } else {
  2322. b43legacy_radio_turn_off(dev, 0);
  2323. b43legacyinfo(dev->wl, "Radio turned off by"
  2324. " software\n");
  2325. }
  2326. }
  2327. spin_lock_irqsave(&wl->irq_lock, flags);
  2328. b43legacy_interrupt_enable(dev, savedirqs);
  2329. mmiowb();
  2330. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2331. out_unlock_mutex:
  2332. mutex_unlock(&wl->mutex);
  2333. return err;
  2334. }
  2335. static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
  2336. unsigned int changed,
  2337. unsigned int *fflags,
  2338. int mc_count,
  2339. struct dev_addr_list *mc_list)
  2340. {
  2341. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2342. struct b43legacy_wldev *dev = wl->current_dev;
  2343. unsigned long flags;
  2344. if (!dev) {
  2345. *fflags = 0;
  2346. return;
  2347. }
  2348. spin_lock_irqsave(&wl->irq_lock, flags);
  2349. *fflags &= FIF_PROMISC_IN_BSS |
  2350. FIF_ALLMULTI |
  2351. FIF_FCSFAIL |
  2352. FIF_PLCPFAIL |
  2353. FIF_CONTROL |
  2354. FIF_OTHER_BSS |
  2355. FIF_BCN_PRBRESP_PROMISC;
  2356. changed &= FIF_PROMISC_IN_BSS |
  2357. FIF_ALLMULTI |
  2358. FIF_FCSFAIL |
  2359. FIF_PLCPFAIL |
  2360. FIF_CONTROL |
  2361. FIF_OTHER_BSS |
  2362. FIF_BCN_PRBRESP_PROMISC;
  2363. wl->filter_flags = *fflags;
  2364. if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
  2365. b43legacy_adjust_opmode(dev);
  2366. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2367. }
  2368. static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
  2369. struct ieee80211_vif *vif,
  2370. struct ieee80211_if_conf *conf)
  2371. {
  2372. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2373. struct b43legacy_wldev *dev = wl->current_dev;
  2374. unsigned long flags;
  2375. if (!dev)
  2376. return -ENODEV;
  2377. mutex_lock(&wl->mutex);
  2378. spin_lock_irqsave(&wl->irq_lock, flags);
  2379. B43legacy_WARN_ON(wl->vif != vif);
  2380. if (conf->bssid)
  2381. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  2382. else
  2383. memset(wl->bssid, 0, ETH_ALEN);
  2384. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
  2385. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  2386. B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
  2387. b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
  2388. if (conf->beacon)
  2389. b43legacy_update_templates(wl, conf->beacon);
  2390. }
  2391. b43legacy_write_mac_bssid_templates(dev);
  2392. }
  2393. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2394. mutex_unlock(&wl->mutex);
  2395. return 0;
  2396. }
  2397. /* Locking: wl->mutex */
  2398. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
  2399. {
  2400. struct b43legacy_wl *wl = dev->wl;
  2401. unsigned long flags;
  2402. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  2403. return;
  2404. /* Disable and sync interrupts. We must do this before than
  2405. * setting the status to INITIALIZED, as the interrupt handler
  2406. * won't care about IRQs then. */
  2407. spin_lock_irqsave(&wl->irq_lock, flags);
  2408. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  2409. B43legacy_IRQ_ALL);
  2410. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
  2411. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2412. b43legacy_synchronize_irq(dev);
  2413. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2414. mutex_unlock(&wl->mutex);
  2415. /* Must unlock as it would otherwise deadlock. No races here.
  2416. * Cancel the possibly running self-rearming periodic work. */
  2417. cancel_delayed_work_sync(&dev->periodic_work);
  2418. mutex_lock(&wl->mutex);
  2419. ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
  2420. b43legacy_mac_suspend(dev);
  2421. free_irq(dev->dev->irq, dev);
  2422. b43legacydbg(wl, "Wireless interface stopped\n");
  2423. }
  2424. /* Locking: wl->mutex */
  2425. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
  2426. {
  2427. int err;
  2428. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
  2429. drain_txstatus_queue(dev);
  2430. err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
  2431. IRQF_SHARED, KBUILD_MODNAME, dev);
  2432. if (err) {
  2433. b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
  2434. dev->dev->irq);
  2435. goto out;
  2436. }
  2437. /* We are ready to run. */
  2438. b43legacy_set_status(dev, B43legacy_STAT_STARTED);
  2439. /* Start data flow (TX/RX) */
  2440. b43legacy_mac_enable(dev);
  2441. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  2442. ieee80211_start_queues(dev->wl->hw);
  2443. /* Start maintenance work */
  2444. b43legacy_periodic_tasks_setup(dev);
  2445. b43legacydbg(dev->wl, "Wireless interface started\n");
  2446. out:
  2447. return err;
  2448. }
  2449. /* Get PHY and RADIO versioning numbers */
  2450. static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
  2451. {
  2452. struct b43legacy_phy *phy = &dev->phy;
  2453. u32 tmp;
  2454. u8 analog_type;
  2455. u8 phy_type;
  2456. u8 phy_rev;
  2457. u16 radio_manuf;
  2458. u16 radio_ver;
  2459. u16 radio_rev;
  2460. int unsupported = 0;
  2461. /* Get PHY versioning */
  2462. tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
  2463. analog_type = (tmp & B43legacy_PHYVER_ANALOG)
  2464. >> B43legacy_PHYVER_ANALOG_SHIFT;
  2465. phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
  2466. phy_rev = (tmp & B43legacy_PHYVER_VERSION);
  2467. switch (phy_type) {
  2468. case B43legacy_PHYTYPE_B:
  2469. if (phy_rev != 2 && phy_rev != 4
  2470. && phy_rev != 6 && phy_rev != 7)
  2471. unsupported = 1;
  2472. break;
  2473. case B43legacy_PHYTYPE_G:
  2474. if (phy_rev > 8)
  2475. unsupported = 1;
  2476. break;
  2477. default:
  2478. unsupported = 1;
  2479. };
  2480. if (unsupported) {
  2481. b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
  2482. "(Analog %u, Type %u, Revision %u)\n",
  2483. analog_type, phy_type, phy_rev);
  2484. return -EOPNOTSUPP;
  2485. }
  2486. b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  2487. analog_type, phy_type, phy_rev);
  2488. /* Get RADIO versioning */
  2489. if (dev->dev->bus->chip_id == 0x4317) {
  2490. if (dev->dev->bus->chip_rev == 0)
  2491. tmp = 0x3205017F;
  2492. else if (dev->dev->bus->chip_rev == 1)
  2493. tmp = 0x4205017F;
  2494. else
  2495. tmp = 0x5205017F;
  2496. } else {
  2497. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2498. B43legacy_RADIOCTL_ID);
  2499. tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
  2500. tmp <<= 16;
  2501. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2502. B43legacy_RADIOCTL_ID);
  2503. tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
  2504. }
  2505. radio_manuf = (tmp & 0x00000FFF);
  2506. radio_ver = (tmp & 0x0FFFF000) >> 12;
  2507. radio_rev = (tmp & 0xF0000000) >> 28;
  2508. switch (phy_type) {
  2509. case B43legacy_PHYTYPE_B:
  2510. if ((radio_ver & 0xFFF0) != 0x2050)
  2511. unsupported = 1;
  2512. break;
  2513. case B43legacy_PHYTYPE_G:
  2514. if (radio_ver != 0x2050)
  2515. unsupported = 1;
  2516. break;
  2517. default:
  2518. B43legacy_BUG_ON(1);
  2519. }
  2520. if (unsupported) {
  2521. b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
  2522. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  2523. radio_manuf, radio_ver, radio_rev);
  2524. return -EOPNOTSUPP;
  2525. }
  2526. b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
  2527. " Revision %u\n", radio_manuf, radio_ver, radio_rev);
  2528. phy->radio_manuf = radio_manuf;
  2529. phy->radio_ver = radio_ver;
  2530. phy->radio_rev = radio_rev;
  2531. phy->analog = analog_type;
  2532. phy->type = phy_type;
  2533. phy->rev = phy_rev;
  2534. return 0;
  2535. }
  2536. static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
  2537. struct b43legacy_phy *phy)
  2538. {
  2539. struct b43legacy_lopair *lo;
  2540. int i;
  2541. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2542. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2543. /* Assume the radio is enabled. If it's not enabled, the state will
  2544. * immediately get fixed on the first periodic work run. */
  2545. dev->radio_hw_enable = 1;
  2546. phy->savedpctlreg = 0xFFFF;
  2547. phy->aci_enable = 0;
  2548. phy->aci_wlan_automatic = 0;
  2549. phy->aci_hw_rssi = 0;
  2550. lo = phy->_lo_pairs;
  2551. if (lo)
  2552. memset(lo, 0, sizeof(struct b43legacy_lopair) *
  2553. B43legacy_LO_COUNT);
  2554. phy->max_lb_gain = 0;
  2555. phy->trsw_rx_gain = 0;
  2556. /* Set default attenuation values. */
  2557. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2558. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2559. phy->txctl1 = b43legacy_default_txctl1(dev);
  2560. phy->txpwr_offset = 0;
  2561. /* NRSSI */
  2562. phy->nrssislope = 0;
  2563. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2564. phy->nrssi[i] = -1000;
  2565. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2566. phy->nrssi_lt[i] = i;
  2567. phy->lofcal = 0xFFFF;
  2568. phy->initval = 0xFFFF;
  2569. phy->interfmode = B43legacy_INTERFMODE_NONE;
  2570. phy->channel = 0xFF;
  2571. }
  2572. static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
  2573. {
  2574. /* Flags */
  2575. dev->dfq_valid = 0;
  2576. /* Stats */
  2577. memset(&dev->stats, 0, sizeof(dev->stats));
  2578. setup_struct_phy_for_init(dev, &dev->phy);
  2579. /* IRQ related flags */
  2580. dev->irq_reason = 0;
  2581. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  2582. dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
  2583. dev->mac_suspended = 1;
  2584. /* Noise calculation context */
  2585. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  2586. }
  2587. static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
  2588. {
  2589. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2590. struct ssb_bus *bus = dev->dev->bus;
  2591. u32 tmp;
  2592. if (bus->pcicore.dev &&
  2593. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  2594. bus->pcicore.dev->id.revision <= 5) {
  2595. /* IMCFGLO timeouts workaround. */
  2596. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  2597. tmp &= ~SSB_IMCFGLO_REQTO;
  2598. tmp &= ~SSB_IMCFGLO_SERTO;
  2599. switch (bus->bustype) {
  2600. case SSB_BUSTYPE_PCI:
  2601. case SSB_BUSTYPE_PCMCIA:
  2602. tmp |= 0x32;
  2603. break;
  2604. case SSB_BUSTYPE_SSB:
  2605. tmp |= 0x53;
  2606. break;
  2607. }
  2608. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  2609. }
  2610. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  2611. }
  2612. /* Write the short and long frame retry limit values. */
  2613. static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
  2614. unsigned int short_retry,
  2615. unsigned int long_retry)
  2616. {
  2617. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  2618. * the chip-internal counter. */
  2619. short_retry = min(short_retry, (unsigned int)0xF);
  2620. long_retry = min(long_retry, (unsigned int)0xF);
  2621. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
  2622. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
  2623. }
  2624. /* Shutdown a wireless core */
  2625. /* Locking: wl->mutex */
  2626. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
  2627. {
  2628. struct b43legacy_wl *wl = dev->wl;
  2629. struct b43legacy_phy *phy = &dev->phy;
  2630. u32 macctl;
  2631. B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
  2632. if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
  2633. return;
  2634. b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
  2635. /* Stop the microcode PSM. */
  2636. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2637. macctl &= ~B43legacy_MACCTL_PSM_RUN;
  2638. macctl |= B43legacy_MACCTL_PSM_JMP0;
  2639. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  2640. mutex_unlock(&wl->mutex);
  2641. /* Must unlock as it would otherwise deadlock. No races here.
  2642. * Cancel possibly pending workqueues. */
  2643. cancel_work_sync(&dev->restart_work);
  2644. mutex_lock(&wl->mutex);
  2645. b43legacy_leds_exit(dev);
  2646. b43legacy_rng_exit(dev->wl);
  2647. b43legacy_pio_free(dev);
  2648. b43legacy_dma_free(dev);
  2649. b43legacy_chip_exit(dev);
  2650. b43legacy_radio_turn_off(dev, 1);
  2651. b43legacy_switch_analog(dev, 0);
  2652. if (phy->dyn_tssi_tbl)
  2653. kfree(phy->tssi2dbm);
  2654. kfree(phy->lo_control);
  2655. phy->lo_control = NULL;
  2656. if (dev->wl->current_beacon) {
  2657. dev_kfree_skb_any(dev->wl->current_beacon);
  2658. dev->wl->current_beacon = NULL;
  2659. }
  2660. ssb_device_disable(dev->dev, 0);
  2661. ssb_bus_may_powerdown(dev->dev->bus);
  2662. }
  2663. static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
  2664. {
  2665. struct b43legacy_phy *phy = &dev->phy;
  2666. int i;
  2667. /* Set default attenuation values. */
  2668. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2669. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2670. phy->txctl1 = b43legacy_default_txctl1(dev);
  2671. phy->txctl2 = 0xFFFF;
  2672. phy->txpwr_offset = 0;
  2673. /* NRSSI */
  2674. phy->nrssislope = 0;
  2675. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2676. phy->nrssi[i] = -1000;
  2677. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2678. phy->nrssi_lt[i] = i;
  2679. phy->lofcal = 0xFFFF;
  2680. phy->initval = 0xFFFF;
  2681. phy->aci_enable = 0;
  2682. phy->aci_wlan_automatic = 0;
  2683. phy->aci_hw_rssi = 0;
  2684. phy->antenna_diversity = 0xFFFF;
  2685. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2686. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2687. /* Flags */
  2688. phy->calibrated = 0;
  2689. if (phy->_lo_pairs)
  2690. memset(phy->_lo_pairs, 0,
  2691. sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
  2692. memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
  2693. }
  2694. /* Initialize a wireless core */
  2695. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
  2696. {
  2697. struct b43legacy_wl *wl = dev->wl;
  2698. struct ssb_bus *bus = dev->dev->bus;
  2699. struct b43legacy_phy *phy = &dev->phy;
  2700. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  2701. int err;
  2702. u32 hf;
  2703. u32 tmp;
  2704. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2705. err = ssb_bus_powerup(bus, 0);
  2706. if (err)
  2707. goto out;
  2708. if (!ssb_device_is_enabled(dev->dev)) {
  2709. tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
  2710. b43legacy_wireless_core_reset(dev, tmp);
  2711. }
  2712. if ((phy->type == B43legacy_PHYTYPE_B) ||
  2713. (phy->type == B43legacy_PHYTYPE_G)) {
  2714. phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
  2715. * B43legacy_LO_COUNT,
  2716. GFP_KERNEL);
  2717. if (!phy->_lo_pairs)
  2718. return -ENOMEM;
  2719. }
  2720. setup_struct_wldev_for_init(dev);
  2721. err = b43legacy_phy_init_tssi2dbm_table(dev);
  2722. if (err)
  2723. goto err_kfree_lo_control;
  2724. /* Enable IRQ routing to this device. */
  2725. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  2726. b43legacy_imcfglo_timeouts_workaround(dev);
  2727. prepare_phy_data_for_init(dev);
  2728. b43legacy_phy_calibrate(dev);
  2729. err = b43legacy_chip_init(dev);
  2730. if (err)
  2731. goto err_kfree_tssitbl;
  2732. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2733. B43legacy_SHM_SH_WLCOREREV,
  2734. dev->dev->id.revision);
  2735. hf = b43legacy_hf_read(dev);
  2736. if (phy->type == B43legacy_PHYTYPE_G) {
  2737. hf |= B43legacy_HF_SYMW;
  2738. if (phy->rev == 1)
  2739. hf |= B43legacy_HF_GDCW;
  2740. if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
  2741. hf |= B43legacy_HF_OFDMPABOOST;
  2742. } else if (phy->type == B43legacy_PHYTYPE_B) {
  2743. hf |= B43legacy_HF_SYMW;
  2744. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  2745. hf &= ~B43legacy_HF_GDCW;
  2746. }
  2747. b43legacy_hf_write(dev, hf);
  2748. b43legacy_set_retry_limits(dev,
  2749. B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
  2750. B43legacy_DEFAULT_LONG_RETRY_LIMIT);
  2751. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2752. 0x0044, 3);
  2753. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2754. 0x0046, 2);
  2755. /* Disable sending probe responses from firmware.
  2756. * Setting the MaxTime to one usec will always trigger
  2757. * a timeout, so we never send any probe resp.
  2758. * A timeout of zero is infinite. */
  2759. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2760. B43legacy_SHM_SH_PRMAXTIME, 1);
  2761. b43legacy_rate_memory_init(dev);
  2762. /* Minimum Contention Window */
  2763. if (phy->type == B43legacy_PHYTYPE_B)
  2764. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2765. 0x0003, 31);
  2766. else
  2767. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2768. 0x0003, 15);
  2769. /* Maximum Contention Window */
  2770. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2771. 0x0004, 1023);
  2772. do {
  2773. if (b43legacy_using_pio(dev))
  2774. err = b43legacy_pio_init(dev);
  2775. else {
  2776. err = b43legacy_dma_init(dev);
  2777. if (!err)
  2778. b43legacy_qos_init(dev);
  2779. }
  2780. } while (err == -EAGAIN);
  2781. if (err)
  2782. goto err_chip_exit;
  2783. b43legacy_write16(dev, 0x0612, 0x0050);
  2784. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
  2785. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
  2786. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  2787. b43legacy_upload_card_macaddress(dev);
  2788. b43legacy_security_init(dev);
  2789. b43legacy_rng_init(wl);
  2790. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2791. b43legacy_leds_init(dev);
  2792. out:
  2793. return err;
  2794. err_chip_exit:
  2795. b43legacy_chip_exit(dev);
  2796. err_kfree_tssitbl:
  2797. if (phy->dyn_tssi_tbl)
  2798. kfree(phy->tssi2dbm);
  2799. err_kfree_lo_control:
  2800. kfree(phy->lo_control);
  2801. phy->lo_control = NULL;
  2802. ssb_bus_may_powerdown(bus);
  2803. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2804. return err;
  2805. }
  2806. static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
  2807. struct ieee80211_if_init_conf *conf)
  2808. {
  2809. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2810. struct b43legacy_wldev *dev;
  2811. unsigned long flags;
  2812. int err = -EOPNOTSUPP;
  2813. /* TODO: allow WDS/AP devices to coexist */
  2814. if (conf->type != IEEE80211_IF_TYPE_AP &&
  2815. conf->type != IEEE80211_IF_TYPE_STA &&
  2816. conf->type != IEEE80211_IF_TYPE_WDS &&
  2817. conf->type != IEEE80211_IF_TYPE_IBSS)
  2818. return -EOPNOTSUPP;
  2819. mutex_lock(&wl->mutex);
  2820. if (wl->operating)
  2821. goto out_mutex_unlock;
  2822. b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
  2823. dev = wl->current_dev;
  2824. wl->operating = 1;
  2825. wl->vif = conf->vif;
  2826. wl->if_type = conf->type;
  2827. memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
  2828. spin_lock_irqsave(&wl->irq_lock, flags);
  2829. b43legacy_adjust_opmode(dev);
  2830. b43legacy_upload_card_macaddress(dev);
  2831. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2832. err = 0;
  2833. out_mutex_unlock:
  2834. mutex_unlock(&wl->mutex);
  2835. return err;
  2836. }
  2837. static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
  2838. struct ieee80211_if_init_conf *conf)
  2839. {
  2840. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2841. struct b43legacy_wldev *dev = wl->current_dev;
  2842. unsigned long flags;
  2843. b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
  2844. mutex_lock(&wl->mutex);
  2845. B43legacy_WARN_ON(!wl->operating);
  2846. B43legacy_WARN_ON(wl->vif != conf->vif);
  2847. wl->vif = NULL;
  2848. wl->operating = 0;
  2849. spin_lock_irqsave(&wl->irq_lock, flags);
  2850. b43legacy_adjust_opmode(dev);
  2851. memset(wl->mac_addr, 0, ETH_ALEN);
  2852. b43legacy_upload_card_macaddress(dev);
  2853. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2854. mutex_unlock(&wl->mutex);
  2855. }
  2856. static int b43legacy_op_start(struct ieee80211_hw *hw)
  2857. {
  2858. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2859. struct b43legacy_wldev *dev = wl->current_dev;
  2860. int did_init = 0;
  2861. int err = 0;
  2862. bool do_rfkill_exit = 0;
  2863. /* First register RFkill.
  2864. * LEDs that are registered later depend on it. */
  2865. b43legacy_rfkill_init(dev);
  2866. /* Kill all old instance specific information to make sure
  2867. * the card won't use it in the short timeframe between start
  2868. * and mac80211 reconfiguring it. */
  2869. memset(wl->bssid, 0, ETH_ALEN);
  2870. memset(wl->mac_addr, 0, ETH_ALEN);
  2871. wl->filter_flags = 0;
  2872. mutex_lock(&wl->mutex);
  2873. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2874. err = b43legacy_wireless_core_init(dev);
  2875. if (err) {
  2876. do_rfkill_exit = 1;
  2877. goto out_mutex_unlock;
  2878. }
  2879. did_init = 1;
  2880. }
  2881. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2882. err = b43legacy_wireless_core_start(dev);
  2883. if (err) {
  2884. if (did_init)
  2885. b43legacy_wireless_core_exit(dev);
  2886. do_rfkill_exit = 1;
  2887. goto out_mutex_unlock;
  2888. }
  2889. }
  2890. out_mutex_unlock:
  2891. mutex_unlock(&wl->mutex);
  2892. if (do_rfkill_exit)
  2893. b43legacy_rfkill_exit(dev);
  2894. return err;
  2895. }
  2896. static void b43legacy_op_stop(struct ieee80211_hw *hw)
  2897. {
  2898. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2899. struct b43legacy_wldev *dev = wl->current_dev;
  2900. b43legacy_rfkill_exit(dev);
  2901. mutex_lock(&wl->mutex);
  2902. if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
  2903. b43legacy_wireless_core_stop(dev);
  2904. b43legacy_wireless_core_exit(dev);
  2905. mutex_unlock(&wl->mutex);
  2906. }
  2907. static int b43legacy_op_set_retry_limit(struct ieee80211_hw *hw,
  2908. u32 short_retry_limit,
  2909. u32 long_retry_limit)
  2910. {
  2911. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2912. struct b43legacy_wldev *dev;
  2913. int err = 0;
  2914. mutex_lock(&wl->mutex);
  2915. dev = wl->current_dev;
  2916. if (unlikely(!dev ||
  2917. (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED))) {
  2918. err = -ENODEV;
  2919. goto out_unlock;
  2920. }
  2921. b43legacy_set_retry_limits(dev, short_retry_limit, long_retry_limit);
  2922. out_unlock:
  2923. mutex_unlock(&wl->mutex);
  2924. return err;
  2925. }
  2926. static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
  2927. int aid, int set)
  2928. {
  2929. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2930. struct sk_buff *beacon;
  2931. unsigned long flags;
  2932. /* We could modify the existing beacon and set the aid bit in the TIM
  2933. * field, but that would probably require resizing and moving of data
  2934. * within the beacon template. Simply request a new beacon and let
  2935. * mac80211 do the hard work. */
  2936. beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
  2937. if (unlikely(!beacon))
  2938. return -ENOMEM;
  2939. spin_lock_irqsave(&wl->irq_lock, flags);
  2940. b43legacy_update_templates(wl, beacon);
  2941. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2942. return 0;
  2943. }
  2944. static int b43legacy_op_ibss_beacon_update(struct ieee80211_hw *hw,
  2945. struct sk_buff *beacon,
  2946. struct ieee80211_tx_control *ctl)
  2947. {
  2948. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2949. unsigned long flags;
  2950. spin_lock_irqsave(&wl->irq_lock, flags);
  2951. b43legacy_update_templates(wl, beacon);
  2952. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2953. return 0;
  2954. }
  2955. static const struct ieee80211_ops b43legacy_hw_ops = {
  2956. .tx = b43legacy_op_tx,
  2957. .conf_tx = b43legacy_op_conf_tx,
  2958. .add_interface = b43legacy_op_add_interface,
  2959. .remove_interface = b43legacy_op_remove_interface,
  2960. .config = b43legacy_op_dev_config,
  2961. .config_interface = b43legacy_op_config_interface,
  2962. .configure_filter = b43legacy_op_configure_filter,
  2963. .get_stats = b43legacy_op_get_stats,
  2964. .get_tx_stats = b43legacy_op_get_tx_stats,
  2965. .start = b43legacy_op_start,
  2966. .stop = b43legacy_op_stop,
  2967. .set_retry_limit = b43legacy_op_set_retry_limit,
  2968. .set_tim = b43legacy_op_beacon_set_tim,
  2969. .beacon_update = b43legacy_op_ibss_beacon_update,
  2970. };
  2971. /* Hard-reset the chip. Do not call this directly.
  2972. * Use b43legacy_controller_restart()
  2973. */
  2974. static void b43legacy_chip_reset(struct work_struct *work)
  2975. {
  2976. struct b43legacy_wldev *dev =
  2977. container_of(work, struct b43legacy_wldev, restart_work);
  2978. struct b43legacy_wl *wl = dev->wl;
  2979. int err = 0;
  2980. int prev_status;
  2981. mutex_lock(&wl->mutex);
  2982. prev_status = b43legacy_status(dev);
  2983. /* Bring the device down... */
  2984. if (prev_status >= B43legacy_STAT_STARTED)
  2985. b43legacy_wireless_core_stop(dev);
  2986. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2987. b43legacy_wireless_core_exit(dev);
  2988. /* ...and up again. */
  2989. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2990. err = b43legacy_wireless_core_init(dev);
  2991. if (err)
  2992. goto out;
  2993. }
  2994. if (prev_status >= B43legacy_STAT_STARTED) {
  2995. err = b43legacy_wireless_core_start(dev);
  2996. if (err) {
  2997. b43legacy_wireless_core_exit(dev);
  2998. goto out;
  2999. }
  3000. }
  3001. out:
  3002. mutex_unlock(&wl->mutex);
  3003. if (err)
  3004. b43legacyerr(wl, "Controller restart FAILED\n");
  3005. else
  3006. b43legacyinfo(wl, "Controller restarted\n");
  3007. }
  3008. static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
  3009. int have_bphy,
  3010. int have_gphy)
  3011. {
  3012. struct ieee80211_hw *hw = dev->wl->hw;
  3013. struct b43legacy_phy *phy = &dev->phy;
  3014. phy->possible_phymodes = 0;
  3015. if (have_bphy) {
  3016. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3017. &b43legacy_band_2GHz_BPHY;
  3018. phy->possible_phymodes |= B43legacy_PHYMODE_B;
  3019. }
  3020. if (have_gphy) {
  3021. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3022. &b43legacy_band_2GHz_GPHY;
  3023. phy->possible_phymodes |= B43legacy_PHYMODE_G;
  3024. }
  3025. return 0;
  3026. }
  3027. static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
  3028. {
  3029. /* We release firmware that late to not be required to re-request
  3030. * is all the time when we reinit the core. */
  3031. b43legacy_release_firmware(dev);
  3032. }
  3033. static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
  3034. {
  3035. struct b43legacy_wl *wl = dev->wl;
  3036. struct ssb_bus *bus = dev->dev->bus;
  3037. struct pci_dev *pdev = bus->host_pci;
  3038. int err;
  3039. int have_bphy = 0;
  3040. int have_gphy = 0;
  3041. u32 tmp;
  3042. /* Do NOT do any device initialization here.
  3043. * Do it in wireless_core_init() instead.
  3044. * This function is for gathering basic information about the HW, only.
  3045. * Also some structs may be set up here. But most likely you want to
  3046. * have that in core_init(), too.
  3047. */
  3048. err = ssb_bus_powerup(bus, 0);
  3049. if (err) {
  3050. b43legacyerr(wl, "Bus powerup failed\n");
  3051. goto out;
  3052. }
  3053. /* Get the PHY type. */
  3054. if (dev->dev->id.revision >= 5) {
  3055. u32 tmshigh;
  3056. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  3057. have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
  3058. if (!have_gphy)
  3059. have_bphy = 1;
  3060. } else if (dev->dev->id.revision == 4)
  3061. have_gphy = 1;
  3062. else
  3063. have_bphy = 1;
  3064. dev->phy.gmode = (have_gphy || have_bphy);
  3065. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3066. b43legacy_wireless_core_reset(dev, tmp);
  3067. err = b43legacy_phy_versioning(dev);
  3068. if (err)
  3069. goto err_powerdown;
  3070. /* Check if this device supports multiband. */
  3071. if (!pdev ||
  3072. (pdev->device != 0x4312 &&
  3073. pdev->device != 0x4319 &&
  3074. pdev->device != 0x4324)) {
  3075. /* No multiband support. */
  3076. have_bphy = 0;
  3077. have_gphy = 0;
  3078. switch (dev->phy.type) {
  3079. case B43legacy_PHYTYPE_B:
  3080. have_bphy = 1;
  3081. break;
  3082. case B43legacy_PHYTYPE_G:
  3083. have_gphy = 1;
  3084. break;
  3085. default:
  3086. B43legacy_BUG_ON(1);
  3087. }
  3088. }
  3089. dev->phy.gmode = (have_gphy || have_bphy);
  3090. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3091. b43legacy_wireless_core_reset(dev, tmp);
  3092. err = b43legacy_validate_chipaccess(dev);
  3093. if (err)
  3094. goto err_powerdown;
  3095. err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
  3096. if (err)
  3097. goto err_powerdown;
  3098. /* Now set some default "current_dev" */
  3099. if (!wl->current_dev)
  3100. wl->current_dev = dev;
  3101. INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
  3102. b43legacy_radio_turn_off(dev, 1);
  3103. b43legacy_switch_analog(dev, 0);
  3104. ssb_device_disable(dev->dev, 0);
  3105. ssb_bus_may_powerdown(bus);
  3106. out:
  3107. return err;
  3108. err_powerdown:
  3109. ssb_bus_may_powerdown(bus);
  3110. return err;
  3111. }
  3112. static void b43legacy_one_core_detach(struct ssb_device *dev)
  3113. {
  3114. struct b43legacy_wldev *wldev;
  3115. struct b43legacy_wl *wl;
  3116. wldev = ssb_get_drvdata(dev);
  3117. wl = wldev->wl;
  3118. cancel_work_sync(&wldev->restart_work);
  3119. b43legacy_debugfs_remove_device(wldev);
  3120. b43legacy_wireless_core_detach(wldev);
  3121. list_del(&wldev->list);
  3122. wl->nr_devs--;
  3123. ssb_set_drvdata(dev, NULL);
  3124. kfree(wldev);
  3125. }
  3126. static int b43legacy_one_core_attach(struct ssb_device *dev,
  3127. struct b43legacy_wl *wl)
  3128. {
  3129. struct b43legacy_wldev *wldev;
  3130. struct pci_dev *pdev;
  3131. int err = -ENOMEM;
  3132. if (!list_empty(&wl->devlist)) {
  3133. /* We are not the first core on this chip. */
  3134. pdev = dev->bus->host_pci;
  3135. /* Only special chips support more than one wireless
  3136. * core, although some of the other chips have more than
  3137. * one wireless core as well. Check for this and
  3138. * bail out early.
  3139. */
  3140. if (!pdev ||
  3141. ((pdev->device != 0x4321) &&
  3142. (pdev->device != 0x4313) &&
  3143. (pdev->device != 0x431A))) {
  3144. b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
  3145. return -ENODEV;
  3146. }
  3147. }
  3148. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3149. if (!wldev)
  3150. goto out;
  3151. wldev->dev = dev;
  3152. wldev->wl = wl;
  3153. b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
  3154. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3155. tasklet_init(&wldev->isr_tasklet,
  3156. (void (*)(unsigned long))b43legacy_interrupt_tasklet,
  3157. (unsigned long)wldev);
  3158. if (modparam_pio)
  3159. wldev->__using_pio = 1;
  3160. INIT_LIST_HEAD(&wldev->list);
  3161. err = b43legacy_wireless_core_attach(wldev);
  3162. if (err)
  3163. goto err_kfree_wldev;
  3164. list_add(&wldev->list, &wl->devlist);
  3165. wl->nr_devs++;
  3166. ssb_set_drvdata(dev, wldev);
  3167. b43legacy_debugfs_add_device(wldev);
  3168. out:
  3169. return err;
  3170. err_kfree_wldev:
  3171. kfree(wldev);
  3172. return err;
  3173. }
  3174. static void b43legacy_sprom_fixup(struct ssb_bus *bus)
  3175. {
  3176. /* boardflags workarounds */
  3177. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3178. bus->boardinfo.type == 0x4E &&
  3179. bus->boardinfo.rev > 0x40)
  3180. bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
  3181. }
  3182. static void b43legacy_wireless_exit(struct ssb_device *dev,
  3183. struct b43legacy_wl *wl)
  3184. {
  3185. struct ieee80211_hw *hw = wl->hw;
  3186. ssb_set_devtypedata(dev, NULL);
  3187. ieee80211_free_hw(hw);
  3188. }
  3189. static int b43legacy_wireless_init(struct ssb_device *dev)
  3190. {
  3191. struct ssb_sprom *sprom = &dev->bus->sprom;
  3192. struct ieee80211_hw *hw;
  3193. struct b43legacy_wl *wl;
  3194. int err = -ENOMEM;
  3195. b43legacy_sprom_fixup(dev->bus);
  3196. hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
  3197. if (!hw) {
  3198. b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
  3199. goto out;
  3200. }
  3201. /* fill hw info */
  3202. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  3203. IEEE80211_HW_RX_INCLUDES_FCS;
  3204. hw->max_signal = 100;
  3205. hw->max_rssi = -110;
  3206. hw->max_noise = -110;
  3207. hw->queues = 1; /* FIXME: hardware has more queues */
  3208. SET_IEEE80211_DEV(hw, dev->dev);
  3209. if (is_valid_ether_addr(sprom->et1mac))
  3210. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  3211. else
  3212. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  3213. /* Get and initialize struct b43legacy_wl */
  3214. wl = hw_to_b43legacy_wl(hw);
  3215. memset(wl, 0, sizeof(*wl));
  3216. wl->hw = hw;
  3217. spin_lock_init(&wl->irq_lock);
  3218. spin_lock_init(&wl->leds_lock);
  3219. mutex_init(&wl->mutex);
  3220. INIT_LIST_HEAD(&wl->devlist);
  3221. ssb_set_devtypedata(dev, wl);
  3222. b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3223. err = 0;
  3224. out:
  3225. return err;
  3226. }
  3227. static int b43legacy_probe(struct ssb_device *dev,
  3228. const struct ssb_device_id *id)
  3229. {
  3230. struct b43legacy_wl *wl;
  3231. int err;
  3232. int first = 0;
  3233. wl = ssb_get_devtypedata(dev);
  3234. if (!wl) {
  3235. /* Probing the first core - setup common struct b43legacy_wl */
  3236. first = 1;
  3237. err = b43legacy_wireless_init(dev);
  3238. if (err)
  3239. goto out;
  3240. wl = ssb_get_devtypedata(dev);
  3241. B43legacy_WARN_ON(!wl);
  3242. }
  3243. err = b43legacy_one_core_attach(dev, wl);
  3244. if (err)
  3245. goto err_wireless_exit;
  3246. if (first) {
  3247. err = ieee80211_register_hw(wl->hw);
  3248. if (err)
  3249. goto err_one_core_detach;
  3250. }
  3251. out:
  3252. return err;
  3253. err_one_core_detach:
  3254. b43legacy_one_core_detach(dev);
  3255. err_wireless_exit:
  3256. if (first)
  3257. b43legacy_wireless_exit(dev, wl);
  3258. return err;
  3259. }
  3260. static void b43legacy_remove(struct ssb_device *dev)
  3261. {
  3262. struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
  3263. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3264. B43legacy_WARN_ON(!wl);
  3265. if (wl->current_dev == wldev)
  3266. ieee80211_unregister_hw(wl->hw);
  3267. b43legacy_one_core_detach(dev);
  3268. if (list_empty(&wl->devlist))
  3269. /* Last core on the chip unregistered.
  3270. * We can destroy common struct b43legacy_wl.
  3271. */
  3272. b43legacy_wireless_exit(dev, wl);
  3273. }
  3274. /* Perform a hardware reset. This can be called from any context. */
  3275. void b43legacy_controller_restart(struct b43legacy_wldev *dev,
  3276. const char *reason)
  3277. {
  3278. /* Must avoid requeueing, if we are in shutdown. */
  3279. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
  3280. return;
  3281. b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
  3282. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3283. }
  3284. #ifdef CONFIG_PM
  3285. static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
  3286. {
  3287. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3288. struct b43legacy_wl *wl = wldev->wl;
  3289. b43legacydbg(wl, "Suspending...\n");
  3290. mutex_lock(&wl->mutex);
  3291. wldev->suspend_init_status = b43legacy_status(wldev);
  3292. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
  3293. b43legacy_wireless_core_stop(wldev);
  3294. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
  3295. b43legacy_wireless_core_exit(wldev);
  3296. mutex_unlock(&wl->mutex);
  3297. b43legacydbg(wl, "Device suspended.\n");
  3298. return 0;
  3299. }
  3300. static int b43legacy_resume(struct ssb_device *dev)
  3301. {
  3302. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3303. struct b43legacy_wl *wl = wldev->wl;
  3304. int err = 0;
  3305. b43legacydbg(wl, "Resuming...\n");
  3306. mutex_lock(&wl->mutex);
  3307. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
  3308. err = b43legacy_wireless_core_init(wldev);
  3309. if (err) {
  3310. b43legacyerr(wl, "Resume failed at core init\n");
  3311. goto out;
  3312. }
  3313. }
  3314. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
  3315. err = b43legacy_wireless_core_start(wldev);
  3316. if (err) {
  3317. b43legacy_wireless_core_exit(wldev);
  3318. b43legacyerr(wl, "Resume failed at core start\n");
  3319. goto out;
  3320. }
  3321. }
  3322. mutex_unlock(&wl->mutex);
  3323. b43legacydbg(wl, "Device resumed.\n");
  3324. out:
  3325. return err;
  3326. }
  3327. #else /* CONFIG_PM */
  3328. # define b43legacy_suspend NULL
  3329. # define b43legacy_resume NULL
  3330. #endif /* CONFIG_PM */
  3331. static struct ssb_driver b43legacy_ssb_driver = {
  3332. .name = KBUILD_MODNAME,
  3333. .id_table = b43legacy_ssb_tbl,
  3334. .probe = b43legacy_probe,
  3335. .remove = b43legacy_remove,
  3336. .suspend = b43legacy_suspend,
  3337. .resume = b43legacy_resume,
  3338. };
  3339. static void b43legacy_print_driverinfo(void)
  3340. {
  3341. const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
  3342. *feat_pio = "", *feat_dma = "";
  3343. #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
  3344. feat_pci = "P";
  3345. #endif
  3346. #ifdef CONFIG_B43LEGACY_LEDS
  3347. feat_leds = "L";
  3348. #endif
  3349. #ifdef CONFIG_B43LEGACY_RFKILL
  3350. feat_rfkill = "R";
  3351. #endif
  3352. #ifdef CONFIG_B43LEGACY_PIO
  3353. feat_pio = "I";
  3354. #endif
  3355. #ifdef CONFIG_B43LEGACY_DMA
  3356. feat_dma = "D";
  3357. #endif
  3358. printk(KERN_INFO "Broadcom 43xx driver loaded "
  3359. "[ Features: %s%s%s%s%s, Firmware-ID: "
  3360. B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
  3361. feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
  3362. }
  3363. static int __init b43legacy_init(void)
  3364. {
  3365. int err;
  3366. b43legacy_debugfs_init();
  3367. err = ssb_driver_register(&b43legacy_ssb_driver);
  3368. if (err)
  3369. goto err_dfs_exit;
  3370. b43legacy_print_driverinfo();
  3371. return err;
  3372. err_dfs_exit:
  3373. b43legacy_debugfs_exit();
  3374. return err;
  3375. }
  3376. static void __exit b43legacy_exit(void)
  3377. {
  3378. ssb_driver_unregister(&b43legacy_ssb_driver);
  3379. b43legacy_debugfs_exit();
  3380. }
  3381. module_init(b43legacy_init)
  3382. module_exit(b43legacy_exit)