core.c 4.1 KB

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  1. /*
  2. * linux/arch/arm/mach-integrator/core.c
  3. *
  4. * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2, as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/types.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/export.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/irq.h>
  18. #include <linux/memblock.h>
  19. #include <linux/sched.h>
  20. #include <linux/smp.h>
  21. #include <linux/termios.h>
  22. #include <linux/amba/bus.h>
  23. #include <linux/amba/serial.h>
  24. #include <linux/io.h>
  25. #include <mach/hardware.h>
  26. #include <mach/platform.h>
  27. #include <mach/cm.h>
  28. #include <mach/irqs.h>
  29. #include <asm/leds.h>
  30. #include <asm/mach-types.h>
  31. #include <asm/mach/time.h>
  32. #include <asm/pgtable.h>
  33. #include "common.h"
  34. #ifdef CONFIG_ATAGS
  35. #define INTEGRATOR_RTC_IRQ { IRQ_RTCINT }
  36. #define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 }
  37. #define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 }
  38. #define KMI0_IRQ { IRQ_KMIINT0 }
  39. #define KMI1_IRQ { IRQ_KMIINT1 }
  40. static AMBA_APB_DEVICE(rtc, "rtc", 0,
  41. INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
  42. static AMBA_APB_DEVICE(uart0, "uart0", 0,
  43. INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
  44. static AMBA_APB_DEVICE(uart1, "uart1", 0,
  45. INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
  46. static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
  47. static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
  48. static struct amba_device *amba_devs[] __initdata = {
  49. &rtc_device,
  50. &uart0_device,
  51. &uart1_device,
  52. &kmi0_device,
  53. &kmi1_device,
  54. };
  55. int __init integrator_init(bool is_cp)
  56. {
  57. int i;
  58. /*
  59. * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
  60. * hard-code them. The Integator/CP and forward have proper cell IDs.
  61. * Else we leave them undefined to the bus driver can autoprobe them.
  62. */
  63. if (!is_cp) {
  64. rtc_device.periphid = 0x00041030;
  65. uart0_device.periphid = 0x00041010;
  66. uart1_device.periphid = 0x00041010;
  67. kmi0_device.periphid = 0x00041050;
  68. kmi1_device.periphid = 0x00041050;
  69. }
  70. for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
  71. struct amba_device *d = amba_devs[i];
  72. amba_device_register(d, &iomem_resource);
  73. }
  74. return 0;
  75. }
  76. #endif
  77. /*
  78. * On the Integrator platform, the port RTS and DTR are provided by
  79. * bits in the following SC_CTRLS register bits:
  80. * RTS DTR
  81. * UART0 7 6
  82. * UART1 5 4
  83. */
  84. #define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC)
  85. #define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS)
  86. static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
  87. {
  88. unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
  89. u32 phybase = dev->res.start;
  90. if (phybase == INTEGRATOR_UART0_BASE) {
  91. /* UART0 */
  92. rts_mask = 1 << 4;
  93. dtr_mask = 1 << 5;
  94. } else {
  95. /* UART1 */
  96. rts_mask = 1 << 6;
  97. dtr_mask = 1 << 7;
  98. }
  99. if (mctrl & TIOCM_RTS)
  100. ctrlc |= rts_mask;
  101. else
  102. ctrls |= rts_mask;
  103. if (mctrl & TIOCM_DTR)
  104. ctrlc |= dtr_mask;
  105. else
  106. ctrls |= dtr_mask;
  107. __raw_writel(ctrls, SC_CTRLS);
  108. __raw_writel(ctrlc, SC_CTRLC);
  109. }
  110. struct amba_pl010_data integrator_uart_data = {
  111. .set_mctrl = integrator_uart_set_mctrl,
  112. };
  113. #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
  114. static DEFINE_RAW_SPINLOCK(cm_lock);
  115. /**
  116. * cm_control - update the CM_CTRL register.
  117. * @mask: bits to change
  118. * @set: bits to set
  119. */
  120. void cm_control(u32 mask, u32 set)
  121. {
  122. unsigned long flags;
  123. u32 val;
  124. raw_spin_lock_irqsave(&cm_lock, flags);
  125. val = readl(CM_CTRL) & ~mask;
  126. writel(val | set, CM_CTRL);
  127. raw_spin_unlock_irqrestore(&cm_lock, flags);
  128. }
  129. EXPORT_SYMBOL(cm_control);
  130. /*
  131. * We need to stop things allocating the low memory; ideally we need a
  132. * better implementation of GFP_DMA which does not assume that DMA-able
  133. * memory starts at zero.
  134. */
  135. void __init integrator_reserve(void)
  136. {
  137. memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
  138. }
  139. /*
  140. * To reset, we hit the on-board reset register in the system FPGA
  141. */
  142. void integrator_restart(char mode, const char *cmd)
  143. {
  144. cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
  145. }