processor.h 24 KB

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  1. #ifndef _ASM_X86_PROCESSOR_H
  2. #define _ASM_X86_PROCESSOR_H
  3. #include <asm/processor-flags.h>
  4. /* Forward declaration, a strange C thing */
  5. struct task_struct;
  6. struct mm_struct;
  7. #include <asm/vm86.h>
  8. #include <asm/math_emu.h>
  9. #include <asm/segment.h>
  10. #include <asm/types.h>
  11. #include <asm/sigcontext.h>
  12. #include <asm/current.h>
  13. #include <asm/cpufeature.h>
  14. #include <asm/page.h>
  15. #include <asm/pgtable_types.h>
  16. #include <asm/percpu.h>
  17. #include <asm/msr.h>
  18. #include <asm/desc_defs.h>
  19. #include <asm/nops.h>
  20. #include <asm/special_insns.h>
  21. #include <linux/personality.h>
  22. #include <linux/cpumask.h>
  23. #include <linux/cache.h>
  24. #include <linux/threads.h>
  25. #include <linux/math64.h>
  26. #include <linux/init.h>
  27. #include <linux/err.h>
  28. #include <linux/irqflags.h>
  29. /*
  30. * We handle most unaligned accesses in hardware. On the other hand
  31. * unaligned DMA can be quite expensive on some Nehalem processors.
  32. *
  33. * Based on this we disable the IP header alignment in network drivers.
  34. */
  35. #define NET_IP_ALIGN 0
  36. #define HBP_NUM 4
  37. /*
  38. * Default implementation of macro that returns current
  39. * instruction pointer ("program counter").
  40. */
  41. static inline void *current_text_addr(void)
  42. {
  43. void *pc;
  44. asm volatile("mov $1f, %0; 1:":"=r" (pc));
  45. return pc;
  46. }
  47. #ifdef CONFIG_X86_VSMP
  48. # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
  49. # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
  50. #else
  51. # define ARCH_MIN_TASKALIGN 16
  52. # define ARCH_MIN_MMSTRUCT_ALIGN 0
  53. #endif
  54. enum tlb_infos {
  55. ENTRIES,
  56. NR_INFO
  57. };
  58. extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  59. extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  60. extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  61. extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  62. extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  63. extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  64. extern s8 __read_mostly tlb_flushall_shift;
  65. /*
  66. * CPU type and hardware bug flags. Kept separately for each CPU.
  67. * Members of this structure are referenced in head.S, so think twice
  68. * before touching them. [mj]
  69. */
  70. struct cpuinfo_x86 {
  71. __u8 x86; /* CPU family */
  72. __u8 x86_vendor; /* CPU vendor */
  73. __u8 x86_model;
  74. __u8 x86_mask;
  75. #ifdef CONFIG_X86_32
  76. char wp_works_ok; /* It doesn't on 386's */
  77. /* Problems on some 486Dx4's and old 386's: */
  78. char hlt_works_ok;
  79. char hard_math;
  80. char rfu;
  81. char fdiv_bug;
  82. char f00f_bug;
  83. char coma_bug;
  84. char pad0;
  85. #else
  86. /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  87. int x86_tlbsize;
  88. #endif
  89. __u8 x86_virt_bits;
  90. __u8 x86_phys_bits;
  91. /* CPUID returned core id bits: */
  92. __u8 x86_coreid_bits;
  93. /* Max extended CPUID function supported: */
  94. __u32 extended_cpuid_level;
  95. /* Maximum supported CPUID level, -1=no CPUID: */
  96. int cpuid_level;
  97. __u32 x86_capability[NCAPINTS];
  98. char x86_vendor_id[16];
  99. char x86_model_id[64];
  100. /* in KB - valid for CPUS which support this call: */
  101. int x86_cache_size;
  102. int x86_cache_alignment; /* In bytes */
  103. int x86_power;
  104. unsigned long loops_per_jiffy;
  105. /* cpuid returned max cores value: */
  106. u16 x86_max_cores;
  107. u16 apicid;
  108. u16 initial_apicid;
  109. u16 x86_clflush_size;
  110. /* number of cores as seen by the OS: */
  111. u16 booted_cores;
  112. /* Physical processor id: */
  113. u16 phys_proc_id;
  114. /* Core id: */
  115. u16 cpu_core_id;
  116. /* Compute unit id */
  117. u8 compute_unit_id;
  118. /* Index into per_cpu list: */
  119. u16 cpu_index;
  120. u32 microcode;
  121. } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  122. #define X86_VENDOR_INTEL 0
  123. #define X86_VENDOR_CYRIX 1
  124. #define X86_VENDOR_AMD 2
  125. #define X86_VENDOR_UMC 3
  126. #define X86_VENDOR_CENTAUR 5
  127. #define X86_VENDOR_TRANSMETA 7
  128. #define X86_VENDOR_NSC 8
  129. #define X86_VENDOR_NUM 9
  130. #define X86_VENDOR_UNKNOWN 0xff
  131. /*
  132. * capabilities of CPUs
  133. */
  134. extern struct cpuinfo_x86 boot_cpu_data;
  135. extern struct cpuinfo_x86 new_cpu_data;
  136. extern struct tss_struct doublefault_tss;
  137. extern __u32 cpu_caps_cleared[NCAPINTS];
  138. extern __u32 cpu_caps_set[NCAPINTS];
  139. #ifdef CONFIG_SMP
  140. DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
  141. #define cpu_data(cpu) per_cpu(cpu_info, cpu)
  142. #else
  143. #define cpu_info boot_cpu_data
  144. #define cpu_data(cpu) boot_cpu_data
  145. #endif
  146. extern const struct seq_operations cpuinfo_op;
  147. static inline int hlt_works(int cpu)
  148. {
  149. #ifdef CONFIG_X86_32
  150. return cpu_data(cpu).hlt_works_ok;
  151. #else
  152. return 1;
  153. #endif
  154. }
  155. #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
  156. extern void cpu_detect(struct cpuinfo_x86 *c);
  157. extern struct pt_regs *idle_regs(struct pt_regs *);
  158. extern void early_cpu_init(void);
  159. extern void identify_boot_cpu(void);
  160. extern void identify_secondary_cpu(struct cpuinfo_x86 *);
  161. extern void print_cpu_info(struct cpuinfo_x86 *);
  162. void print_cpu_msr(struct cpuinfo_x86 *);
  163. extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
  164. extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
  165. extern unsigned short num_cache_leaves;
  166. extern void detect_extended_topology(struct cpuinfo_x86 *c);
  167. extern void detect_ht(struct cpuinfo_x86 *c);
  168. static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
  169. unsigned int *ecx, unsigned int *edx)
  170. {
  171. /* ecx is often an input as well as an output. */
  172. asm volatile("cpuid"
  173. : "=a" (*eax),
  174. "=b" (*ebx),
  175. "=c" (*ecx),
  176. "=d" (*edx)
  177. : "0" (*eax), "2" (*ecx)
  178. : "memory");
  179. }
  180. static inline void load_cr3(pgd_t *pgdir)
  181. {
  182. write_cr3(__pa(pgdir));
  183. }
  184. #ifdef CONFIG_X86_32
  185. /* This is the TSS defined by the hardware. */
  186. struct x86_hw_tss {
  187. unsigned short back_link, __blh;
  188. unsigned long sp0;
  189. unsigned short ss0, __ss0h;
  190. unsigned long sp1;
  191. /* ss1 caches MSR_IA32_SYSENTER_CS: */
  192. unsigned short ss1, __ss1h;
  193. unsigned long sp2;
  194. unsigned short ss2, __ss2h;
  195. unsigned long __cr3;
  196. unsigned long ip;
  197. unsigned long flags;
  198. unsigned long ax;
  199. unsigned long cx;
  200. unsigned long dx;
  201. unsigned long bx;
  202. unsigned long sp;
  203. unsigned long bp;
  204. unsigned long si;
  205. unsigned long di;
  206. unsigned short es, __esh;
  207. unsigned short cs, __csh;
  208. unsigned short ss, __ssh;
  209. unsigned short ds, __dsh;
  210. unsigned short fs, __fsh;
  211. unsigned short gs, __gsh;
  212. unsigned short ldt, __ldth;
  213. unsigned short trace;
  214. unsigned short io_bitmap_base;
  215. } __attribute__((packed));
  216. #else
  217. struct x86_hw_tss {
  218. u32 reserved1;
  219. u64 sp0;
  220. u64 sp1;
  221. u64 sp2;
  222. u64 reserved2;
  223. u64 ist[7];
  224. u32 reserved3;
  225. u32 reserved4;
  226. u16 reserved5;
  227. u16 io_bitmap_base;
  228. } __attribute__((packed)) ____cacheline_aligned;
  229. #endif
  230. /*
  231. * IO-bitmap sizes:
  232. */
  233. #define IO_BITMAP_BITS 65536
  234. #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
  235. #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
  236. #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
  237. #define INVALID_IO_BITMAP_OFFSET 0x8000
  238. struct tss_struct {
  239. /*
  240. * The hardware state:
  241. */
  242. struct x86_hw_tss x86_tss;
  243. /*
  244. * The extra 1 is there because the CPU will access an
  245. * additional byte beyond the end of the IO permission
  246. * bitmap. The extra byte must be all 1 bits, and must
  247. * be within the limit.
  248. */
  249. unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
  250. /*
  251. * .. and then another 0x100 bytes for the emergency kernel stack:
  252. */
  253. unsigned long stack[64];
  254. } ____cacheline_aligned;
  255. DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
  256. /*
  257. * Save the original ist values for checking stack pointers during debugging
  258. */
  259. struct orig_ist {
  260. unsigned long ist[7];
  261. };
  262. #define MXCSR_DEFAULT 0x1f80
  263. struct i387_fsave_struct {
  264. u32 cwd; /* FPU Control Word */
  265. u32 swd; /* FPU Status Word */
  266. u32 twd; /* FPU Tag Word */
  267. u32 fip; /* FPU IP Offset */
  268. u32 fcs; /* FPU IP Selector */
  269. u32 foo; /* FPU Operand Pointer Offset */
  270. u32 fos; /* FPU Operand Pointer Selector */
  271. /* 8*10 bytes for each FP-reg = 80 bytes: */
  272. u32 st_space[20];
  273. /* Software status information [not touched by FSAVE ]: */
  274. u32 status;
  275. };
  276. struct i387_fxsave_struct {
  277. u16 cwd; /* Control Word */
  278. u16 swd; /* Status Word */
  279. u16 twd; /* Tag Word */
  280. u16 fop; /* Last Instruction Opcode */
  281. union {
  282. struct {
  283. u64 rip; /* Instruction Pointer */
  284. u64 rdp; /* Data Pointer */
  285. };
  286. struct {
  287. u32 fip; /* FPU IP Offset */
  288. u32 fcs; /* FPU IP Selector */
  289. u32 foo; /* FPU Operand Offset */
  290. u32 fos; /* FPU Operand Selector */
  291. };
  292. };
  293. u32 mxcsr; /* MXCSR Register State */
  294. u32 mxcsr_mask; /* MXCSR Mask */
  295. /* 8*16 bytes for each FP-reg = 128 bytes: */
  296. u32 st_space[32];
  297. /* 16*16 bytes for each XMM-reg = 256 bytes: */
  298. u32 xmm_space[64];
  299. u32 padding[12];
  300. union {
  301. u32 padding1[12];
  302. u32 sw_reserved[12];
  303. };
  304. } __attribute__((aligned(16)));
  305. struct i387_soft_struct {
  306. u32 cwd;
  307. u32 swd;
  308. u32 twd;
  309. u32 fip;
  310. u32 fcs;
  311. u32 foo;
  312. u32 fos;
  313. /* 8*10 bytes for each FP-reg = 80 bytes: */
  314. u32 st_space[20];
  315. u8 ftop;
  316. u8 changed;
  317. u8 lookahead;
  318. u8 no_update;
  319. u8 rm;
  320. u8 alimit;
  321. struct math_emu_info *info;
  322. u32 entry_eip;
  323. };
  324. struct ymmh_struct {
  325. /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
  326. u32 ymmh_space[64];
  327. };
  328. struct xsave_hdr_struct {
  329. u64 xstate_bv;
  330. u64 reserved1[2];
  331. u64 reserved2[5];
  332. } __attribute__((packed));
  333. struct xsave_struct {
  334. struct i387_fxsave_struct i387;
  335. struct xsave_hdr_struct xsave_hdr;
  336. struct ymmh_struct ymmh;
  337. /* new processor state extensions will go here */
  338. } __attribute__ ((packed, aligned (64)));
  339. union thread_xstate {
  340. struct i387_fsave_struct fsave;
  341. struct i387_fxsave_struct fxsave;
  342. struct i387_soft_struct soft;
  343. struct xsave_struct xsave;
  344. };
  345. struct fpu {
  346. unsigned int last_cpu;
  347. unsigned int has_fpu;
  348. union thread_xstate *state;
  349. };
  350. #ifdef CONFIG_X86_64
  351. DECLARE_PER_CPU(struct orig_ist, orig_ist);
  352. union irq_stack_union {
  353. char irq_stack[IRQ_STACK_SIZE];
  354. /*
  355. * GCC hardcodes the stack canary as %gs:40. Since the
  356. * irq_stack is the object at %gs:0, we reserve the bottom
  357. * 48 bytes of the irq stack for the canary.
  358. */
  359. struct {
  360. char gs_base[40];
  361. unsigned long stack_canary;
  362. };
  363. };
  364. DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
  365. DECLARE_INIT_PER_CPU(irq_stack_union);
  366. DECLARE_PER_CPU(char *, irq_stack_ptr);
  367. DECLARE_PER_CPU(unsigned int, irq_count);
  368. extern asmlinkage void ignore_sysret(void);
  369. #else /* X86_64 */
  370. #ifdef CONFIG_CC_STACKPROTECTOR
  371. /*
  372. * Make sure stack canary segment base is cached-aligned:
  373. * "For Intel Atom processors, avoid non zero segment base address
  374. * that is not aligned to cache line boundary at all cost."
  375. * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
  376. */
  377. struct stack_canary {
  378. char __pad[20]; /* canary at %gs:20 */
  379. unsigned long canary;
  380. };
  381. DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
  382. #endif
  383. #endif /* X86_64 */
  384. extern unsigned int xstate_size;
  385. extern void free_thread_xstate(struct task_struct *);
  386. extern struct kmem_cache *task_xstate_cachep;
  387. struct perf_event;
  388. struct thread_struct {
  389. /* Cached TLS descriptors: */
  390. struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
  391. unsigned long sp0;
  392. unsigned long sp;
  393. #ifdef CONFIG_X86_32
  394. unsigned long sysenter_cs;
  395. #else
  396. unsigned long usersp; /* Copy from PDA */
  397. unsigned short es;
  398. unsigned short ds;
  399. unsigned short fsindex;
  400. unsigned short gsindex;
  401. #endif
  402. #ifdef CONFIG_X86_32
  403. unsigned long ip;
  404. #endif
  405. #ifdef CONFIG_X86_64
  406. unsigned long fs;
  407. #endif
  408. unsigned long gs;
  409. /* Save middle states of ptrace breakpoints */
  410. struct perf_event *ptrace_bps[HBP_NUM];
  411. /* Debug status used for traps, single steps, etc... */
  412. unsigned long debugreg6;
  413. /* Keep track of the exact dr7 value set by the user */
  414. unsigned long ptrace_dr7;
  415. /* Fault info: */
  416. unsigned long cr2;
  417. unsigned long trap_nr;
  418. unsigned long error_code;
  419. /* floating point and extended processor state */
  420. struct fpu fpu;
  421. #ifdef CONFIG_X86_32
  422. /* Virtual 86 mode info */
  423. struct vm86_struct __user *vm86_info;
  424. unsigned long screen_bitmap;
  425. unsigned long v86flags;
  426. unsigned long v86mask;
  427. unsigned long saved_sp0;
  428. unsigned int saved_fs;
  429. unsigned int saved_gs;
  430. #endif
  431. /* IO permissions: */
  432. unsigned long *io_bitmap_ptr;
  433. unsigned long iopl;
  434. /* Max allowed port in the bitmap, in bytes: */
  435. unsigned io_bitmap_max;
  436. };
  437. /*
  438. * Set IOPL bits in EFLAGS from given mask
  439. */
  440. static inline void native_set_iopl_mask(unsigned mask)
  441. {
  442. #ifdef CONFIG_X86_32
  443. unsigned int reg;
  444. asm volatile ("pushfl;"
  445. "popl %0;"
  446. "andl %1, %0;"
  447. "orl %2, %0;"
  448. "pushl %0;"
  449. "popfl"
  450. : "=&r" (reg)
  451. : "i" (~X86_EFLAGS_IOPL), "r" (mask));
  452. #endif
  453. }
  454. static inline void
  455. native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
  456. {
  457. tss->x86_tss.sp0 = thread->sp0;
  458. #ifdef CONFIG_X86_32
  459. /* Only happens when SEP is enabled, no need to test "SEP"arately: */
  460. if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
  461. tss->x86_tss.ss1 = thread->sysenter_cs;
  462. wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
  463. }
  464. #endif
  465. }
  466. static inline void native_swapgs(void)
  467. {
  468. #ifdef CONFIG_X86_64
  469. asm volatile("swapgs" ::: "memory");
  470. #endif
  471. }
  472. #ifdef CONFIG_PARAVIRT
  473. #include <asm/paravirt.h>
  474. #else
  475. #define __cpuid native_cpuid
  476. #define paravirt_enabled() 0
  477. static inline void load_sp0(struct tss_struct *tss,
  478. struct thread_struct *thread)
  479. {
  480. native_load_sp0(tss, thread);
  481. }
  482. #define set_iopl_mask native_set_iopl_mask
  483. #endif /* CONFIG_PARAVIRT */
  484. /*
  485. * Save the cr4 feature set we're using (ie
  486. * Pentium 4MB enable and PPro Global page
  487. * enable), so that any CPU's that boot up
  488. * after us can get the correct flags.
  489. */
  490. extern unsigned long mmu_cr4_features;
  491. extern u32 *trampoline_cr4_features;
  492. static inline void set_in_cr4(unsigned long mask)
  493. {
  494. unsigned long cr4;
  495. mmu_cr4_features |= mask;
  496. if (trampoline_cr4_features)
  497. *trampoline_cr4_features = mmu_cr4_features;
  498. cr4 = read_cr4();
  499. cr4 |= mask;
  500. write_cr4(cr4);
  501. }
  502. static inline void clear_in_cr4(unsigned long mask)
  503. {
  504. unsigned long cr4;
  505. mmu_cr4_features &= ~mask;
  506. if (trampoline_cr4_features)
  507. *trampoline_cr4_features = mmu_cr4_features;
  508. cr4 = read_cr4();
  509. cr4 &= ~mask;
  510. write_cr4(cr4);
  511. }
  512. typedef struct {
  513. unsigned long seg;
  514. } mm_segment_t;
  515. /* Free all resources held by a thread. */
  516. extern void release_thread(struct task_struct *);
  517. unsigned long get_wchan(struct task_struct *p);
  518. /*
  519. * Generic CPUID function
  520. * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
  521. * resulting in stale register contents being returned.
  522. */
  523. static inline void cpuid(unsigned int op,
  524. unsigned int *eax, unsigned int *ebx,
  525. unsigned int *ecx, unsigned int *edx)
  526. {
  527. *eax = op;
  528. *ecx = 0;
  529. __cpuid(eax, ebx, ecx, edx);
  530. }
  531. /* Some CPUID calls want 'count' to be placed in ecx */
  532. static inline void cpuid_count(unsigned int op, int count,
  533. unsigned int *eax, unsigned int *ebx,
  534. unsigned int *ecx, unsigned int *edx)
  535. {
  536. *eax = op;
  537. *ecx = count;
  538. __cpuid(eax, ebx, ecx, edx);
  539. }
  540. /*
  541. * CPUID functions returning a single datum
  542. */
  543. static inline unsigned int cpuid_eax(unsigned int op)
  544. {
  545. unsigned int eax, ebx, ecx, edx;
  546. cpuid(op, &eax, &ebx, &ecx, &edx);
  547. return eax;
  548. }
  549. static inline unsigned int cpuid_ebx(unsigned int op)
  550. {
  551. unsigned int eax, ebx, ecx, edx;
  552. cpuid(op, &eax, &ebx, &ecx, &edx);
  553. return ebx;
  554. }
  555. static inline unsigned int cpuid_ecx(unsigned int op)
  556. {
  557. unsigned int eax, ebx, ecx, edx;
  558. cpuid(op, &eax, &ebx, &ecx, &edx);
  559. return ecx;
  560. }
  561. static inline unsigned int cpuid_edx(unsigned int op)
  562. {
  563. unsigned int eax, ebx, ecx, edx;
  564. cpuid(op, &eax, &ebx, &ecx, &edx);
  565. return edx;
  566. }
  567. /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
  568. static inline void rep_nop(void)
  569. {
  570. asm volatile("rep; nop" ::: "memory");
  571. }
  572. static inline void cpu_relax(void)
  573. {
  574. rep_nop();
  575. }
  576. /* Stop speculative execution and prefetching of modified code. */
  577. static inline void sync_core(void)
  578. {
  579. int tmp;
  580. #ifdef CONFIG_M486
  581. /*
  582. * Do a CPUID if available, otherwise do a jump. The jump
  583. * can conveniently enough be the jump around CPUID.
  584. */
  585. asm volatile("cmpl %2,%1\n\t"
  586. "jl 1f\n\t"
  587. "cpuid\n"
  588. "1:"
  589. : "=a" (tmp)
  590. : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
  591. : "ebx", "ecx", "edx", "memory");
  592. #else
  593. /*
  594. * CPUID is a barrier to speculative execution.
  595. * Prefetched instructions are automatically
  596. * invalidated when modified.
  597. */
  598. asm volatile("cpuid"
  599. : "=a" (tmp)
  600. : "0" (1)
  601. : "ebx", "ecx", "edx", "memory");
  602. #endif
  603. }
  604. static inline void __monitor(const void *eax, unsigned long ecx,
  605. unsigned long edx)
  606. {
  607. /* "monitor %eax, %ecx, %edx;" */
  608. asm volatile(".byte 0x0f, 0x01, 0xc8;"
  609. :: "a" (eax), "c" (ecx), "d"(edx));
  610. }
  611. static inline void __mwait(unsigned long eax, unsigned long ecx)
  612. {
  613. /* "mwait %eax, %ecx;" */
  614. asm volatile(".byte 0x0f, 0x01, 0xc9;"
  615. :: "a" (eax), "c" (ecx));
  616. }
  617. static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
  618. {
  619. trace_hardirqs_on();
  620. /* "mwait %eax, %ecx;" */
  621. asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
  622. :: "a" (eax), "c" (ecx));
  623. }
  624. extern void select_idle_routine(const struct cpuinfo_x86 *c);
  625. extern void init_amd_e400_c1e_mask(void);
  626. extern unsigned long boot_option_idle_override;
  627. extern bool amd_e400_c1e_detected;
  628. enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
  629. IDLE_POLL, IDLE_FORCE_MWAIT};
  630. extern void enable_sep_cpu(void);
  631. extern int sysenter_setup(void);
  632. extern void early_trap_init(void);
  633. /* Defined in head.S */
  634. extern struct desc_ptr early_gdt_descr;
  635. extern void cpu_set_gdt(int);
  636. extern void switch_to_new_gdt(int);
  637. extern void load_percpu_segment(int);
  638. extern void cpu_init(void);
  639. static inline unsigned long get_debugctlmsr(void)
  640. {
  641. unsigned long debugctlmsr = 0;
  642. #ifndef CONFIG_X86_DEBUGCTLMSR
  643. if (boot_cpu_data.x86 < 6)
  644. return 0;
  645. #endif
  646. rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
  647. return debugctlmsr;
  648. }
  649. static inline void update_debugctlmsr(unsigned long debugctlmsr)
  650. {
  651. #ifndef CONFIG_X86_DEBUGCTLMSR
  652. if (boot_cpu_data.x86 < 6)
  653. return;
  654. #endif
  655. wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
  656. }
  657. extern void set_task_blockstep(struct task_struct *task, bool on);
  658. /*
  659. * from system description table in BIOS. Mostly for MCA use, but
  660. * others may find it useful:
  661. */
  662. extern unsigned int machine_id;
  663. extern unsigned int machine_submodel_id;
  664. extern unsigned int BIOS_revision;
  665. /* Boot loader type from the setup header: */
  666. extern int bootloader_type;
  667. extern int bootloader_version;
  668. extern char ignore_fpu_irq;
  669. #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  670. #define ARCH_HAS_PREFETCHW
  671. #define ARCH_HAS_SPINLOCK_PREFETCH
  672. #ifdef CONFIG_X86_32
  673. # define BASE_PREFETCH ASM_NOP4
  674. # define ARCH_HAS_PREFETCH
  675. #else
  676. # define BASE_PREFETCH "prefetcht0 (%1)"
  677. #endif
  678. /*
  679. * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
  680. *
  681. * It's not worth to care about 3dnow prefetches for the K6
  682. * because they are microcoded there and very slow.
  683. */
  684. static inline void prefetch(const void *x)
  685. {
  686. alternative_input(BASE_PREFETCH,
  687. "prefetchnta (%1)",
  688. X86_FEATURE_XMM,
  689. "r" (x));
  690. }
  691. /*
  692. * 3dnow prefetch to get an exclusive cache line.
  693. * Useful for spinlocks to avoid one state transition in the
  694. * cache coherency protocol:
  695. */
  696. static inline void prefetchw(const void *x)
  697. {
  698. alternative_input(BASE_PREFETCH,
  699. "prefetchw (%1)",
  700. X86_FEATURE_3DNOW,
  701. "r" (x));
  702. }
  703. static inline void spin_lock_prefetch(const void *x)
  704. {
  705. prefetchw(x);
  706. }
  707. #ifdef CONFIG_X86_32
  708. /*
  709. * User space process size: 3GB (default).
  710. */
  711. #define TASK_SIZE PAGE_OFFSET
  712. #define TASK_SIZE_MAX TASK_SIZE
  713. #define STACK_TOP TASK_SIZE
  714. #define STACK_TOP_MAX STACK_TOP
  715. #define INIT_THREAD { \
  716. .sp0 = sizeof(init_stack) + (long)&init_stack, \
  717. .vm86_info = NULL, \
  718. .sysenter_cs = __KERNEL_CS, \
  719. .io_bitmap_ptr = NULL, \
  720. }
  721. /*
  722. * Note that the .io_bitmap member must be extra-big. This is because
  723. * the CPU will access an additional byte beyond the end of the IO
  724. * permission bitmap. The extra byte must be all 1 bits, and must
  725. * be within the limit.
  726. */
  727. #define INIT_TSS { \
  728. .x86_tss = { \
  729. .sp0 = sizeof(init_stack) + (long)&init_stack, \
  730. .ss0 = __KERNEL_DS, \
  731. .ss1 = __KERNEL_CS, \
  732. .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
  733. }, \
  734. .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
  735. }
  736. extern unsigned long thread_saved_pc(struct task_struct *tsk);
  737. #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
  738. #define KSTK_TOP(info) \
  739. ({ \
  740. unsigned long *__ptr = (unsigned long *)(info); \
  741. (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
  742. })
  743. /*
  744. * The below -8 is to reserve 8 bytes on top of the ring0 stack.
  745. * This is necessary to guarantee that the entire "struct pt_regs"
  746. * is accessible even if the CPU haven't stored the SS/ESP registers
  747. * on the stack (interrupt gate does not save these registers
  748. * when switching to the same priv ring).
  749. * Therefore beware: accessing the ss/esp fields of the
  750. * "struct pt_regs" is possible, but they may contain the
  751. * completely wrong values.
  752. */
  753. #define task_pt_regs(task) \
  754. ({ \
  755. struct pt_regs *__regs__; \
  756. __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
  757. __regs__ - 1; \
  758. })
  759. #define KSTK_ESP(task) (task_pt_regs(task)->sp)
  760. #else
  761. /*
  762. * User space process size. 47bits minus one guard page.
  763. */
  764. #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
  765. /* This decides where the kernel will search for a free chunk of vm
  766. * space during mmap's.
  767. */
  768. #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
  769. 0xc0000000 : 0xFFFFe000)
  770. #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
  771. IA32_PAGE_OFFSET : TASK_SIZE_MAX)
  772. #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
  773. IA32_PAGE_OFFSET : TASK_SIZE_MAX)
  774. #define STACK_TOP TASK_SIZE
  775. #define STACK_TOP_MAX TASK_SIZE_MAX
  776. #define INIT_THREAD { \
  777. .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
  778. }
  779. #define INIT_TSS { \
  780. .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
  781. }
  782. /*
  783. * Return saved PC of a blocked thread.
  784. * What is this good for? it will be always the scheduler or ret_from_fork.
  785. */
  786. #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
  787. #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
  788. extern unsigned long KSTK_ESP(struct task_struct *task);
  789. /*
  790. * User space RSP while inside the SYSCALL fast path
  791. */
  792. DECLARE_PER_CPU(unsigned long, old_rsp);
  793. #endif /* CONFIG_X86_64 */
  794. extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
  795. unsigned long new_sp);
  796. /*
  797. * This decides where the kernel will search for a free chunk of vm
  798. * space during mmap's.
  799. */
  800. #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
  801. #define KSTK_EIP(task) (task_pt_regs(task)->ip)
  802. /* Get/set a process' ability to use the timestamp counter instruction */
  803. #define GET_TSC_CTL(adr) get_tsc_mode((adr))
  804. #define SET_TSC_CTL(val) set_tsc_mode((val))
  805. extern int get_tsc_mode(unsigned long adr);
  806. extern int set_tsc_mode(unsigned int val);
  807. extern int amd_get_nb_id(int cpu);
  808. struct aperfmperf {
  809. u64 aperf, mperf;
  810. };
  811. static inline void get_aperfmperf(struct aperfmperf *am)
  812. {
  813. WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
  814. rdmsrl(MSR_IA32_APERF, am->aperf);
  815. rdmsrl(MSR_IA32_MPERF, am->mperf);
  816. }
  817. #define APERFMPERF_SHIFT 10
  818. static inline
  819. unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
  820. struct aperfmperf *new)
  821. {
  822. u64 aperf = new->aperf - old->aperf;
  823. u64 mperf = new->mperf - old->mperf;
  824. unsigned long ratio = aperf;
  825. mperf >>= APERFMPERF_SHIFT;
  826. if (mperf)
  827. ratio = div64_u64(aperf, mperf);
  828. return ratio;
  829. }
  830. /*
  831. * AMD errata checking
  832. */
  833. #ifdef CONFIG_CPU_SUP_AMD
  834. extern const int amd_erratum_383[];
  835. extern const int amd_erratum_400[];
  836. extern bool cpu_has_amd_erratum(const int *);
  837. #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
  838. #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
  839. #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
  840. ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
  841. #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
  842. #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
  843. #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
  844. #else
  845. #define cpu_has_amd_erratum(x) (false)
  846. #endif /* CONFIG_CPU_SUP_AMD */
  847. extern unsigned long arch_align_stack(unsigned long sp);
  848. extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
  849. void default_idle(void);
  850. bool set_pm_idle_to_default(void);
  851. void stop_this_cpu(void *dummy);
  852. #endif /* _ASM_X86_PROCESSOR_H */