ktlb.S 4.9 KB

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  1. /* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
  2. *
  3. * Copyright (C) 1995, 1997, 2005 David S. Miller <davem@davemloft.net>
  4. * Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de)
  5. * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  7. */
  8. #include <linux/config.h>
  9. #include <asm/head.h>
  10. #include <asm/asi.h>
  11. #include <asm/page.h>
  12. #include <asm/pgtable.h>
  13. #include <asm/tsb.h>
  14. .text
  15. .align 32
  16. kvmap_itlb:
  17. /* g6: TAG TARGET */
  18. mov TLB_TAG_ACCESS, %g4
  19. ldxa [%g4] ASI_IMMU, %g4
  20. /* sun4v_itlb_miss branches here with the missing virtual
  21. * address already loaded into %g4
  22. */
  23. kvmap_itlb_4v:
  24. kvmap_itlb_nonlinear:
  25. /* Catch kernel NULL pointer calls. */
  26. sethi %hi(PAGE_SIZE), %g5
  27. cmp %g4, %g5
  28. bleu,pn %xcc, kvmap_dtlb_longpath
  29. nop
  30. KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
  31. kvmap_itlb_tsb_miss:
  32. sethi %hi(LOW_OBP_ADDRESS), %g5
  33. cmp %g4, %g5
  34. blu,pn %xcc, kvmap_itlb_vmalloc_addr
  35. mov 0x1, %g5
  36. sllx %g5, 32, %g5
  37. cmp %g4, %g5
  38. blu,pn %xcc, kvmap_itlb_obp
  39. nop
  40. kvmap_itlb_vmalloc_addr:
  41. KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
  42. KTSB_LOCK_TAG(%g1, %g2, %g7)
  43. /* Load and check PTE. */
  44. ldxa [%g5] ASI_PHYS_USE_EC, %g5
  45. brgez,a,pn %g5, kvmap_itlb_longpath
  46. KTSB_STORE(%g1, %g0)
  47. KTSB_WRITE(%g1, %g5, %g6)
  48. /* fallthrough to TLB load */
  49. kvmap_itlb_load:
  50. 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
  51. retry
  52. .section .sun4v_2insn_patch, "ax"
  53. .word 661b
  54. nop
  55. nop
  56. .previous
  57. /* For sun4v the ASI_ITLB_DATA_IN store and the retry
  58. * instruction get nop'd out and we get here to branch
  59. * to the sun4v tlb load code. The registers are setup
  60. * as follows:
  61. *
  62. * %g4: vaddr
  63. * %g5: PTE
  64. * %g6: TAG
  65. *
  66. * The sun4v TLB load wants the PTE in %g3 so we fix that
  67. * up here.
  68. */
  69. ba,pt %xcc, sun4v_itlb_load
  70. mov %g5, %g3
  71. kvmap_itlb_longpath:
  72. 661: rdpr %pstate, %g5
  73. wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
  74. .section .sun4v_2insn_patch, "ax"
  75. .word 661b
  76. nop
  77. nop
  78. .previous
  79. rdpr %tpc, %g5
  80. ba,pt %xcc, sparc64_realfault_common
  81. mov FAULT_CODE_ITLB, %g4
  82. kvmap_itlb_obp:
  83. OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
  84. KTSB_LOCK_TAG(%g1, %g2, %g7)
  85. KTSB_WRITE(%g1, %g5, %g6)
  86. ba,pt %xcc, kvmap_itlb_load
  87. nop
  88. kvmap_dtlb_obp:
  89. OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
  90. KTSB_LOCK_TAG(%g1, %g2, %g7)
  91. KTSB_WRITE(%g1, %g5, %g6)
  92. ba,pt %xcc, kvmap_dtlb_load
  93. nop
  94. .align 32
  95. kvmap_dtlb:
  96. /* %g6: TAG TARGET */
  97. mov TLB_TAG_ACCESS, %g4
  98. ldxa [%g4] ASI_DMMU, %g4
  99. /* sun4v_dtlb_miss branches here with the missing virtual
  100. * address already loaded into %g4
  101. */
  102. kvmap_dtlb_4v:
  103. brgez,pn %g4, kvmap_dtlb_nonlinear
  104. nop
  105. #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
  106. #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
  107. sethi %uhi(KERN_HIGHBITS), %g2
  108. or %g2, %ulo(KERN_HIGHBITS), %g2
  109. sllx %g2, 32, %g2
  110. or %g2, KERN_LOWBITS, %g2
  111. #undef KERN_HIGHBITS
  112. #undef KERN_LOWBITS
  113. .globl kvmap_linear_patch
  114. kvmap_linear_patch:
  115. ba,pt %xcc, kvmap_dtlb_load
  116. xor %g2, %g4, %g5
  117. kvmap_dtlb_vmalloc_addr:
  118. KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
  119. KTSB_LOCK_TAG(%g1, %g2, %g7)
  120. /* Load and check PTE. */
  121. ldxa [%g5] ASI_PHYS_USE_EC, %g5
  122. brgez,a,pn %g5, kvmap_dtlb_longpath
  123. KTSB_STORE(%g1, %g0)
  124. KTSB_WRITE(%g1, %g5, %g6)
  125. /* fallthrough to TLB load */
  126. kvmap_dtlb_load:
  127. 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
  128. retry
  129. .section .sun4v_2insn_patch, "ax"
  130. .word 661b
  131. nop
  132. nop
  133. .previous
  134. /* For sun4v the ASI_DTLB_DATA_IN store and the retry
  135. * instruction get nop'd out and we get here to branch
  136. * to the sun4v tlb load code. The registers are setup
  137. * as follows:
  138. *
  139. * %g4: vaddr
  140. * %g5: PTE
  141. * %g6: TAG
  142. *
  143. * The sun4v TLB load wants the PTE in %g3 so we fix that
  144. * up here.
  145. */
  146. ba,pt %xcc, sun4v_dtlb_load
  147. mov %g5, %g3
  148. kvmap_dtlb_nonlinear:
  149. /* Catch kernel NULL pointer derefs. */
  150. sethi %hi(PAGE_SIZE), %g5
  151. cmp %g4, %g5
  152. bleu,pn %xcc, kvmap_dtlb_longpath
  153. nop
  154. KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
  155. kvmap_dtlb_tsbmiss:
  156. sethi %hi(MODULES_VADDR), %g5
  157. cmp %g4, %g5
  158. blu,pn %xcc, kvmap_dtlb_longpath
  159. mov (VMALLOC_END >> 24), %g5
  160. sllx %g5, 24, %g5
  161. cmp %g4, %g5
  162. bgeu,pn %xcc, kvmap_dtlb_longpath
  163. nop
  164. kvmap_check_obp:
  165. sethi %hi(LOW_OBP_ADDRESS), %g5
  166. cmp %g4, %g5
  167. blu,pn %xcc, kvmap_dtlb_vmalloc_addr
  168. mov 0x1, %g5
  169. sllx %g5, 32, %g5
  170. cmp %g4, %g5
  171. blu,pn %xcc, kvmap_dtlb_obp
  172. nop
  173. ba,pt %xcc, kvmap_dtlb_vmalloc_addr
  174. nop
  175. kvmap_dtlb_longpath:
  176. 661: rdpr %pstate, %g5
  177. wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
  178. .section .sun4v_2insn_patch, "ax"
  179. .word 661b
  180. nop
  181. nop
  182. .previous
  183. rdpr %tl, %g3
  184. cmp %g3, 1
  185. 661: mov TLB_TAG_ACCESS, %g4
  186. ldxa [%g4] ASI_DMMU, %g5
  187. .section .sun4v_2insn_patch, "ax"
  188. .word 661b
  189. mov %g4, %g5
  190. nop
  191. .previous
  192. be,pt %xcc, sparc64_realfault_common
  193. mov FAULT_CODE_DTLB, %g4
  194. ba,pt %xcc, winfix_trampoline
  195. nop