en_rx.c 30 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/if_ether.h>
  37. #include <linux/if_vlan.h>
  38. #include <linux/vmalloc.h>
  39. #include "mlx4_en.h"
  40. static void *get_wqe(struct mlx4_en_rx_ring *ring, int n)
  41. {
  42. int offset = n << ring->srq.wqe_shift;
  43. return ring->buf + offset;
  44. }
  45. static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type)
  46. {
  47. return;
  48. }
  49. static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr,
  50. void **ip_hdr, void **tcpudp_hdr,
  51. u64 *hdr_flags, void *priv)
  52. {
  53. *mac_hdr = page_address(frags->page) + frags->page_offset;
  54. *ip_hdr = *mac_hdr + ETH_HLEN;
  55. *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr));
  56. *hdr_flags = LRO_IPV4 | LRO_TCP;
  57. return 0;
  58. }
  59. static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
  60. struct mlx4_en_rx_desc *rx_desc,
  61. struct skb_frag_struct *skb_frags,
  62. struct mlx4_en_rx_alloc *ring_alloc,
  63. int i)
  64. {
  65. struct mlx4_en_dev *mdev = priv->mdev;
  66. struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  67. struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
  68. struct page *page;
  69. dma_addr_t dma;
  70. if (page_alloc->offset == frag_info->last_offset) {
  71. /* Allocate new page */
  72. page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
  73. if (!page)
  74. return -ENOMEM;
  75. skb_frags[i].page = page_alloc->page;
  76. skb_frags[i].page_offset = page_alloc->offset;
  77. page_alloc->page = page;
  78. page_alloc->offset = frag_info->frag_align;
  79. } else {
  80. page = page_alloc->page;
  81. get_page(page);
  82. skb_frags[i].page = page;
  83. skb_frags[i].page_offset = page_alloc->offset;
  84. page_alloc->offset += frag_info->frag_stride;
  85. }
  86. dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
  87. skb_frags[i].page_offset, frag_info->frag_size,
  88. PCI_DMA_FROMDEVICE);
  89. rx_desc->data[i].addr = cpu_to_be64(dma);
  90. return 0;
  91. }
  92. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  93. struct mlx4_en_rx_ring *ring)
  94. {
  95. struct mlx4_en_rx_alloc *page_alloc;
  96. int i;
  97. for (i = 0; i < priv->num_frags; i++) {
  98. page_alloc = &ring->page_alloc[i];
  99. page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  100. MLX4_EN_ALLOC_ORDER);
  101. if (!page_alloc->page)
  102. goto out;
  103. page_alloc->offset = priv->frag_info[i].frag_align;
  104. en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
  105. i, page_alloc->page);
  106. }
  107. return 0;
  108. out:
  109. while (i--) {
  110. page_alloc = &ring->page_alloc[i];
  111. put_page(page_alloc->page);
  112. page_alloc->page = NULL;
  113. }
  114. return -ENOMEM;
  115. }
  116. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  117. struct mlx4_en_rx_ring *ring)
  118. {
  119. struct mlx4_en_rx_alloc *page_alloc;
  120. int i;
  121. for (i = 0; i < priv->num_frags; i++) {
  122. page_alloc = &ring->page_alloc[i];
  123. en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  124. i, page_count(page_alloc->page));
  125. put_page(page_alloc->page);
  126. page_alloc->page = NULL;
  127. }
  128. }
  129. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  130. struct mlx4_en_rx_ring *ring, int index)
  131. {
  132. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  133. struct skb_frag_struct *skb_frags = ring->rx_info +
  134. (index << priv->log_rx_info);
  135. int possible_frags;
  136. int i;
  137. /* Pre-link descriptor */
  138. rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask);
  139. /* Set size and memtype fields */
  140. for (i = 0; i < priv->num_frags; i++) {
  141. skb_frags[i].size = priv->frag_info[i].frag_size;
  142. rx_desc->data[i].byte_count =
  143. cpu_to_be32(priv->frag_info[i].frag_size);
  144. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  145. }
  146. /* If the number of used fragments does not fill up the ring stride,
  147. * remaining (unused) fragments must be padded with null address/size
  148. * and a special memory key */
  149. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  150. for (i = priv->num_frags; i < possible_frags; i++) {
  151. rx_desc->data[i].byte_count = 0;
  152. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  153. rx_desc->data[i].addr = 0;
  154. }
  155. }
  156. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  157. struct mlx4_en_rx_ring *ring, int index)
  158. {
  159. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  160. struct skb_frag_struct *skb_frags = ring->rx_info +
  161. (index << priv->log_rx_info);
  162. int i;
  163. for (i = 0; i < priv->num_frags; i++)
  164. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
  165. goto err;
  166. return 0;
  167. err:
  168. while (i--)
  169. put_page(skb_frags[i].page);
  170. return -ENOMEM;
  171. }
  172. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  173. {
  174. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  175. }
  176. static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
  177. struct mlx4_en_rx_ring *ring,
  178. int index)
  179. {
  180. struct mlx4_en_dev *mdev = priv->mdev;
  181. struct skb_frag_struct *skb_frags;
  182. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
  183. dma_addr_t dma;
  184. int nr;
  185. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  186. for (nr = 0; nr < priv->num_frags; nr++) {
  187. en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  188. dma = be64_to_cpu(rx_desc->data[nr].addr);
  189. en_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
  190. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  191. PCI_DMA_FROMDEVICE);
  192. put_page(skb_frags[nr].page);
  193. }
  194. }
  195. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  196. {
  197. struct mlx4_en_rx_ring *ring;
  198. int ring_ind;
  199. int buf_ind;
  200. int new_size;
  201. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  202. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  203. ring = &priv->rx_ring[ring_ind];
  204. if (mlx4_en_prepare_rx_desc(priv, ring,
  205. ring->actual_size)) {
  206. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  207. en_err(priv, "Failed to allocate "
  208. "enough rx buffers\n");
  209. return -ENOMEM;
  210. } else {
  211. new_size = rounddown_pow_of_two(ring->actual_size);
  212. en_warn(priv, "Only %d buffers allocated "
  213. "reducing ring size to %d",
  214. ring->actual_size, new_size);
  215. goto reduce_rings;
  216. }
  217. }
  218. ring->actual_size++;
  219. ring->prod++;
  220. }
  221. }
  222. return 0;
  223. reduce_rings:
  224. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  225. ring = &priv->rx_ring[ring_ind];
  226. while (ring->actual_size > new_size) {
  227. ring->actual_size--;
  228. ring->prod--;
  229. mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
  230. }
  231. ring->size_mask = ring->actual_size - 1;
  232. }
  233. return 0;
  234. }
  235. static int mlx4_en_fill_rx_buf(struct net_device *dev,
  236. struct mlx4_en_rx_ring *ring)
  237. {
  238. struct mlx4_en_priv *priv = netdev_priv(dev);
  239. int num = 0;
  240. int err;
  241. while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
  242. err = mlx4_en_prepare_rx_desc(priv, ring, ring->prod &
  243. ring->size_mask);
  244. if (err) {
  245. if (netif_msg_rx_err(priv))
  246. en_warn(priv, "Failed preparing rx descriptor\n");
  247. priv->port_stats.rx_alloc_failed++;
  248. break;
  249. }
  250. ++num;
  251. ++ring->prod;
  252. }
  253. if ((u32) (ring->prod - ring->cons) == ring->actual_size)
  254. ring->full = 1;
  255. return num;
  256. }
  257. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  258. struct mlx4_en_rx_ring *ring)
  259. {
  260. int index;
  261. en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  262. ring->cons, ring->prod);
  263. /* Unmap and free Rx buffers */
  264. BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
  265. while (ring->cons != ring->prod) {
  266. index = ring->cons & ring->size_mask;
  267. en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  268. mlx4_en_free_rx_desc(priv, ring, index);
  269. ++ring->cons;
  270. }
  271. }
  272. void mlx4_en_rx_refill(struct work_struct *work)
  273. {
  274. struct delayed_work *delay = to_delayed_work(work);
  275. struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
  276. refill_task);
  277. struct mlx4_en_dev *mdev = priv->mdev;
  278. struct net_device *dev = priv->dev;
  279. struct mlx4_en_rx_ring *ring;
  280. int need_refill = 0;
  281. int i;
  282. mutex_lock(&mdev->state_lock);
  283. if (!mdev->device_up || !priv->port_up)
  284. goto out;
  285. /* We only get here if there are no receive buffers, so we can't race
  286. * with Rx interrupts while filling buffers */
  287. for (i = 0; i < priv->rx_ring_num; i++) {
  288. ring = &priv->rx_ring[i];
  289. if (ring->need_refill) {
  290. if (mlx4_en_fill_rx_buf(dev, ring)) {
  291. ring->need_refill = 0;
  292. mlx4_en_update_rx_prod_db(ring);
  293. } else
  294. need_refill = 1;
  295. }
  296. }
  297. if (need_refill)
  298. queue_delayed_work(mdev->workqueue, &priv->refill_task, HZ);
  299. out:
  300. mutex_unlock(&mdev->state_lock);
  301. }
  302. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  303. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  304. {
  305. struct mlx4_en_dev *mdev = priv->mdev;
  306. int err;
  307. int tmp;
  308. /* Sanity check SRQ size before proceeding */
  309. if (size >= mdev->dev->caps.max_srq_wqes)
  310. return -EINVAL;
  311. ring->prod = 0;
  312. ring->cons = 0;
  313. ring->size = size;
  314. ring->size_mask = size - 1;
  315. ring->stride = stride;
  316. ring->log_stride = ffs(ring->stride) - 1;
  317. ring->buf_size = ring->size * ring->stride;
  318. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  319. sizeof(struct skb_frag_struct));
  320. ring->rx_info = vmalloc(tmp);
  321. if (!ring->rx_info) {
  322. en_err(priv, "Failed allocating rx_info ring\n");
  323. return -ENOMEM;
  324. }
  325. en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  326. ring->rx_info, tmp);
  327. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  328. ring->buf_size, 2 * PAGE_SIZE);
  329. if (err)
  330. goto err_ring;
  331. err = mlx4_en_map_buffer(&ring->wqres.buf);
  332. if (err) {
  333. en_err(priv, "Failed to map RX buffer\n");
  334. goto err_hwq;
  335. }
  336. ring->buf = ring->wqres.buf.direct.buf;
  337. /* Configure lro mngr */
  338. memset(&ring->lro, 0, sizeof(struct net_lro_mgr));
  339. ring->lro.dev = priv->dev;
  340. ring->lro.features = LRO_F_NAPI;
  341. ring->lro.frag_align_pad = NET_IP_ALIGN;
  342. ring->lro.ip_summed = CHECKSUM_UNNECESSARY;
  343. ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  344. ring->lro.max_desc = mdev->profile.num_lro;
  345. ring->lro.max_aggr = MAX_SKB_FRAGS;
  346. ring->lro.lro_arr = kzalloc(mdev->profile.num_lro *
  347. sizeof(struct net_lro_desc),
  348. GFP_KERNEL);
  349. if (!ring->lro.lro_arr) {
  350. en_err(priv, "Failed to allocate lro array\n");
  351. goto err_map;
  352. }
  353. ring->lro.get_frag_header = mlx4_en_get_frag_header;
  354. return 0;
  355. err_map:
  356. mlx4_en_unmap_buffer(&ring->wqres.buf);
  357. err_hwq:
  358. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  359. err_ring:
  360. vfree(ring->rx_info);
  361. ring->rx_info = NULL;
  362. return err;
  363. }
  364. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  365. {
  366. struct mlx4_en_dev *mdev = priv->mdev;
  367. struct mlx4_wqe_srq_next_seg *next;
  368. struct mlx4_en_rx_ring *ring;
  369. int i;
  370. int ring_ind;
  371. int err;
  372. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  373. DS_SIZE * priv->num_frags);
  374. int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE;
  375. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  376. ring = &priv->rx_ring[ring_ind];
  377. ring->prod = 0;
  378. ring->cons = 0;
  379. ring->actual_size = 0;
  380. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  381. ring->stride = stride;
  382. ring->log_stride = ffs(ring->stride) - 1;
  383. ring->buf_size = ring->size * ring->stride;
  384. memset(ring->buf, 0, ring->buf_size);
  385. mlx4_en_update_rx_prod_db(ring);
  386. /* Initailize all descriptors */
  387. for (i = 0; i < ring->size; i++)
  388. mlx4_en_init_rx_desc(priv, ring, i);
  389. /* Initialize page allocators */
  390. err = mlx4_en_init_allocator(priv, ring);
  391. if (err) {
  392. en_err(priv, "Failed initializing ring allocator\n");
  393. ring_ind--;
  394. goto err_allocator;
  395. }
  396. /* Fill Rx buffers */
  397. ring->full = 0;
  398. }
  399. err = mlx4_en_fill_rx_buffers(priv);
  400. if (err)
  401. goto err_buffers;
  402. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  403. ring = &priv->rx_ring[ring_ind];
  404. mlx4_en_update_rx_prod_db(ring);
  405. /* Configure SRQ representing the ring */
  406. ring->srq.max = ring->actual_size;
  407. ring->srq.max_gs = max_gs;
  408. ring->srq.wqe_shift = ilog2(ring->stride);
  409. for (i = 0; i < ring->srq.max; ++i) {
  410. next = get_wqe(ring, i);
  411. next->next_wqe_index =
  412. cpu_to_be16((i + 1) & (ring->srq.max - 1));
  413. }
  414. err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, &ring->wqres.mtt,
  415. ring->wqres.db.dma, &ring->srq);
  416. if (err){
  417. en_err(priv, "Failed to allocate srq\n");
  418. ring_ind--;
  419. goto err_srq;
  420. }
  421. ring->srq.event = mlx4_en_srq_event;
  422. }
  423. return 0;
  424. err_srq:
  425. while (ring_ind >= 0) {
  426. ring = &priv->rx_ring[ring_ind];
  427. mlx4_srq_free(mdev->dev, &ring->srq);
  428. ring_ind--;
  429. }
  430. err_buffers:
  431. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  432. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  433. ring_ind = priv->rx_ring_num - 1;
  434. err_allocator:
  435. while (ring_ind >= 0) {
  436. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  437. ring_ind--;
  438. }
  439. return err;
  440. }
  441. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  442. struct mlx4_en_rx_ring *ring)
  443. {
  444. struct mlx4_en_dev *mdev = priv->mdev;
  445. kfree(ring->lro.lro_arr);
  446. mlx4_en_unmap_buffer(&ring->wqres.buf);
  447. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  448. vfree(ring->rx_info);
  449. ring->rx_info = NULL;
  450. }
  451. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  452. struct mlx4_en_rx_ring *ring)
  453. {
  454. struct mlx4_en_dev *mdev = priv->mdev;
  455. mlx4_srq_free(mdev->dev, &ring->srq);
  456. mlx4_en_free_rx_buf(priv, ring);
  457. mlx4_en_destroy_allocator(priv, ring);
  458. }
  459. /* Unmap a completed descriptor and free unused pages */
  460. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  461. struct mlx4_en_rx_desc *rx_desc,
  462. struct skb_frag_struct *skb_frags,
  463. struct skb_frag_struct *skb_frags_rx,
  464. struct mlx4_en_rx_alloc *page_alloc,
  465. int length)
  466. {
  467. struct mlx4_en_dev *mdev = priv->mdev;
  468. struct mlx4_en_frag_info *frag_info;
  469. int nr;
  470. dma_addr_t dma;
  471. /* Collect used fragments while replacing them in the HW descirptors */
  472. for (nr = 0; nr < priv->num_frags; nr++) {
  473. frag_info = &priv->frag_info[nr];
  474. if (length <= frag_info->frag_prefix_size)
  475. break;
  476. /* Save page reference in skb */
  477. skb_frags_rx[nr].page = skb_frags[nr].page;
  478. skb_frags_rx[nr].size = skb_frags[nr].size;
  479. skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
  480. dma = be64_to_cpu(rx_desc->data[nr].addr);
  481. /* Allocate a replacement page */
  482. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
  483. goto fail;
  484. /* Unmap buffer */
  485. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  486. PCI_DMA_FROMDEVICE);
  487. }
  488. /* Adjust size of last fragment to match actual length */
  489. skb_frags_rx[nr - 1].size = length -
  490. priv->frag_info[nr - 1].frag_prefix_size;
  491. return nr;
  492. fail:
  493. /* Drop all accumulated fragments (which have already been replaced in
  494. * the descriptor) of this packet; remaining fragments are reused... */
  495. while (nr > 0) {
  496. nr--;
  497. put_page(skb_frags_rx[nr].page);
  498. }
  499. return 0;
  500. }
  501. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  502. struct mlx4_en_rx_desc *rx_desc,
  503. struct skb_frag_struct *skb_frags,
  504. struct mlx4_en_rx_alloc *page_alloc,
  505. unsigned int length)
  506. {
  507. struct mlx4_en_dev *mdev = priv->mdev;
  508. struct sk_buff *skb;
  509. void *va;
  510. int used_frags;
  511. dma_addr_t dma;
  512. skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
  513. if (!skb) {
  514. en_dbg(RX_ERR, priv, "Failed allocating skb\n");
  515. return NULL;
  516. }
  517. skb->dev = priv->dev;
  518. skb_reserve(skb, NET_IP_ALIGN);
  519. skb->len = length;
  520. skb->truesize = length + sizeof(struct sk_buff);
  521. /* Get pointer to first fragment so we could copy the headers into the
  522. * (linear part of the) skb */
  523. va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
  524. if (length <= SMALL_PACKET_SIZE) {
  525. /* We are copying all relevant data to the skb - temporarily
  526. * synch buffers for the copy */
  527. dma = be64_to_cpu(rx_desc->data[0].addr);
  528. dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0,
  529. length, DMA_FROM_DEVICE);
  530. skb_copy_to_linear_data(skb, va, length);
  531. dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0,
  532. length, DMA_FROM_DEVICE);
  533. skb->tail += length;
  534. } else {
  535. /* Move relevant fragments to skb */
  536. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
  537. skb_shinfo(skb)->frags,
  538. page_alloc, length);
  539. if (unlikely(!used_frags)) {
  540. kfree_skb(skb);
  541. return NULL;
  542. }
  543. skb_shinfo(skb)->nr_frags = used_frags;
  544. /* Copy headers into the skb linear buffer */
  545. memcpy(skb->data, va, HEADER_COPY_SIZE);
  546. skb->tail += HEADER_COPY_SIZE;
  547. /* Skip headers in first fragment */
  548. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  549. /* Adjust size of first fragment */
  550. skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
  551. skb->data_len = length - HEADER_COPY_SIZE;
  552. }
  553. return skb;
  554. }
  555. static void mlx4_en_copy_desc(struct mlx4_en_priv *priv,
  556. struct mlx4_en_rx_ring *ring,
  557. int from, int to, int num)
  558. {
  559. struct skb_frag_struct *skb_frags_from;
  560. struct skb_frag_struct *skb_frags_to;
  561. struct mlx4_en_rx_desc *rx_desc_from;
  562. struct mlx4_en_rx_desc *rx_desc_to;
  563. int from_index, to_index;
  564. int nr, i;
  565. for (i = 0; i < num; i++) {
  566. from_index = (from + i) & ring->size_mask;
  567. to_index = (to + i) & ring->size_mask;
  568. skb_frags_from = ring->rx_info + (from_index << priv->log_rx_info);
  569. skb_frags_to = ring->rx_info + (to_index << priv->log_rx_info);
  570. rx_desc_from = ring->buf + (from_index << ring->log_stride);
  571. rx_desc_to = ring->buf + (to_index << ring->log_stride);
  572. for (nr = 0; nr < priv->num_frags; nr++) {
  573. skb_frags_to[nr].page = skb_frags_from[nr].page;
  574. skb_frags_to[nr].page_offset = skb_frags_from[nr].page_offset;
  575. rx_desc_to->data[nr].addr = rx_desc_from->data[nr].addr;
  576. }
  577. }
  578. }
  579. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  580. {
  581. struct mlx4_en_priv *priv = netdev_priv(dev);
  582. struct mlx4_cqe *cqe;
  583. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  584. struct skb_frag_struct *skb_frags;
  585. struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS];
  586. struct mlx4_en_rx_desc *rx_desc;
  587. struct sk_buff *skb;
  588. int index;
  589. int nr;
  590. unsigned int length;
  591. int polled = 0;
  592. int ip_summed;
  593. if (!priv->port_up)
  594. return 0;
  595. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  596. * descriptor offset can be deduced from the CQE index instead of
  597. * reading 'cqe->index' */
  598. index = cq->mcq.cons_index & ring->size_mask;
  599. cqe = &cq->buf[index];
  600. /* Process all completed CQEs */
  601. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  602. cq->mcq.cons_index & cq->size)) {
  603. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  604. rx_desc = ring->buf + (index << ring->log_stride);
  605. /*
  606. * make sure we read the CQE after we read the ownership bit
  607. */
  608. rmb();
  609. /* Drop packet on bad receive or bad checksum */
  610. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  611. MLX4_CQE_OPCODE_ERROR)) {
  612. en_err(priv, "CQE completed in error - vendor "
  613. "syndrom:%d syndrom:%d\n",
  614. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  615. ((struct mlx4_err_cqe *) cqe)->syndrome);
  616. goto next;
  617. }
  618. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  619. en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  620. goto next;
  621. }
  622. /*
  623. * Packet is OK - process it.
  624. */
  625. length = be32_to_cpu(cqe->byte_cnt);
  626. ring->bytes += length;
  627. ring->packets++;
  628. if (likely(priv->rx_csum)) {
  629. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  630. (cqe->checksum == cpu_to_be16(0xffff))) {
  631. priv->port_stats.rx_chksum_good++;
  632. /* This packet is eligible for LRO if it is:
  633. * - DIX Ethernet (type interpretation)
  634. * - TCP/IP (v4)
  635. * - without IP options
  636. * - not an IP fragment */
  637. if (mlx4_en_can_lro(cqe->status) &&
  638. dev->features & NETIF_F_LRO) {
  639. nr = mlx4_en_complete_rx_desc(
  640. priv, rx_desc,
  641. skb_frags, lro_frags,
  642. ring->page_alloc, length);
  643. if (!nr)
  644. goto next;
  645. if (priv->vlgrp && (cqe->vlan_my_qpn &
  646. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) {
  647. lro_vlan_hwaccel_receive_frags(
  648. &ring->lro, lro_frags,
  649. length, length,
  650. priv->vlgrp,
  651. be16_to_cpu(cqe->sl_vid),
  652. NULL, 0);
  653. } else
  654. lro_receive_frags(&ring->lro,
  655. lro_frags,
  656. length,
  657. length,
  658. NULL, 0);
  659. goto next;
  660. }
  661. /* LRO not possible, complete processing here */
  662. ip_summed = CHECKSUM_UNNECESSARY;
  663. INC_PERF_COUNTER(priv->pstats.lro_misses);
  664. } else {
  665. ip_summed = CHECKSUM_NONE;
  666. priv->port_stats.rx_chksum_none++;
  667. }
  668. } else {
  669. ip_summed = CHECKSUM_NONE;
  670. priv->port_stats.rx_chksum_none++;
  671. }
  672. skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
  673. ring->page_alloc, length);
  674. if (!skb) {
  675. priv->stats.rx_dropped++;
  676. goto next;
  677. }
  678. skb->ip_summed = ip_summed;
  679. skb->protocol = eth_type_trans(skb, dev);
  680. skb_record_rx_queue(skb, cq->ring);
  681. /* Push it up the stack */
  682. if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
  683. MLX4_CQE_VLAN_PRESENT_MASK)) {
  684. vlan_hwaccel_receive_skb(skb, priv->vlgrp,
  685. be16_to_cpu(cqe->sl_vid));
  686. } else
  687. netif_receive_skb(skb);
  688. next:
  689. ++cq->mcq.cons_index;
  690. index = (cq->mcq.cons_index) & ring->size_mask;
  691. cqe = &cq->buf[index];
  692. if (++polled == budget) {
  693. /* We are here because we reached the NAPI budget -
  694. * flush only pending LRO sessions */
  695. lro_flush_all(&ring->lro);
  696. goto out;
  697. }
  698. }
  699. /* If CQ is empty flush all LRO sessions unconditionally */
  700. lro_flush_all(&ring->lro);
  701. out:
  702. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  703. mlx4_cq_set_ci(&cq->mcq);
  704. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  705. ring->cons = cq->mcq.cons_index;
  706. ring->prod += polled; /* Polled descriptors were realocated in place */
  707. if (unlikely(!ring->full)) {
  708. mlx4_en_copy_desc(priv, ring, ring->cons - polled,
  709. ring->prod - polled, polled);
  710. mlx4_en_fill_rx_buf(dev, ring);
  711. }
  712. mlx4_en_update_rx_prod_db(ring);
  713. return polled;
  714. }
  715. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  716. {
  717. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  718. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  719. if (priv->port_up)
  720. napi_schedule(&cq->napi);
  721. else
  722. mlx4_en_arm_cq(priv, cq);
  723. }
  724. /* Rx CQ polling - called by NAPI */
  725. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  726. {
  727. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  728. struct net_device *dev = cq->dev;
  729. struct mlx4_en_priv *priv = netdev_priv(dev);
  730. int done;
  731. done = mlx4_en_process_rx_cq(dev, cq, budget);
  732. /* If we used up all the quota - we're probably not done yet... */
  733. if (done == budget)
  734. INC_PERF_COUNTER(priv->pstats.napi_quota);
  735. else {
  736. /* Done for now */
  737. napi_complete(napi);
  738. mlx4_en_arm_cq(priv, cq);
  739. }
  740. return done;
  741. }
  742. /* Calculate the last offset position that accomodates a full fragment
  743. * (assuming fagment size = stride-align) */
  744. static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
  745. {
  746. u16 res = MLX4_EN_ALLOC_SIZE % stride;
  747. u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
  748. en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
  749. "res:%d offset:%d\n", stride, align, res, offset);
  750. return offset;
  751. }
  752. static int frag_sizes[] = {
  753. FRAG_SZ0,
  754. FRAG_SZ1,
  755. FRAG_SZ2,
  756. FRAG_SZ3
  757. };
  758. void mlx4_en_calc_rx_buf(struct net_device *dev)
  759. {
  760. struct mlx4_en_priv *priv = netdev_priv(dev);
  761. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  762. int buf_size = 0;
  763. int i = 0;
  764. while (buf_size < eff_mtu) {
  765. priv->frag_info[i].frag_size =
  766. (eff_mtu > buf_size + frag_sizes[i]) ?
  767. frag_sizes[i] : eff_mtu - buf_size;
  768. priv->frag_info[i].frag_prefix_size = buf_size;
  769. if (!i) {
  770. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  771. priv->frag_info[i].frag_stride =
  772. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  773. } else {
  774. priv->frag_info[i].frag_align = 0;
  775. priv->frag_info[i].frag_stride =
  776. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  777. }
  778. priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
  779. priv, priv->frag_info[i].frag_stride,
  780. priv->frag_info[i].frag_align);
  781. buf_size += priv->frag_info[i].frag_size;
  782. i++;
  783. }
  784. priv->num_frags = i;
  785. priv->rx_skb_size = eff_mtu;
  786. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
  787. en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  788. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  789. for (i = 0; i < priv->num_frags; i++) {
  790. en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
  791. "stride:%d last_offset:%d\n", i,
  792. priv->frag_info[i].frag_size,
  793. priv->frag_info[i].frag_prefix_size,
  794. priv->frag_info[i].frag_align,
  795. priv->frag_info[i].frag_stride,
  796. priv->frag_info[i].last_offset);
  797. }
  798. }
  799. /* RSS related functions */
  800. /* Calculate rss size and map each entry in rss table to rx ring */
  801. void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
  802. struct mlx4_en_rss_map *rss_map,
  803. int num_entries, int num_rings)
  804. {
  805. int i;
  806. rss_map->size = roundup_pow_of_two(num_entries);
  807. en_dbg(DRV, priv, "Setting default RSS map of %d entires\n",
  808. rss_map->size);
  809. for (i = 0; i < rss_map->size; i++) {
  810. rss_map->map[i] = i % num_rings;
  811. en_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]);
  812. }
  813. }
  814. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv,
  815. int qpn, int srqn, int cqn,
  816. enum mlx4_qp_state *state,
  817. struct mlx4_qp *qp)
  818. {
  819. struct mlx4_en_dev *mdev = priv->mdev;
  820. struct mlx4_qp_context *context;
  821. int err = 0;
  822. context = kmalloc(sizeof *context , GFP_KERNEL);
  823. if (!context) {
  824. en_err(priv, "Failed to allocate qp context\n");
  825. return -ENOMEM;
  826. }
  827. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  828. if (err) {
  829. en_err(priv, "Failed to allocate qp #%x\n", qpn);
  830. goto out;
  831. }
  832. qp->event = mlx4_en_sqp_event;
  833. memset(context, 0, sizeof *context);
  834. mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context);
  835. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state);
  836. if (err) {
  837. mlx4_qp_remove(mdev->dev, qp);
  838. mlx4_qp_free(mdev->dev, qp);
  839. }
  840. out:
  841. kfree(context);
  842. return err;
  843. }
  844. /* Allocate rx qp's and configure them according to rss map */
  845. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  846. {
  847. struct mlx4_en_dev *mdev = priv->mdev;
  848. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  849. struct mlx4_qp_context context;
  850. struct mlx4_en_rss_context *rss_context;
  851. void *ptr;
  852. int rss_xor = mdev->profile.rss_xor;
  853. u8 rss_mask = mdev->profile.rss_mask;
  854. int i, srqn, qpn, cqn;
  855. int err = 0;
  856. int good_qps = 0;
  857. en_dbg(DRV, priv, "Configuring rss steering\n");
  858. err = mlx4_qp_reserve_range(mdev->dev, rss_map->size,
  859. rss_map->size, &rss_map->base_qpn);
  860. if (err) {
  861. en_err(priv, "Failed reserving %d qps\n", rss_map->size);
  862. return err;
  863. }
  864. for (i = 0; i < rss_map->size; i++) {
  865. cqn = priv->rx_ring[rss_map->map[i]].cqn;
  866. srqn = priv->rx_ring[rss_map->map[i]].srq.srqn;
  867. qpn = rss_map->base_qpn + i;
  868. err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn,
  869. &rss_map->state[i],
  870. &rss_map->qps[i]);
  871. if (err)
  872. goto rss_err;
  873. ++good_qps;
  874. }
  875. /* Configure RSS indirection qp */
  876. err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn);
  877. if (err) {
  878. en_err(priv, "Failed to reserve range for RSS "
  879. "indirection qp\n");
  880. goto rss_err;
  881. }
  882. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  883. if (err) {
  884. en_err(priv, "Failed to allocate RSS indirection QP\n");
  885. goto reserve_err;
  886. }
  887. rss_map->indir_qp.event = mlx4_en_sqp_event;
  888. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  889. priv->rx_ring[0].cqn, 0, &context);
  890. ptr = ((void *) &context) + 0x3c;
  891. rss_context = (struct mlx4_en_rss_context *) ptr;
  892. rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size) << 24 |
  893. (rss_map->base_qpn));
  894. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  895. rss_context->hash_fn = rss_xor & 0x3;
  896. rss_context->flags = rss_mask << 2;
  897. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  898. &rss_map->indir_qp, &rss_map->indir_state);
  899. if (err)
  900. goto indir_err;
  901. return 0;
  902. indir_err:
  903. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  904. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  905. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  906. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  907. reserve_err:
  908. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  909. rss_err:
  910. for (i = 0; i < good_qps; i++) {
  911. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  912. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  913. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  914. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  915. }
  916. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  917. return err;
  918. }
  919. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  920. {
  921. struct mlx4_en_dev *mdev = priv->mdev;
  922. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  923. int i;
  924. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  925. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  926. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  927. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  928. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  929. for (i = 0; i < rss_map->size; i++) {
  930. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  931. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  932. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  933. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  934. }
  935. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  936. }