cx88-dvb.c 45 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * MPEG Transport Stream (DVB) routines
  5. *
  6. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  7. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/fs.h>
  27. #include <linux/kthread.h>
  28. #include <linux/file.h>
  29. #include <linux/suspend.h>
  30. #include "cx88.h"
  31. #include "dvb-pll.h"
  32. #include <media/v4l2-common.h>
  33. #include "mt352.h"
  34. #include "mt352_priv.h"
  35. #include "cx88-vp3054-i2c.h"
  36. #include "zl10353.h"
  37. #include "cx22702.h"
  38. #include "or51132.h"
  39. #include "lgdt330x.h"
  40. #include "s5h1409.h"
  41. #include "xc5000.h"
  42. #include "nxt200x.h"
  43. #include "cx24123.h"
  44. #include "isl6421.h"
  45. #include "tuner-simple.h"
  46. #include "tda9887.h"
  47. #include "s5h1411.h"
  48. #include "stv0299.h"
  49. #include "z0194a.h"
  50. #include "stv0288.h"
  51. #include "stb6000.h"
  52. #include "cx24116.h"
  53. #include "stv0900.h"
  54. #include "stb6100.h"
  55. #include "stb6100_proc.h"
  56. #include "mb86a16.h"
  57. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  58. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  59. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  60. MODULE_LICENSE("GPL");
  61. static unsigned int debug;
  62. module_param(debug, int, 0644);
  63. MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
  64. static unsigned int dvb_buf_tscnt = 32;
  65. module_param(dvb_buf_tscnt, int, 0644);
  66. MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]");
  67. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  68. #define dprintk(level,fmt, arg...) if (debug >= level) \
  69. printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
  70. /* ------------------------------------------------------------------ */
  71. static int dvb_buf_setup(struct videobuf_queue *q,
  72. unsigned int *count, unsigned int *size)
  73. {
  74. struct cx8802_dev *dev = q->priv_data;
  75. dev->ts_packet_size = 188 * 4;
  76. dev->ts_packet_count = dvb_buf_tscnt;
  77. *size = dev->ts_packet_size * dev->ts_packet_count;
  78. *count = dvb_buf_tscnt;
  79. return 0;
  80. }
  81. static int dvb_buf_prepare(struct videobuf_queue *q,
  82. struct videobuf_buffer *vb, enum v4l2_field field)
  83. {
  84. struct cx8802_dev *dev = q->priv_data;
  85. return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
  86. }
  87. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  88. {
  89. struct cx8802_dev *dev = q->priv_data;
  90. cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
  91. }
  92. static void dvb_buf_release(struct videobuf_queue *q,
  93. struct videobuf_buffer *vb)
  94. {
  95. cx88_free_buffer(q, (struct cx88_buffer*)vb);
  96. }
  97. static const struct videobuf_queue_ops dvb_qops = {
  98. .buf_setup = dvb_buf_setup,
  99. .buf_prepare = dvb_buf_prepare,
  100. .buf_queue = dvb_buf_queue,
  101. .buf_release = dvb_buf_release,
  102. };
  103. /* ------------------------------------------------------------------ */
  104. static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
  105. {
  106. struct cx8802_dev *dev= fe->dvb->priv;
  107. struct cx8802_driver *drv = NULL;
  108. int ret = 0;
  109. int fe_id;
  110. fe_id = videobuf_dvb_find_frontend(&dev->frontends, fe);
  111. if (!fe_id) {
  112. printk(KERN_ERR "%s() No frontend found\n", __func__);
  113. return -EINVAL;
  114. }
  115. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  116. if (drv) {
  117. if (acquire){
  118. dev->frontends.active_fe_id = fe_id;
  119. ret = drv->request_acquire(drv);
  120. } else {
  121. ret = drv->request_release(drv);
  122. dev->frontends.active_fe_id = 0;
  123. }
  124. }
  125. return ret;
  126. }
  127. static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open)
  128. {
  129. struct videobuf_dvb_frontends *f;
  130. struct videobuf_dvb_frontend *fe;
  131. if (!core->dvbdev)
  132. return;
  133. f = &core->dvbdev->frontends;
  134. if (!f)
  135. return;
  136. if (f->gate <= 1) /* undefined or fe0 */
  137. fe = videobuf_dvb_get_frontend(f, 1);
  138. else
  139. fe = videobuf_dvb_get_frontend(f, f->gate);
  140. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  141. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  142. }
  143. /* ------------------------------------------------------------------ */
  144. static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
  145. {
  146. static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
  147. static const u8 reset [] = { RESET, 0x80 };
  148. static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  149. static const u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
  150. static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  151. static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  152. mt352_write(fe, clock_config, sizeof(clock_config));
  153. udelay(200);
  154. mt352_write(fe, reset, sizeof(reset));
  155. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  156. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  157. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  158. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  159. return 0;
  160. }
  161. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  162. {
  163. static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
  164. static const u8 reset [] = { RESET, 0x80 };
  165. static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  166. static const u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
  167. static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  168. static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  169. mt352_write(fe, clock_config, sizeof(clock_config));
  170. udelay(200);
  171. mt352_write(fe, reset, sizeof(reset));
  172. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  173. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  174. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  175. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  176. return 0;
  177. }
  178. static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
  179. {
  180. static const u8 clock_config [] = { 0x89, 0x38, 0x39 };
  181. static const u8 reset [] = { 0x50, 0x80 };
  182. static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  183. static const u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  184. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  185. static const u8 dntv_extra[] = { 0xB5, 0x7A };
  186. static const u8 capt_range_cfg[] = { 0x75, 0x32 };
  187. mt352_write(fe, clock_config, sizeof(clock_config));
  188. udelay(2000);
  189. mt352_write(fe, reset, sizeof(reset));
  190. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  191. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  192. udelay(2000);
  193. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  194. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  195. return 0;
  196. }
  197. static const struct mt352_config dvico_fusionhdtv = {
  198. .demod_address = 0x0f,
  199. .demod_init = dvico_fusionhdtv_demod_init,
  200. };
  201. static const struct mt352_config dntv_live_dvbt_config = {
  202. .demod_address = 0x0f,
  203. .demod_init = dntv_live_dvbt_demod_init,
  204. };
  205. static const struct mt352_config dvico_fusionhdtv_dual = {
  206. .demod_address = 0x0f,
  207. .demod_init = dvico_dual_demod_init,
  208. };
  209. static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = {
  210. .demod_address = (0x1e >> 1),
  211. .no_tuner = 1,
  212. .if2 = 45600,
  213. };
  214. static struct mb86a16_config twinhan_vp1027 = {
  215. .demod_address = 0x08,
  216. };
  217. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  218. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
  219. {
  220. static const u8 clock_config [] = { 0x89, 0x38, 0x38 };
  221. static const u8 reset [] = { 0x50, 0x80 };
  222. static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  223. static const u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  224. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  225. static const u8 dntv_extra[] = { 0xB5, 0x7A };
  226. static const u8 capt_range_cfg[] = { 0x75, 0x32 };
  227. mt352_write(fe, clock_config, sizeof(clock_config));
  228. udelay(2000);
  229. mt352_write(fe, reset, sizeof(reset));
  230. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  231. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  232. udelay(2000);
  233. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  234. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  235. return 0;
  236. }
  237. static const struct mt352_config dntv_live_dvbt_pro_config = {
  238. .demod_address = 0x0f,
  239. .no_tuner = 1,
  240. .demod_init = dntv_live_dvbt_pro_demod_init,
  241. };
  242. #endif
  243. static const struct zl10353_config dvico_fusionhdtv_hybrid = {
  244. .demod_address = 0x0f,
  245. .no_tuner = 1,
  246. };
  247. static const struct zl10353_config dvico_fusionhdtv_xc3028 = {
  248. .demod_address = 0x0f,
  249. .if2 = 45600,
  250. .no_tuner = 1,
  251. };
  252. static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
  253. .demod_address = 0x0f,
  254. .if2 = 4560,
  255. .no_tuner = 1,
  256. .demod_init = dvico_fusionhdtv_demod_init,
  257. };
  258. static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  259. .demod_address = 0x0f,
  260. };
  261. static const struct cx22702_config connexant_refboard_config = {
  262. .demod_address = 0x43,
  263. .output_mode = CX22702_SERIAL_OUTPUT,
  264. };
  265. static const struct cx22702_config hauppauge_hvr_config = {
  266. .demod_address = 0x63,
  267. .output_mode = CX22702_SERIAL_OUTPUT,
  268. };
  269. static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  270. {
  271. struct cx8802_dev *dev= fe->dvb->priv;
  272. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  273. return 0;
  274. }
  275. static const struct or51132_config pchdtv_hd3000 = {
  276. .demod_address = 0x15,
  277. .set_ts_params = or51132_set_ts_param,
  278. };
  279. static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
  280. {
  281. struct cx8802_dev *dev= fe->dvb->priv;
  282. struct cx88_core *core = dev->core;
  283. dprintk(1, "%s: index = %d\n", __func__, index);
  284. if (index == 0)
  285. cx_clear(MO_GP0_IO, 8);
  286. else
  287. cx_set(MO_GP0_IO, 8);
  288. return 0;
  289. }
  290. static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  291. {
  292. struct cx8802_dev *dev= fe->dvb->priv;
  293. if (is_punctured)
  294. dev->ts_gen_cntrl |= 0x04;
  295. else
  296. dev->ts_gen_cntrl &= ~0x04;
  297. return 0;
  298. }
  299. static struct lgdt330x_config fusionhdtv_3_gold = {
  300. .demod_address = 0x0e,
  301. .demod_chip = LGDT3302,
  302. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  303. .set_ts_params = lgdt330x_set_ts_param,
  304. };
  305. static const struct lgdt330x_config fusionhdtv_5_gold = {
  306. .demod_address = 0x0e,
  307. .demod_chip = LGDT3303,
  308. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  309. .set_ts_params = lgdt330x_set_ts_param,
  310. };
  311. static const struct lgdt330x_config pchdtv_hd5500 = {
  312. .demod_address = 0x59,
  313. .demod_chip = LGDT3303,
  314. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  315. .set_ts_params = lgdt330x_set_ts_param,
  316. };
  317. static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  318. {
  319. struct cx8802_dev *dev= fe->dvb->priv;
  320. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  321. return 0;
  322. }
  323. static const struct nxt200x_config ati_hdtvwonder = {
  324. .demod_address = 0x0a,
  325. .set_ts_params = nxt200x_set_ts_param,
  326. };
  327. static int cx24123_set_ts_param(struct dvb_frontend* fe,
  328. int is_punctured)
  329. {
  330. struct cx8802_dev *dev= fe->dvb->priv;
  331. dev->ts_gen_cntrl = 0x02;
  332. return 0;
  333. }
  334. static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
  335. fe_sec_voltage_t voltage)
  336. {
  337. struct cx8802_dev *dev= fe->dvb->priv;
  338. struct cx88_core *core = dev->core;
  339. if (voltage == SEC_VOLTAGE_OFF)
  340. cx_write(MO_GP0_IO, 0x000006fb);
  341. else
  342. cx_write(MO_GP0_IO, 0x000006f9);
  343. if (core->prev_set_voltage)
  344. return core->prev_set_voltage(fe, voltage);
  345. return 0;
  346. }
  347. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  348. fe_sec_voltage_t voltage)
  349. {
  350. struct cx8802_dev *dev= fe->dvb->priv;
  351. struct cx88_core *core = dev->core;
  352. if (voltage == SEC_VOLTAGE_OFF) {
  353. dprintk(1,"LNB Voltage OFF\n");
  354. cx_write(MO_GP0_IO, 0x0000efff);
  355. }
  356. if (core->prev_set_voltage)
  357. return core->prev_set_voltage(fe, voltage);
  358. return 0;
  359. }
  360. static int tevii_dvbs_set_voltage(struct dvb_frontend *fe,
  361. fe_sec_voltage_t voltage)
  362. {
  363. struct cx8802_dev *dev= fe->dvb->priv;
  364. struct cx88_core *core = dev->core;
  365. cx_set(MO_GP0_IO, 0x6040);
  366. switch (voltage) {
  367. case SEC_VOLTAGE_13:
  368. cx_clear(MO_GP0_IO, 0x20);
  369. break;
  370. case SEC_VOLTAGE_18:
  371. cx_set(MO_GP0_IO, 0x20);
  372. break;
  373. case SEC_VOLTAGE_OFF:
  374. cx_clear(MO_GP0_IO, 0x20);
  375. break;
  376. }
  377. if (core->prev_set_voltage)
  378. return core->prev_set_voltage(fe, voltage);
  379. return 0;
  380. }
  381. static int vp1027_set_voltage(struct dvb_frontend *fe,
  382. fe_sec_voltage_t voltage)
  383. {
  384. struct cx8802_dev *dev = fe->dvb->priv;
  385. struct cx88_core *core = dev->core;
  386. switch (voltage) {
  387. case SEC_VOLTAGE_13:
  388. dprintk(1, "LNB SEC Voltage=13\n");
  389. cx_write(MO_GP0_IO, 0x00001220);
  390. break;
  391. case SEC_VOLTAGE_18:
  392. dprintk(1, "LNB SEC Voltage=18\n");
  393. cx_write(MO_GP0_IO, 0x00001222);
  394. break;
  395. case SEC_VOLTAGE_OFF:
  396. dprintk(1, "LNB Voltage OFF\n");
  397. cx_write(MO_GP0_IO, 0x00001230);
  398. break;
  399. }
  400. if (core->prev_set_voltage)
  401. return core->prev_set_voltage(fe, voltage);
  402. return 0;
  403. }
  404. static const struct cx24123_config geniatech_dvbs_config = {
  405. .demod_address = 0x55,
  406. .set_ts_params = cx24123_set_ts_param,
  407. };
  408. static const struct cx24123_config hauppauge_novas_config = {
  409. .demod_address = 0x55,
  410. .set_ts_params = cx24123_set_ts_param,
  411. };
  412. static const struct cx24123_config kworld_dvbs_100_config = {
  413. .demod_address = 0x15,
  414. .set_ts_params = cx24123_set_ts_param,
  415. .lnb_polarity = 1,
  416. };
  417. static const struct s5h1409_config pinnacle_pctv_hd_800i_config = {
  418. .demod_address = 0x32 >> 1,
  419. .output_mode = S5H1409_PARALLEL_OUTPUT,
  420. .gpio = S5H1409_GPIO_ON,
  421. .qam_if = 44000,
  422. .inversion = S5H1409_INVERSION_OFF,
  423. .status_mode = S5H1409_DEMODLOCKING,
  424. .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
  425. };
  426. static const struct s5h1409_config dvico_hdtv5_pci_nano_config = {
  427. .demod_address = 0x32 >> 1,
  428. .output_mode = S5H1409_SERIAL_OUTPUT,
  429. .gpio = S5H1409_GPIO_OFF,
  430. .inversion = S5H1409_INVERSION_OFF,
  431. .status_mode = S5H1409_DEMODLOCKING,
  432. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  433. };
  434. static const struct s5h1409_config kworld_atsc_120_config = {
  435. .demod_address = 0x32 >> 1,
  436. .output_mode = S5H1409_SERIAL_OUTPUT,
  437. .gpio = S5H1409_GPIO_OFF,
  438. .inversion = S5H1409_INVERSION_OFF,
  439. .status_mode = S5H1409_DEMODLOCKING,
  440. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  441. };
  442. static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
  443. .i2c_address = 0x64,
  444. .if_khz = 5380,
  445. };
  446. static const struct zl10353_config cx88_pinnacle_hybrid_pctv = {
  447. .demod_address = (0x1e >> 1),
  448. .no_tuner = 1,
  449. .if2 = 45600,
  450. };
  451. static const struct zl10353_config cx88_geniatech_x8000_mt = {
  452. .demod_address = (0x1e >> 1),
  453. .no_tuner = 1,
  454. .disable_i2c_gate_ctrl = 1,
  455. };
  456. static const struct s5h1411_config dvico_fusionhdtv7_config = {
  457. .output_mode = S5H1411_SERIAL_OUTPUT,
  458. .gpio = S5H1411_GPIO_ON,
  459. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  460. .qam_if = S5H1411_IF_44000,
  461. .vsb_if = S5H1411_IF_44000,
  462. .inversion = S5H1411_INVERSION_OFF,
  463. .status_mode = S5H1411_DEMODLOCKING
  464. };
  465. static const struct xc5000_config dvico_fusionhdtv7_tuner_config = {
  466. .i2c_address = 0xc2 >> 1,
  467. .if_khz = 5380,
  468. };
  469. static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
  470. {
  471. struct dvb_frontend *fe;
  472. struct videobuf_dvb_frontend *fe0 = NULL;
  473. struct xc2028_ctrl ctl;
  474. struct xc2028_config cfg = {
  475. .i2c_adap = &dev->core->i2c_adap,
  476. .i2c_addr = addr,
  477. .ctrl = &ctl,
  478. };
  479. /* Get the first frontend */
  480. fe0 = videobuf_dvb_get_frontend(&dev->frontends, 1);
  481. if (!fe0)
  482. return -EINVAL;
  483. if (!fe0->dvb.frontend) {
  484. printk(KERN_ERR "%s/2: dvb frontend not attached. "
  485. "Can't attach xc3028\n",
  486. dev->core->name);
  487. return -EINVAL;
  488. }
  489. /*
  490. * Some xc3028 devices may be hidden by an I2C gate. This is known
  491. * to happen with some s5h1409-based devices.
  492. * Now that I2C gate is open, sets up xc3028 configuration
  493. */
  494. cx88_setup_xc3028(dev->core, &ctl);
  495. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
  496. if (!fe) {
  497. printk(KERN_ERR "%s/2: xc3028 attach failed\n",
  498. dev->core->name);
  499. dvb_frontend_detach(fe0->dvb.frontend);
  500. dvb_unregister_frontend(fe0->dvb.frontend);
  501. fe0->dvb.frontend = NULL;
  502. return -EINVAL;
  503. }
  504. printk(KERN_INFO "%s/2: xc3028 attached\n",
  505. dev->core->name);
  506. return 0;
  507. }
  508. static int cx24116_set_ts_param(struct dvb_frontend *fe,
  509. int is_punctured)
  510. {
  511. struct cx8802_dev *dev = fe->dvb->priv;
  512. dev->ts_gen_cntrl = 0x2;
  513. return 0;
  514. }
  515. static int stv0900_set_ts_param(struct dvb_frontend *fe,
  516. int is_punctured)
  517. {
  518. struct cx8802_dev *dev = fe->dvb->priv;
  519. dev->ts_gen_cntrl = 0;
  520. return 0;
  521. }
  522. static int cx24116_reset_device(struct dvb_frontend *fe)
  523. {
  524. struct cx8802_dev *dev = fe->dvb->priv;
  525. struct cx88_core *core = dev->core;
  526. /* Reset the part */
  527. /* Put the cx24116 into reset */
  528. cx_write(MO_SRST_IO, 0);
  529. msleep(10);
  530. /* Take the cx24116 out of reset */
  531. cx_write(MO_SRST_IO, 1);
  532. msleep(10);
  533. return 0;
  534. }
  535. static const struct cx24116_config hauppauge_hvr4000_config = {
  536. .demod_address = 0x05,
  537. .set_ts_params = cx24116_set_ts_param,
  538. .reset_device = cx24116_reset_device,
  539. };
  540. static const struct cx24116_config tevii_s460_config = {
  541. .demod_address = 0x55,
  542. .set_ts_params = cx24116_set_ts_param,
  543. .reset_device = cx24116_reset_device,
  544. };
  545. static const struct stv0900_config prof_7301_stv0900_config = {
  546. .demod_address = 0x6a,
  547. /* demod_mode = 0,*/
  548. .xtal = 27000000,
  549. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  550. .diseqc_mode = 2,/* 2/3 PWM */
  551. .tun1_maddress = 0,/* 0x60 */
  552. .tun1_adc = 0,/* 2 Vpp */
  553. .path1_mode = 3,
  554. .set_ts_params = stv0900_set_ts_param,
  555. };
  556. static const struct stb6100_config prof_7301_stb6100_config = {
  557. .tuner_address = 0x60,
  558. .refclock = 27000000,
  559. };
  560. static const struct stv0299_config tevii_tuner_sharp_config = {
  561. .demod_address = 0x68,
  562. .inittab = sharp_z0194a_inittab,
  563. .mclk = 88000000UL,
  564. .invert = 1,
  565. .skip_reinit = 0,
  566. .lock_output = 1,
  567. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  568. .min_delay_ms = 100,
  569. .set_symbol_rate = sharp_z0194a_set_symbol_rate,
  570. .set_ts_params = cx24116_set_ts_param,
  571. };
  572. static const struct stv0288_config tevii_tuner_earda_config = {
  573. .demod_address = 0x68,
  574. .min_delay_ms = 100,
  575. .set_ts_params = cx24116_set_ts_param,
  576. };
  577. static int cx8802_alloc_frontends(struct cx8802_dev *dev)
  578. {
  579. struct cx88_core *core = dev->core;
  580. struct videobuf_dvb_frontend *fe = NULL;
  581. int i;
  582. mutex_init(&dev->frontends.lock);
  583. INIT_LIST_HEAD(&dev->frontends.felist);
  584. if (!core->board.num_frontends)
  585. return -ENODEV;
  586. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  587. core->board.num_frontends);
  588. for (i = 1; i <= core->board.num_frontends; i++) {
  589. fe = videobuf_dvb_alloc_frontend(&dev->frontends, i);
  590. if (!fe) {
  591. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  592. videobuf_dvb_dealloc_frontends(&dev->frontends);
  593. return -ENOMEM;
  594. }
  595. }
  596. return 0;
  597. }
  598. static const u8 samsung_smt_7020_inittab[] = {
  599. 0x01, 0x15,
  600. 0x02, 0x00,
  601. 0x03, 0x00,
  602. 0x04, 0x7D,
  603. 0x05, 0x0F,
  604. 0x06, 0x02,
  605. 0x07, 0x00,
  606. 0x08, 0x60,
  607. 0x0A, 0xC2,
  608. 0x0B, 0x00,
  609. 0x0C, 0x01,
  610. 0x0D, 0x81,
  611. 0x0E, 0x44,
  612. 0x0F, 0x09,
  613. 0x10, 0x3C,
  614. 0x11, 0x84,
  615. 0x12, 0xDA,
  616. 0x13, 0x99,
  617. 0x14, 0x8D,
  618. 0x15, 0xCE,
  619. 0x16, 0xE8,
  620. 0x17, 0x43,
  621. 0x18, 0x1C,
  622. 0x19, 0x1B,
  623. 0x1A, 0x1D,
  624. 0x1C, 0x12,
  625. 0x1D, 0x00,
  626. 0x1E, 0x00,
  627. 0x1F, 0x00,
  628. 0x20, 0x00,
  629. 0x21, 0x00,
  630. 0x22, 0x00,
  631. 0x23, 0x00,
  632. 0x28, 0x02,
  633. 0x29, 0x28,
  634. 0x2A, 0x14,
  635. 0x2B, 0x0F,
  636. 0x2C, 0x09,
  637. 0x2D, 0x05,
  638. 0x31, 0x1F,
  639. 0x32, 0x19,
  640. 0x33, 0xFC,
  641. 0x34, 0x13,
  642. 0xff, 0xff,
  643. };
  644. static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe,
  645. struct dvb_frontend_parameters *params)
  646. {
  647. struct cx8802_dev *dev = fe->dvb->priv;
  648. u8 buf[4];
  649. u32 div;
  650. struct i2c_msg msg = {
  651. .addr = 0x61,
  652. .flags = 0,
  653. .buf = buf,
  654. .len = sizeof(buf) };
  655. div = params->frequency / 125;
  656. buf[0] = (div >> 8) & 0x7f;
  657. buf[1] = div & 0xff;
  658. buf[2] = 0x84; /* 0xC4 */
  659. buf[3] = 0x00;
  660. if (params->frequency < 1500000)
  661. buf[3] |= 0x10;
  662. if (fe->ops.i2c_gate_ctrl)
  663. fe->ops.i2c_gate_ctrl(fe, 1);
  664. if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1)
  665. return -EIO;
  666. return 0;
  667. }
  668. static int samsung_smt_7020_set_tone(struct dvb_frontend *fe,
  669. fe_sec_tone_mode_t tone)
  670. {
  671. struct cx8802_dev *dev = fe->dvb->priv;
  672. struct cx88_core *core = dev->core;
  673. cx_set(MO_GP0_IO, 0x0800);
  674. switch (tone) {
  675. case SEC_TONE_ON:
  676. cx_set(MO_GP0_IO, 0x08);
  677. break;
  678. case SEC_TONE_OFF:
  679. cx_clear(MO_GP0_IO, 0x08);
  680. break;
  681. default:
  682. return -EINVAL;
  683. }
  684. return 0;
  685. }
  686. static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
  687. fe_sec_voltage_t voltage)
  688. {
  689. struct cx8802_dev *dev = fe->dvb->priv;
  690. struct cx88_core *core = dev->core;
  691. u8 data;
  692. struct i2c_msg msg = {
  693. .addr = 8,
  694. .flags = 0,
  695. .buf = &data,
  696. .len = sizeof(data) };
  697. cx_set(MO_GP0_IO, 0x8000);
  698. switch (voltage) {
  699. case SEC_VOLTAGE_OFF:
  700. break;
  701. case SEC_VOLTAGE_13:
  702. data = ISL6421_EN1 | ISL6421_LLC1;
  703. cx_clear(MO_GP0_IO, 0x80);
  704. break;
  705. case SEC_VOLTAGE_18:
  706. data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1;
  707. cx_clear(MO_GP0_IO, 0x80);
  708. break;
  709. default:
  710. return -EINVAL;
  711. };
  712. return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
  713. }
  714. static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe,
  715. u32 srate, u32 ratio)
  716. {
  717. u8 aclk = 0;
  718. u8 bclk = 0;
  719. if (srate < 1500000) {
  720. aclk = 0xb7;
  721. bclk = 0x47;
  722. } else if (srate < 3000000) {
  723. aclk = 0xb7;
  724. bclk = 0x4b;
  725. } else if (srate < 7000000) {
  726. aclk = 0xb7;
  727. bclk = 0x4f;
  728. } else if (srate < 14000000) {
  729. aclk = 0xb7;
  730. bclk = 0x53;
  731. } else if (srate < 30000000) {
  732. aclk = 0xb6;
  733. bclk = 0x53;
  734. } else if (srate < 45000000) {
  735. aclk = 0xb4;
  736. bclk = 0x51;
  737. }
  738. stv0299_writereg(fe, 0x13, aclk);
  739. stv0299_writereg(fe, 0x14, bclk);
  740. stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
  741. stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
  742. stv0299_writereg(fe, 0x21, ratio & 0xf0);
  743. return 0;
  744. }
  745. static const struct stv0299_config samsung_stv0299_config = {
  746. .demod_address = 0x68,
  747. .inittab = samsung_smt_7020_inittab,
  748. .mclk = 88000000UL,
  749. .invert = 0,
  750. .skip_reinit = 0,
  751. .lock_output = STV0299_LOCKOUTPUT_LK,
  752. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  753. .min_delay_ms = 100,
  754. .set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate,
  755. };
  756. static int dvb_register(struct cx8802_dev *dev)
  757. {
  758. struct cx88_core *core = dev->core;
  759. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  760. int mfe_shared = 0; /* bus not shared by default */
  761. if (0 != core->i2c_rc) {
  762. printk(KERN_ERR "%s/2: no i2c-bus available, cannot attach dvb drivers\n", core->name);
  763. goto frontend_detach;
  764. }
  765. /* Get the first frontend */
  766. fe0 = videobuf_dvb_get_frontend(&dev->frontends, 1);
  767. if (!fe0)
  768. goto frontend_detach;
  769. /* multi-frontend gate control is undefined or defaults to fe0 */
  770. dev->frontends.gate = 0;
  771. /* Sets the gate control callback to be used by i2c command calls */
  772. core->gate_ctrl = cx88_dvb_gate_ctrl;
  773. /* init frontend(s) */
  774. switch (core->boardnr) {
  775. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  776. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  777. &connexant_refboard_config,
  778. &core->i2c_adap);
  779. if (fe0->dvb.frontend != NULL) {
  780. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  781. 0x61, &core->i2c_adap,
  782. DVB_PLL_THOMSON_DTT759X))
  783. goto frontend_detach;
  784. }
  785. break;
  786. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  787. case CX88_BOARD_CONEXANT_DVB_T1:
  788. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  789. case CX88_BOARD_WINFAST_DTV1000:
  790. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  791. &connexant_refboard_config,
  792. &core->i2c_adap);
  793. if (fe0->dvb.frontend != NULL) {
  794. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  795. 0x60, &core->i2c_adap,
  796. DVB_PLL_THOMSON_DTT7579))
  797. goto frontend_detach;
  798. }
  799. break;
  800. case CX88_BOARD_WINFAST_DTV2000H:
  801. case CX88_BOARD_WINFAST_DTV2000H_J:
  802. case CX88_BOARD_HAUPPAUGE_HVR1100:
  803. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  804. case CX88_BOARD_HAUPPAUGE_HVR1300:
  805. fe0->dvb.frontend = dvb_attach(cx22702_attach,
  806. &hauppauge_hvr_config,
  807. &core->i2c_adap);
  808. if (fe0->dvb.frontend != NULL) {
  809. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  810. &core->i2c_adap, 0x61,
  811. TUNER_PHILIPS_FMD1216ME_MK3))
  812. goto frontend_detach;
  813. }
  814. break;
  815. case CX88_BOARD_HAUPPAUGE_HVR3000:
  816. /* MFE frontend 1 */
  817. mfe_shared = 1;
  818. dev->frontends.gate = 2;
  819. /* DVB-S init */
  820. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  821. &hauppauge_novas_config,
  822. &dev->core->i2c_adap);
  823. if (fe0->dvb.frontend) {
  824. if (!dvb_attach(isl6421_attach,
  825. fe0->dvb.frontend,
  826. &dev->core->i2c_adap,
  827. 0x08, ISL6421_DCL, 0x00))
  828. goto frontend_detach;
  829. }
  830. /* MFE frontend 2 */
  831. fe1 = videobuf_dvb_get_frontend(&dev->frontends, 2);
  832. if (!fe1)
  833. goto frontend_detach;
  834. /* DVB-T init */
  835. fe1->dvb.frontend = dvb_attach(cx22702_attach,
  836. &hauppauge_hvr_config,
  837. &dev->core->i2c_adap);
  838. if (fe1->dvb.frontend) {
  839. fe1->dvb.frontend->id = 1;
  840. if (!dvb_attach(simple_tuner_attach,
  841. fe1->dvb.frontend,
  842. &dev->core->i2c_adap,
  843. 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
  844. goto frontend_detach;
  845. }
  846. break;
  847. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  848. fe0->dvb.frontend = dvb_attach(mt352_attach,
  849. &dvico_fusionhdtv,
  850. &core->i2c_adap);
  851. if (fe0->dvb.frontend != NULL) {
  852. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  853. 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
  854. goto frontend_detach;
  855. break;
  856. }
  857. /* ZL10353 replaces MT352 on later cards */
  858. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  859. &dvico_fusionhdtv_plus_v1_1,
  860. &core->i2c_adap);
  861. if (fe0->dvb.frontend != NULL) {
  862. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  863. 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
  864. goto frontend_detach;
  865. }
  866. break;
  867. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  868. /* The tin box says DEE1601, but it seems to be DTT7579
  869. * compatible, with a slightly different MT352 AGC gain. */
  870. fe0->dvb.frontend = dvb_attach(mt352_attach,
  871. &dvico_fusionhdtv_dual,
  872. &core->i2c_adap);
  873. if (fe0->dvb.frontend != NULL) {
  874. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  875. 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
  876. goto frontend_detach;
  877. break;
  878. }
  879. /* ZL10353 replaces MT352 on later cards */
  880. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  881. &dvico_fusionhdtv_plus_v1_1,
  882. &core->i2c_adap);
  883. if (fe0->dvb.frontend != NULL) {
  884. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  885. 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
  886. goto frontend_detach;
  887. }
  888. break;
  889. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  890. fe0->dvb.frontend = dvb_attach(mt352_attach,
  891. &dvico_fusionhdtv,
  892. &core->i2c_adap);
  893. if (fe0->dvb.frontend != NULL) {
  894. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  895. 0x61, NULL, DVB_PLL_LG_Z201))
  896. goto frontend_detach;
  897. }
  898. break;
  899. case CX88_BOARD_KWORLD_DVB_T:
  900. case CX88_BOARD_DNTV_LIVE_DVB_T:
  901. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  902. fe0->dvb.frontend = dvb_attach(mt352_attach,
  903. &dntv_live_dvbt_config,
  904. &core->i2c_adap);
  905. if (fe0->dvb.frontend != NULL) {
  906. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
  907. 0x61, NULL, DVB_PLL_UNKNOWN_1))
  908. goto frontend_detach;
  909. }
  910. break;
  911. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  912. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  913. /* MT352 is on a secondary I2C bus made from some GPIO lines */
  914. fe0->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
  915. &dev->vp3054->adap);
  916. if (fe0->dvb.frontend != NULL) {
  917. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  918. &core->i2c_adap, 0x61,
  919. TUNER_PHILIPS_FMD1216ME_MK3))
  920. goto frontend_detach;
  921. }
  922. #else
  923. printk(KERN_ERR "%s/2: built without vp3054 support\n",
  924. core->name);
  925. #endif
  926. break;
  927. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  928. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  929. &dvico_fusionhdtv_hybrid,
  930. &core->i2c_adap);
  931. if (fe0->dvb.frontend != NULL) {
  932. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  933. &core->i2c_adap, 0x61,
  934. TUNER_THOMSON_FE6600))
  935. goto frontend_detach;
  936. }
  937. break;
  938. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
  939. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  940. &dvico_fusionhdtv_xc3028,
  941. &core->i2c_adap);
  942. if (fe0->dvb.frontend == NULL)
  943. fe0->dvb.frontend = dvb_attach(mt352_attach,
  944. &dvico_fusionhdtv_mt352_xc3028,
  945. &core->i2c_adap);
  946. /*
  947. * On this board, the demod provides the I2C bus pullup.
  948. * We must not permit gate_ctrl to be performed, or
  949. * the xc3028 cannot communicate on the bus.
  950. */
  951. if (fe0->dvb.frontend)
  952. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  953. if (attach_xc3028(0x61, dev) < 0)
  954. goto frontend_detach;
  955. break;
  956. case CX88_BOARD_PCHDTV_HD3000:
  957. fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  958. &core->i2c_adap);
  959. if (fe0->dvb.frontend != NULL) {
  960. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  961. &core->i2c_adap, 0x61,
  962. TUNER_THOMSON_DTT761X))
  963. goto frontend_detach;
  964. }
  965. break;
  966. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  967. dev->ts_gen_cntrl = 0x08;
  968. /* Do a hardware reset of chip before using it. */
  969. cx_clear(MO_GP0_IO, 1);
  970. mdelay(100);
  971. cx_set(MO_GP0_IO, 1);
  972. mdelay(200);
  973. /* Select RF connector callback */
  974. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  975. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  976. &fusionhdtv_3_gold,
  977. &core->i2c_adap);
  978. if (fe0->dvb.frontend != NULL) {
  979. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  980. &core->i2c_adap, 0x61,
  981. TUNER_MICROTUNE_4042FI5))
  982. goto frontend_detach;
  983. }
  984. break;
  985. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  986. dev->ts_gen_cntrl = 0x08;
  987. /* Do a hardware reset of chip before using it. */
  988. cx_clear(MO_GP0_IO, 1);
  989. mdelay(100);
  990. cx_set(MO_GP0_IO, 9);
  991. mdelay(200);
  992. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  993. &fusionhdtv_3_gold,
  994. &core->i2c_adap);
  995. if (fe0->dvb.frontend != NULL) {
  996. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  997. &core->i2c_adap, 0x61,
  998. TUNER_THOMSON_DTT761X))
  999. goto frontend_detach;
  1000. }
  1001. break;
  1002. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  1003. dev->ts_gen_cntrl = 0x08;
  1004. /* Do a hardware reset of chip before using it. */
  1005. cx_clear(MO_GP0_IO, 1);
  1006. mdelay(100);
  1007. cx_set(MO_GP0_IO, 1);
  1008. mdelay(200);
  1009. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  1010. &fusionhdtv_5_gold,
  1011. &core->i2c_adap);
  1012. if (fe0->dvb.frontend != NULL) {
  1013. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1014. &core->i2c_adap, 0x61,
  1015. TUNER_LG_TDVS_H06XF))
  1016. goto frontend_detach;
  1017. if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
  1018. &core->i2c_adap, 0x43))
  1019. goto frontend_detach;
  1020. }
  1021. break;
  1022. case CX88_BOARD_PCHDTV_HD5500:
  1023. dev->ts_gen_cntrl = 0x08;
  1024. /* Do a hardware reset of chip before using it. */
  1025. cx_clear(MO_GP0_IO, 1);
  1026. mdelay(100);
  1027. cx_set(MO_GP0_IO, 1);
  1028. mdelay(200);
  1029. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  1030. &pchdtv_hd5500,
  1031. &core->i2c_adap);
  1032. if (fe0->dvb.frontend != NULL) {
  1033. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1034. &core->i2c_adap, 0x61,
  1035. TUNER_LG_TDVS_H06XF))
  1036. goto frontend_detach;
  1037. if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
  1038. &core->i2c_adap, 0x43))
  1039. goto frontend_detach;
  1040. }
  1041. break;
  1042. case CX88_BOARD_ATI_HDTVWONDER:
  1043. fe0->dvb.frontend = dvb_attach(nxt200x_attach,
  1044. &ati_hdtvwonder,
  1045. &core->i2c_adap);
  1046. if (fe0->dvb.frontend != NULL) {
  1047. if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  1048. &core->i2c_adap, 0x61,
  1049. TUNER_PHILIPS_TUV1236D))
  1050. goto frontend_detach;
  1051. }
  1052. break;
  1053. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  1054. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  1055. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  1056. &hauppauge_novas_config,
  1057. &core->i2c_adap);
  1058. if (fe0->dvb.frontend) {
  1059. if (!dvb_attach(isl6421_attach, fe0->dvb.frontend,
  1060. &core->i2c_adap, 0x08, ISL6421_DCL, 0x00))
  1061. goto frontend_detach;
  1062. }
  1063. break;
  1064. case CX88_BOARD_KWORLD_DVBS_100:
  1065. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  1066. &kworld_dvbs_100_config,
  1067. &core->i2c_adap);
  1068. if (fe0->dvb.frontend) {
  1069. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1070. fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  1071. }
  1072. break;
  1073. case CX88_BOARD_GENIATECH_DVBS:
  1074. fe0->dvb.frontend = dvb_attach(cx24123_attach,
  1075. &geniatech_dvbs_config,
  1076. &core->i2c_adap);
  1077. if (fe0->dvb.frontend) {
  1078. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1079. fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  1080. }
  1081. break;
  1082. case CX88_BOARD_PINNACLE_PCTV_HD_800i:
  1083. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1084. &pinnacle_pctv_hd_800i_config,
  1085. &core->i2c_adap);
  1086. if (fe0->dvb.frontend != NULL) {
  1087. if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
  1088. &core->i2c_adap,
  1089. &pinnacle_pctv_hd_800i_tuner_config))
  1090. goto frontend_detach;
  1091. }
  1092. break;
  1093. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  1094. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1095. &dvico_hdtv5_pci_nano_config,
  1096. &core->i2c_adap);
  1097. if (fe0->dvb.frontend != NULL) {
  1098. struct dvb_frontend *fe;
  1099. struct xc2028_config cfg = {
  1100. .i2c_adap = &core->i2c_adap,
  1101. .i2c_addr = 0x61,
  1102. };
  1103. static struct xc2028_ctrl ctl = {
  1104. .fname = XC2028_DEFAULT_FIRMWARE,
  1105. .max_len = 64,
  1106. .scode_table = XC3028_FE_OREN538,
  1107. };
  1108. fe = dvb_attach(xc2028_attach,
  1109. fe0->dvb.frontend, &cfg);
  1110. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  1111. fe->ops.tuner_ops.set_config(fe, &ctl);
  1112. }
  1113. break;
  1114. case CX88_BOARD_PINNACLE_HYBRID_PCTV:
  1115. case CX88_BOARD_WINFAST_DTV1800H:
  1116. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1117. &cx88_pinnacle_hybrid_pctv,
  1118. &core->i2c_adap);
  1119. if (fe0->dvb.frontend) {
  1120. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1121. if (attach_xc3028(0x61, dev) < 0)
  1122. goto frontend_detach;
  1123. }
  1124. break;
  1125. case CX88_BOARD_GENIATECH_X8000_MT:
  1126. dev->ts_gen_cntrl = 0x00;
  1127. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1128. &cx88_geniatech_x8000_mt,
  1129. &core->i2c_adap);
  1130. if (attach_xc3028(0x61, dev) < 0)
  1131. goto frontend_detach;
  1132. break;
  1133. case CX88_BOARD_KWORLD_ATSC_120:
  1134. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1135. &kworld_atsc_120_config,
  1136. &core->i2c_adap);
  1137. if (attach_xc3028(0x61, dev) < 0)
  1138. goto frontend_detach;
  1139. break;
  1140. case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
  1141. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1142. &dvico_fusionhdtv7_config,
  1143. &core->i2c_adap);
  1144. if (fe0->dvb.frontend != NULL) {
  1145. if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
  1146. &core->i2c_adap,
  1147. &dvico_fusionhdtv7_tuner_config))
  1148. goto frontend_detach;
  1149. }
  1150. break;
  1151. case CX88_BOARD_HAUPPAUGE_HVR4000:
  1152. /* MFE frontend 1 */
  1153. mfe_shared = 1;
  1154. dev->frontends.gate = 2;
  1155. /* DVB-S/S2 Init */
  1156. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1157. &hauppauge_hvr4000_config,
  1158. &dev->core->i2c_adap);
  1159. if (fe0->dvb.frontend) {
  1160. if (!dvb_attach(isl6421_attach,
  1161. fe0->dvb.frontend,
  1162. &dev->core->i2c_adap,
  1163. 0x08, ISL6421_DCL, 0x00))
  1164. goto frontend_detach;
  1165. }
  1166. /* MFE frontend 2 */
  1167. fe1 = videobuf_dvb_get_frontend(&dev->frontends, 2);
  1168. if (!fe1)
  1169. goto frontend_detach;
  1170. /* DVB-T Init */
  1171. fe1->dvb.frontend = dvb_attach(cx22702_attach,
  1172. &hauppauge_hvr_config,
  1173. &dev->core->i2c_adap);
  1174. if (fe1->dvb.frontend) {
  1175. fe1->dvb.frontend->id = 1;
  1176. if (!dvb_attach(simple_tuner_attach,
  1177. fe1->dvb.frontend,
  1178. &dev->core->i2c_adap,
  1179. 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
  1180. goto frontend_detach;
  1181. }
  1182. break;
  1183. case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
  1184. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1185. &hauppauge_hvr4000_config,
  1186. &dev->core->i2c_adap);
  1187. if (fe0->dvb.frontend) {
  1188. if (!dvb_attach(isl6421_attach,
  1189. fe0->dvb.frontend,
  1190. &dev->core->i2c_adap,
  1191. 0x08, ISL6421_DCL, 0x00))
  1192. goto frontend_detach;
  1193. }
  1194. break;
  1195. case CX88_BOARD_PROF_6200:
  1196. case CX88_BOARD_TBS_8910:
  1197. case CX88_BOARD_TEVII_S420:
  1198. fe0->dvb.frontend = dvb_attach(stv0299_attach,
  1199. &tevii_tuner_sharp_config,
  1200. &core->i2c_adap);
  1201. if (fe0->dvb.frontend != NULL) {
  1202. if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
  1203. &core->i2c_adap, DVB_PLL_OPERA1))
  1204. goto frontend_detach;
  1205. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1206. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1207. } else {
  1208. fe0->dvb.frontend = dvb_attach(stv0288_attach,
  1209. &tevii_tuner_earda_config,
  1210. &core->i2c_adap);
  1211. if (fe0->dvb.frontend != NULL) {
  1212. if (!dvb_attach(stb6000_attach, fe0->dvb.frontend, 0x61,
  1213. &core->i2c_adap))
  1214. goto frontend_detach;
  1215. core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
  1216. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1217. }
  1218. }
  1219. break;
  1220. case CX88_BOARD_TEVII_S460:
  1221. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1222. &tevii_s460_config,
  1223. &core->i2c_adap);
  1224. if (fe0->dvb.frontend != NULL)
  1225. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1226. break;
  1227. case CX88_BOARD_OMICOM_SS4_PCI:
  1228. case CX88_BOARD_TBS_8920:
  1229. case CX88_BOARD_PROF_7300:
  1230. case CX88_BOARD_SATTRADE_ST4200:
  1231. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1232. &hauppauge_hvr4000_config,
  1233. &core->i2c_adap);
  1234. if (fe0->dvb.frontend != NULL)
  1235. fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
  1236. break;
  1237. case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
  1238. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1239. &cx88_terratec_cinergy_ht_pci_mkii_config,
  1240. &core->i2c_adap);
  1241. if (fe0->dvb.frontend) {
  1242. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1243. if (attach_xc3028(0x61, dev) < 0)
  1244. goto frontend_detach;
  1245. }
  1246. break;
  1247. case CX88_BOARD_PROF_7301:{
  1248. struct dvb_tuner_ops *tuner_ops = NULL;
  1249. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  1250. &prof_7301_stv0900_config,
  1251. &core->i2c_adap, 0);
  1252. if (fe0->dvb.frontend != NULL) {
  1253. if (!dvb_attach(stb6100_attach, fe0->dvb.frontend,
  1254. &prof_7301_stb6100_config,
  1255. &core->i2c_adap))
  1256. goto frontend_detach;
  1257. tuner_ops = &fe0->dvb.frontend->ops.tuner_ops;
  1258. tuner_ops->set_frequency = stb6100_set_freq;
  1259. tuner_ops->get_frequency = stb6100_get_freq;
  1260. tuner_ops->set_bandwidth = stb6100_set_bandw;
  1261. tuner_ops->get_bandwidth = stb6100_get_bandw;
  1262. core->prev_set_voltage =
  1263. fe0->dvb.frontend->ops.set_voltage;
  1264. fe0->dvb.frontend->ops.set_voltage =
  1265. tevii_dvbs_set_voltage;
  1266. }
  1267. break;
  1268. }
  1269. case CX88_BOARD_SAMSUNG_SMT_7020:
  1270. dev->ts_gen_cntrl = 0x08;
  1271. cx_set(MO_GP0_IO, 0x0101);
  1272. cx_clear(MO_GP0_IO, 0x01);
  1273. mdelay(100);
  1274. cx_set(MO_GP0_IO, 0x01);
  1275. mdelay(200);
  1276. fe0->dvb.frontend = dvb_attach(stv0299_attach,
  1277. &samsung_stv0299_config,
  1278. &dev->core->i2c_adap);
  1279. if (fe0->dvb.frontend) {
  1280. fe0->dvb.frontend->ops.tuner_ops.set_params =
  1281. samsung_smt_7020_tuner_set_params;
  1282. fe0->dvb.frontend->tuner_priv =
  1283. &dev->core->i2c_adap;
  1284. fe0->dvb.frontend->ops.set_voltage =
  1285. samsung_smt_7020_set_voltage;
  1286. fe0->dvb.frontend->ops.set_tone =
  1287. samsung_smt_7020_set_tone;
  1288. }
  1289. break;
  1290. case CX88_BOARD_TWINHAN_VP1027_DVBS:
  1291. dev->ts_gen_cntrl = 0x00;
  1292. fe0->dvb.frontend = dvb_attach(mb86a16_attach,
  1293. &twinhan_vp1027,
  1294. &core->i2c_adap);
  1295. if (fe0->dvb.frontend) {
  1296. core->prev_set_voltage =
  1297. fe0->dvb.frontend->ops.set_voltage;
  1298. fe0->dvb.frontend->ops.set_voltage =
  1299. vp1027_set_voltage;
  1300. }
  1301. break;
  1302. default:
  1303. printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
  1304. core->name);
  1305. break;
  1306. }
  1307. if ( (NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend) ) {
  1308. printk(KERN_ERR
  1309. "%s/2: frontend initialization failed\n",
  1310. core->name);
  1311. goto frontend_detach;
  1312. }
  1313. /* define general-purpose callback pointer */
  1314. fe0->dvb.frontend->callback = cx88_tuner_callback;
  1315. /* Ensure all frontends negotiate bus access */
  1316. fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  1317. if (fe1)
  1318. fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  1319. /* Put the analog decoder in standby to keep it quiet */
  1320. call_all(core, core, s_power, 0);
  1321. /* register everything */
  1322. return videobuf_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
  1323. &dev->pci->dev, adapter_nr, mfe_shared, NULL);
  1324. frontend_detach:
  1325. core->gate_ctrl = NULL;
  1326. videobuf_dvb_dealloc_frontends(&dev->frontends);
  1327. return -EINVAL;
  1328. }
  1329. /* ----------------------------------------------------------- */
  1330. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  1331. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  1332. {
  1333. struct cx88_core *core = drv->core;
  1334. int err = 0;
  1335. dprintk( 1, "%s\n", __func__);
  1336. switch (core->boardnr) {
  1337. case CX88_BOARD_HAUPPAUGE_HVR1300:
  1338. /* We arrive here with either the cx23416 or the cx22702
  1339. * on the bus. Take the bus from the cx23416 and enable the
  1340. * cx22702 demod
  1341. */
  1342. /* Toggle reset on cx22702 leaving i2c active */
  1343. cx_set(MO_GP0_IO, 0x00000080);
  1344. udelay(1000);
  1345. cx_clear(MO_GP0_IO, 0x00000080);
  1346. udelay(50);
  1347. cx_set(MO_GP0_IO, 0x00000080);
  1348. udelay(1000);
  1349. /* enable the cx22702 pins */
  1350. cx_clear(MO_GP0_IO, 0x00000004);
  1351. udelay(1000);
  1352. break;
  1353. case CX88_BOARD_HAUPPAUGE_HVR3000:
  1354. case CX88_BOARD_HAUPPAUGE_HVR4000:
  1355. /* Toggle reset on cx22702 leaving i2c active */
  1356. cx_set(MO_GP0_IO, 0x00000080);
  1357. udelay(1000);
  1358. cx_clear(MO_GP0_IO, 0x00000080);
  1359. udelay(50);
  1360. cx_set(MO_GP0_IO, 0x00000080);
  1361. udelay(1000);
  1362. switch (core->dvbdev->frontends.active_fe_id) {
  1363. case 1: /* DVB-S/S2 Enabled */
  1364. /* tri-state the cx22702 pins */
  1365. cx_set(MO_GP0_IO, 0x00000004);
  1366. /* Take the cx24116/cx24123 out of reset */
  1367. cx_write(MO_SRST_IO, 1);
  1368. core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */
  1369. break;
  1370. case 2: /* DVB-T Enabled */
  1371. /* Put the cx24116/cx24123 into reset */
  1372. cx_write(MO_SRST_IO, 0);
  1373. /* enable the cx22702 pins */
  1374. cx_clear(MO_GP0_IO, 0x00000004);
  1375. core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */
  1376. break;
  1377. }
  1378. udelay(1000);
  1379. break;
  1380. default:
  1381. err = -ENODEV;
  1382. }
  1383. return err;
  1384. }
  1385. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  1386. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  1387. {
  1388. struct cx88_core *core = drv->core;
  1389. int err = 0;
  1390. dprintk( 1, "%s\n", __func__);
  1391. switch (core->boardnr) {
  1392. case CX88_BOARD_HAUPPAUGE_HVR1300:
  1393. /* Do Nothing, leave the cx22702 on the bus. */
  1394. break;
  1395. case CX88_BOARD_HAUPPAUGE_HVR3000:
  1396. case CX88_BOARD_HAUPPAUGE_HVR4000:
  1397. break;
  1398. default:
  1399. err = -ENODEV;
  1400. }
  1401. return err;
  1402. }
  1403. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  1404. {
  1405. struct cx88_core *core = drv->core;
  1406. struct cx8802_dev *dev = drv->core->dvbdev;
  1407. int err;
  1408. struct videobuf_dvb_frontend *fe;
  1409. int i;
  1410. dprintk( 1, "%s\n", __func__);
  1411. dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1412. core->boardnr,
  1413. core->name,
  1414. core->pci_bus,
  1415. core->pci_slot);
  1416. err = -ENODEV;
  1417. if (!(core->board.mpeg & CX88_MPEG_DVB))
  1418. goto fail_core;
  1419. /* If vp3054 isn't enabled, a stub will just return 0 */
  1420. err = vp3054_i2c_probe(dev);
  1421. if (0 != err)
  1422. goto fail_core;
  1423. /* dvb stuff */
  1424. printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
  1425. dev->ts_gen_cntrl = 0x0c;
  1426. err = cx8802_alloc_frontends(dev);
  1427. if (err)
  1428. goto fail_core;
  1429. err = -ENODEV;
  1430. for (i = 1; i <= core->board.num_frontends; i++) {
  1431. fe = videobuf_dvb_get_frontend(&core->dvbdev->frontends, i);
  1432. if (fe == NULL) {
  1433. printk(KERN_ERR "%s() failed to get frontend(%d)\n",
  1434. __func__, i);
  1435. goto fail_probe;
  1436. }
  1437. videobuf_queue_sg_init(&fe->dvb.dvbq, &dvb_qops,
  1438. &dev->pci->dev, &dev->slock,
  1439. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  1440. V4L2_FIELD_TOP,
  1441. sizeof(struct cx88_buffer),
  1442. dev, NULL);
  1443. /* init struct videobuf_dvb */
  1444. fe->dvb.name = dev->core->name;
  1445. }
  1446. err = dvb_register(dev);
  1447. if (err)
  1448. /* frontends/adapter de-allocated in dvb_register */
  1449. printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
  1450. core->name, err);
  1451. return err;
  1452. fail_probe:
  1453. videobuf_dvb_dealloc_frontends(&core->dvbdev->frontends);
  1454. fail_core:
  1455. return err;
  1456. }
  1457. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  1458. {
  1459. struct cx88_core *core = drv->core;
  1460. struct cx8802_dev *dev = drv->core->dvbdev;
  1461. dprintk( 1, "%s\n", __func__);
  1462. videobuf_dvb_unregister_bus(&dev->frontends);
  1463. vp3054_i2c_remove(dev);
  1464. core->gate_ctrl = NULL;
  1465. return 0;
  1466. }
  1467. static struct cx8802_driver cx8802_dvb_driver = {
  1468. .type_id = CX88_MPEG_DVB,
  1469. .hw_access = CX8802_DRVCTL_SHARED,
  1470. .probe = cx8802_dvb_probe,
  1471. .remove = cx8802_dvb_remove,
  1472. .advise_acquire = cx8802_dvb_advise_acquire,
  1473. .advise_release = cx8802_dvb_advise_release,
  1474. };
  1475. static int __init dvb_init(void)
  1476. {
  1477. printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n",
  1478. (CX88_VERSION_CODE >> 16) & 0xff,
  1479. (CX88_VERSION_CODE >> 8) & 0xff,
  1480. CX88_VERSION_CODE & 0xff);
  1481. #ifdef SNAPSHOT
  1482. printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
  1483. SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
  1484. #endif
  1485. return cx8802_register_driver(&cx8802_dvb_driver);
  1486. }
  1487. static void __exit dvb_fini(void)
  1488. {
  1489. cx8802_unregister_driver(&cx8802_dvb_driver);
  1490. }
  1491. module_init(dvb_init);
  1492. module_exit(dvb_fini);
  1493. /*
  1494. * Local variables:
  1495. * c-basic-offset: 8
  1496. * compile-command: "make DVB=1"
  1497. * End:
  1498. */