smsc95xx.c 34 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329
  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include "smsc95xx.h"
  32. #define SMSC_CHIPNAME "smsc95xx"
  33. #define SMSC_DRIVER_VERSION "1.0.4"
  34. #define HS_USB_PKT_SIZE (512)
  35. #define FS_USB_PKT_SIZE (64)
  36. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  37. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  38. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  39. #define MAX_SINGLE_PACKET_SIZE (2048)
  40. #define LAN95XX_EEPROM_MAGIC (0x9500)
  41. #define EEPROM_MAC_OFFSET (0x01)
  42. #define DEFAULT_TX_CSUM_ENABLE (true)
  43. #define DEFAULT_RX_CSUM_ENABLE (true)
  44. #define SMSC95XX_INTERNAL_PHY_ID (1)
  45. #define SMSC95XX_TX_OVERHEAD (8)
  46. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  47. struct smsc95xx_priv {
  48. u32 mac_cr;
  49. u32 hash_hi;
  50. u32 hash_lo;
  51. spinlock_t mac_cr_lock;
  52. };
  53. struct usb_context {
  54. struct usb_ctrlrequest req;
  55. struct usbnet *dev;
  56. };
  57. static bool turbo_mode = true;
  58. module_param(turbo_mode, bool, 0644);
  59. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  60. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  61. {
  62. u32 *buf = kmalloc(4, GFP_KERNEL);
  63. int ret;
  64. BUG_ON(!dev);
  65. if (!buf)
  66. return -ENOMEM;
  67. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  68. USB_VENDOR_REQUEST_READ_REGISTER,
  69. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  70. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  71. if (unlikely(ret < 0))
  72. netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index);
  73. le32_to_cpus(buf);
  74. *data = *buf;
  75. kfree(buf);
  76. return ret;
  77. }
  78. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  79. {
  80. u32 *buf = kmalloc(4, GFP_KERNEL);
  81. int ret;
  82. BUG_ON(!dev);
  83. if (!buf)
  84. return -ENOMEM;
  85. *buf = data;
  86. cpu_to_le32s(buf);
  87. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  88. USB_VENDOR_REQUEST_WRITE_REGISTER,
  89. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  90. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  91. if (unlikely(ret < 0))
  92. netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
  93. kfree(buf);
  94. return ret;
  95. }
  96. /* Loop until the read is completed with timeout
  97. * called with phy_mutex held */
  98. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  99. {
  100. unsigned long start_time = jiffies;
  101. u32 val;
  102. do {
  103. smsc95xx_read_reg(dev, MII_ADDR, &val);
  104. if (!(val & MII_BUSY_))
  105. return 0;
  106. } while (!time_after(jiffies, start_time + HZ));
  107. return -EIO;
  108. }
  109. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  110. {
  111. struct usbnet *dev = netdev_priv(netdev);
  112. u32 val, addr;
  113. mutex_lock(&dev->phy_mutex);
  114. /* confirm MII not busy */
  115. if (smsc95xx_phy_wait_not_busy(dev)) {
  116. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  117. mutex_unlock(&dev->phy_mutex);
  118. return -EIO;
  119. }
  120. /* set the address, index & direction (read from PHY) */
  121. phy_id &= dev->mii.phy_id_mask;
  122. idx &= dev->mii.reg_num_mask;
  123. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  124. smsc95xx_write_reg(dev, MII_ADDR, addr);
  125. if (smsc95xx_phy_wait_not_busy(dev)) {
  126. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  127. mutex_unlock(&dev->phy_mutex);
  128. return -EIO;
  129. }
  130. smsc95xx_read_reg(dev, MII_DATA, &val);
  131. mutex_unlock(&dev->phy_mutex);
  132. return (u16)(val & 0xFFFF);
  133. }
  134. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  135. int regval)
  136. {
  137. struct usbnet *dev = netdev_priv(netdev);
  138. u32 val, addr;
  139. mutex_lock(&dev->phy_mutex);
  140. /* confirm MII not busy */
  141. if (smsc95xx_phy_wait_not_busy(dev)) {
  142. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  143. mutex_unlock(&dev->phy_mutex);
  144. return;
  145. }
  146. val = regval;
  147. smsc95xx_write_reg(dev, MII_DATA, val);
  148. /* set the address, index & direction (write to PHY) */
  149. phy_id &= dev->mii.phy_id_mask;
  150. idx &= dev->mii.reg_num_mask;
  151. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  152. smsc95xx_write_reg(dev, MII_ADDR, addr);
  153. if (smsc95xx_phy_wait_not_busy(dev))
  154. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  155. mutex_unlock(&dev->phy_mutex);
  156. }
  157. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  158. {
  159. unsigned long start_time = jiffies;
  160. u32 val;
  161. do {
  162. smsc95xx_read_reg(dev, E2P_CMD, &val);
  163. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  164. break;
  165. udelay(40);
  166. } while (!time_after(jiffies, start_time + HZ));
  167. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  168. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  169. return -EIO;
  170. }
  171. return 0;
  172. }
  173. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  174. {
  175. unsigned long start_time = jiffies;
  176. u32 val;
  177. do {
  178. smsc95xx_read_reg(dev, E2P_CMD, &val);
  179. if (!(val & E2P_CMD_BUSY_))
  180. return 0;
  181. udelay(40);
  182. } while (!time_after(jiffies, start_time + HZ));
  183. netdev_warn(dev->net, "EEPROM is busy\n");
  184. return -EIO;
  185. }
  186. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  187. u8 *data)
  188. {
  189. u32 val;
  190. int i, ret;
  191. BUG_ON(!dev);
  192. BUG_ON(!data);
  193. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  194. if (ret)
  195. return ret;
  196. for (i = 0; i < length; i++) {
  197. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  198. smsc95xx_write_reg(dev, E2P_CMD, val);
  199. ret = smsc95xx_wait_eeprom(dev);
  200. if (ret < 0)
  201. return ret;
  202. smsc95xx_read_reg(dev, E2P_DATA, &val);
  203. data[i] = val & 0xFF;
  204. offset++;
  205. }
  206. return 0;
  207. }
  208. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  209. u8 *data)
  210. {
  211. u32 val;
  212. int i, ret;
  213. BUG_ON(!dev);
  214. BUG_ON(!data);
  215. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  216. if (ret)
  217. return ret;
  218. /* Issue write/erase enable command */
  219. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  220. smsc95xx_write_reg(dev, E2P_CMD, val);
  221. ret = smsc95xx_wait_eeprom(dev);
  222. if (ret < 0)
  223. return ret;
  224. for (i = 0; i < length; i++) {
  225. /* Fill data register */
  226. val = data[i];
  227. smsc95xx_write_reg(dev, E2P_DATA, val);
  228. /* Send "write" command */
  229. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  230. smsc95xx_write_reg(dev, E2P_CMD, val);
  231. ret = smsc95xx_wait_eeprom(dev);
  232. if (ret < 0)
  233. return ret;
  234. offset++;
  235. }
  236. return 0;
  237. }
  238. static void smsc95xx_async_cmd_callback(struct urb *urb)
  239. {
  240. struct usb_context *usb_context = urb->context;
  241. struct usbnet *dev = usb_context->dev;
  242. int status = urb->status;
  243. if (status < 0)
  244. netdev_warn(dev->net, "async callback failed with %d\n", status);
  245. kfree(usb_context);
  246. usb_free_urb(urb);
  247. }
  248. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  249. {
  250. struct usb_context *usb_context;
  251. int status;
  252. struct urb *urb;
  253. const u16 size = 4;
  254. urb = usb_alloc_urb(0, GFP_ATOMIC);
  255. if (!urb) {
  256. netdev_warn(dev->net, "Error allocating URB\n");
  257. return -ENOMEM;
  258. }
  259. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  260. if (usb_context == NULL) {
  261. netdev_warn(dev->net, "Error allocating control msg\n");
  262. usb_free_urb(urb);
  263. return -ENOMEM;
  264. }
  265. usb_context->req.bRequestType =
  266. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  267. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  268. usb_context->req.wValue = 00;
  269. usb_context->req.wIndex = cpu_to_le16(index);
  270. usb_context->req.wLength = cpu_to_le16(size);
  271. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  272. (void *)&usb_context->req, data, size,
  273. smsc95xx_async_cmd_callback,
  274. (void *)usb_context);
  275. status = usb_submit_urb(urb, GFP_ATOMIC);
  276. if (status < 0) {
  277. netdev_warn(dev->net, "Error submitting control msg, sts=%d\n",
  278. status);
  279. kfree(usb_context);
  280. usb_free_urb(urb);
  281. }
  282. return status;
  283. }
  284. /* returns hash bit number for given MAC address
  285. * example:
  286. * 01 00 5E 00 00 01 -> returns bit number 31 */
  287. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  288. {
  289. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  290. }
  291. static void smsc95xx_set_multicast(struct net_device *netdev)
  292. {
  293. struct usbnet *dev = netdev_priv(netdev);
  294. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  295. unsigned long flags;
  296. pdata->hash_hi = 0;
  297. pdata->hash_lo = 0;
  298. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  299. if (dev->net->flags & IFF_PROMISC) {
  300. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  301. pdata->mac_cr |= MAC_CR_PRMS_;
  302. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  303. } else if (dev->net->flags & IFF_ALLMULTI) {
  304. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  305. pdata->mac_cr |= MAC_CR_MCPAS_;
  306. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  307. } else if (!netdev_mc_empty(dev->net)) {
  308. struct netdev_hw_addr *ha;
  309. pdata->mac_cr |= MAC_CR_HPFILT_;
  310. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  311. netdev_for_each_mc_addr(ha, netdev) {
  312. u32 bitnum = smsc95xx_hash(ha->addr);
  313. u32 mask = 0x01 << (bitnum & 0x1F);
  314. if (bitnum & 0x20)
  315. pdata->hash_hi |= mask;
  316. else
  317. pdata->hash_lo |= mask;
  318. }
  319. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  320. pdata->hash_hi, pdata->hash_lo);
  321. } else {
  322. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  323. pdata->mac_cr &=
  324. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  325. }
  326. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  327. /* Initiate async writes, as we can't wait for completion here */
  328. smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi);
  329. smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo);
  330. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  331. }
  332. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  333. u16 lcladv, u16 rmtadv)
  334. {
  335. u32 flow, afc_cfg = 0;
  336. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  337. if (ret < 0) {
  338. netdev_warn(dev->net, "error reading AFC_CFG\n");
  339. return;
  340. }
  341. if (duplex == DUPLEX_FULL) {
  342. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  343. if (cap & FLOW_CTRL_RX)
  344. flow = 0xFFFF0002;
  345. else
  346. flow = 0;
  347. if (cap & FLOW_CTRL_TX)
  348. afc_cfg |= 0xF;
  349. else
  350. afc_cfg &= ~0xF;
  351. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  352. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  353. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  354. } else {
  355. netif_dbg(dev, link, dev->net, "half duplex\n");
  356. flow = 0;
  357. afc_cfg |= 0xF;
  358. }
  359. smsc95xx_write_reg(dev, FLOW, flow);
  360. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  361. }
  362. static int smsc95xx_link_reset(struct usbnet *dev)
  363. {
  364. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  365. struct mii_if_info *mii = &dev->mii;
  366. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  367. unsigned long flags;
  368. u16 lcladv, rmtadv;
  369. /* clear interrupt status */
  370. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  371. smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  372. mii_check_media(mii, 1, 1);
  373. mii_ethtool_gset(&dev->mii, &ecmd);
  374. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  375. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  376. netif_dbg(dev, link, dev->net,
  377. "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  378. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  379. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  380. if (ecmd.duplex != DUPLEX_FULL) {
  381. pdata->mac_cr &= ~MAC_CR_FDPX_;
  382. pdata->mac_cr |= MAC_CR_RCVOWN_;
  383. } else {
  384. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  385. pdata->mac_cr |= MAC_CR_FDPX_;
  386. }
  387. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  388. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  389. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  390. return 0;
  391. }
  392. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  393. {
  394. u32 intdata;
  395. if (urb->actual_length != 4) {
  396. netdev_warn(dev->net, "unexpected urb length %d\n",
  397. urb->actual_length);
  398. return;
  399. }
  400. memcpy(&intdata, urb->transfer_buffer, 4);
  401. le32_to_cpus(&intdata);
  402. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  403. if (intdata & INT_ENP_PHY_INT_)
  404. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  405. else
  406. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  407. intdata);
  408. }
  409. /* Enable or disable Tx & Rx checksum offload engines */
  410. static int smsc95xx_set_features(struct net_device *netdev,
  411. netdev_features_t features)
  412. {
  413. struct usbnet *dev = netdev_priv(netdev);
  414. u32 read_buf;
  415. int ret;
  416. ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  417. if (ret < 0) {
  418. netdev_warn(dev->net, "Failed to read COE_CR: %d\n", ret);
  419. return ret;
  420. }
  421. if (features & NETIF_F_HW_CSUM)
  422. read_buf |= Tx_COE_EN_;
  423. else
  424. read_buf &= ~Tx_COE_EN_;
  425. if (features & NETIF_F_RXCSUM)
  426. read_buf |= Rx_COE_EN_;
  427. else
  428. read_buf &= ~Rx_COE_EN_;
  429. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  430. if (ret < 0) {
  431. netdev_warn(dev->net, "Failed to write COE_CR: %d\n", ret);
  432. return ret;
  433. }
  434. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  435. return 0;
  436. }
  437. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  438. {
  439. return MAX_EEPROM_SIZE;
  440. }
  441. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  442. struct ethtool_eeprom *ee, u8 *data)
  443. {
  444. struct usbnet *dev = netdev_priv(netdev);
  445. ee->magic = LAN95XX_EEPROM_MAGIC;
  446. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  447. }
  448. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  449. struct ethtool_eeprom *ee, u8 *data)
  450. {
  451. struct usbnet *dev = netdev_priv(netdev);
  452. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  453. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  454. ee->magic);
  455. return -EINVAL;
  456. }
  457. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  458. }
  459. static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
  460. {
  461. /* all smsc95xx registers */
  462. return COE_CR - ID_REV + 1;
  463. }
  464. static void
  465. smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
  466. void *buf)
  467. {
  468. struct usbnet *dev = netdev_priv(netdev);
  469. unsigned int i, j;
  470. int retval;
  471. u32 *data = buf;
  472. retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
  473. if (retval < 0) {
  474. netdev_warn(netdev, "REGS: cannot read ID_REV\n");
  475. return;
  476. }
  477. for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
  478. retval = smsc95xx_read_reg(dev, i, &data[j]);
  479. if (retval < 0) {
  480. netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
  481. return;
  482. }
  483. }
  484. }
  485. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  486. .get_link = usbnet_get_link,
  487. .nway_reset = usbnet_nway_reset,
  488. .get_drvinfo = usbnet_get_drvinfo,
  489. .get_msglevel = usbnet_get_msglevel,
  490. .set_msglevel = usbnet_set_msglevel,
  491. .get_settings = usbnet_get_settings,
  492. .set_settings = usbnet_set_settings,
  493. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  494. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  495. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  496. .get_regs_len = smsc95xx_ethtool_getregslen,
  497. .get_regs = smsc95xx_ethtool_getregs,
  498. };
  499. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  500. {
  501. struct usbnet *dev = netdev_priv(netdev);
  502. if (!netif_running(netdev))
  503. return -EINVAL;
  504. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  505. }
  506. static void smsc95xx_init_mac_address(struct usbnet *dev)
  507. {
  508. /* try reading mac address from EEPROM */
  509. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  510. dev->net->dev_addr) == 0) {
  511. if (is_valid_ether_addr(dev->net->dev_addr)) {
  512. /* eeprom values are valid so use them */
  513. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  514. return;
  515. }
  516. }
  517. /* no eeprom, or eeprom values are invalid. generate random MAC */
  518. eth_hw_addr_random(dev->net);
  519. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  520. }
  521. static int smsc95xx_set_mac_address(struct usbnet *dev)
  522. {
  523. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  524. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  525. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  526. int ret;
  527. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  528. if (ret < 0) {
  529. netdev_warn(dev->net, "Failed to write ADDRL: %d\n", ret);
  530. return ret;
  531. }
  532. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  533. if (ret < 0) {
  534. netdev_warn(dev->net, "Failed to write ADDRH: %d\n", ret);
  535. return ret;
  536. }
  537. return 0;
  538. }
  539. /* starts the TX path */
  540. static void smsc95xx_start_tx_path(struct usbnet *dev)
  541. {
  542. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  543. unsigned long flags;
  544. /* Enable Tx at MAC */
  545. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  546. pdata->mac_cr |= MAC_CR_TXEN_;
  547. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  548. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  549. /* Enable Tx at SCSRs */
  550. smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
  551. }
  552. /* Starts the Receive path */
  553. static void smsc95xx_start_rx_path(struct usbnet *dev)
  554. {
  555. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  556. unsigned long flags;
  557. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  558. pdata->mac_cr |= MAC_CR_RXEN_;
  559. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  560. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  561. }
  562. static int smsc95xx_phy_initialize(struct usbnet *dev)
  563. {
  564. int bmcr, timeout = 0;
  565. /* Initialize MII structure */
  566. dev->mii.dev = dev->net;
  567. dev->mii.mdio_read = smsc95xx_mdio_read;
  568. dev->mii.mdio_write = smsc95xx_mdio_write;
  569. dev->mii.phy_id_mask = 0x1f;
  570. dev->mii.reg_num_mask = 0x1f;
  571. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  572. /* reset phy and wait for reset to complete */
  573. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  574. do {
  575. msleep(10);
  576. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  577. timeout++;
  578. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  579. if (timeout >= 100) {
  580. netdev_warn(dev->net, "timeout on PHY Reset");
  581. return -EIO;
  582. }
  583. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  584. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  585. ADVERTISE_PAUSE_ASYM);
  586. /* read to clear */
  587. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  588. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  589. PHY_INT_MASK_DEFAULT_);
  590. mii_nway_restart(&dev->mii);
  591. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  592. return 0;
  593. }
  594. static int smsc95xx_reset(struct usbnet *dev)
  595. {
  596. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  597. u32 read_buf, write_buf, burst_cap;
  598. int ret = 0, timeout;
  599. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  600. ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
  601. if (ret < 0) {
  602. netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n",
  603. ret);
  604. return ret;
  605. }
  606. timeout = 0;
  607. do {
  608. msleep(10);
  609. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  610. if (ret < 0) {
  611. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  612. return ret;
  613. }
  614. timeout++;
  615. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  616. if (timeout >= 100) {
  617. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  618. return ret;
  619. }
  620. ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
  621. if (ret < 0) {
  622. netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret);
  623. return ret;
  624. }
  625. timeout = 0;
  626. do {
  627. msleep(10);
  628. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  629. if (ret < 0) {
  630. netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret);
  631. return ret;
  632. }
  633. timeout++;
  634. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  635. if (timeout >= 100) {
  636. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  637. return ret;
  638. }
  639. ret = smsc95xx_set_mac_address(dev);
  640. if (ret < 0)
  641. return ret;
  642. netif_dbg(dev, ifup, dev->net,
  643. "MAC Address: %pM\n", dev->net->dev_addr);
  644. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  645. if (ret < 0) {
  646. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  647. return ret;
  648. }
  649. netif_dbg(dev, ifup, dev->net,
  650. "Read Value from HW_CFG : 0x%08x\n", read_buf);
  651. read_buf |= HW_CFG_BIR_;
  652. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  653. if (ret < 0) {
  654. netdev_warn(dev->net, "Failed to write HW_CFG_BIR_ bit in HW_CFG register, ret = %d\n",
  655. ret);
  656. return ret;
  657. }
  658. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  659. if (ret < 0) {
  660. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  661. return ret;
  662. }
  663. netif_dbg(dev, ifup, dev->net,
  664. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  665. read_buf);
  666. if (!turbo_mode) {
  667. burst_cap = 0;
  668. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  669. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  670. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  671. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  672. } else {
  673. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  674. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  675. }
  676. netif_dbg(dev, ifup, dev->net,
  677. "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
  678. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  679. if (ret < 0) {
  680. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  681. return ret;
  682. }
  683. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  684. if (ret < 0) {
  685. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  686. return ret;
  687. }
  688. netif_dbg(dev, ifup, dev->net,
  689. "Read Value from BURST_CAP after writing: 0x%08x\n",
  690. read_buf);
  691. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  692. if (ret < 0) {
  693. netdev_warn(dev->net, "ret = %d\n", ret);
  694. return ret;
  695. }
  696. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  697. if (ret < 0) {
  698. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  699. return ret;
  700. }
  701. netif_dbg(dev, ifup, dev->net,
  702. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  703. read_buf);
  704. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  705. if (ret < 0) {
  706. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  707. return ret;
  708. }
  709. netif_dbg(dev, ifup, dev->net,
  710. "Read Value from HW_CFG: 0x%08x\n", read_buf);
  711. if (turbo_mode)
  712. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  713. read_buf &= ~HW_CFG_RXDOFF_;
  714. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  715. read_buf |= NET_IP_ALIGN << 9;
  716. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  717. if (ret < 0) {
  718. netdev_warn(dev->net, "Failed to write HW_CFG register, ret=%d\n",
  719. ret);
  720. return ret;
  721. }
  722. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  723. if (ret < 0) {
  724. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  725. return ret;
  726. }
  727. netif_dbg(dev, ifup, dev->net,
  728. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  729. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  730. if (ret < 0) {
  731. netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n",
  732. ret);
  733. return ret;
  734. }
  735. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  736. if (ret < 0) {
  737. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  738. return ret;
  739. }
  740. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  741. /* Configure GPIO pins as LED outputs */
  742. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  743. LED_GPIO_CFG_FDX_LED;
  744. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  745. if (ret < 0) {
  746. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG register, ret=%d\n",
  747. ret);
  748. return ret;
  749. }
  750. /* Init Tx */
  751. ret = smsc95xx_write_reg(dev, FLOW, 0);
  752. if (ret < 0) {
  753. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  754. return ret;
  755. }
  756. ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
  757. if (ret < 0) {
  758. netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret);
  759. return ret;
  760. }
  761. /* Don't need mac_cr_lock during initialisation */
  762. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  763. if (ret < 0) {
  764. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  765. return ret;
  766. }
  767. /* Init Rx */
  768. /* Set Vlan */
  769. ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
  770. if (ret < 0) {
  771. netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret);
  772. return ret;
  773. }
  774. /* Enable or disable checksum offload engines */
  775. smsc95xx_set_features(dev->net, dev->net->features);
  776. smsc95xx_set_multicast(dev->net);
  777. if (smsc95xx_phy_initialize(dev) < 0)
  778. return -EIO;
  779. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  780. if (ret < 0) {
  781. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  782. return ret;
  783. }
  784. /* enable PHY interrupts */
  785. read_buf |= INT_EP_CTL_PHY_INT_;
  786. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  787. if (ret < 0) {
  788. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  789. return ret;
  790. }
  791. smsc95xx_start_tx_path(dev);
  792. smsc95xx_start_rx_path(dev);
  793. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  794. return 0;
  795. }
  796. static const struct net_device_ops smsc95xx_netdev_ops = {
  797. .ndo_open = usbnet_open,
  798. .ndo_stop = usbnet_stop,
  799. .ndo_start_xmit = usbnet_start_xmit,
  800. .ndo_tx_timeout = usbnet_tx_timeout,
  801. .ndo_change_mtu = usbnet_change_mtu,
  802. .ndo_set_mac_address = eth_mac_addr,
  803. .ndo_validate_addr = eth_validate_addr,
  804. .ndo_do_ioctl = smsc95xx_ioctl,
  805. .ndo_set_rx_mode = smsc95xx_set_multicast,
  806. .ndo_set_features = smsc95xx_set_features,
  807. };
  808. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  809. {
  810. struct smsc95xx_priv *pdata = NULL;
  811. int ret;
  812. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  813. ret = usbnet_get_endpoints(dev, intf);
  814. if (ret < 0) {
  815. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  816. return ret;
  817. }
  818. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  819. GFP_KERNEL);
  820. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  821. if (!pdata) {
  822. netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
  823. return -ENOMEM;
  824. }
  825. spin_lock_init(&pdata->mac_cr_lock);
  826. if (DEFAULT_TX_CSUM_ENABLE)
  827. dev->net->features |= NETIF_F_HW_CSUM;
  828. if (DEFAULT_RX_CSUM_ENABLE)
  829. dev->net->features |= NETIF_F_RXCSUM;
  830. dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  831. smsc95xx_init_mac_address(dev);
  832. /* Init all registers */
  833. ret = smsc95xx_reset(dev);
  834. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  835. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  836. dev->net->flags |= IFF_MULTICAST;
  837. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
  838. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  839. return 0;
  840. }
  841. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  842. {
  843. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  844. if (pdata) {
  845. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  846. kfree(pdata);
  847. pdata = NULL;
  848. dev->data[0] = 0;
  849. }
  850. }
  851. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  852. {
  853. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  854. skb->ip_summed = CHECKSUM_COMPLETE;
  855. skb_trim(skb, skb->len - 2);
  856. }
  857. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  858. {
  859. while (skb->len > 0) {
  860. u32 header, align_count;
  861. struct sk_buff *ax_skb;
  862. unsigned char *packet;
  863. u16 size;
  864. memcpy(&header, skb->data, sizeof(header));
  865. le32_to_cpus(&header);
  866. skb_pull(skb, 4 + NET_IP_ALIGN);
  867. packet = skb->data;
  868. /* get the packet length */
  869. size = (u16)((header & RX_STS_FL_) >> 16);
  870. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  871. if (unlikely(header & RX_STS_ES_)) {
  872. netif_dbg(dev, rx_err, dev->net,
  873. "Error header=0x%08x\n", header);
  874. dev->net->stats.rx_errors++;
  875. dev->net->stats.rx_dropped++;
  876. if (header & RX_STS_CRC_) {
  877. dev->net->stats.rx_crc_errors++;
  878. } else {
  879. if (header & (RX_STS_TL_ | RX_STS_RF_))
  880. dev->net->stats.rx_frame_errors++;
  881. if ((header & RX_STS_LE_) &&
  882. (!(header & RX_STS_FT_)))
  883. dev->net->stats.rx_length_errors++;
  884. }
  885. } else {
  886. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  887. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  888. netif_dbg(dev, rx_err, dev->net,
  889. "size err header=0x%08x\n", header);
  890. return 0;
  891. }
  892. /* last frame in this batch */
  893. if (skb->len == size) {
  894. if (dev->net->features & NETIF_F_RXCSUM)
  895. smsc95xx_rx_csum_offload(skb);
  896. skb_trim(skb, skb->len - 4); /* remove fcs */
  897. skb->truesize = size + sizeof(struct sk_buff);
  898. return 1;
  899. }
  900. ax_skb = skb_clone(skb, GFP_ATOMIC);
  901. if (unlikely(!ax_skb)) {
  902. netdev_warn(dev->net, "Error allocating skb\n");
  903. return 0;
  904. }
  905. ax_skb->len = size;
  906. ax_skb->data = packet;
  907. skb_set_tail_pointer(ax_skb, size);
  908. if (dev->net->features & NETIF_F_RXCSUM)
  909. smsc95xx_rx_csum_offload(ax_skb);
  910. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  911. ax_skb->truesize = size + sizeof(struct sk_buff);
  912. usbnet_skb_return(dev, ax_skb);
  913. }
  914. skb_pull(skb, size);
  915. /* padding bytes before the next frame starts */
  916. if (skb->len)
  917. skb_pull(skb, align_count);
  918. }
  919. if (unlikely(skb->len < 0)) {
  920. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  921. return 0;
  922. }
  923. return 1;
  924. }
  925. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  926. {
  927. u16 low_16 = (u16)skb_checksum_start_offset(skb);
  928. u16 high_16 = low_16 + skb->csum_offset;
  929. return (high_16 << 16) | low_16;
  930. }
  931. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  932. struct sk_buff *skb, gfp_t flags)
  933. {
  934. bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
  935. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  936. u32 tx_cmd_a, tx_cmd_b;
  937. /* We do not advertise SG, so skbs should be already linearized */
  938. BUG_ON(skb_shinfo(skb)->nr_frags);
  939. if (skb_headroom(skb) < overhead) {
  940. struct sk_buff *skb2 = skb_copy_expand(skb,
  941. overhead, 0, flags);
  942. dev_kfree_skb_any(skb);
  943. skb = skb2;
  944. if (!skb)
  945. return NULL;
  946. }
  947. if (csum) {
  948. if (skb->len <= 45) {
  949. /* workaround - hardware tx checksum does not work
  950. * properly with extremely small packets */
  951. long csstart = skb_checksum_start_offset(skb);
  952. __wsum calc = csum_partial(skb->data + csstart,
  953. skb->len - csstart, 0);
  954. *((__sum16 *)(skb->data + csstart
  955. + skb->csum_offset)) = csum_fold(calc);
  956. csum = false;
  957. } else {
  958. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  959. skb_push(skb, 4);
  960. memcpy(skb->data, &csum_preamble, 4);
  961. }
  962. }
  963. skb_push(skb, 4);
  964. tx_cmd_b = (u32)(skb->len - 4);
  965. if (csum)
  966. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  967. cpu_to_le32s(&tx_cmd_b);
  968. memcpy(skb->data, &tx_cmd_b, 4);
  969. skb_push(skb, 4);
  970. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  971. TX_CMD_A_LAST_SEG_;
  972. cpu_to_le32s(&tx_cmd_a);
  973. memcpy(skb->data, &tx_cmd_a, 4);
  974. return skb;
  975. }
  976. static const struct driver_info smsc95xx_info = {
  977. .description = "smsc95xx USB 2.0 Ethernet",
  978. .bind = smsc95xx_bind,
  979. .unbind = smsc95xx_unbind,
  980. .link_reset = smsc95xx_link_reset,
  981. .reset = smsc95xx_reset,
  982. .rx_fixup = smsc95xx_rx_fixup,
  983. .tx_fixup = smsc95xx_tx_fixup,
  984. .status = smsc95xx_status,
  985. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  986. };
  987. static const struct usb_device_id products[] = {
  988. {
  989. /* SMSC9500 USB Ethernet Device */
  990. USB_DEVICE(0x0424, 0x9500),
  991. .driver_info = (unsigned long) &smsc95xx_info,
  992. },
  993. {
  994. /* SMSC9505 USB Ethernet Device */
  995. USB_DEVICE(0x0424, 0x9505),
  996. .driver_info = (unsigned long) &smsc95xx_info,
  997. },
  998. {
  999. /* SMSC9500A USB Ethernet Device */
  1000. USB_DEVICE(0x0424, 0x9E00),
  1001. .driver_info = (unsigned long) &smsc95xx_info,
  1002. },
  1003. {
  1004. /* SMSC9505A USB Ethernet Device */
  1005. USB_DEVICE(0x0424, 0x9E01),
  1006. .driver_info = (unsigned long) &smsc95xx_info,
  1007. },
  1008. {
  1009. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1010. USB_DEVICE(0x0424, 0xec00),
  1011. .driver_info = (unsigned long) &smsc95xx_info,
  1012. },
  1013. {
  1014. /* SMSC9500 USB Ethernet Device (SAL10) */
  1015. USB_DEVICE(0x0424, 0x9900),
  1016. .driver_info = (unsigned long) &smsc95xx_info,
  1017. },
  1018. {
  1019. /* SMSC9505 USB Ethernet Device (SAL10) */
  1020. USB_DEVICE(0x0424, 0x9901),
  1021. .driver_info = (unsigned long) &smsc95xx_info,
  1022. },
  1023. {
  1024. /* SMSC9500A USB Ethernet Device (SAL10) */
  1025. USB_DEVICE(0x0424, 0x9902),
  1026. .driver_info = (unsigned long) &smsc95xx_info,
  1027. },
  1028. {
  1029. /* SMSC9505A USB Ethernet Device (SAL10) */
  1030. USB_DEVICE(0x0424, 0x9903),
  1031. .driver_info = (unsigned long) &smsc95xx_info,
  1032. },
  1033. {
  1034. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1035. USB_DEVICE(0x0424, 0x9904),
  1036. .driver_info = (unsigned long) &smsc95xx_info,
  1037. },
  1038. {
  1039. /* SMSC9500A USB Ethernet Device (HAL) */
  1040. USB_DEVICE(0x0424, 0x9905),
  1041. .driver_info = (unsigned long) &smsc95xx_info,
  1042. },
  1043. {
  1044. /* SMSC9505A USB Ethernet Device (HAL) */
  1045. USB_DEVICE(0x0424, 0x9906),
  1046. .driver_info = (unsigned long) &smsc95xx_info,
  1047. },
  1048. {
  1049. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1050. USB_DEVICE(0x0424, 0x9907),
  1051. .driver_info = (unsigned long) &smsc95xx_info,
  1052. },
  1053. {
  1054. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1055. USB_DEVICE(0x0424, 0x9908),
  1056. .driver_info = (unsigned long) &smsc95xx_info,
  1057. },
  1058. {
  1059. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1060. USB_DEVICE(0x0424, 0x9909),
  1061. .driver_info = (unsigned long) &smsc95xx_info,
  1062. },
  1063. {
  1064. /* SMSC LAN9530 USB Ethernet Device */
  1065. USB_DEVICE(0x0424, 0x9530),
  1066. .driver_info = (unsigned long) &smsc95xx_info,
  1067. },
  1068. {
  1069. /* SMSC LAN9730 USB Ethernet Device */
  1070. USB_DEVICE(0x0424, 0x9730),
  1071. .driver_info = (unsigned long) &smsc95xx_info,
  1072. },
  1073. {
  1074. /* SMSC LAN89530 USB Ethernet Device */
  1075. USB_DEVICE(0x0424, 0x9E08),
  1076. .driver_info = (unsigned long) &smsc95xx_info,
  1077. },
  1078. { }, /* END */
  1079. };
  1080. MODULE_DEVICE_TABLE(usb, products);
  1081. static struct usb_driver smsc95xx_driver = {
  1082. .name = "smsc95xx",
  1083. .id_table = products,
  1084. .probe = usbnet_probe,
  1085. .suspend = usbnet_suspend,
  1086. .resume = usbnet_resume,
  1087. .disconnect = usbnet_disconnect,
  1088. .disable_hub_initiated_lpm = 1,
  1089. };
  1090. module_usb_driver(smsc95xx_driver);
  1091. MODULE_AUTHOR("Nancy Lin");
  1092. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1093. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1094. MODULE_LICENSE("GPL");