iwl-4965.c 110 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-eeprom.h"
  40. #include "iwl-dev.h"
  41. #include "iwl-core.h"
  42. #include "iwl-io.h"
  43. #include "iwl-helpers.h"
  44. #include "iwl-calib.h"
  45. /* module parameters */
  46. static struct iwl_mod_params iwl4965_mod_params = {
  47. .num_of_queues = IWL49_NUM_QUEUES,
  48. .enable_qos = 1,
  49. .amsdu_size_8K = 1,
  50. /* the rest are 0 by default */
  51. };
  52. #ifdef CONFIG_IWL4965_HT
  53. static const u16 default_tid_to_tx_fifo[] = {
  54. IWL_TX_FIFO_AC1,
  55. IWL_TX_FIFO_AC0,
  56. IWL_TX_FIFO_AC0,
  57. IWL_TX_FIFO_AC1,
  58. IWL_TX_FIFO_AC2,
  59. IWL_TX_FIFO_AC2,
  60. IWL_TX_FIFO_AC3,
  61. IWL_TX_FIFO_AC3,
  62. IWL_TX_FIFO_NONE,
  63. IWL_TX_FIFO_NONE,
  64. IWL_TX_FIFO_NONE,
  65. IWL_TX_FIFO_NONE,
  66. IWL_TX_FIFO_NONE,
  67. IWL_TX_FIFO_NONE,
  68. IWL_TX_FIFO_NONE,
  69. IWL_TX_FIFO_NONE,
  70. IWL_TX_FIFO_AC3
  71. };
  72. #endif /*CONFIG_IWL4965_HT */
  73. /* check contents of special bootstrap uCode SRAM */
  74. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  75. {
  76. __le32 *image = priv->ucode_boot.v_addr;
  77. u32 len = priv->ucode_boot.len;
  78. u32 reg;
  79. u32 val;
  80. IWL_DEBUG_INFO("Begin verify bsm\n");
  81. /* verify BSM SRAM contents */
  82. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  83. for (reg = BSM_SRAM_LOWER_BOUND;
  84. reg < BSM_SRAM_LOWER_BOUND + len;
  85. reg += sizeof(u32), image++) {
  86. val = iwl_read_prph(priv, reg);
  87. if (val != le32_to_cpu(*image)) {
  88. IWL_ERROR("BSM uCode verification failed at "
  89. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  90. BSM_SRAM_LOWER_BOUND,
  91. reg - BSM_SRAM_LOWER_BOUND, len,
  92. val, le32_to_cpu(*image));
  93. return -EIO;
  94. }
  95. }
  96. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  97. return 0;
  98. }
  99. /**
  100. * iwl4965_load_bsm - Load bootstrap instructions
  101. *
  102. * BSM operation:
  103. *
  104. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  105. * in special SRAM that does not power down during RFKILL. When powering back
  106. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  107. * the bootstrap program into the on-board processor, and starts it.
  108. *
  109. * The bootstrap program loads (via DMA) instructions and data for a new
  110. * program from host DRAM locations indicated by the host driver in the
  111. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  112. * automatically.
  113. *
  114. * When initializing the NIC, the host driver points the BSM to the
  115. * "initialize" uCode image. This uCode sets up some internal data, then
  116. * notifies host via "initialize alive" that it is complete.
  117. *
  118. * The host then replaces the BSM_DRAM_* pointer values to point to the
  119. * normal runtime uCode instructions and a backup uCode data cache buffer
  120. * (filled initially with starting data values for the on-board processor),
  121. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  122. * which begins normal operation.
  123. *
  124. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  125. * the backup data cache in DRAM before SRAM is powered down.
  126. *
  127. * When powering back up, the BSM loads the bootstrap program. This reloads
  128. * the runtime uCode instructions and the backup data cache into SRAM,
  129. * and re-launches the runtime uCode from where it left off.
  130. */
  131. static int iwl4965_load_bsm(struct iwl_priv *priv)
  132. {
  133. __le32 *image = priv->ucode_boot.v_addr;
  134. u32 len = priv->ucode_boot.len;
  135. dma_addr_t pinst;
  136. dma_addr_t pdata;
  137. u32 inst_len;
  138. u32 data_len;
  139. int i;
  140. u32 done;
  141. u32 reg_offset;
  142. int ret;
  143. IWL_DEBUG_INFO("Begin load bsm\n");
  144. /* make sure bootstrap program is no larger than BSM's SRAM size */
  145. if (len > IWL_MAX_BSM_SIZE)
  146. return -EINVAL;
  147. /* Tell bootstrap uCode where to find the "Initialize" uCode
  148. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  149. * NOTE: iwl4965_initialize_alive_start() will replace these values,
  150. * after the "initialize" uCode has run, to point to
  151. * runtime/protocol instructions and backup data cache. */
  152. pinst = priv->ucode_init.p_addr >> 4;
  153. pdata = priv->ucode_init_data.p_addr >> 4;
  154. inst_len = priv->ucode_init.len;
  155. data_len = priv->ucode_init_data.len;
  156. ret = iwl_grab_nic_access(priv);
  157. if (ret)
  158. return ret;
  159. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  160. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  161. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  162. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  163. /* Fill BSM memory with bootstrap instructions */
  164. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  165. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  166. reg_offset += sizeof(u32), image++)
  167. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  168. ret = iwl4965_verify_bsm(priv);
  169. if (ret) {
  170. iwl_release_nic_access(priv);
  171. return ret;
  172. }
  173. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  174. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  175. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
  176. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  177. /* Load bootstrap code into instruction SRAM now,
  178. * to prepare to load "initialize" uCode */
  179. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  180. /* Wait for load of bootstrap uCode to finish */
  181. for (i = 0; i < 100; i++) {
  182. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  183. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  184. break;
  185. udelay(10);
  186. }
  187. if (i < 100)
  188. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  189. else {
  190. IWL_ERROR("BSM write did not complete!\n");
  191. return -EIO;
  192. }
  193. /* Enable future boot loads whenever power management unit triggers it
  194. * (e.g. when powering back up after power-save shutdown) */
  195. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  196. iwl_release_nic_access(priv);
  197. return 0;
  198. }
  199. /**
  200. * iwl4965_set_ucode_ptrs - Set uCode address location
  201. *
  202. * Tell initialization uCode where to find runtime uCode.
  203. *
  204. * BSM registers initially contain pointers to initialization uCode.
  205. * We need to replace them to load runtime uCode inst and data,
  206. * and to save runtime data when powering down.
  207. */
  208. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  209. {
  210. dma_addr_t pinst;
  211. dma_addr_t pdata;
  212. unsigned long flags;
  213. int ret = 0;
  214. /* bits 35:4 for 4965 */
  215. pinst = priv->ucode_code.p_addr >> 4;
  216. pdata = priv->ucode_data_backup.p_addr >> 4;
  217. spin_lock_irqsave(&priv->lock, flags);
  218. ret = iwl_grab_nic_access(priv);
  219. if (ret) {
  220. spin_unlock_irqrestore(&priv->lock, flags);
  221. return ret;
  222. }
  223. /* Tell bootstrap uCode where to find image to load */
  224. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  225. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  226. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  227. priv->ucode_data.len);
  228. /* Inst bytecount must be last to set up, bit 31 signals uCode
  229. * that all new ptr/size info is in place */
  230. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  231. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  232. iwl_release_nic_access(priv);
  233. spin_unlock_irqrestore(&priv->lock, flags);
  234. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  235. return ret;
  236. }
  237. /**
  238. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  239. *
  240. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  241. *
  242. * The 4965 "initialize" ALIVE reply contains calibration data for:
  243. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  244. * (3945 does not contain this data).
  245. *
  246. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  247. */
  248. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  249. {
  250. /* Check alive response for "valid" sign from uCode */
  251. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  252. /* We had an error bringing up the hardware, so take it
  253. * all the way back down so we can try again */
  254. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  255. goto restart;
  256. }
  257. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  258. * This is a paranoid check, because we would not have gotten the
  259. * "initialize" alive if code weren't properly loaded. */
  260. if (iwl_verify_ucode(priv)) {
  261. /* Runtime instruction load was bad;
  262. * take it all the way back down so we can try again */
  263. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  264. goto restart;
  265. }
  266. /* Calculate temperature */
  267. priv->temperature = iwl4965_get_temperature(priv);
  268. /* Send pointers to protocol/runtime uCode image ... init code will
  269. * load and launch runtime uCode, which will send us another "Alive"
  270. * notification. */
  271. IWL_DEBUG_INFO("Initialization Alive received.\n");
  272. if (iwl4965_set_ucode_ptrs(priv)) {
  273. /* Runtime instruction load won't happen;
  274. * take it all the way back down so we can try again */
  275. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  276. goto restart;
  277. }
  278. return;
  279. restart:
  280. queue_work(priv->workqueue, &priv->restart);
  281. }
  282. static int is_fat_channel(__le32 rxon_flags)
  283. {
  284. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  285. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  286. }
  287. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  288. {
  289. int idx = 0;
  290. /* 4965 HT rate format */
  291. if (rate_n_flags & RATE_MCS_HT_MSK) {
  292. idx = (rate_n_flags & 0xff);
  293. if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  294. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  295. idx += IWL_FIRST_OFDM_RATE;
  296. /* skip 9M not supported in ht*/
  297. if (idx >= IWL_RATE_9M_INDEX)
  298. idx += 1;
  299. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  300. return idx;
  301. /* 4965 legacy rate format, search for match in table */
  302. } else {
  303. for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
  304. if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
  305. return idx;
  306. }
  307. return -1;
  308. }
  309. /**
  310. * translate ucode response to mac80211 tx status control values
  311. */
  312. void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  313. struct ieee80211_tx_control *control)
  314. {
  315. int rate_index;
  316. control->antenna_sel_tx =
  317. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  318. if (rate_n_flags & RATE_MCS_HT_MSK)
  319. control->flags |= IEEE80211_TXCTL_OFDM_HT;
  320. if (rate_n_flags & RATE_MCS_GF_MSK)
  321. control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
  322. if (rate_n_flags & RATE_MCS_FAT_MSK)
  323. control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
  324. if (rate_n_flags & RATE_MCS_DUP_MSK)
  325. control->flags |= IEEE80211_TXCTL_DUP_DATA;
  326. if (rate_n_flags & RATE_MCS_SGI_MSK)
  327. control->flags |= IEEE80211_TXCTL_SHORT_GI;
  328. /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
  329. * IEEE80211_BAND_2GHZ band as it contains all the rates */
  330. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  331. if (rate_index == -1)
  332. control->tx_rate = NULL;
  333. else
  334. control->tx_rate =
  335. &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
  336. }
  337. int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
  338. {
  339. int rc;
  340. unsigned long flags;
  341. spin_lock_irqsave(&priv->lock, flags);
  342. rc = iwl_grab_nic_access(priv);
  343. if (rc) {
  344. spin_unlock_irqrestore(&priv->lock, flags);
  345. return rc;
  346. }
  347. /* stop Rx DMA */
  348. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  349. rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  350. (1 << 24), 1000);
  351. if (rc < 0)
  352. IWL_ERROR("Can't stop Rx DMA.\n");
  353. iwl_release_nic_access(priv);
  354. spin_unlock_irqrestore(&priv->lock, flags);
  355. return 0;
  356. }
  357. /*
  358. * EEPROM handlers
  359. */
  360. static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
  361. {
  362. u16 eeprom_ver;
  363. u16 calib_ver;
  364. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  365. calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  366. if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
  367. calib_ver < EEPROM_4965_TX_POWER_VERSION)
  368. goto err;
  369. return 0;
  370. err:
  371. IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
  372. eeprom_ver, EEPROM_4965_EEPROM_VERSION,
  373. calib_ver, EEPROM_4965_TX_POWER_VERSION);
  374. return -EINVAL;
  375. }
  376. int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  377. {
  378. int ret;
  379. unsigned long flags;
  380. spin_lock_irqsave(&priv->lock, flags);
  381. ret = iwl_grab_nic_access(priv);
  382. if (ret) {
  383. spin_unlock_irqrestore(&priv->lock, flags);
  384. return ret;
  385. }
  386. if (src == IWL_PWR_SRC_VAUX) {
  387. u32 val;
  388. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  389. &val);
  390. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
  391. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  392. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  393. ~APMG_PS_CTRL_MSK_PWR_SRC);
  394. }
  395. } else {
  396. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  397. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  398. ~APMG_PS_CTRL_MSK_PWR_SRC);
  399. }
  400. iwl_release_nic_access(priv);
  401. spin_unlock_irqrestore(&priv->lock, flags);
  402. return ret;
  403. }
  404. static int iwl4965_disable_tx_fifo(struct iwl_priv *priv)
  405. {
  406. unsigned long flags;
  407. int ret;
  408. spin_lock_irqsave(&priv->lock, flags);
  409. ret = iwl_grab_nic_access(priv);
  410. if (unlikely(ret)) {
  411. IWL_ERROR("Tx fifo reset failed");
  412. spin_unlock_irqrestore(&priv->lock, flags);
  413. return ret;
  414. }
  415. iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
  416. iwl_release_nic_access(priv);
  417. spin_unlock_irqrestore(&priv->lock, flags);
  418. return 0;
  419. }
  420. static int iwl4965_apm_init(struct iwl_priv *priv)
  421. {
  422. unsigned long flags;
  423. int ret = 0;
  424. spin_lock_irqsave(&priv->lock, flags);
  425. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  426. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  427. /* set "initialization complete" bit to move adapter
  428. * D0U* --> D0A* state */
  429. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  430. /* wait for clock stabilization */
  431. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  432. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  433. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  434. if (ret < 0) {
  435. IWL_DEBUG_INFO("Failed to init the card\n");
  436. goto out;
  437. }
  438. ret = iwl_grab_nic_access(priv);
  439. if (ret)
  440. goto out;
  441. /* enable DMA */
  442. iwl_write_prph(priv, APMG_CLK_CTRL_REG,
  443. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  444. udelay(20);
  445. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  446. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  447. iwl_release_nic_access(priv);
  448. out:
  449. spin_unlock_irqrestore(&priv->lock, flags);
  450. return ret;
  451. }
  452. static void iwl4965_nic_config(struct iwl_priv *priv)
  453. {
  454. unsigned long flags;
  455. u32 val;
  456. u16 radio_cfg;
  457. u8 val_link;
  458. spin_lock_irqsave(&priv->lock, flags);
  459. if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
  460. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  461. /* Enable No Snoop field */
  462. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  463. val & ~(1 << 11));
  464. }
  465. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  466. /* disable L1 entry -- workaround for pre-B1 */
  467. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  468. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  469. /* write radio config values to register */
  470. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  471. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  472. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  473. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  474. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  475. /* set CSR_HW_CONFIG_REG for uCode use */
  476. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  477. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  478. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  479. priv->calib_info = (struct iwl_eeprom_calib_info *)
  480. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  481. spin_unlock_irqrestore(&priv->lock, flags);
  482. }
  483. int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
  484. {
  485. int rc = 0;
  486. u32 reg_val;
  487. unsigned long flags;
  488. spin_lock_irqsave(&priv->lock, flags);
  489. /* set stop master bit */
  490. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  491. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  492. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  493. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  494. IWL_DEBUG_INFO("Card in power save, master is already "
  495. "stopped\n");
  496. else {
  497. rc = iwl_poll_bit(priv, CSR_RESET,
  498. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  499. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  500. if (rc < 0) {
  501. spin_unlock_irqrestore(&priv->lock, flags);
  502. return rc;
  503. }
  504. }
  505. spin_unlock_irqrestore(&priv->lock, flags);
  506. IWL_DEBUG_INFO("stop master\n");
  507. return rc;
  508. }
  509. /**
  510. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  511. */
  512. void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
  513. {
  514. int txq_id;
  515. unsigned long flags;
  516. /* Stop each Tx DMA channel, and wait for it to be idle */
  517. for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
  518. spin_lock_irqsave(&priv->lock, flags);
  519. if (iwl_grab_nic_access(priv)) {
  520. spin_unlock_irqrestore(&priv->lock, flags);
  521. continue;
  522. }
  523. iwl_write_direct32(priv,
  524. FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
  525. iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
  526. FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  527. (txq_id), 200);
  528. iwl_release_nic_access(priv);
  529. spin_unlock_irqrestore(&priv->lock, flags);
  530. }
  531. /* Deallocate memory for all Tx queues */
  532. iwl_hw_txq_ctx_free(priv);
  533. }
  534. int iwl4965_hw_nic_reset(struct iwl_priv *priv)
  535. {
  536. int rc = 0;
  537. unsigned long flags;
  538. iwl4965_hw_nic_stop_master(priv);
  539. spin_lock_irqsave(&priv->lock, flags);
  540. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  541. udelay(10);
  542. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  543. rc = iwl_poll_bit(priv, CSR_RESET,
  544. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  545. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  546. udelay(10);
  547. rc = iwl_grab_nic_access(priv);
  548. if (!rc) {
  549. iwl_write_prph(priv, APMG_CLK_EN_REG,
  550. APMG_CLK_VAL_DMA_CLK_RQT |
  551. APMG_CLK_VAL_BSM_CLK_RQT);
  552. udelay(10);
  553. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  554. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  555. iwl_release_nic_access(priv);
  556. }
  557. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  558. wake_up_interruptible(&priv->wait_command_queue);
  559. spin_unlock_irqrestore(&priv->lock, flags);
  560. return rc;
  561. }
  562. #define REG_RECALIB_PERIOD (60)
  563. /**
  564. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  565. *
  566. * This callback is provided in order to send a statistics request.
  567. *
  568. * This timer function is continually reset to execute within
  569. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  570. * was received. We need to ensure we receive the statistics in order
  571. * to update the temperature used for calibrating the TXPOWER.
  572. */
  573. static void iwl4965_bg_statistics_periodic(unsigned long data)
  574. {
  575. struct iwl_priv *priv = (struct iwl_priv *)data;
  576. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  577. return;
  578. iwl_send_statistics_request(priv, CMD_ASYNC);
  579. }
  580. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  581. {
  582. struct iwl4965_ct_kill_config cmd;
  583. unsigned long flags;
  584. int ret = 0;
  585. spin_lock_irqsave(&priv->lock, flags);
  586. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  587. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  588. spin_unlock_irqrestore(&priv->lock, flags);
  589. cmd.critical_temperature_R =
  590. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  591. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  592. sizeof(cmd), &cmd);
  593. if (ret)
  594. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  595. else
  596. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
  597. "critical temperature is %d\n",
  598. cmd.critical_temperature_R);
  599. }
  600. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  601. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  602. * Called after every association, but this runs only once!
  603. * ... once chain noise is calibrated the first time, it's good forever. */
  604. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  605. {
  606. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  607. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  608. struct iwl4965_calibration_cmd cmd;
  609. memset(&cmd, 0, sizeof(cmd));
  610. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  611. cmd.diff_gain_a = 0;
  612. cmd.diff_gain_b = 0;
  613. cmd.diff_gain_c = 0;
  614. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  615. sizeof(cmd), &cmd))
  616. IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
  617. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  618. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  619. }
  620. }
  621. static void iwl4965_gain_computation(struct iwl_priv *priv,
  622. u32 *average_noise,
  623. u16 min_average_noise_antenna_i,
  624. u32 min_average_noise)
  625. {
  626. int i, ret;
  627. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  628. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  629. for (i = 0; i < NUM_RX_CHAINS; i++) {
  630. s32 delta_g = 0;
  631. if (!(data->disconn_array[i]) &&
  632. (data->delta_gain_code[i] ==
  633. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  634. delta_g = average_noise[i] - min_average_noise;
  635. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  636. data->delta_gain_code[i] =
  637. min(data->delta_gain_code[i],
  638. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  639. data->delta_gain_code[i] =
  640. (data->delta_gain_code[i] | (1 << 2));
  641. } else {
  642. data->delta_gain_code[i] = 0;
  643. }
  644. }
  645. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  646. data->delta_gain_code[0],
  647. data->delta_gain_code[1],
  648. data->delta_gain_code[2]);
  649. /* Differential gain gets sent to uCode only once */
  650. if (!data->radio_write) {
  651. struct iwl4965_calibration_cmd cmd;
  652. data->radio_write = 1;
  653. memset(&cmd, 0, sizeof(cmd));
  654. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  655. cmd.diff_gain_a = data->delta_gain_code[0];
  656. cmd.diff_gain_b = data->delta_gain_code[1];
  657. cmd.diff_gain_c = data->delta_gain_code[2];
  658. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  659. sizeof(cmd), &cmd);
  660. if (ret)
  661. IWL_DEBUG_CALIB("fail sending cmd "
  662. "REPLY_PHY_CALIBRATION_CMD \n");
  663. /* TODO we might want recalculate
  664. * rx_chain in rxon cmd */
  665. /* Mark so we run this algo only once! */
  666. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  667. }
  668. data->chain_noise_a = 0;
  669. data->chain_noise_b = 0;
  670. data->chain_noise_c = 0;
  671. data->chain_signal_a = 0;
  672. data->chain_signal_b = 0;
  673. data->chain_signal_c = 0;
  674. data->beacon_count = 0;
  675. }
  676. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  677. {
  678. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  679. sensitivity_work);
  680. mutex_lock(&priv->mutex);
  681. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  682. test_bit(STATUS_SCANNING, &priv->status)) {
  683. mutex_unlock(&priv->mutex);
  684. return;
  685. }
  686. if (priv->start_calib) {
  687. iwl_chain_noise_calibration(priv, &priv->statistics);
  688. iwl_sensitivity_calibration(priv, &priv->statistics);
  689. }
  690. mutex_unlock(&priv->mutex);
  691. return;
  692. }
  693. #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
  694. static void iwl4965_bg_txpower_work(struct work_struct *work)
  695. {
  696. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  697. txpower_work);
  698. /* If a scan happened to start before we got here
  699. * then just return; the statistics notification will
  700. * kick off another scheduled work to compensate for
  701. * any temperature delta we missed here. */
  702. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  703. test_bit(STATUS_SCANNING, &priv->status))
  704. return;
  705. mutex_lock(&priv->mutex);
  706. /* Regardless of if we are assocaited, we must reconfigure the
  707. * TX power since frames can be sent on non-radar channels while
  708. * not associated */
  709. iwl4965_hw_reg_send_txpower(priv);
  710. /* Update last_temperature to keep is_calib_needed from running
  711. * when it isn't needed... */
  712. priv->last_temperature = priv->temperature;
  713. mutex_unlock(&priv->mutex);
  714. }
  715. /*
  716. * Acquire priv->lock before calling this function !
  717. */
  718. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  719. {
  720. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  721. (index & 0xff) | (txq_id << 8));
  722. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  723. }
  724. /**
  725. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  726. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  727. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  728. *
  729. * NOTE: Acquire priv->lock before calling this function !
  730. */
  731. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  732. struct iwl4965_tx_queue *txq,
  733. int tx_fifo_id, int scd_retry)
  734. {
  735. int txq_id = txq->q.id;
  736. /* Find out whether to activate Tx queue */
  737. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  738. /* Set up and activate */
  739. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  740. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  741. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  742. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  743. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  744. IWL49_SCD_QUEUE_STTS_REG_MSK);
  745. txq->sched_retry = scd_retry;
  746. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  747. active ? "Activate" : "Deactivate",
  748. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  749. }
  750. static const u16 default_queue_to_tx_fifo[] = {
  751. IWL_TX_FIFO_AC3,
  752. IWL_TX_FIFO_AC2,
  753. IWL_TX_FIFO_AC1,
  754. IWL_TX_FIFO_AC0,
  755. IWL49_CMD_FIFO_NUM,
  756. IWL_TX_FIFO_HCCA_1,
  757. IWL_TX_FIFO_HCCA_2
  758. };
  759. static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
  760. {
  761. set_bit(txq_id, &priv->txq_ctx_active_msk);
  762. }
  763. static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
  764. {
  765. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  766. }
  767. int iwl4965_alive_notify(struct iwl_priv *priv)
  768. {
  769. u32 a;
  770. int i = 0;
  771. unsigned long flags;
  772. int ret;
  773. spin_lock_irqsave(&priv->lock, flags);
  774. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  775. memset(&(priv->sensitivity_data), 0,
  776. sizeof(struct iwl_sensitivity_data));
  777. memset(&(priv->chain_noise_data), 0,
  778. sizeof(struct iwl_chain_noise_data));
  779. for (i = 0; i < NUM_RX_CHAINS; i++)
  780. priv->chain_noise_data.delta_gain_code[i] =
  781. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  782. #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
  783. ret = iwl_grab_nic_access(priv);
  784. if (ret) {
  785. spin_unlock_irqrestore(&priv->lock, flags);
  786. return ret;
  787. }
  788. /* Clear 4965's internal Tx Scheduler data base */
  789. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  790. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  791. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  792. iwl_write_targ_mem(priv, a, 0);
  793. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  794. iwl_write_targ_mem(priv, a, 0);
  795. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  796. iwl_write_targ_mem(priv, a, 0);
  797. /* Tel 4965 where to find Tx byte count tables */
  798. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  799. (priv->shared_phys +
  800. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  801. /* Disable chain mode for all queues */
  802. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  803. /* Initialize each Tx queue (including the command queue) */
  804. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  805. /* TFD circular buffer read/write indexes */
  806. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  807. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  808. /* Max Tx Window size for Scheduler-ACK mode */
  809. iwl_write_targ_mem(priv, priv->scd_base_addr +
  810. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  811. (SCD_WIN_SIZE <<
  812. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  813. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  814. /* Frame limit */
  815. iwl_write_targ_mem(priv, priv->scd_base_addr +
  816. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  817. sizeof(u32),
  818. (SCD_FRAME_LIMIT <<
  819. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  820. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  821. }
  822. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  823. (1 << priv->hw_params.max_txq_num) - 1);
  824. /* Activate all Tx DMA/FIFO channels */
  825. iwl_write_prph(priv, IWL49_SCD_TXFACT,
  826. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  827. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  828. /* Map each Tx/cmd queue to its corresponding fifo */
  829. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  830. int ac = default_queue_to_tx_fifo[i];
  831. iwl4965_txq_ctx_activate(priv, i);
  832. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  833. }
  834. iwl_release_nic_access(priv);
  835. spin_unlock_irqrestore(&priv->lock, flags);
  836. /* Ask for statistics now, the uCode will send statistics notification
  837. * periodically after association */
  838. iwl_send_statistics_request(priv, CMD_ASYNC);
  839. return ret;
  840. }
  841. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  842. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  843. .min_nrg_cck = 97,
  844. .max_nrg_cck = 0,
  845. .auto_corr_min_ofdm = 85,
  846. .auto_corr_min_ofdm_mrc = 170,
  847. .auto_corr_min_ofdm_x1 = 105,
  848. .auto_corr_min_ofdm_mrc_x1 = 220,
  849. .auto_corr_max_ofdm = 120,
  850. .auto_corr_max_ofdm_mrc = 210,
  851. .auto_corr_max_ofdm_x1 = 140,
  852. .auto_corr_max_ofdm_mrc_x1 = 270,
  853. .auto_corr_min_cck = 125,
  854. .auto_corr_max_cck = 200,
  855. .auto_corr_min_cck_mrc = 200,
  856. .auto_corr_max_cck_mrc = 400,
  857. .nrg_th_cck = 100,
  858. .nrg_th_ofdm = 100,
  859. };
  860. #endif
  861. /**
  862. * iwl4965_hw_set_hw_params
  863. *
  864. * Called when initializing driver
  865. */
  866. int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  867. {
  868. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  869. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  870. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  871. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  872. return -EINVAL;
  873. }
  874. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  875. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  876. priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
  877. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  878. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  879. if (priv->cfg->mod_params->amsdu_size_8K)
  880. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  881. else
  882. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  883. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  884. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  885. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  886. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  887. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  888. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  889. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  890. priv->hw_params.tx_chains_num = 2;
  891. priv->hw_params.rx_chains_num = 2;
  892. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  893. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  894. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  895. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  896. priv->hw_params.sens = &iwl4965_sensitivity;
  897. #endif
  898. return 0;
  899. }
  900. /* set card power command */
  901. static int iwl4965_set_power(struct iwl_priv *priv,
  902. void *cmd)
  903. {
  904. int ret = 0;
  905. ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
  906. sizeof(struct iwl4965_powertable_cmd),
  907. cmd, NULL);
  908. return ret;
  909. }
  910. int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  911. {
  912. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  913. return -EINVAL;
  914. }
  915. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  916. {
  917. s32 sign = 1;
  918. if (num < 0) {
  919. sign = -sign;
  920. num = -num;
  921. }
  922. if (denom < 0) {
  923. sign = -sign;
  924. denom = -denom;
  925. }
  926. *res = 1;
  927. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  928. return 1;
  929. }
  930. /**
  931. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  932. *
  933. * Determines power supply voltage compensation for txpower calculations.
  934. * Returns number of 1/2-dB steps to subtract from gain table index,
  935. * to compensate for difference between power supply voltage during
  936. * factory measurements, vs. current power supply voltage.
  937. *
  938. * Voltage indication is higher for lower voltage.
  939. * Lower voltage requires more gain (lower gain table index).
  940. */
  941. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  942. s32 current_voltage)
  943. {
  944. s32 comp = 0;
  945. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  946. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  947. return 0;
  948. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  949. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  950. if (current_voltage > eeprom_voltage)
  951. comp *= 2;
  952. if ((comp < -2) || (comp > 2))
  953. comp = 0;
  954. return comp;
  955. }
  956. static const struct iwl_channel_info *
  957. iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
  958. enum ieee80211_band band, u16 channel)
  959. {
  960. const struct iwl_channel_info *ch_info;
  961. ch_info = iwl_get_channel_info(priv, band, channel);
  962. if (!is_channel_valid(ch_info))
  963. return NULL;
  964. return ch_info;
  965. }
  966. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  967. {
  968. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  969. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  970. return CALIB_CH_GROUP_5;
  971. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  972. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  973. return CALIB_CH_GROUP_1;
  974. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  975. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  976. return CALIB_CH_GROUP_2;
  977. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  978. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  979. return CALIB_CH_GROUP_3;
  980. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  981. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  982. return CALIB_CH_GROUP_4;
  983. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  984. return -1;
  985. }
  986. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  987. {
  988. s32 b = -1;
  989. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  990. if (priv->calib_info->band_info[b].ch_from == 0)
  991. continue;
  992. if ((channel >= priv->calib_info->band_info[b].ch_from)
  993. && (channel <= priv->calib_info->band_info[b].ch_to))
  994. break;
  995. }
  996. return b;
  997. }
  998. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  999. {
  1000. s32 val;
  1001. if (x2 == x1)
  1002. return y1;
  1003. else {
  1004. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1005. return val + y2;
  1006. }
  1007. }
  1008. /**
  1009. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  1010. *
  1011. * Interpolates factory measurements from the two sample channels within a
  1012. * sub-band, to apply to channel of interest. Interpolation is proportional to
  1013. * differences in channel frequencies, which is proportional to differences
  1014. * in channel number.
  1015. */
  1016. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1017. struct iwl_eeprom_calib_ch_info *chan_info)
  1018. {
  1019. s32 s = -1;
  1020. u32 c;
  1021. u32 m;
  1022. const struct iwl_eeprom_calib_measure *m1;
  1023. const struct iwl_eeprom_calib_measure *m2;
  1024. struct iwl_eeprom_calib_measure *omeas;
  1025. u32 ch_i1;
  1026. u32 ch_i2;
  1027. s = iwl4965_get_sub_band(priv, channel);
  1028. if (s >= EEPROM_TX_POWER_BANDS) {
  1029. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1030. return -1;
  1031. }
  1032. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  1033. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  1034. chan_info->ch_num = (u8) channel;
  1035. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1036. channel, s, ch_i1, ch_i2);
  1037. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1038. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1039. m1 = &(priv->calib_info->band_info[s].ch1.
  1040. measurements[c][m]);
  1041. m2 = &(priv->calib_info->band_info[s].ch2.
  1042. measurements[c][m]);
  1043. omeas = &(chan_info->measurements[c][m]);
  1044. omeas->actual_pow =
  1045. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1046. m1->actual_pow,
  1047. ch_i2,
  1048. m2->actual_pow);
  1049. omeas->gain_idx =
  1050. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1051. m1->gain_idx, ch_i2,
  1052. m2->gain_idx);
  1053. omeas->temperature =
  1054. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1055. m1->temperature,
  1056. ch_i2,
  1057. m2->temperature);
  1058. omeas->pa_det =
  1059. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1060. m1->pa_det, ch_i2,
  1061. m2->pa_det);
  1062. IWL_DEBUG_TXPOWER
  1063. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1064. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1065. IWL_DEBUG_TXPOWER
  1066. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1067. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1068. IWL_DEBUG_TXPOWER
  1069. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1070. m1->pa_det, m2->pa_det, omeas->pa_det);
  1071. IWL_DEBUG_TXPOWER
  1072. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1073. m1->temperature, m2->temperature,
  1074. omeas->temperature);
  1075. }
  1076. }
  1077. return 0;
  1078. }
  1079. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1080. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1081. static s32 back_off_table[] = {
  1082. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1083. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1084. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1085. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1086. 10 /* CCK */
  1087. };
  1088. /* Thermal compensation values for txpower for various frequency ranges ...
  1089. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1090. static struct iwl4965_txpower_comp_entry {
  1091. s32 degrees_per_05db_a;
  1092. s32 degrees_per_05db_a_denom;
  1093. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1094. {9, 2}, /* group 0 5.2, ch 34-43 */
  1095. {4, 1}, /* group 1 5.2, ch 44-70 */
  1096. {4, 1}, /* group 2 5.2, ch 71-124 */
  1097. {4, 1}, /* group 3 5.2, ch 125-200 */
  1098. {3, 1} /* group 4 2.4, ch all */
  1099. };
  1100. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1101. {
  1102. if (!band) {
  1103. if ((rate_power_index & 7) <= 4)
  1104. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1105. }
  1106. return MIN_TX_GAIN_INDEX;
  1107. }
  1108. struct gain_entry {
  1109. u8 dsp;
  1110. u8 radio;
  1111. };
  1112. static const struct gain_entry gain_table[2][108] = {
  1113. /* 5.2GHz power gain index table */
  1114. {
  1115. {123, 0x3F}, /* highest txpower */
  1116. {117, 0x3F},
  1117. {110, 0x3F},
  1118. {104, 0x3F},
  1119. {98, 0x3F},
  1120. {110, 0x3E},
  1121. {104, 0x3E},
  1122. {98, 0x3E},
  1123. {110, 0x3D},
  1124. {104, 0x3D},
  1125. {98, 0x3D},
  1126. {110, 0x3C},
  1127. {104, 0x3C},
  1128. {98, 0x3C},
  1129. {110, 0x3B},
  1130. {104, 0x3B},
  1131. {98, 0x3B},
  1132. {110, 0x3A},
  1133. {104, 0x3A},
  1134. {98, 0x3A},
  1135. {110, 0x39},
  1136. {104, 0x39},
  1137. {98, 0x39},
  1138. {110, 0x38},
  1139. {104, 0x38},
  1140. {98, 0x38},
  1141. {110, 0x37},
  1142. {104, 0x37},
  1143. {98, 0x37},
  1144. {110, 0x36},
  1145. {104, 0x36},
  1146. {98, 0x36},
  1147. {110, 0x35},
  1148. {104, 0x35},
  1149. {98, 0x35},
  1150. {110, 0x34},
  1151. {104, 0x34},
  1152. {98, 0x34},
  1153. {110, 0x33},
  1154. {104, 0x33},
  1155. {98, 0x33},
  1156. {110, 0x32},
  1157. {104, 0x32},
  1158. {98, 0x32},
  1159. {110, 0x31},
  1160. {104, 0x31},
  1161. {98, 0x31},
  1162. {110, 0x30},
  1163. {104, 0x30},
  1164. {98, 0x30},
  1165. {110, 0x25},
  1166. {104, 0x25},
  1167. {98, 0x25},
  1168. {110, 0x24},
  1169. {104, 0x24},
  1170. {98, 0x24},
  1171. {110, 0x23},
  1172. {104, 0x23},
  1173. {98, 0x23},
  1174. {110, 0x22},
  1175. {104, 0x18},
  1176. {98, 0x18},
  1177. {110, 0x17},
  1178. {104, 0x17},
  1179. {98, 0x17},
  1180. {110, 0x16},
  1181. {104, 0x16},
  1182. {98, 0x16},
  1183. {110, 0x15},
  1184. {104, 0x15},
  1185. {98, 0x15},
  1186. {110, 0x14},
  1187. {104, 0x14},
  1188. {98, 0x14},
  1189. {110, 0x13},
  1190. {104, 0x13},
  1191. {98, 0x13},
  1192. {110, 0x12},
  1193. {104, 0x08},
  1194. {98, 0x08},
  1195. {110, 0x07},
  1196. {104, 0x07},
  1197. {98, 0x07},
  1198. {110, 0x06},
  1199. {104, 0x06},
  1200. {98, 0x06},
  1201. {110, 0x05},
  1202. {104, 0x05},
  1203. {98, 0x05},
  1204. {110, 0x04},
  1205. {104, 0x04},
  1206. {98, 0x04},
  1207. {110, 0x03},
  1208. {104, 0x03},
  1209. {98, 0x03},
  1210. {110, 0x02},
  1211. {104, 0x02},
  1212. {98, 0x02},
  1213. {110, 0x01},
  1214. {104, 0x01},
  1215. {98, 0x01},
  1216. {110, 0x00},
  1217. {104, 0x00},
  1218. {98, 0x00},
  1219. {93, 0x00},
  1220. {88, 0x00},
  1221. {83, 0x00},
  1222. {78, 0x00},
  1223. },
  1224. /* 2.4GHz power gain index table */
  1225. {
  1226. {110, 0x3f}, /* highest txpower */
  1227. {104, 0x3f},
  1228. {98, 0x3f},
  1229. {110, 0x3e},
  1230. {104, 0x3e},
  1231. {98, 0x3e},
  1232. {110, 0x3d},
  1233. {104, 0x3d},
  1234. {98, 0x3d},
  1235. {110, 0x3c},
  1236. {104, 0x3c},
  1237. {98, 0x3c},
  1238. {110, 0x3b},
  1239. {104, 0x3b},
  1240. {98, 0x3b},
  1241. {110, 0x3a},
  1242. {104, 0x3a},
  1243. {98, 0x3a},
  1244. {110, 0x39},
  1245. {104, 0x39},
  1246. {98, 0x39},
  1247. {110, 0x38},
  1248. {104, 0x38},
  1249. {98, 0x38},
  1250. {110, 0x37},
  1251. {104, 0x37},
  1252. {98, 0x37},
  1253. {110, 0x36},
  1254. {104, 0x36},
  1255. {98, 0x36},
  1256. {110, 0x35},
  1257. {104, 0x35},
  1258. {98, 0x35},
  1259. {110, 0x34},
  1260. {104, 0x34},
  1261. {98, 0x34},
  1262. {110, 0x33},
  1263. {104, 0x33},
  1264. {98, 0x33},
  1265. {110, 0x32},
  1266. {104, 0x32},
  1267. {98, 0x32},
  1268. {110, 0x31},
  1269. {104, 0x31},
  1270. {98, 0x31},
  1271. {110, 0x30},
  1272. {104, 0x30},
  1273. {98, 0x30},
  1274. {110, 0x6},
  1275. {104, 0x6},
  1276. {98, 0x6},
  1277. {110, 0x5},
  1278. {104, 0x5},
  1279. {98, 0x5},
  1280. {110, 0x4},
  1281. {104, 0x4},
  1282. {98, 0x4},
  1283. {110, 0x3},
  1284. {104, 0x3},
  1285. {98, 0x3},
  1286. {110, 0x2},
  1287. {104, 0x2},
  1288. {98, 0x2},
  1289. {110, 0x1},
  1290. {104, 0x1},
  1291. {98, 0x1},
  1292. {110, 0x0},
  1293. {104, 0x0},
  1294. {98, 0x0},
  1295. {97, 0},
  1296. {96, 0},
  1297. {95, 0},
  1298. {94, 0},
  1299. {93, 0},
  1300. {92, 0},
  1301. {91, 0},
  1302. {90, 0},
  1303. {89, 0},
  1304. {88, 0},
  1305. {87, 0},
  1306. {86, 0},
  1307. {85, 0},
  1308. {84, 0},
  1309. {83, 0},
  1310. {82, 0},
  1311. {81, 0},
  1312. {80, 0},
  1313. {79, 0},
  1314. {78, 0},
  1315. {77, 0},
  1316. {76, 0},
  1317. {75, 0},
  1318. {74, 0},
  1319. {73, 0},
  1320. {72, 0},
  1321. {71, 0},
  1322. {70, 0},
  1323. {69, 0},
  1324. {68, 0},
  1325. {67, 0},
  1326. {66, 0},
  1327. {65, 0},
  1328. {64, 0},
  1329. {63, 0},
  1330. {62, 0},
  1331. {61, 0},
  1332. {60, 0},
  1333. {59, 0},
  1334. }
  1335. };
  1336. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1337. u8 is_fat, u8 ctrl_chan_high,
  1338. struct iwl4965_tx_power_db *tx_power_tbl)
  1339. {
  1340. u8 saturation_power;
  1341. s32 target_power;
  1342. s32 user_target_power;
  1343. s32 power_limit;
  1344. s32 current_temp;
  1345. s32 reg_limit;
  1346. s32 current_regulatory;
  1347. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1348. int i;
  1349. int c;
  1350. const struct iwl_channel_info *ch_info = NULL;
  1351. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1352. const struct iwl_eeprom_calib_measure *measurement;
  1353. s16 voltage;
  1354. s32 init_voltage;
  1355. s32 voltage_compensation;
  1356. s32 degrees_per_05db_num;
  1357. s32 degrees_per_05db_denom;
  1358. s32 factory_temp;
  1359. s32 temperature_comp[2];
  1360. s32 factory_gain_index[2];
  1361. s32 factory_actual_pwr[2];
  1362. s32 power_index;
  1363. /* Sanity check requested level (dBm) */
  1364. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1365. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1366. priv->user_txpower_limit);
  1367. return -EINVAL;
  1368. }
  1369. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1370. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1371. priv->user_txpower_limit);
  1372. return -EINVAL;
  1373. }
  1374. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1375. * are used for indexing into txpower table) */
  1376. user_target_power = 2 * priv->user_txpower_limit;
  1377. /* Get current (RXON) channel, band, width */
  1378. ch_info =
  1379. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  1380. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1381. is_fat);
  1382. if (!ch_info)
  1383. return -EINVAL;
  1384. /* get txatten group, used to select 1) thermal txpower adjustment
  1385. * and 2) mimo txpower balance between Tx chains. */
  1386. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1387. if (txatten_grp < 0)
  1388. return -EINVAL;
  1389. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1390. channel, txatten_grp);
  1391. if (is_fat) {
  1392. if (ctrl_chan_high)
  1393. channel -= 2;
  1394. else
  1395. channel += 2;
  1396. }
  1397. /* hardware txpower limits ...
  1398. * saturation (clipping distortion) txpowers are in half-dBm */
  1399. if (band)
  1400. saturation_power = priv->calib_info->saturation_power24;
  1401. else
  1402. saturation_power = priv->calib_info->saturation_power52;
  1403. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1404. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1405. if (band)
  1406. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1407. else
  1408. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1409. }
  1410. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1411. * max_power_avg values are in dBm, convert * 2 */
  1412. if (is_fat)
  1413. reg_limit = ch_info->fat_max_power_avg * 2;
  1414. else
  1415. reg_limit = ch_info->max_power_avg * 2;
  1416. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1417. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1418. if (band)
  1419. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1420. else
  1421. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1422. }
  1423. /* Interpolate txpower calibration values for this channel,
  1424. * based on factory calibration tests on spaced channels. */
  1425. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1426. /* calculate tx gain adjustment based on power supply voltage */
  1427. voltage = priv->calib_info->voltage;
  1428. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1429. voltage_compensation =
  1430. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1431. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1432. init_voltage,
  1433. voltage, voltage_compensation);
  1434. /* get current temperature (Celsius) */
  1435. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1436. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1437. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1438. /* select thermal txpower adjustment params, based on channel group
  1439. * (same frequency group used for mimo txatten adjustment) */
  1440. degrees_per_05db_num =
  1441. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1442. degrees_per_05db_denom =
  1443. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1444. /* get per-chain txpower values from factory measurements */
  1445. for (c = 0; c < 2; c++) {
  1446. measurement = &ch_eeprom_info.measurements[c][1];
  1447. /* txgain adjustment (in half-dB steps) based on difference
  1448. * between factory and current temperature */
  1449. factory_temp = measurement->temperature;
  1450. iwl4965_math_div_round((current_temp - factory_temp) *
  1451. degrees_per_05db_denom,
  1452. degrees_per_05db_num,
  1453. &temperature_comp[c]);
  1454. factory_gain_index[c] = measurement->gain_idx;
  1455. factory_actual_pwr[c] = measurement->actual_pow;
  1456. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  1457. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  1458. "curr tmp %d, comp %d steps\n",
  1459. factory_temp, current_temp,
  1460. temperature_comp[c]);
  1461. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  1462. factory_gain_index[c],
  1463. factory_actual_pwr[c]);
  1464. }
  1465. /* for each of 33 bit-rates (including 1 for CCK) */
  1466. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1467. u8 is_mimo_rate;
  1468. union iwl4965_tx_power_dual_stream tx_power;
  1469. /* for mimo, reduce each chain's txpower by half
  1470. * (3dB, 6 steps), so total output power is regulatory
  1471. * compliant. */
  1472. if (i & 0x8) {
  1473. current_regulatory = reg_limit -
  1474. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1475. is_mimo_rate = 1;
  1476. } else {
  1477. current_regulatory = reg_limit;
  1478. is_mimo_rate = 0;
  1479. }
  1480. /* find txpower limit, either hardware or regulatory */
  1481. power_limit = saturation_power - back_off_table[i];
  1482. if (power_limit > current_regulatory)
  1483. power_limit = current_regulatory;
  1484. /* reduce user's txpower request if necessary
  1485. * for this rate on this channel */
  1486. target_power = user_target_power;
  1487. if (target_power > power_limit)
  1488. target_power = power_limit;
  1489. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  1490. i, saturation_power - back_off_table[i],
  1491. current_regulatory, user_target_power,
  1492. target_power);
  1493. /* for each of 2 Tx chains (radio transmitters) */
  1494. for (c = 0; c < 2; c++) {
  1495. s32 atten_value;
  1496. if (is_mimo_rate)
  1497. atten_value =
  1498. (s32)le32_to_cpu(priv->card_alive_init.
  1499. tx_atten[txatten_grp][c]);
  1500. else
  1501. atten_value = 0;
  1502. /* calculate index; higher index means lower txpower */
  1503. power_index = (u8) (factory_gain_index[c] -
  1504. (target_power -
  1505. factory_actual_pwr[c]) -
  1506. temperature_comp[c] -
  1507. voltage_compensation +
  1508. atten_value);
  1509. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  1510. power_index); */
  1511. if (power_index < get_min_power_index(i, band))
  1512. power_index = get_min_power_index(i, band);
  1513. /* adjust 5 GHz index to support negative indexes */
  1514. if (!band)
  1515. power_index += 9;
  1516. /* CCK, rate 32, reduce txpower for CCK */
  1517. if (i == POWER_TABLE_CCK_ENTRY)
  1518. power_index +=
  1519. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1520. /* stay within the table! */
  1521. if (power_index > 107) {
  1522. IWL_WARNING("txpower index %d > 107\n",
  1523. power_index);
  1524. power_index = 107;
  1525. }
  1526. if (power_index < 0) {
  1527. IWL_WARNING("txpower index %d < 0\n",
  1528. power_index);
  1529. power_index = 0;
  1530. }
  1531. /* fill txpower command for this rate/chain */
  1532. tx_power.s.radio_tx_gain[c] =
  1533. gain_table[band][power_index].radio;
  1534. tx_power.s.dsp_predis_atten[c] =
  1535. gain_table[band][power_index].dsp;
  1536. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  1537. "gain 0x%02x dsp %d\n",
  1538. c, atten_value, power_index,
  1539. tx_power.s.radio_tx_gain[c],
  1540. tx_power.s.dsp_predis_atten[c]);
  1541. }/* for each chain */
  1542. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1543. }/* for each rate */
  1544. return 0;
  1545. }
  1546. /**
  1547. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  1548. *
  1549. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1550. * The power limit is taken from priv->user_txpower_limit.
  1551. */
  1552. int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
  1553. {
  1554. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1555. int ret;
  1556. u8 band = 0;
  1557. u8 is_fat = 0;
  1558. u8 ctrl_chan_high = 0;
  1559. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1560. /* If this gets hit a lot, switch it to a BUG() and catch
  1561. * the stack trace to find out who is calling this during
  1562. * a scan. */
  1563. IWL_WARNING("TX Power requested while scanning!\n");
  1564. return -EAGAIN;
  1565. }
  1566. band = priv->band == IEEE80211_BAND_2GHZ;
  1567. is_fat = is_fat_channel(priv->active_rxon.flags);
  1568. if (is_fat &&
  1569. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1570. ctrl_chan_high = 1;
  1571. cmd.band = band;
  1572. cmd.channel = priv->active_rxon.channel;
  1573. ret = iwl4965_fill_txpower_tbl(priv, band,
  1574. le16_to_cpu(priv->active_rxon.channel),
  1575. is_fat, ctrl_chan_high, &cmd.tx_power);
  1576. if (ret)
  1577. goto out;
  1578. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1579. out:
  1580. return ret;
  1581. }
  1582. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1583. {
  1584. int ret = 0;
  1585. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1586. const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
  1587. const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
  1588. if ((rxon1->flags == rxon2->flags) &&
  1589. (rxon1->filter_flags == rxon2->filter_flags) &&
  1590. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1591. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1592. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1593. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1594. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1595. (rxon1->rx_chain == rxon2->rx_chain) &&
  1596. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1597. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  1598. return 0;
  1599. }
  1600. rxon_assoc.flags = priv->staging_rxon.flags;
  1601. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1602. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1603. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1604. rxon_assoc.reserved = 0;
  1605. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1606. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1607. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1608. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1609. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1610. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1611. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1612. if (ret)
  1613. return ret;
  1614. return ret;
  1615. }
  1616. int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1617. {
  1618. int rc;
  1619. u8 band = 0;
  1620. u8 is_fat = 0;
  1621. u8 ctrl_chan_high = 0;
  1622. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1623. const struct iwl_channel_info *ch_info;
  1624. band = priv->band == IEEE80211_BAND_2GHZ;
  1625. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1626. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1627. if (is_fat &&
  1628. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1629. ctrl_chan_high = 1;
  1630. cmd.band = band;
  1631. cmd.expect_beacon = 0;
  1632. cmd.channel = cpu_to_le16(channel);
  1633. cmd.rxon_flags = priv->active_rxon.flags;
  1634. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1635. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1636. if (ch_info)
  1637. cmd.expect_beacon = is_channel_radar(ch_info);
  1638. else
  1639. cmd.expect_beacon = 1;
  1640. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1641. ctrl_chan_high, &cmd.tx_power);
  1642. if (rc) {
  1643. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  1644. return rc;
  1645. }
  1646. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1647. return rc;
  1648. }
  1649. #define RTS_HCCA_RETRY_LIMIT 3
  1650. #define RTS_DFAULT_RETRY_LIMIT 60
  1651. void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
  1652. struct iwl_cmd *cmd,
  1653. struct ieee80211_tx_control *ctrl,
  1654. struct ieee80211_hdr *hdr, int sta_id,
  1655. int is_hcca)
  1656. {
  1657. struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
  1658. u8 rts_retry_limit = 0;
  1659. u8 data_retry_limit = 0;
  1660. u16 fc = le16_to_cpu(hdr->frame_control);
  1661. u8 rate_plcp;
  1662. u16 rate_flags = 0;
  1663. int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
  1664. rate_plcp = iwl4965_rates[rate_idx].plcp;
  1665. rts_retry_limit = (is_hcca) ?
  1666. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  1667. if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
  1668. rate_flags |= RATE_MCS_CCK_MSK;
  1669. if (ieee80211_is_probe_response(fc)) {
  1670. data_retry_limit = 3;
  1671. if (data_retry_limit < rts_retry_limit)
  1672. rts_retry_limit = data_retry_limit;
  1673. } else
  1674. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  1675. if (priv->data_retry_limit != -1)
  1676. data_retry_limit = priv->data_retry_limit;
  1677. if (ieee80211_is_data(fc)) {
  1678. tx->initial_rate_index = 0;
  1679. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  1680. } else {
  1681. switch (fc & IEEE80211_FCTL_STYPE) {
  1682. case IEEE80211_STYPE_AUTH:
  1683. case IEEE80211_STYPE_DEAUTH:
  1684. case IEEE80211_STYPE_ASSOC_REQ:
  1685. case IEEE80211_STYPE_REASSOC_REQ:
  1686. if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
  1687. tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1688. tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
  1689. }
  1690. break;
  1691. default:
  1692. break;
  1693. }
  1694. /* Alternate between antenna A and B for successive frames */
  1695. if (priv->use_ant_b_for_management_frame) {
  1696. priv->use_ant_b_for_management_frame = 0;
  1697. rate_flags |= RATE_MCS_ANT_B_MSK;
  1698. } else {
  1699. priv->use_ant_b_for_management_frame = 1;
  1700. rate_flags |= RATE_MCS_ANT_A_MSK;
  1701. }
  1702. }
  1703. tx->rts_retry_limit = rts_retry_limit;
  1704. tx->data_retry_limit = data_retry_limit;
  1705. tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
  1706. }
  1707. int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
  1708. {
  1709. struct iwl4965_shared *s = priv->shared_virt;
  1710. return le32_to_cpu(s->rb_closed) & 0xFFF;
  1711. }
  1712. int iwl4965_hw_get_temperature(struct iwl_priv *priv)
  1713. {
  1714. return priv->temperature;
  1715. }
  1716. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  1717. struct iwl4965_frame *frame, u8 rate)
  1718. {
  1719. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  1720. unsigned int frame_size;
  1721. tx_beacon_cmd = &frame->u.beacon;
  1722. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  1723. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  1724. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1725. frame_size = iwl4965_fill_beacon_frame(priv,
  1726. tx_beacon_cmd->frame,
  1727. iwl4965_broadcast_addr,
  1728. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  1729. BUG_ON(frame_size > MAX_MPDU_SIZE);
  1730. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  1731. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  1732. tx_beacon_cmd->tx.rate_n_flags =
  1733. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  1734. else
  1735. tx_beacon_cmd->tx.rate_n_flags =
  1736. iwl4965_hw_set_rate_n_flags(rate, 0);
  1737. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  1738. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  1739. return (sizeof(*tx_beacon_cmd) + frame_size);
  1740. }
  1741. int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
  1742. dma_addr_t addr, u16 len)
  1743. {
  1744. int index, is_odd;
  1745. struct iwl_tfd_frame *tfd = ptr;
  1746. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  1747. /* Each TFD can point to a maximum 20 Tx buffers */
  1748. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  1749. IWL_ERROR("Error can not send more than %d chunks\n",
  1750. MAX_NUM_OF_TBS);
  1751. return -EINVAL;
  1752. }
  1753. index = num_tbs / 2;
  1754. is_odd = num_tbs & 0x1;
  1755. if (!is_odd) {
  1756. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  1757. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  1758. iwl_get_dma_hi_address(addr));
  1759. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  1760. } else {
  1761. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  1762. (u32) (addr & 0xffff));
  1763. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  1764. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  1765. }
  1766. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  1767. return 0;
  1768. }
  1769. static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
  1770. {
  1771. priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
  1772. sizeof(struct iwl4965_shared),
  1773. &priv->shared_phys);
  1774. if (!priv->shared_virt)
  1775. return -ENOMEM;
  1776. memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
  1777. return 0;
  1778. }
  1779. static void iwl4965_free_shared_mem(struct iwl_priv *priv)
  1780. {
  1781. if (priv->shared_virt)
  1782. pci_free_consistent(priv->pci_dev,
  1783. sizeof(struct iwl4965_shared),
  1784. priv->shared_virt,
  1785. priv->shared_phys);
  1786. }
  1787. /**
  1788. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1789. */
  1790. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1791. struct iwl4965_tx_queue *txq,
  1792. u16 byte_cnt)
  1793. {
  1794. int len;
  1795. int txq_id = txq->q.id;
  1796. struct iwl4965_shared *shared_data = priv->shared_virt;
  1797. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1798. /* Set up byte count within first 256 entries */
  1799. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1800. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  1801. /* If within first 64 entries, duplicate at end */
  1802. if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
  1803. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  1804. tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
  1805. byte_cnt, len);
  1806. }
  1807. /**
  1808. * sign_extend - Sign extend a value using specified bit as sign-bit
  1809. *
  1810. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1811. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1812. *
  1813. * @param oper value to sign extend
  1814. * @param index 0 based bit index (0<=index<32) to sign bit
  1815. */
  1816. static s32 sign_extend(u32 oper, int index)
  1817. {
  1818. u8 shift = 31 - index;
  1819. return (s32)(oper << shift) >> shift;
  1820. }
  1821. /**
  1822. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  1823. * @statistics: Provides the temperature reading from the uCode
  1824. *
  1825. * A return of <0 indicates bogus data in the statistics
  1826. */
  1827. int iwl4965_get_temperature(const struct iwl_priv *priv)
  1828. {
  1829. s32 temperature;
  1830. s32 vt;
  1831. s32 R1, R2, R3;
  1832. u32 R4;
  1833. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1834. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1835. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  1836. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1837. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1838. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1839. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1840. } else {
  1841. IWL_DEBUG_TEMP("Running temperature calibration\n");
  1842. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1843. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1844. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1845. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1846. }
  1847. /*
  1848. * Temperature is only 23 bits, so sign extend out to 32.
  1849. *
  1850. * NOTE If we haven't received a statistics notification yet
  1851. * with an updated temperature, use R4 provided to us in the
  1852. * "initialize" ALIVE response.
  1853. */
  1854. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1855. vt = sign_extend(R4, 23);
  1856. else
  1857. vt = sign_extend(
  1858. le32_to_cpu(priv->statistics.general.temperature), 23);
  1859. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  1860. R1, R2, R3, vt);
  1861. if (R3 == R1) {
  1862. IWL_ERROR("Calibration conflict R1 == R3\n");
  1863. return -1;
  1864. }
  1865. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1866. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1867. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1868. temperature /= (R3 - R1);
  1869. temperature = (temperature * 97) / 100 +
  1870. TEMPERATURE_CALIB_KELVIN_OFFSET;
  1871. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  1872. KELVIN_TO_CELSIUS(temperature));
  1873. return temperature;
  1874. }
  1875. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1876. #define IWL_TEMPERATURE_THRESHOLD 3
  1877. /**
  1878. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1879. *
  1880. * If the temperature changed has changed sufficiently, then a recalibration
  1881. * is needed.
  1882. *
  1883. * Assumes caller will replace priv->last_temperature once calibration
  1884. * executed.
  1885. */
  1886. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1887. {
  1888. int temp_diff;
  1889. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1890. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  1891. return 0;
  1892. }
  1893. temp_diff = priv->temperature - priv->last_temperature;
  1894. /* get absolute value */
  1895. if (temp_diff < 0) {
  1896. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  1897. temp_diff = -temp_diff;
  1898. } else if (temp_diff == 0)
  1899. IWL_DEBUG_POWER("Same temp, \n");
  1900. else
  1901. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  1902. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1903. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  1904. return 0;
  1905. }
  1906. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  1907. return 1;
  1908. }
  1909. /* Calculate noise level, based on measurements during network silence just
  1910. * before arriving beacon. This measurement can be done only if we know
  1911. * exactly when to expect beacons, therefore only when we're associated. */
  1912. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  1913. {
  1914. struct statistics_rx_non_phy *rx_info
  1915. = &(priv->statistics.rx.general);
  1916. int num_active_rx = 0;
  1917. int total_silence = 0;
  1918. int bcn_silence_a =
  1919. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  1920. int bcn_silence_b =
  1921. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  1922. int bcn_silence_c =
  1923. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  1924. if (bcn_silence_a) {
  1925. total_silence += bcn_silence_a;
  1926. num_active_rx++;
  1927. }
  1928. if (bcn_silence_b) {
  1929. total_silence += bcn_silence_b;
  1930. num_active_rx++;
  1931. }
  1932. if (bcn_silence_c) {
  1933. total_silence += bcn_silence_c;
  1934. num_active_rx++;
  1935. }
  1936. /* Average among active antennas */
  1937. if (num_active_rx)
  1938. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  1939. else
  1940. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1941. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  1942. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  1943. priv->last_rx_noise);
  1944. }
  1945. void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
  1946. struct iwl_rx_mem_buffer *rxb)
  1947. {
  1948. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1949. int change;
  1950. s32 temp;
  1951. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  1952. (int)sizeof(priv->statistics), pkt->len);
  1953. change = ((priv->statistics.general.temperature !=
  1954. pkt->u.stats.general.temperature) ||
  1955. ((priv->statistics.flag &
  1956. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  1957. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  1958. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  1959. set_bit(STATUS_STATISTICS, &priv->status);
  1960. /* Reschedule the statistics timer to occur in
  1961. * REG_RECALIB_PERIOD seconds to ensure we get a
  1962. * thermal update even if the uCode doesn't give
  1963. * us one */
  1964. mod_timer(&priv->statistics_periodic, jiffies +
  1965. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  1966. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1967. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  1968. iwl4965_rx_calc_noise(priv);
  1969. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  1970. queue_work(priv->workqueue, &priv->sensitivity_work);
  1971. #endif
  1972. }
  1973. iwl_leds_background(priv);
  1974. /* If the hardware hasn't reported a change in
  1975. * temperature then don't bother computing a
  1976. * calibrated temperature value */
  1977. if (!change)
  1978. return;
  1979. temp = iwl4965_get_temperature(priv);
  1980. if (temp < 0)
  1981. return;
  1982. if (priv->temperature != temp) {
  1983. if (priv->temperature)
  1984. IWL_DEBUG_TEMP("Temperature changed "
  1985. "from %dC to %dC\n",
  1986. KELVIN_TO_CELSIUS(priv->temperature),
  1987. KELVIN_TO_CELSIUS(temp));
  1988. else
  1989. IWL_DEBUG_TEMP("Temperature "
  1990. "initialized to %dC\n",
  1991. KELVIN_TO_CELSIUS(temp));
  1992. }
  1993. priv->temperature = temp;
  1994. set_bit(STATUS_TEMPERATURE, &priv->status);
  1995. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1996. iwl4965_is_temp_calib_needed(priv))
  1997. queue_work(priv->workqueue, &priv->txpower_work);
  1998. }
  1999. static void iwl4965_add_radiotap(struct iwl_priv *priv,
  2000. struct sk_buff *skb,
  2001. struct iwl4965_rx_phy_res *rx_start,
  2002. struct ieee80211_rx_status *stats,
  2003. u32 ampdu_status)
  2004. {
  2005. s8 signal = stats->ssi;
  2006. s8 noise = 0;
  2007. int rate = stats->rate_idx;
  2008. u64 tsf = stats->mactime;
  2009. __le16 antenna;
  2010. __le16 phy_flags_hw = rx_start->phy_flags;
  2011. struct iwl4965_rt_rx_hdr {
  2012. struct ieee80211_radiotap_header rt_hdr;
  2013. __le64 rt_tsf; /* TSF */
  2014. u8 rt_flags; /* radiotap packet flags */
  2015. u8 rt_rate; /* rate in 500kb/s */
  2016. __le16 rt_channelMHz; /* channel in MHz */
  2017. __le16 rt_chbitmask; /* channel bitfield */
  2018. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  2019. s8 rt_dbmnoise;
  2020. u8 rt_antenna; /* antenna number */
  2021. } __attribute__ ((packed)) *iwl4965_rt;
  2022. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  2023. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  2024. if (net_ratelimit())
  2025. printk(KERN_ERR "not enough headroom [%d] for "
  2026. "radiotap head [%zd]\n",
  2027. skb_headroom(skb), sizeof(*iwl4965_rt));
  2028. return;
  2029. }
  2030. /* put radiotap header in front of 802.11 header and data */
  2031. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  2032. /* initialise radiotap header */
  2033. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2034. iwl4965_rt->rt_hdr.it_pad = 0;
  2035. /* total header + data */
  2036. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  2037. &iwl4965_rt->rt_hdr.it_len);
  2038. /* Indicate all the fields we add to the radiotap header */
  2039. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2040. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2041. (1 << IEEE80211_RADIOTAP_RATE) |
  2042. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2043. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2044. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2045. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  2046. &iwl4965_rt->rt_hdr.it_present);
  2047. /* Zero the flags, we'll add to them as we go */
  2048. iwl4965_rt->rt_flags = 0;
  2049. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  2050. iwl4965_rt->rt_dbmsignal = signal;
  2051. iwl4965_rt->rt_dbmnoise = noise;
  2052. /* Convert the channel frequency and set the flags */
  2053. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  2054. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2055. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2056. IEEE80211_CHAN_5GHZ),
  2057. &iwl4965_rt->rt_chbitmask);
  2058. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2059. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  2060. IEEE80211_CHAN_2GHZ),
  2061. &iwl4965_rt->rt_chbitmask);
  2062. else /* 802.11g */
  2063. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2064. IEEE80211_CHAN_2GHZ),
  2065. &iwl4965_rt->rt_chbitmask);
  2066. if (rate == -1)
  2067. iwl4965_rt->rt_rate = 0;
  2068. else
  2069. iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
  2070. /*
  2071. * "antenna number"
  2072. *
  2073. * It seems that the antenna field in the phy flags value
  2074. * is actually a bitfield. This is undefined by radiotap,
  2075. * it wants an actual antenna number but I always get "7"
  2076. * for most legacy frames I receive indicating that the
  2077. * same frame was received on all three RX chains.
  2078. *
  2079. * I think this field should be removed in favour of a
  2080. * new 802.11n radiotap field "RX chains" that is defined
  2081. * as a bitmask.
  2082. */
  2083. antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
  2084. iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
  2085. /* set the preamble flag if appropriate */
  2086. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2087. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2088. stats->flag |= RX_FLAG_RADIOTAP;
  2089. }
  2090. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  2091. {
  2092. /* 0 - mgmt, 1 - cnt, 2 - data */
  2093. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  2094. priv->rx_stats[idx].cnt++;
  2095. priv->rx_stats[idx].bytes += len;
  2096. }
  2097. /*
  2098. * returns non-zero if packet should be dropped
  2099. */
  2100. static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
  2101. struct ieee80211_hdr *hdr,
  2102. u32 decrypt_res,
  2103. struct ieee80211_rx_status *stats)
  2104. {
  2105. u16 fc = le16_to_cpu(hdr->frame_control);
  2106. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2107. return 0;
  2108. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2109. return 0;
  2110. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2111. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2112. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2113. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2114. * Decryption will be done in SW. */
  2115. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2116. RX_RES_STATUS_BAD_KEY_TTAK)
  2117. break;
  2118. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2119. RX_RES_STATUS_BAD_ICV_MIC) {
  2120. /* bad ICV, the packet is destroyed since the
  2121. * decryption is inplace, drop it */
  2122. IWL_DEBUG_RX("Packet destroyed\n");
  2123. return -1;
  2124. }
  2125. case RX_RES_STATUS_SEC_TYPE_WEP:
  2126. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2127. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2128. RX_RES_STATUS_DECRYPT_OK) {
  2129. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2130. stats->flag |= RX_FLAG_DECRYPTED;
  2131. }
  2132. break;
  2133. default:
  2134. break;
  2135. }
  2136. return 0;
  2137. }
  2138. static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  2139. {
  2140. u32 decrypt_out = 0;
  2141. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  2142. RX_RES_STATUS_STATION_FOUND)
  2143. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  2144. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  2145. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  2146. /* packet was not encrypted */
  2147. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2148. RX_RES_STATUS_SEC_TYPE_NONE)
  2149. return decrypt_out;
  2150. /* packet was encrypted with unknown alg */
  2151. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  2152. RX_RES_STATUS_SEC_TYPE_ERR)
  2153. return decrypt_out;
  2154. /* decryption was not done in HW */
  2155. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  2156. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  2157. return decrypt_out;
  2158. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  2159. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2160. /* alg is CCM: check MIC only */
  2161. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  2162. /* Bad MIC */
  2163. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2164. else
  2165. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2166. break;
  2167. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2168. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  2169. /* Bad TTAK */
  2170. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  2171. break;
  2172. }
  2173. /* fall through if TTAK OK */
  2174. default:
  2175. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  2176. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  2177. else
  2178. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  2179. break;
  2180. };
  2181. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  2182. decrypt_in, decrypt_out);
  2183. return decrypt_out;
  2184. }
  2185. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  2186. int include_phy,
  2187. struct iwl_rx_mem_buffer *rxb,
  2188. struct ieee80211_rx_status *stats)
  2189. {
  2190. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2191. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2192. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  2193. struct ieee80211_hdr *hdr;
  2194. u16 len;
  2195. __le32 *rx_end;
  2196. unsigned int skblen;
  2197. u32 ampdu_status;
  2198. u32 ampdu_status_legacy;
  2199. if (!include_phy && priv->last_phy_res[0])
  2200. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2201. if (!rx_start) {
  2202. IWL_ERROR("MPDU frame without a PHY data\n");
  2203. return;
  2204. }
  2205. if (include_phy) {
  2206. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  2207. rx_start->cfg_phy_cnt);
  2208. len = le16_to_cpu(rx_start->byte_count);
  2209. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2210. sizeof(struct iwl4965_rx_phy_res) +
  2211. rx_start->cfg_phy_cnt + len);
  2212. } else {
  2213. struct iwl4965_rx_mpdu_res_start *amsdu =
  2214. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2215. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2216. sizeof(struct iwl4965_rx_mpdu_res_start));
  2217. len = le16_to_cpu(amsdu->byte_count);
  2218. rx_start->byte_count = amsdu->byte_count;
  2219. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2220. }
  2221. /* In monitor mode allow 802.11 ACk frames (10 bytes) */
  2222. if (len > priv->hw_params.max_pkt_size ||
  2223. len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
  2224. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  2225. return;
  2226. }
  2227. ampdu_status = le32_to_cpu(*rx_end);
  2228. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2229. if (!include_phy) {
  2230. /* New status scheme, need to translate */
  2231. ampdu_status_legacy = ampdu_status;
  2232. ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
  2233. }
  2234. /* start from MAC */
  2235. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2236. skb_put(rxb->skb, len); /* end where data ends */
  2237. /* We only process data packets if the interface is open */
  2238. if (unlikely(!priv->is_open)) {
  2239. IWL_DEBUG_DROP_LIMIT
  2240. ("Dropping packet while interface is not open.\n");
  2241. return;
  2242. }
  2243. stats->flag = 0;
  2244. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2245. /* in case of HW accelerated crypto and bad decryption, drop */
  2246. if (!priv->hw_params.sw_crypto &&
  2247. iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  2248. return;
  2249. if (priv->add_radiotap)
  2250. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2251. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  2252. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2253. priv->alloc_rxb_skb--;
  2254. rxb->skb = NULL;
  2255. }
  2256. /* Calc max signal level (dBm) among 3 possible receivers */
  2257. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  2258. struct iwl4965_rx_phy_res *rx_resp)
  2259. {
  2260. /* data from PHY/DSP regarding signal strength, etc.,
  2261. * contents are always there, not configurable by host. */
  2262. struct iwl4965_rx_non_cfg_phy *ncphy =
  2263. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2264. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2265. >> IWL_AGC_DB_POS;
  2266. u32 valid_antennae =
  2267. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2268. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2269. u8 max_rssi = 0;
  2270. u32 i;
  2271. /* Find max rssi among 3 possible receivers.
  2272. * These values are measured by the digital signal processor (DSP).
  2273. * They should stay fairly constant even as the signal strength varies,
  2274. * if the radio's automatic gain control (AGC) is working right.
  2275. * AGC value (see below) will provide the "interesting" info. */
  2276. for (i = 0; i < 3; i++)
  2277. if (valid_antennae & (1 << i))
  2278. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2279. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2280. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2281. max_rssi, agc);
  2282. /* dBm = max_rssi dB - agc dB - constant.
  2283. * Higher AGC (higher radio gain) means lower signal. */
  2284. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2285. }
  2286. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  2287. {
  2288. unsigned long flags;
  2289. spin_lock_irqsave(&priv->sta_lock, flags);
  2290. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2291. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2292. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2293. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2294. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2295. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2296. }
  2297. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  2298. {
  2299. /* FIXME: need locking over ps_status ??? */
  2300. u8 sta_id = iwl_find_station(priv, addr);
  2301. if (sta_id != IWL_INVALID_STATION) {
  2302. u8 sta_awake = priv->stations[sta_id].
  2303. ps_status == STA_PS_STATUS_WAKE;
  2304. if (sta_awake && ps_bit)
  2305. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  2306. else if (!sta_awake && !ps_bit) {
  2307. iwl4965_sta_modify_ps_wake(priv, sta_id);
  2308. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  2309. }
  2310. }
  2311. }
  2312. #ifdef CONFIG_IWLWIFI_DEBUG
  2313. /**
  2314. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  2315. *
  2316. * You may hack this function to show different aspects of received frames,
  2317. * including selective frame dumps.
  2318. * group100 parameter selects whether to show 1 out of 100 good frames.
  2319. *
  2320. * TODO: This was originally written for 3945, need to audit for
  2321. * proper operation with 4965.
  2322. */
  2323. static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2324. struct iwl_rx_packet *pkt,
  2325. struct ieee80211_hdr *header, int group100)
  2326. {
  2327. u32 to_us;
  2328. u32 print_summary = 0;
  2329. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  2330. u32 hundred = 0;
  2331. u32 dataframe = 0;
  2332. u16 fc;
  2333. u16 seq_ctl;
  2334. u16 channel;
  2335. u16 phy_flags;
  2336. int rate_sym;
  2337. u16 length;
  2338. u16 status;
  2339. u16 bcn_tmr;
  2340. u32 tsf_low;
  2341. u64 tsf;
  2342. u8 rssi;
  2343. u8 agc;
  2344. u16 sig_avg;
  2345. u16 noise_diff;
  2346. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  2347. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  2348. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  2349. u8 *data = IWL_RX_DATA(pkt);
  2350. if (likely(!(priv->debug_level & IWL_DL_RX)))
  2351. return;
  2352. /* MAC header */
  2353. fc = le16_to_cpu(header->frame_control);
  2354. seq_ctl = le16_to_cpu(header->seq_ctrl);
  2355. /* metadata */
  2356. channel = le16_to_cpu(rx_hdr->channel);
  2357. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  2358. rate_sym = rx_hdr->rate;
  2359. length = le16_to_cpu(rx_hdr->len);
  2360. /* end-of-frame status and timestamp */
  2361. status = le32_to_cpu(rx_end->status);
  2362. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  2363. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  2364. tsf = le64_to_cpu(rx_end->timestamp);
  2365. /* signal statistics */
  2366. rssi = rx_stats->rssi;
  2367. agc = rx_stats->agc;
  2368. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  2369. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  2370. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  2371. /* if data frame is to us and all is good,
  2372. * (optionally) print summary for only 1 out of every 100 */
  2373. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  2374. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  2375. dataframe = 1;
  2376. if (!group100)
  2377. print_summary = 1; /* print each frame */
  2378. else if (priv->framecnt_to_us < 100) {
  2379. priv->framecnt_to_us++;
  2380. print_summary = 0;
  2381. } else {
  2382. priv->framecnt_to_us = 0;
  2383. print_summary = 1;
  2384. hundred = 1;
  2385. }
  2386. } else {
  2387. /* print summary for all other frames */
  2388. print_summary = 1;
  2389. }
  2390. if (print_summary) {
  2391. char *title;
  2392. int rate_idx;
  2393. u32 bitrate;
  2394. if (hundred)
  2395. title = "100Frames";
  2396. else if (fc & IEEE80211_FCTL_RETRY)
  2397. title = "Retry";
  2398. else if (ieee80211_is_assoc_response(fc))
  2399. title = "AscRsp";
  2400. else if (ieee80211_is_reassoc_response(fc))
  2401. title = "RasRsp";
  2402. else if (ieee80211_is_probe_response(fc)) {
  2403. title = "PrbRsp";
  2404. print_dump = 1; /* dump frame contents */
  2405. } else if (ieee80211_is_beacon(fc)) {
  2406. title = "Beacon";
  2407. print_dump = 1; /* dump frame contents */
  2408. } else if (ieee80211_is_atim(fc))
  2409. title = "ATIM";
  2410. else if (ieee80211_is_auth(fc))
  2411. title = "Auth";
  2412. else if (ieee80211_is_deauth(fc))
  2413. title = "DeAuth";
  2414. else if (ieee80211_is_disassoc(fc))
  2415. title = "DisAssoc";
  2416. else
  2417. title = "Frame";
  2418. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  2419. if (unlikely(rate_idx == -1))
  2420. bitrate = 0;
  2421. else
  2422. bitrate = iwl4965_rates[rate_idx].ieee / 2;
  2423. /* print frame summary.
  2424. * MAC addresses show just the last byte (for brevity),
  2425. * but you can hack it to show more, if you'd like to. */
  2426. if (dataframe)
  2427. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  2428. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  2429. title, fc, header->addr1[5],
  2430. length, rssi, channel, bitrate);
  2431. else {
  2432. /* src/dst addresses assume managed mode */
  2433. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  2434. "src=0x%02x, rssi=%u, tim=%lu usec, "
  2435. "phy=0x%02x, chnl=%d\n",
  2436. title, fc, header->addr1[5],
  2437. header->addr3[5], rssi,
  2438. tsf_low - priv->scan_start_tsf,
  2439. phy_flags, channel);
  2440. }
  2441. }
  2442. if (print_dump)
  2443. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  2444. }
  2445. #else
  2446. static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
  2447. struct iwl_rx_packet *pkt,
  2448. struct ieee80211_hdr *header,
  2449. int group100)
  2450. {
  2451. }
  2452. #endif
  2453. /* Called for REPLY_RX (legacy ABG frames), or
  2454. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  2455. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  2456. struct iwl_rx_mem_buffer *rxb)
  2457. {
  2458. struct ieee80211_hdr *header;
  2459. struct ieee80211_rx_status rx_status;
  2460. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2461. /* Use phy data (Rx signal strength, etc.) contained within
  2462. * this rx packet for legacy frames,
  2463. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  2464. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  2465. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2466. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  2467. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2468. __le32 *rx_end;
  2469. unsigned int len = 0;
  2470. u16 fc;
  2471. u8 network_packet;
  2472. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  2473. rx_status.freq =
  2474. ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
  2475. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  2476. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  2477. rx_status.rate_idx =
  2478. iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  2479. if (rx_status.band == IEEE80211_BAND_5GHZ)
  2480. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  2481. rx_status.antenna = 0;
  2482. rx_status.flag = 0;
  2483. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  2484. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  2485. rx_start->cfg_phy_cnt);
  2486. return;
  2487. }
  2488. if (!include_phy) {
  2489. if (priv->last_phy_res[0])
  2490. rx_start = (struct iwl4965_rx_phy_res *)
  2491. &priv->last_phy_res[1];
  2492. else
  2493. rx_start = NULL;
  2494. }
  2495. if (!rx_start) {
  2496. IWL_ERROR("MPDU frame without a PHY data\n");
  2497. return;
  2498. }
  2499. if (include_phy) {
  2500. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  2501. + rx_start->cfg_phy_cnt);
  2502. len = le16_to_cpu(rx_start->byte_count);
  2503. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  2504. sizeof(struct iwl4965_rx_phy_res) + len);
  2505. } else {
  2506. struct iwl4965_rx_mpdu_res_start *amsdu =
  2507. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2508. header = (void *)(pkt->u.raw +
  2509. sizeof(struct iwl4965_rx_mpdu_res_start));
  2510. len = le16_to_cpu(amsdu->byte_count);
  2511. rx_end = (__le32 *) (pkt->u.raw +
  2512. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  2513. }
  2514. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  2515. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  2516. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  2517. le32_to_cpu(*rx_end));
  2518. return;
  2519. }
  2520. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  2521. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  2522. rx_status.ssi = iwl4965_calc_rssi(priv, rx_start);
  2523. /* Meaningful noise values are available only from beacon statistics,
  2524. * which are gathered only when associated, and indicate noise
  2525. * only for the associated network channel ...
  2526. * Ignore these noise values while scanning (other channels) */
  2527. if (iwl_is_associated(priv) &&
  2528. !test_bit(STATUS_SCANNING, &priv->status)) {
  2529. rx_status.noise = priv->last_rx_noise;
  2530. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
  2531. rx_status.noise);
  2532. } else {
  2533. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2534. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
  2535. }
  2536. /* Reset beacon noise level if not associated. */
  2537. if (!iwl_is_associated(priv))
  2538. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2539. /* Set "1" to report good data frames in groups of 100 */
  2540. /* FIXME: need to optimze the call: */
  2541. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  2542. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  2543. rx_status.ssi, rx_status.noise, rx_status.signal,
  2544. (unsigned long long)rx_status.mactime);
  2545. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2546. iwl4965_handle_data_packet(priv, 1, include_phy,
  2547. rxb, &rx_status);
  2548. return;
  2549. }
  2550. network_packet = iwl4965_is_network_packet(priv, header);
  2551. if (network_packet) {
  2552. priv->last_rx_rssi = rx_status.ssi;
  2553. priv->last_beacon_time = priv->ucode_beacon_time;
  2554. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  2555. }
  2556. fc = le16_to_cpu(header->frame_control);
  2557. switch (fc & IEEE80211_FCTL_FTYPE) {
  2558. case IEEE80211_FTYPE_MGMT:
  2559. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2560. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2561. header->addr2);
  2562. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  2563. break;
  2564. case IEEE80211_FTYPE_CTL:
  2565. #ifdef CONFIG_IWL4965_HT
  2566. switch (fc & IEEE80211_FCTL_STYPE) {
  2567. case IEEE80211_STYPE_BACK_REQ:
  2568. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  2569. iwl4965_handle_data_packet(priv, 0, include_phy,
  2570. rxb, &rx_status);
  2571. break;
  2572. default:
  2573. break;
  2574. }
  2575. #endif
  2576. break;
  2577. case IEEE80211_FTYPE_DATA: {
  2578. DECLARE_MAC_BUF(mac1);
  2579. DECLARE_MAC_BUF(mac2);
  2580. DECLARE_MAC_BUF(mac3);
  2581. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  2582. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  2583. header->addr2);
  2584. if (unlikely(!network_packet))
  2585. IWL_DEBUG_DROP("Dropping (non network): "
  2586. "%s, %s, %s\n",
  2587. print_mac(mac1, header->addr1),
  2588. print_mac(mac2, header->addr2),
  2589. print_mac(mac3, header->addr3));
  2590. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  2591. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  2592. print_mac(mac1, header->addr1),
  2593. print_mac(mac2, header->addr2),
  2594. print_mac(mac3, header->addr3));
  2595. else
  2596. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  2597. &rx_status);
  2598. break;
  2599. }
  2600. default:
  2601. break;
  2602. }
  2603. }
  2604. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  2605. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  2606. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  2607. struct iwl_rx_mem_buffer *rxb)
  2608. {
  2609. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2610. priv->last_phy_res[0] = 1;
  2611. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  2612. sizeof(struct iwl4965_rx_phy_res));
  2613. }
  2614. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  2615. struct iwl_rx_mem_buffer *rxb)
  2616. {
  2617. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  2618. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2619. struct iwl4965_missed_beacon_notif *missed_beacon;
  2620. missed_beacon = &pkt->u.missed_beacon;
  2621. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  2622. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  2623. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  2624. le32_to_cpu(missed_beacon->total_missed_becons),
  2625. le32_to_cpu(missed_beacon->num_recvd_beacons),
  2626. le32_to_cpu(missed_beacon->num_expected_beacons));
  2627. if (!test_bit(STATUS_SCANNING, &priv->status))
  2628. iwl_init_sensitivity(priv);
  2629. }
  2630. #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
  2631. }
  2632. #ifdef CONFIG_IWL4965_HT
  2633. /**
  2634. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  2635. */
  2636. static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  2637. int sta_id, int tid)
  2638. {
  2639. unsigned long flags;
  2640. /* Remove "disable" flag, to enable Tx for this TID */
  2641. spin_lock_irqsave(&priv->sta_lock, flags);
  2642. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  2643. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  2644. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2645. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2646. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2647. }
  2648. /**
  2649. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  2650. *
  2651. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  2652. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  2653. */
  2654. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  2655. struct iwl_ht_agg *agg,
  2656. struct iwl4965_compressed_ba_resp*
  2657. ba_resp)
  2658. {
  2659. int i, sh, ack;
  2660. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  2661. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2662. u64 bitmap;
  2663. int successes = 0;
  2664. struct ieee80211_tx_status *tx_status;
  2665. if (unlikely(!agg->wait_for_ba)) {
  2666. IWL_ERROR("Received BA when not expected\n");
  2667. return -EINVAL;
  2668. }
  2669. /* Mark that the expected block-ack response arrived */
  2670. agg->wait_for_ba = 0;
  2671. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  2672. /* Calculate shift to align block-ack bits with our Tx window bits */
  2673. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  2674. if (sh < 0) /* tbw something is wrong with indices */
  2675. sh += 0x100;
  2676. /* don't use 64-bit values for now */
  2677. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  2678. if (agg->frame_count > (64 - sh)) {
  2679. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  2680. return -1;
  2681. }
  2682. /* check for success or failure according to the
  2683. * transmitted bitmap and block-ack bitmap */
  2684. bitmap &= agg->bitmap;
  2685. /* For each frame attempted in aggregation,
  2686. * update driver's record of tx frame's status. */
  2687. for (i = 0; i < agg->frame_count ; i++) {
  2688. ack = bitmap & (1 << i);
  2689. successes += !!ack;
  2690. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  2691. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  2692. agg->start_idx + i);
  2693. }
  2694. tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
  2695. tx_status->flags = IEEE80211_TX_STATUS_ACK;
  2696. tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
  2697. tx_status->ampdu_ack_map = successes;
  2698. tx_status->ampdu_ack_len = agg->frame_count;
  2699. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
  2700. &tx_status->control);
  2701. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
  2702. return 0;
  2703. }
  2704. /**
  2705. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  2706. */
  2707. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  2708. u16 txq_id)
  2709. {
  2710. /* Simply stop the queue, but don't change any configuration;
  2711. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  2712. iwl_write_prph(priv,
  2713. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2714. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  2715. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  2716. }
  2717. /**
  2718. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  2719. * priv->lock must be held by the caller
  2720. */
  2721. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  2722. u16 ssn_idx, u8 tx_fifo)
  2723. {
  2724. int ret = 0;
  2725. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  2726. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2727. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2728. return -EINVAL;
  2729. }
  2730. ret = iwl_grab_nic_access(priv);
  2731. if (ret)
  2732. return ret;
  2733. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2734. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2735. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2736. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2737. /* supposes that ssn_idx is valid (!= 0xFFF) */
  2738. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2739. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2740. iwl4965_txq_ctx_deactivate(priv, txq_id);
  2741. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  2742. iwl_release_nic_access(priv);
  2743. return 0;
  2744. }
  2745. int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
  2746. u8 tid, int txq_id)
  2747. {
  2748. struct iwl4965_queue *q = &priv->txq[txq_id].q;
  2749. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  2750. struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  2751. switch (priv->stations[sta_id].tid[tid].agg.state) {
  2752. case IWL_EMPTYING_HW_QUEUE_DELBA:
  2753. /* We are reclaiming the last packet of the */
  2754. /* aggregated HW queue */
  2755. if (txq_id == tid_data->agg.txq_id &&
  2756. q->read_ptr == q->write_ptr) {
  2757. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  2758. int tx_fifo = default_tid_to_tx_fifo[tid];
  2759. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  2760. iwl4965_tx_queue_agg_disable(priv, txq_id,
  2761. ssn, tx_fifo);
  2762. tid_data->agg.state = IWL_AGG_OFF;
  2763. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  2764. }
  2765. break;
  2766. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  2767. /* We are reclaiming the last packet of the queue */
  2768. if (tid_data->tfds_in_queue == 0) {
  2769. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  2770. tid_data->agg.state = IWL_AGG_ON;
  2771. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  2772. }
  2773. break;
  2774. }
  2775. return 0;
  2776. }
  2777. /**
  2778. * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
  2779. * @index -- current index
  2780. * @n_bd -- total number of entries in queue (s/b power of 2)
  2781. */
  2782. static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
  2783. {
  2784. return (index == 0) ? n_bd - 1 : index - 1;
  2785. }
  2786. /**
  2787. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  2788. *
  2789. * Handles block-acknowledge notification from device, which reports success
  2790. * of frames sent via aggregation.
  2791. */
  2792. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  2793. struct iwl_rx_mem_buffer *rxb)
  2794. {
  2795. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2796. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  2797. int index;
  2798. struct iwl4965_tx_queue *txq = NULL;
  2799. struct iwl_ht_agg *agg;
  2800. DECLARE_MAC_BUF(mac);
  2801. /* "flow" corresponds to Tx queue */
  2802. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  2803. /* "ssn" is start of block-ack Tx window, corresponds to index
  2804. * (in Tx queue's circular buffer) of first TFD/frame in window */
  2805. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  2806. if (scd_flow >= priv->hw_params.max_txq_num) {
  2807. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  2808. return;
  2809. }
  2810. txq = &priv->txq[scd_flow];
  2811. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  2812. /* Find index just before block-ack window */
  2813. index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  2814. /* TODO: Need to get this copy more safely - now good for debug */
  2815. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  2816. "sta_id = %d\n",
  2817. agg->wait_for_ba,
  2818. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  2819. ba_resp->sta_id);
  2820. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  2821. "%d, scd_ssn = %d\n",
  2822. ba_resp->tid,
  2823. ba_resp->seq_ctl,
  2824. (unsigned long long)le64_to_cpu(ba_resp->bitmap),
  2825. ba_resp->scd_flow,
  2826. ba_resp->scd_ssn);
  2827. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  2828. agg->start_idx,
  2829. (unsigned long long)agg->bitmap);
  2830. /* Update driver's record of ACK vs. not for each frame in window */
  2831. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  2832. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  2833. * block-ack window (we assume that they've been successfully
  2834. * transmitted ... if not, it's too late anyway). */
  2835. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  2836. /* calculate mac80211 ampdu sw queue to wake */
  2837. int ampdu_q =
  2838. scd_flow - IWL_BACK_QUEUE_FIRST_ID + priv->hw->queues;
  2839. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  2840. priv->stations[ba_resp->sta_id].
  2841. tid[ba_resp->tid].tfds_in_queue -= freed;
  2842. if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
  2843. priv->mac80211_registered &&
  2844. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  2845. ieee80211_wake_queue(priv->hw, ampdu_q);
  2846. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  2847. ba_resp->tid, scd_flow);
  2848. }
  2849. }
  2850. /**
  2851. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  2852. */
  2853. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  2854. u16 txq_id)
  2855. {
  2856. u32 tbl_dw_addr;
  2857. u32 tbl_dw;
  2858. u16 scd_q2ratid;
  2859. scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  2860. tbl_dw_addr = priv->scd_base_addr +
  2861. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  2862. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  2863. if (txq_id & 0x1)
  2864. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  2865. else
  2866. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  2867. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  2868. return 0;
  2869. }
  2870. /**
  2871. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  2872. *
  2873. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  2874. * i.e. it must be one of the higher queues used for aggregation
  2875. */
  2876. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  2877. int tx_fifo, int sta_id, int tid,
  2878. u16 ssn_idx)
  2879. {
  2880. unsigned long flags;
  2881. int rc;
  2882. u16 ra_tid;
  2883. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  2884. IWL_WARNING("queue number too small: %d, must be > %d\n",
  2885. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  2886. ra_tid = BUILD_RAxTID(sta_id, tid);
  2887. /* Modify device's station table to Tx this TID */
  2888. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  2889. spin_lock_irqsave(&priv->lock, flags);
  2890. rc = iwl_grab_nic_access(priv);
  2891. if (rc) {
  2892. spin_unlock_irqrestore(&priv->lock, flags);
  2893. return rc;
  2894. }
  2895. /* Stop this Tx queue before configuring it */
  2896. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  2897. /* Map receiver-address / traffic-ID to this queue */
  2898. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  2899. /* Set this queue as a chain-building queue */
  2900. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  2901. /* Place first TFD at index corresponding to start sequence number.
  2902. * Assumes that ssn_idx is valid (!= 0xFFF) */
  2903. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  2904. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  2905. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  2906. /* Set up Tx window size and frame limit for this queue */
  2907. iwl_write_targ_mem(priv,
  2908. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  2909. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  2910. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  2911. iwl_write_targ_mem(priv, priv->scd_base_addr +
  2912. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  2913. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  2914. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  2915. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  2916. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  2917. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  2918. iwl_release_nic_access(priv);
  2919. spin_unlock_irqrestore(&priv->lock, flags);
  2920. return 0;
  2921. }
  2922. #endif /* CONFIG_IWL4965_HT */
  2923. /**
  2924. * iwl4965_add_station - Initialize a station's hardware rate table
  2925. *
  2926. * The uCode's station table contains a table of fallback rates
  2927. * for automatic fallback during transmission.
  2928. *
  2929. * NOTE: This sets up a default set of values. These will be replaced later
  2930. * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
  2931. * rc80211_simple.
  2932. *
  2933. * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
  2934. * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
  2935. * which requires station table entry to exist).
  2936. */
  2937. void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  2938. {
  2939. int i, r;
  2940. struct iwl_link_quality_cmd link_cmd = {
  2941. .reserved1 = 0,
  2942. };
  2943. u16 rate_flags;
  2944. /* Set up the rate scaling to start at selected rate, fall back
  2945. * all the way down to 1M in IEEE order, and then spin on 1M */
  2946. if (is_ap)
  2947. r = IWL_RATE_54M_INDEX;
  2948. else if (priv->band == IEEE80211_BAND_5GHZ)
  2949. r = IWL_RATE_6M_INDEX;
  2950. else
  2951. r = IWL_RATE_1M_INDEX;
  2952. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  2953. rate_flags = 0;
  2954. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  2955. rate_flags |= RATE_MCS_CCK_MSK;
  2956. /* Use Tx antenna B only */
  2957. rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
  2958. link_cmd.rs_table[i].rate_n_flags =
  2959. iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
  2960. r = iwl4965_get_prev_ieee_rate(r);
  2961. }
  2962. link_cmd.general_params.single_stream_ant_msk = 2;
  2963. link_cmd.general_params.dual_stream_ant_msk = 3;
  2964. link_cmd.agg_params.agg_dis_start_th = 3;
  2965. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  2966. /* Update the rate scaling for control frame Tx to AP */
  2967. link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
  2968. iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
  2969. sizeof(link_cmd), &link_cmd, NULL);
  2970. }
  2971. #ifdef CONFIG_IWL4965_HT
  2972. void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
  2973. struct ieee80211_ht_info *sta_ht_inf)
  2974. {
  2975. __le32 sta_flags;
  2976. u8 mimo_ps_mode;
  2977. if (!sta_ht_inf || !sta_ht_inf->ht_supported)
  2978. goto done;
  2979. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
  2980. sta_flags = priv->stations[index].sta.station_flags;
  2981. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  2982. switch (mimo_ps_mode) {
  2983. case WLAN_HT_CAP_MIMO_PS_STATIC:
  2984. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  2985. break;
  2986. case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
  2987. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  2988. break;
  2989. case WLAN_HT_CAP_MIMO_PS_DISABLED:
  2990. break;
  2991. default:
  2992. IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
  2993. break;
  2994. }
  2995. sta_flags |= cpu_to_le32(
  2996. (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  2997. sta_flags |= cpu_to_le32(
  2998. (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  2999. if (iwl_is_fat_tx_allowed(priv, sta_ht_inf))
  3000. sta_flags |= STA_FLG_FAT_EN_MSK;
  3001. else
  3002. sta_flags &= ~STA_FLG_FAT_EN_MSK;
  3003. priv->stations[index].sta.station_flags = sta_flags;
  3004. done:
  3005. return;
  3006. }
  3007. static int iwl4965_rx_agg_start(struct iwl_priv *priv,
  3008. const u8 *addr, int tid, u16 ssn)
  3009. {
  3010. unsigned long flags;
  3011. int sta_id;
  3012. sta_id = iwl_find_station(priv, addr);
  3013. if (sta_id == IWL_INVALID_STATION)
  3014. return -ENXIO;
  3015. spin_lock_irqsave(&priv->sta_lock, flags);
  3016. priv->stations[sta_id].sta.station_flags_msk = 0;
  3017. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  3018. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  3019. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  3020. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3021. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3022. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  3023. CMD_ASYNC);
  3024. }
  3025. static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
  3026. const u8 *addr, int tid)
  3027. {
  3028. unsigned long flags;
  3029. int sta_id;
  3030. sta_id = iwl_find_station(priv, addr);
  3031. if (sta_id == IWL_INVALID_STATION)
  3032. return -ENXIO;
  3033. spin_lock_irqsave(&priv->sta_lock, flags);
  3034. priv->stations[sta_id].sta.station_flags_msk = 0;
  3035. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  3036. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  3037. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3038. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3039. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  3040. CMD_ASYNC);
  3041. }
  3042. /*
  3043. * Find first available (lowest unused) Tx Queue, mark it "active".
  3044. * Called only when finding queue for aggregation.
  3045. * Should never return anything < 7, because they should already
  3046. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  3047. */
  3048. static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
  3049. {
  3050. int txq_id;
  3051. for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
  3052. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  3053. return txq_id;
  3054. return -1;
  3055. }
  3056. static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
  3057. u16 tid, u16 *start_seq_num)
  3058. {
  3059. struct iwl_priv *priv = hw->priv;
  3060. int sta_id;
  3061. int tx_fifo;
  3062. int txq_id;
  3063. int ssn = -1;
  3064. int ret = 0;
  3065. unsigned long flags;
  3066. struct iwl_tid_data *tid_data;
  3067. DECLARE_MAC_BUF(mac);
  3068. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3069. tx_fifo = default_tid_to_tx_fifo[tid];
  3070. else
  3071. return -EINVAL;
  3072. IWL_WARNING("%s on ra = %s tid = %d\n",
  3073. __func__, print_mac(mac, ra), tid);
  3074. sta_id = iwl_find_station(priv, ra);
  3075. if (sta_id == IWL_INVALID_STATION)
  3076. return -ENXIO;
  3077. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  3078. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  3079. return -ENXIO;
  3080. }
  3081. txq_id = iwl4965_txq_ctx_activate_free(priv);
  3082. if (txq_id == -1)
  3083. return -ENXIO;
  3084. spin_lock_irqsave(&priv->sta_lock, flags);
  3085. tid_data = &priv->stations[sta_id].tid[tid];
  3086. ssn = SEQ_TO_SN(tid_data->seq_number);
  3087. tid_data->agg.txq_id = txq_id;
  3088. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3089. *start_seq_num = ssn;
  3090. ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  3091. sta_id, tid, ssn);
  3092. if (ret)
  3093. return ret;
  3094. ret = 0;
  3095. if (tid_data->tfds_in_queue == 0) {
  3096. printk(KERN_ERR "HW queue is empty\n");
  3097. tid_data->agg.state = IWL_AGG_ON;
  3098. ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
  3099. } else {
  3100. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  3101. tid_data->tfds_in_queue);
  3102. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  3103. }
  3104. return ret;
  3105. }
  3106. static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
  3107. {
  3108. struct iwl_priv *priv = hw->priv;
  3109. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  3110. struct iwl_tid_data *tid_data;
  3111. int ret, write_ptr, read_ptr;
  3112. unsigned long flags;
  3113. DECLARE_MAC_BUF(mac);
  3114. if (!ra) {
  3115. IWL_ERROR("ra = NULL\n");
  3116. return -EINVAL;
  3117. }
  3118. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3119. tx_fifo_id = default_tid_to_tx_fifo[tid];
  3120. else
  3121. return -EINVAL;
  3122. sta_id = iwl_find_station(priv, ra);
  3123. if (sta_id == IWL_INVALID_STATION)
  3124. return -ENXIO;
  3125. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  3126. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  3127. tid_data = &priv->stations[sta_id].tid[tid];
  3128. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  3129. txq_id = tid_data->agg.txq_id;
  3130. write_ptr = priv->txq[txq_id].q.write_ptr;
  3131. read_ptr = priv->txq[txq_id].q.read_ptr;
  3132. /* The queue is not empty */
  3133. if (write_ptr != read_ptr) {
  3134. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  3135. priv->stations[sta_id].tid[tid].agg.state =
  3136. IWL_EMPTYING_HW_QUEUE_DELBA;
  3137. return 0;
  3138. }
  3139. IWL_DEBUG_HT("HW queue is empty\n");
  3140. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  3141. spin_lock_irqsave(&priv->lock, flags);
  3142. ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  3143. spin_unlock_irqrestore(&priv->lock, flags);
  3144. if (ret)
  3145. return ret;
  3146. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
  3147. return 0;
  3148. }
  3149. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  3150. enum ieee80211_ampdu_mlme_action action,
  3151. const u8 *addr, u16 tid, u16 *ssn)
  3152. {
  3153. struct iwl_priv *priv = hw->priv;
  3154. DECLARE_MAC_BUF(mac);
  3155. IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
  3156. print_mac(mac, addr), tid);
  3157. switch (action) {
  3158. case IEEE80211_AMPDU_RX_START:
  3159. IWL_DEBUG_HT("start Rx\n");
  3160. return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
  3161. case IEEE80211_AMPDU_RX_STOP:
  3162. IWL_DEBUG_HT("stop Rx\n");
  3163. return iwl4965_rx_agg_stop(priv, addr, tid);
  3164. case IEEE80211_AMPDU_TX_START:
  3165. IWL_DEBUG_HT("start Tx\n");
  3166. return iwl4965_tx_agg_start(hw, addr, tid, ssn);
  3167. case IEEE80211_AMPDU_TX_STOP:
  3168. IWL_DEBUG_HT("stop Tx\n");
  3169. return iwl4965_tx_agg_stop(hw, addr, tid);
  3170. default:
  3171. IWL_DEBUG_HT("unknown\n");
  3172. return -EINVAL;
  3173. break;
  3174. }
  3175. return 0;
  3176. }
  3177. #endif /* CONFIG_IWL4965_HT */
  3178. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  3179. {
  3180. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  3181. addsta->mode = cmd->mode;
  3182. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  3183. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  3184. addsta->station_flags = cmd->station_flags;
  3185. addsta->station_flags_msk = cmd->station_flags_msk;
  3186. addsta->tid_disable_tx = cmd->tid_disable_tx;
  3187. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  3188. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  3189. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  3190. addsta->reserved1 = __constant_cpu_to_le16(0);
  3191. addsta->reserved2 = __constant_cpu_to_le32(0);
  3192. return (u16)sizeof(struct iwl4965_addsta_cmd);
  3193. }
  3194. /* Set up 4965-specific Rx frame reply handlers */
  3195. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  3196. {
  3197. /* Legacy Rx frames */
  3198. priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
  3199. /* High-throughput (HT) Rx frames */
  3200. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  3201. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  3202. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  3203. iwl4965_rx_missed_beacon_notif;
  3204. #ifdef CONFIG_IWL4965_HT
  3205. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  3206. #endif /* CONFIG_IWL4965_HT */
  3207. }
  3208. void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
  3209. {
  3210. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  3211. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  3212. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  3213. #endif
  3214. init_timer(&priv->statistics_periodic);
  3215. priv->statistics_periodic.data = (unsigned long)priv;
  3216. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  3217. }
  3218. void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
  3219. {
  3220. del_timer_sync(&priv->statistics_periodic);
  3221. cancel_delayed_work(&priv->init_alive_start);
  3222. }
  3223. static struct iwl_hcmd_ops iwl4965_hcmd = {
  3224. .rxon_assoc = iwl4965_send_rxon_assoc,
  3225. };
  3226. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  3227. .enqueue_hcmd = iwl4965_enqueue_hcmd,
  3228. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  3229. #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
  3230. .chain_noise_reset = iwl4965_chain_noise_reset,
  3231. .gain_computation = iwl4965_gain_computation,
  3232. #endif
  3233. };
  3234. static struct iwl_lib_ops iwl4965_lib = {
  3235. .set_hw_params = iwl4965_hw_set_hw_params,
  3236. .alloc_shared_mem = iwl4965_alloc_shared_mem,
  3237. .free_shared_mem = iwl4965_free_shared_mem,
  3238. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  3239. .disable_tx_fifo = iwl4965_disable_tx_fifo,
  3240. .rx_handler_setup = iwl4965_rx_handler_setup,
  3241. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  3242. .alive_notify = iwl4965_alive_notify,
  3243. .init_alive_start = iwl4965_init_alive_start,
  3244. .load_ucode = iwl4965_load_bsm,
  3245. .apm_ops = {
  3246. .init = iwl4965_apm_init,
  3247. .config = iwl4965_nic_config,
  3248. .set_pwr_src = iwl4965_set_pwr_src,
  3249. },
  3250. .eeprom_ops = {
  3251. .regulatory_bands = {
  3252. EEPROM_REGULATORY_BAND_1_CHANNELS,
  3253. EEPROM_REGULATORY_BAND_2_CHANNELS,
  3254. EEPROM_REGULATORY_BAND_3_CHANNELS,
  3255. EEPROM_REGULATORY_BAND_4_CHANNELS,
  3256. EEPROM_REGULATORY_BAND_5_CHANNELS,
  3257. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  3258. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  3259. },
  3260. .verify_signature = iwlcore_eeprom_verify_signature,
  3261. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  3262. .release_semaphore = iwlcore_eeprom_release_semaphore,
  3263. .check_version = iwl4965_eeprom_check_version,
  3264. .query_addr = iwlcore_eeprom_query_addr,
  3265. },
  3266. .radio_kill_sw = iwl4965_radio_kill_sw,
  3267. .set_power = iwl4965_set_power,
  3268. .update_chain_flags = iwl4965_update_chain_flags,
  3269. };
  3270. static struct iwl_ops iwl4965_ops = {
  3271. .lib = &iwl4965_lib,
  3272. .hcmd = &iwl4965_hcmd,
  3273. .utils = &iwl4965_hcmd_utils,
  3274. };
  3275. struct iwl_cfg iwl4965_agn_cfg = {
  3276. .name = "4965AGN",
  3277. .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
  3278. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  3279. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  3280. .ops = &iwl4965_ops,
  3281. .mod_params = &iwl4965_mod_params,
  3282. };
  3283. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  3284. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3285. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  3286. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  3287. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  3288. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
  3289. module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
  3290. MODULE_PARM_DESC(debug, "debug output mask");
  3291. module_param_named(
  3292. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  3293. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3294. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  3295. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3296. /* QoS */
  3297. module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
  3298. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  3299. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  3300. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");