Kconfig 14 KB

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  1. comment "Processor Type"
  2. config CPU_32
  3. bool
  4. default y
  5. # Select CPU types depending on the architecture selected. This selects
  6. # which CPUs we support in the kernel image, and the compiler instruction
  7. # optimiser behaviour.
  8. # ARM610
  9. config CPU_ARM610
  10. bool "Support ARM610 processor"
  11. depends on ARCH_RPC
  12. select CPU_32v3
  13. select CPU_CACHE_V3
  14. select CPU_CACHE_VIVT
  15. select CPU_CP15_MMU
  16. select CPU_COPY_V3 if MMU
  17. select CPU_TLB_V3 if MMU
  18. help
  19. The ARM610 is the successor to the ARM3 processor
  20. and was produced by VLSI Technology Inc.
  21. Say Y if you want support for the ARM610 processor.
  22. Otherwise, say N.
  23. # ARM7TDMI
  24. config CPU_ARM7TDMI
  25. bool "Support ARM7TDMI processor"
  26. select CPU_32v4T
  27. select CPU_ABRT_LV4T
  28. select CPU_CACHE_V4
  29. help
  30. A 32-bit RISC microprocessor based on the ARM7 processor core
  31. which has no memory control unit and cache.
  32. Say Y if you want support for the ARM7TDMI processor.
  33. Otherwise, say N.
  34. # ARM710
  35. config CPU_ARM710
  36. bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  37. default y if ARCH_CLPS7500
  38. select CPU_32v3
  39. select CPU_CACHE_V3
  40. select CPU_CACHE_VIVT
  41. select CPU_CP15_MMU
  42. select CPU_COPY_V3 if MMU
  43. select CPU_TLB_V3 if MMU
  44. help
  45. A 32-bit RISC microprocessor based on the ARM7 processor core
  46. designed by Advanced RISC Machines Ltd. The ARM710 is the
  47. successor to the ARM610 processor. It was released in
  48. July 1994 by VLSI Technology Inc.
  49. Say Y if you want support for the ARM710 processor.
  50. Otherwise, say N.
  51. # ARM720T
  52. config CPU_ARM720T
  53. bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  54. default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  55. select CPU_32v4T
  56. select CPU_ABRT_LV4T
  57. select CPU_CACHE_V4
  58. select CPU_CACHE_VIVT
  59. select CPU_CP15_MMU
  60. select CPU_COPY_V4WT if MMU
  61. select CPU_TLB_V4WT if MMU
  62. help
  63. A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  64. MMU built around an ARM7TDMI core.
  65. Say Y if you want support for the ARM720T processor.
  66. Otherwise, say N.
  67. # ARM740T
  68. config CPU_ARM740T
  69. bool "Support ARM740T processor" if ARCH_INTEGRATOR
  70. select CPU_32v4T
  71. select CPU_ABRT_LV4T
  72. select CPU_CACHE_V3 # although the core is v4t
  73. select CPU_CP15_MPU
  74. help
  75. A 32-bit RISC processor with 8KB cache or 4KB variants,
  76. write buffer and MPU(Protection Unit) built around
  77. an ARM7TDMI core.
  78. Say Y if you want support for the ARM740T processor.
  79. Otherwise, say N.
  80. # ARM9TDMI
  81. config CPU_ARM9TDMI
  82. bool "Support ARM9TDMI processor"
  83. select CPU_32v4T
  84. select CPU_ABRT_EV4T
  85. select CPU_CACHE_V4
  86. help
  87. A 32-bit RISC microprocessor based on the ARM9 processor core
  88. which has no memory control unit and cache.
  89. Say Y if you want support for the ARM9TDMI processor.
  90. Otherwise, say N.
  91. # ARM920T
  92. config CPU_ARM920T
  93. bool "Support ARM920T processor"
  94. depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
  95. default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
  96. select CPU_32v4T
  97. select CPU_ABRT_EV4T
  98. select CPU_CACHE_V4WT
  99. select CPU_CACHE_VIVT
  100. select CPU_CP15_MMU
  101. select CPU_COPY_V4WB if MMU
  102. select CPU_TLB_V4WBI if MMU
  103. help
  104. The ARM920T is licensed to be produced by numerous vendors,
  105. and is used in the Maverick EP9312 and the Samsung S3C2410.
  106. More information on the Maverick EP9312 at
  107. <http://linuxdevices.com/products/PD2382866068.html>.
  108. Say Y if you want support for the ARM920T processor.
  109. Otherwise, say N.
  110. # ARM922T
  111. config CPU_ARM922T
  112. bool "Support ARM922T processor" if ARCH_INTEGRATOR
  113. depends on ARCH_LH7A40X || ARCH_INTEGRATOR
  114. default y if ARCH_LH7A40X
  115. select CPU_32v4T
  116. select CPU_ABRT_EV4T
  117. select CPU_CACHE_V4WT
  118. select CPU_CACHE_VIVT
  119. select CPU_CP15_MMU
  120. select CPU_COPY_V4WB if MMU
  121. select CPU_TLB_V4WBI if MMU
  122. help
  123. The ARM922T is a version of the ARM920T, but with smaller
  124. instruction and data caches. It is used in Altera's
  125. Excalibur XA device family.
  126. Say Y if you want support for the ARM922T processor.
  127. Otherwise, say N.
  128. # ARM925T
  129. config CPU_ARM925T
  130. bool "Support ARM925T processor" if ARCH_OMAP1
  131. depends on ARCH_OMAP15XX
  132. default y if ARCH_OMAP15XX
  133. select CPU_32v4T
  134. select CPU_ABRT_EV4T
  135. select CPU_CACHE_V4WT
  136. select CPU_CACHE_VIVT
  137. select CPU_CP15_MMU
  138. select CPU_COPY_V4WB if MMU
  139. select CPU_TLB_V4WBI if MMU
  140. help
  141. The ARM925T is a mix between the ARM920T and ARM926T, but with
  142. different instruction and data caches. It is used in TI's OMAP
  143. device family.
  144. Say Y if you want support for the ARM925T processor.
  145. Otherwise, say N.
  146. # ARM926T
  147. config CPU_ARM926T
  148. bool "Support ARM926T processor"
  149. depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
  150. default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
  151. select CPU_32v5
  152. select CPU_ABRT_EV5TJ
  153. select CPU_CACHE_VIVT
  154. select CPU_CP15_MMU
  155. select CPU_COPY_V4WB if MMU
  156. select CPU_TLB_V4WBI if MMU
  157. help
  158. This is a variant of the ARM920. It has slightly different
  159. instruction sequences for cache and TLB operations. Curiously,
  160. there is no documentation on it at the ARM corporate website.
  161. Say Y if you want support for the ARM926T processor.
  162. Otherwise, say N.
  163. # ARM1020 - needs validating
  164. config CPU_ARM1020
  165. bool "Support ARM1020T (rev 0) processor"
  166. depends on ARCH_INTEGRATOR
  167. select CPU_32v5
  168. select CPU_ABRT_EV4T
  169. select CPU_CACHE_V4WT
  170. select CPU_CACHE_VIVT
  171. select CPU_CP15_MMU
  172. select CPU_COPY_V4WB if MMU
  173. select CPU_TLB_V4WBI if MMU
  174. help
  175. The ARM1020 is the 32K cached version of the ARM10 processor,
  176. with an addition of a floating-point unit.
  177. Say Y if you want support for the ARM1020 processor.
  178. Otherwise, say N.
  179. # ARM1020E - needs validating
  180. config CPU_ARM1020E
  181. bool "Support ARM1020E processor"
  182. depends on ARCH_INTEGRATOR
  183. select CPU_32v5
  184. select CPU_ABRT_EV4T
  185. select CPU_CACHE_V4WT
  186. select CPU_CACHE_VIVT
  187. select CPU_CP15_MMU
  188. select CPU_COPY_V4WB if MMU
  189. select CPU_TLB_V4WBI if MMU
  190. depends on n
  191. # ARM1022E
  192. config CPU_ARM1022
  193. bool "Support ARM1022E processor"
  194. depends on ARCH_INTEGRATOR
  195. select CPU_32v5
  196. select CPU_ABRT_EV4T
  197. select CPU_CACHE_VIVT
  198. select CPU_CP15_MMU
  199. select CPU_COPY_V4WB if MMU # can probably do better
  200. select CPU_TLB_V4WBI if MMU
  201. help
  202. The ARM1022E is an implementation of the ARMv5TE architecture
  203. based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
  204. embedded trace macrocell, and a floating-point unit.
  205. Say Y if you want support for the ARM1022E processor.
  206. Otherwise, say N.
  207. # ARM1026EJ-S
  208. config CPU_ARM1026
  209. bool "Support ARM1026EJ-S processor"
  210. depends on ARCH_INTEGRATOR
  211. select CPU_32v5
  212. select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
  213. select CPU_CACHE_VIVT
  214. select CPU_CP15_MMU
  215. select CPU_COPY_V4WB if MMU # can probably do better
  216. select CPU_TLB_V4WBI if MMU
  217. help
  218. The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
  219. based upon the ARM10 integer core.
  220. Say Y if you want support for the ARM1026EJ-S processor.
  221. Otherwise, say N.
  222. # SA110
  223. config CPU_SA110
  224. bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
  225. default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
  226. select CPU_32v3 if ARCH_RPC
  227. select CPU_32v4 if !ARCH_RPC
  228. select CPU_ABRT_EV4
  229. select CPU_CACHE_V4WB
  230. select CPU_CACHE_VIVT
  231. select CPU_CP15_MMU
  232. select CPU_COPY_V4WB if MMU
  233. select CPU_TLB_V4WB if MMU
  234. help
  235. The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
  236. is available at five speeds ranging from 100 MHz to 233 MHz.
  237. More information is available at
  238. <http://developer.intel.com/design/strong/sa110.htm>.
  239. Say Y if you want support for the SA-110 processor.
  240. Otherwise, say N.
  241. # SA1100
  242. config CPU_SA1100
  243. bool
  244. depends on ARCH_SA1100
  245. default y
  246. select CPU_32v4
  247. select CPU_ABRT_EV4
  248. select CPU_CACHE_V4WB
  249. select CPU_CACHE_VIVT
  250. select CPU_CP15_MMU
  251. select CPU_TLB_V4WB if MMU
  252. # XScale
  253. config CPU_XSCALE
  254. bool
  255. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
  256. default y
  257. select CPU_32v5
  258. select CPU_ABRT_EV5T
  259. select CPU_CACHE_VIVT
  260. select CPU_CP15_MMU
  261. select CPU_TLB_V4WBI if MMU
  262. # XScale Core Version 3
  263. config CPU_XSC3
  264. bool
  265. depends on ARCH_IXP23XX
  266. default y
  267. select CPU_32v5
  268. select CPU_ABRT_EV5T
  269. select CPU_CACHE_VIVT
  270. select CPU_CP15_MMU
  271. select CPU_TLB_V4WBI if MMU
  272. select IO_36
  273. # ARMv6
  274. config CPU_V6
  275. bool "Support ARM V6 processor"
  276. depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
  277. select CPU_32v6
  278. select CPU_ABRT_EV6
  279. select CPU_CACHE_V6
  280. select CPU_CACHE_VIPT
  281. select CPU_CP15_MMU
  282. select CPU_COPY_V6 if MMU
  283. select CPU_TLB_V6 if MMU
  284. # ARMv6k
  285. config CPU_32v6K
  286. bool "Support ARM V6K processor extensions" if !SMP
  287. depends on CPU_V6
  288. default y if SMP
  289. help
  290. Say Y here if your ARMv6 processor supports the 'K' extension.
  291. This enables the kernel to use some instructions not present
  292. on previous processors, and as such a kernel build with this
  293. enabled will not boot on processors with do not support these
  294. instructions.
  295. # Figure out what processor architecture version we should be using.
  296. # This defines the compiler instruction set which depends on the machine type.
  297. config CPU_32v3
  298. bool
  299. select TLS_REG_EMUL if SMP || !MMU
  300. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  301. config CPU_32v4
  302. bool
  303. select TLS_REG_EMUL if SMP || !MMU
  304. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  305. config CPU_32v4T
  306. bool
  307. select TLS_REG_EMUL if SMP || !MMU
  308. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  309. config CPU_32v5
  310. bool
  311. select TLS_REG_EMUL if SMP || !MMU
  312. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  313. config CPU_32v6
  314. bool
  315. # The abort model
  316. config CPU_ABRT_EV4
  317. bool
  318. config CPU_ABRT_EV4T
  319. bool
  320. config CPU_ABRT_LV4T
  321. bool
  322. config CPU_ABRT_EV5T
  323. bool
  324. config CPU_ABRT_EV5TJ
  325. bool
  326. config CPU_ABRT_EV6
  327. bool
  328. # The cache model
  329. config CPU_CACHE_V3
  330. bool
  331. config CPU_CACHE_V4
  332. bool
  333. config CPU_CACHE_V4WT
  334. bool
  335. config CPU_CACHE_V4WB
  336. bool
  337. config CPU_CACHE_V6
  338. bool
  339. config CPU_CACHE_VIVT
  340. bool
  341. config CPU_CACHE_VIPT
  342. bool
  343. if MMU
  344. # The copy-page model
  345. config CPU_COPY_V3
  346. bool
  347. config CPU_COPY_V4WT
  348. bool
  349. config CPU_COPY_V4WB
  350. bool
  351. config CPU_COPY_V6
  352. bool
  353. # This selects the TLB model
  354. config CPU_TLB_V3
  355. bool
  356. help
  357. ARM Architecture Version 3 TLB.
  358. config CPU_TLB_V4WT
  359. bool
  360. help
  361. ARM Architecture Version 4 TLB with writethrough cache.
  362. config CPU_TLB_V4WB
  363. bool
  364. help
  365. ARM Architecture Version 4 TLB with writeback cache.
  366. config CPU_TLB_V4WBI
  367. bool
  368. help
  369. ARM Architecture Version 4 TLB with writeback cache and invalidate
  370. instruction cache entry.
  371. config CPU_TLB_V6
  372. bool
  373. endif
  374. config CPU_CP15
  375. bool
  376. help
  377. Processor has the CP15 register.
  378. config CPU_CP15_MMU
  379. bool
  380. select CPU_CP15
  381. help
  382. Processor has the CP15 register, which has MMU related registers.
  383. config CPU_CP15_MPU
  384. bool
  385. select CPU_CP15
  386. help
  387. Processor has the CP15 register, which has MPU related registers.
  388. #
  389. # CPU supports 36-bit I/O
  390. #
  391. config IO_36
  392. bool
  393. comment "Processor Features"
  394. config ARM_THUMB
  395. bool "Support Thumb user binaries"
  396. depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
  397. default y
  398. help
  399. Say Y if you want to include kernel support for running user space
  400. Thumb binaries.
  401. The Thumb instruction set is a compressed form of the standard ARM
  402. instruction set resulting in smaller binaries at the expense of
  403. slightly less efficient code.
  404. If you don't know what this all is, saying Y is a safe choice.
  405. config CPU_BIG_ENDIAN
  406. bool "Build big-endian kernel"
  407. depends on ARCH_SUPPORTS_BIG_ENDIAN
  408. help
  409. Say Y if you plan on running a kernel in big-endian mode.
  410. Note that your board must be properly built and your board
  411. port must properly enable any big-endian related features
  412. of your chipset/board/processor.
  413. config CPU_ICACHE_DISABLE
  414. bool "Disable I-Cache (I-bit)"
  415. depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
  416. help
  417. Say Y here to disable the processor instruction cache. Unless
  418. you have a reason not to or are unsure, say N.
  419. config CPU_DCACHE_DISABLE
  420. bool "Disable D-Cache (C-bit)"
  421. depends on CPU_CP15
  422. help
  423. Say Y here to disable the processor data cache. Unless
  424. you have a reason not to or are unsure, say N.
  425. config CPU_DCACHE_WRITETHROUGH
  426. bool "Force write through D-cache"
  427. depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
  428. default y if CPU_ARM925T
  429. help
  430. Say Y here to use the data cache in writethrough mode. Unless you
  431. specifically require this or are unsure, say N.
  432. config CPU_CACHE_ROUND_ROBIN
  433. bool "Round robin I and D cache replacement algorithm"
  434. depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
  435. help
  436. Say Y here to use the predictable round-robin cache replacement
  437. policy. Unless you specifically require this or are unsure, say N.
  438. config CPU_BPREDICT_DISABLE
  439. bool "Disable branch prediction"
  440. depends on CPU_ARM1020 || CPU_V6
  441. help
  442. Say Y here to disable branch prediction. If unsure, say N.
  443. config TLS_REG_EMUL
  444. bool
  445. help
  446. An SMP system using a pre-ARMv6 processor (there are apparently
  447. a few prototypes like that in existence) and therefore access to
  448. that required register must be emulated.
  449. config HAS_TLS_REG
  450. bool
  451. depends on !TLS_REG_EMUL
  452. default y if SMP || CPU_32v7
  453. help
  454. This selects support for the CP15 thread register.
  455. It is defined to be available on some ARMv6 processors (including
  456. all SMP capable ARMv6's) or later processors. User space may
  457. assume directly accessing that register and always obtain the
  458. expected value only on ARMv7 and above.
  459. config NEEDS_SYSCALL_FOR_CMPXCHG
  460. bool
  461. help
  462. SMP on a pre-ARMv6 processor? Well OK then.
  463. Forget about fast user space cmpxchg support.
  464. It is just not possible.