linux-vybrid_public/drivers/media/dvb/frontends/drxk_map.h

#ifndef __DRXK_MAP__H__
#define __DRXK_MAP__H__ 1

#define  AUD_COMM_EXEC__A                                                  0x1000000
#define  AUD_COMM_EXEC__W                                                  2
#define  AUD_COMM_EXEC__M                                                  0x3
#define  AUD_COMM_EXEC__PRE                                                0x0
#define    AUD_COMM_EXEC_STOP                                              0x0

#define  FEC_COMM_EXEC__A                                                  0x1C00000
#define  FEC_COMM_EXEC__W                                                  2
#define  FEC_COMM_EXEC__M                                                  0x3
#define  FEC_COMM_EXEC__PRE                                                0x0
#define    FEC_COMM_EXEC_STOP                                              0x0
#define    FEC_COMM_EXEC_ACTIVE                                            0x1
#define    FEC_COMM_EXEC_HOLD                                              0x2

#define  FEC_COMM_MB__A                                                    0x1C00002
#define  FEC_COMM_MB__W                                                    16
#define  FEC_COMM_MB__M                                                    0xFFFF
#define  FEC_COMM_MB__PRE                                                  0x0
#define  FEC_COMM_INT_REQ__A                                               0x1C00003
#define  FEC_COMM_INT_REQ__W                                               16
#define  FEC_COMM_INT_REQ__M                                               0xFFFF
#define  FEC_COMM_INT_REQ__PRE                                             0x0
#define    FEC_COMM_INT_REQ_OC_REQ__B                                      0
#define    FEC_COMM_INT_REQ_OC_REQ__W                                      1
#define    FEC_COMM_INT_REQ_OC_REQ__M                                      0x1
#define    FEC_COMM_INT_REQ_OC_REQ__PRE                                    0x0
#define    FEC_COMM_INT_REQ_RS_REQ__B                                      1
#define    FEC_COMM_INT_REQ_RS_REQ__W                                      1
#define    FEC_COMM_INT_REQ_RS_REQ__M                                      0x2
#define    FEC_COMM_INT_REQ_RS_REQ__PRE                                    0x0
#define    FEC_COMM_INT_REQ_DI_REQ__B                                      2
#define    FEC_COMM_INT_REQ_DI_REQ__W                                      1
#define    FEC_COMM_INT_REQ_DI_REQ__M                                      0x4
#define    FEC_COMM_INT_REQ_DI_REQ__PRE                                    0x0

#define  FEC_COMM_INT_STA__A                                               0x1C00005
#define  FEC_COMM_INT_STA__W                                               16
#define  FEC_COMM_INT_STA__M                                               0xFFFF
#define  FEC_COMM_INT_STA__PRE                                             0x0
#define  FEC_COMM_INT_MSK__A                                               0x1C00006
#define  FEC_COMM_INT_MSK__W                                               16
#define  FEC_COMM_INT_MSK__M                                               0xFFFF
#define  FEC_COMM_INT_MSK__PRE                                             0x0
#define  FEC_COMM_INT_STM__A                                               0x1C00007
#define  FEC_COMM_INT_STM__W                                               16
#define  FEC_COMM_INT_STM__M                                               0xFFFF
#define  FEC_COMM_INT_STM__PRE                                             0x0



#define  FEC_TOP_COMM_EXEC__A                                              0x1C10000
#define  FEC_TOP_COMM_EXEC__W                                              2
#define  FEC_TOP_COMM_EXEC__M                                              0x3
#define  FEC_TOP_COMM_EXEC__PRE                                            0x0
#define    FEC_TOP_COMM_EXEC_STOP                                          0x0
#define    FEC_TOP_COMM_EXEC_ACTIVE                                        0x1
#define    FEC_TOP_COMM_EXEC_HOLD                                          0x2

#define  FEC_TOP_ANNEX__A                                                  0x1C10010
#define  FEC_TOP_ANNEX__W                                                  2
#define  FEC_TOP_ANNEX__M                                                  0x3
#define  FEC_TOP_ANNEX__PRE                                                0x0
#define    FEC_TOP_ANNEX_A                                                 0x0
#define    FEC_TOP_ANNEX_B                                                 0x1
#define    FEC_TOP_ANNEX_C                                                 0x2
#define    FEC_TOP_ANNEX_D                                                 0x3



#define  FEC_DI_COMM_EXEC__A                                               0x1C20000
#define  FEC_DI_COMM_EXEC__W                                               2
#define  FEC_DI_COMM_EXEC__M                                               0x3
#define  FEC_DI_COMM_EXEC__PRE                                             0x0
#define    FEC_DI_COMM_EXEC_STOP                                           0x0
#define    FEC_DI_COMM_EXEC_ACTIVE                                         0x1
#define    FEC_DI_COMM_EXEC_HOLD                                           0x2

#define  FEC_DI_COMM_MB__A                                                 0x1C20002
#define  FEC_DI_COMM_MB__W                                                 2
#define  FEC_DI_COMM_MB__M                                                 0x3
#define  FEC_DI_COMM_MB__PRE                                               0x0
#define    FEC_DI_COMM_MB_CTL__B                                           0
#define    FEC_DI_COMM_MB_CTL__W                                           1
#define    FEC_DI_COMM_MB_CTL__M                                           0x1
#define    FEC_DI_COMM_MB_CTL__PRE                                         0x0
#define      FEC_DI_COMM_MB_CTL_OFF                                        0x0
#define      FEC_DI_COMM_MB_CTL_ON                                         0x1
#define    FEC_DI_COMM_MB_OBS__B                                           1
#define    FEC_DI_COMM_MB_OBS__W                                           1
#define    FEC_DI_COMM_MB_OBS__M                                           0x2
#define    FEC_DI_COMM_MB_OBS__PRE                                         0x0
#define      FEC_DI_COMM_MB_OBS_OFF                                        0x0
#define      FEC_DI_COMM_MB_OBS_ON                                         0x2

#define  FEC_DI_COMM_INT_REQ__A                                            0x1C20003
#define  FEC_DI_COMM_INT_REQ__W                                            1
#define  FEC_DI_COMM_INT_REQ__M                                            0x1
#define  FEC_DI_COMM_INT_REQ__PRE                                          0x0
#define  FEC_DI_COMM_INT_STA__A                                            0x1C20005
#define  FEC_DI_COMM_INT_STA__W                                            2
#define  FEC_DI_COMM_INT_STA__M                                            0x3
#define  FEC_DI_COMM_INT_STA__PRE                                          0x0

#define    FEC_DI_COMM_INT_STA_STAT_INT__B                                 0
#define    FEC_DI_COMM_INT_STA_STAT_INT__W                                 1
#define    FEC_DI_COMM_INT_STA_STAT_INT__M                                 0x1
#define    FEC_DI_COMM_INT_STA_STAT_INT__PRE                               0x0

#define    FEC_DI_COMM_INT_STA_TIMEOUT_INT__B                              1
#define    FEC_DI_COMM_INT_STA_TIMEOUT_INT__W                              1
#define    FEC_DI_COMM_INT_STA_TIMEOUT_INT__M                              0x2
#define    FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE                            0x0

#define  FEC_DI_COMM_INT_MSK__A                                            0x1C20006
#define  FEC_DI_COMM_INT_MSK__W                                            2
#define  FEC_DI_COMM_INT_MSK__M                                            0x3
#define  FEC_DI_COMM_INT_MSK__PRE                                          0x0
#define    FEC_DI_COMM_INT_MSK_STAT_INT__B                                 0
#define    FEC_DI_COMM_INT_MSK_STAT_INT__W                                 1
#define    FEC_DI_COMM_INT_MSK_STAT_INT__M                                 0x1
#define    FEC_DI_COMM_INT_MSK_STAT_INT__PRE                               0x0
#define    FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B                              1
#define    FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W                              1
#define    FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M                              0x2
#define    FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE                            0x0

#define  FEC_DI_COMM_INT_STM__A                                            0x1C20007
#define  FEC_DI_COMM_INT_STM__W                                            2
#define  FEC_DI_COMM_INT_STM__M                                            0x3
#define  FEC_DI_COMM_INT_STM__PRE                                          0x0
#define    FEC_DI_COMM_INT_STM_STAT_INT__B                                 0
#define    FEC_DI_COMM_INT_STM_STAT_INT__W                                 1
#define    FEC_DI_COMM_INT_STM_STAT_INT__M                                 0x1
#define    FEC_DI_COMM_INT_STM_STAT_INT__PRE                               0x0
#define    FEC_DI_COMM_INT_STM_TIMEOUT_INT__B                              1
#define    FEC_DI_COMM_INT_STM_TIMEOUT_INT__W                              1
#define    FEC_DI_COMM_INT_STM_TIMEOUT_INT__M                              0x2
#define    FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE                            0x0


#define  FEC_DI_STATUS__A                                                  0x1C20010
#define  FEC_DI_STATUS__W                                                  1
#define  FEC_DI_STATUS__M                                                  0x1
#define  FEC_DI_STATUS__PRE                                                0x0
#define  FEC_DI_MODE__A                                                    0x1C20011
#define  FEC_DI_MODE__W                                                    3
#define  FEC_DI_MODE__M                                                    0x7
#define  FEC_DI_MODE__PRE                                                  0x0

#define    FEC_DI_MODE_NO_SYNC__B                                          0
#define    FEC_DI_MODE_NO_SYNC__W                                          1
#define    FEC_DI_MODE_NO_SYNC__M                                          0x1
#define    FEC_DI_MODE_NO_SYNC__PRE                                        0x0

#define    FEC_DI_MODE_IGNORE_LOST_SYNC__B                                 1
#define    FEC_DI_MODE_IGNORE_LOST_SYNC__W                                 1
#define    FEC_DI_MODE_IGNORE_LOST_SYNC__M                                 0x2
#define    FEC_DI_MODE_IGNORE_LOST_SYNC__PRE                               0x0

#define    FEC_DI_MODE_IGNORE_TIMEOUT__B                                   2
#define    FEC_DI_MODE_IGNORE_TIMEOUT__W                                   1
#define    FEC_DI_MODE_IGNORE_TIMEOUT__M                                   0x4
#define    FEC_DI_MODE_IGNORE_TIMEOUT__PRE                                 0x0


#define  FEC_DI_CONTROL_WORD__A                                            0x1C20012
#define  FEC_DI_CONTROL_WORD__W                                            4
#define  FEC_DI_CONTROL_WORD__M                                            0xF
#define  FEC_DI_CONTROL_WORD__PRE                                          0x0

#define  FEC_DI_RESTART__A                                                 0x1C20013
#define  FEC_DI_RESTART__W                                                 1
#define  FEC_DI_RESTART__M                                                 0x1
#define  FEC_DI_RESTART__PRE                                               0x0

#define  FEC_DI_TIMEOUT_LO__A                                              0x1C20014
#define  FEC_DI_TIMEOUT_LO__W                                              16
#define  FEC_DI_TIMEOUT_LO__M                                              0xFFFF
#define  FEC_DI_TIMEOUT_LO__PRE                                            0x0

#define  FEC_DI_TIMEOUT_HI__A                                              0x1C20015
#define  FEC_DI_TIMEOUT_HI__W                                              8
#define  FEC_DI_TIMEOUT_HI__M                                              0xFF
#define  FEC_DI_TIMEOUT_HI__PRE                                            0xA

#define  FEC_DI_INPUT_CTL__A                                               0x1C20016
#define  FEC_DI_INPUT_CTL__W                                               1
#define  FEC_DI_INPUT_CTL__M                                               0x1
#define  FEC_DI_INPUT_CTL__PRE                                             0x0



#define  FEC_RS_COMM_EXEC__A                                               0x1C30000
#define  FEC_RS_COMM_EXEC__W                                               2
#define  FEC_RS_COMM_EXEC__M                                               0x3
#define  FEC_RS_COMM_EXEC__PRE                                             0x0
#define    FEC_RS_COMM_EXEC_STOP                                           0x0
#define    FEC_RS_COMM_EXEC_ACTIVE                                         0x1
#define    FEC_RS_COMM_EXEC_HOLD                                           0x2

#define  FEC_RS_COMM_MB__A                                                 0x1C30002
#define  FEC_RS_COMM_MB__W                                                 2
#define  FEC_RS_COMM_MB__M                                                 0x3
#define  FEC_RS_COMM_MB__PRE                                               0x0
#define    FEC_RS_COMM_MB_CTL__B                                           0
#define    FEC_RS_COMM_MB_CTL__W                                           1
#define    FEC_RS_COMM_MB_CTL__M                                           0x1
#define    FEC_RS_COMM_MB_CTL__PRE                                         0x0
#define      FEC_RS_COMM_MB_CTL_OFF                                        0x0
#define      FEC_RS_COMM_MB_CTL_ON                                         0x1
#define    FEC_RS_COMM_MB_OBS__B                                           1
#define    FEC_RS_COMM_MB_OBS__W                                           1
#define    FEC_RS_COMM_MB_OBS__M                                           0x2
#define    FEC_RS_COMM_MB_OBS__PRE                                         0x0
#define      FEC_RS_COMM_MB_OBS_OFF                                        0x0
#define      FEC_RS_COMM_MB_OBS_ON                                         0x2

#define  FEC_RS_COMM_INT_REQ__A                                            0x1C30003
#define  FEC_RS_COMM_INT_REQ__W                                            1
#define  FEC_RS_COMM_INT_REQ__M                                            0x1
#define  FEC_RS_COMM_INT_REQ__PRE                                          0x0
#define  FEC_RS_COMM_INT_STA__A                                            0x1C30005
#define  FEC_RS_COMM_INT_STA__W                                            2
#define  FEC_RS_COMM_INT_STA__M                                            0x3
#define  FEC_RS_COMM_INT_STA__PRE                                          0x0

#define    FEC_RS_COMM_INT_STA_FAILURE_INT__B                              0
#define    FEC_RS_COMM_INT_STA_FAILURE_INT__W                              1
#define    FEC_RS_COMM_INT_STA_FAILURE_INT__M                              0x1
#define    FEC_RS_COMM_INT_STA_FAILURE_INT__PRE                            0x0

#define    FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B                          1
#define    FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W                          1
#define    FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M                          0x2
#define    FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE                        0x0

#define  FEC_RS_COMM_INT_MSK__A                                            0x1C30006
#define  FEC_RS_COMM_INT_MSK__W                                            2
#define  FEC_RS_COMM_INT_MSK__M                                            0x3
#define  FEC_RS_COMM_INT_MSK__PRE                                          0x0
#define    FEC_RS_COMM_INT_MSK_FAILURE_MSK__B                              0
#define    FEC_RS_COMM_INT_MSK_FAILURE_MSK__W                              1
#define    FEC_RS_COMM_INT_MSK_FAILURE_MSK__M                              0x1
#define    FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE                            0x0
#define    FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B                          1
#define    FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W                          1
#define    FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M                          0x2
#define    FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE                        0x0

#define  FEC_RS_COMM_INT_STM__A                                            0x1C30007
#define  FEC_RS_COMM_INT_STM__W                                            2
#define  FEC_RS_COMM_INT_STM__M                                            0x3
#define  FEC_RS_COMM_INT_STM__PRE                                          0x0
#define    FEC_RS_COMM_INT_STM_FAILURE_MSK__B                              0
#define    FEC_RS_COMM_INT_STM_FAILURE_MSK__W                              1
#define    FEC_RS_COMM_INT_STM_FAILURE_MSK__M                              0x1
#define    FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE                            0x0
#define    FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B                          1
#define    FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W                          1
#define    FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M                          0x2
#define    FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE                        0x0

#define  FEC_RS_STATUS__A                                                  0x1C30010
#define  FEC_RS_STATUS__W                                                  1
#define  FEC_RS_STATUS__M                                                  0x1
#define  FEC_RS_STATUS__PRE                                                0x0
#define  FEC_RS_MODE__A                                                    0x1C30011
#define  FEC_RS_MODE__W                                                    1
#define  FEC_RS_MODE__M                                                    0x1
#define  FEC_RS_MODE__PRE                                                  0x0

#define    FEC_RS_MODE_BYPASS__B                                           0
#define    FEC_RS_MODE_BYPASS__W                                           1
#define    FEC_RS_MODE_BYPASS__M                                           0x1
#define    FEC_RS_MODE_BYPASS__PRE                                         0x0

#define  FEC_RS_MEASUREMENT_PERIOD__A                                      0x1C30012
#define  FEC_RS_MEASUREMENT_PERIOD__W                                      16
#define  FEC_RS_MEASUREMENT_PERIOD__M                                      0xFFFF
#define  FEC_RS_MEASUREMENT_PERIOD__PRE                                    0x993

#define    FEC_RS_MEASUREMENT_PERIOD_PERIOD__B                             0
#define    FEC_RS_MEASUREMENT_PERIOD_PERIOD__W                             16
#define    FEC_RS_MEASUREMENT_PERIOD_PERIOD__M                             0xFFFF
#define    FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE                           0x993

#define  FEC_RS_MEASUREMENT_PRESCALE__A                                    0x1C30013
#define  FEC_RS_MEASUREMENT_PRESCALE__W                                    16
#define  FEC_RS_MEASUREMENT_PRESCALE__M                                    0xFFFF
#define  FEC_RS_MEASUREMENT_PRESCALE__PRE                                  0x1

#define    FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B                         0
#define    FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W                         16
#define    FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M                         0xFFFF
#define    FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE                       0x1

#define  FEC_RS_NR_BIT_ERRORS__A                                           0x1C30014
#define  FEC_RS_NR_BIT_ERRORS__W                                           16
#define  FEC_RS_NR_BIT_ERRORS__M                                           0xFFFF
#define  FEC_RS_NR_BIT_ERRORS__PRE                                         0xFFFF

#define    FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B                              0
#define    FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W                              12
#define    FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M                              0xFFF
#define    FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE                            0xFFF

#define    FEC_RS_NR_BIT_ERRORS_EXP__B                                     12
#define    FEC_RS_NR_BIT_ERRORS_EXP__W                                     4
#define    FEC_RS_NR_BIT_ERRORS_EXP__M                                     0xF000
#define    FEC_RS_NR_BIT_ERRORS_EXP__PRE                                   0xF000

#define  FEC_RS_NR_SYMBOL_ERRORS__A                                        0x1C30015
#define  FEC_RS_NR_SYMBOL_ERRORS__W                                        16
#define  FEC_RS_NR_SYMBOL_ERRORS__M                                        0xFFFF
#define  FEC_RS_NR_SYMBOL_ERRORS__PRE                                      0xFFFF

#define    FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B                           0
#define    FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W                           12
#define    FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M                           0xFFF
#define    FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                         0xFFF

#define    FEC_RS_NR_SYMBOL_ERRORS_EXP__B                                  12
#define    FEC_RS_NR_SYMBOL_ERRORS_EXP__W                                  4
#define    FEC_RS_NR_SYMBOL_ERRORS_EXP__M                                  0xF000
#define    FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE                                0xF000

#define  FEC_RS_NR_PACKET_ERRORS__A                                        0x1C30016
#define  FEC_RS_NR_PACKET_ERRORS__W                                        16
#define  FEC_RS_NR_PACKET_ERRORS__M                                        0xFFFF
#define  FEC_RS_NR_PACKET_ERRORS__PRE                                      0xFFFF

#define    FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B                           0
#define    FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W                           12
#define    FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M                           0xFFF
#define    FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE                         0xFFF

#define    FEC_RS_NR_PACKET_ERRORS_EXP__B                                  12
#define    FEC_RS_NR_PACKET_ERRORS_EXP__W                                  4
#define    FEC_RS_NR_PACKET_ERRORS_EXP__M                                  0xF000
#define    FEC_RS_NR_PACKET_ERRORS_EXP__PRE                                0xF000

#define  FEC_RS_NR_FAILURES__A                                             0x1C30017
#define  FEC_RS_NR_FAILURES__W                                             16
#define  FEC_RS_NR_FAILURES__M                                             0xFFFF
#define  FEC_RS_NR_FAILURES__PRE                                           0x0

#define    FEC_RS_NR_FAILURES_FIXED_MANT__B                                0
#define    FEC_RS_NR_FAILURES_FIXED_MANT__W                                12
#define    FEC_RS_NR_FAILURES_FIXED_MANT__M                                0xFFF
#define    FEC_RS_NR_FAILURES_FIXED_MANT__PRE                              0x0

#define    FEC_RS_NR_FAILURES_EXP__B                                       12
#define    FEC_RS_NR_FAILURES_EXP__W                                       4
#define    FEC_RS_NR_FAILURES_EXP__M                                       0xF000
#define    FEC_RS_NR_FAILURES_EXP__PRE                                     0x0



#define  FEC_OC_COMM_EXEC__A                                               0x1C40000
#define  FEC_OC_COMM_EXEC__W                                               2
#define  FEC_OC_COMM_EXEC__M                                               0x3
#define  FEC_OC_COMM_EXEC__PRE                                             0x0
#define    FEC_OC_COMM_EXEC_STOP                                           0x0
#define    FEC_OC_COMM_EXEC_ACTIVE                                         0x1
#define    FEC_OC_COMM_EXEC_HOLD                                           0x2

#define  FEC_OC_COMM_MB__A                                                 0x1C40002
#define  FEC_OC_COMM_MB__W                                                 2
#define  FEC_OC_COMM_MB__M                                                 0x3
#define  FEC_OC_COMM_MB__PRE                                               0x0
#define    FEC_OC_COMM_MB_CTL__B                                           0
#define    FEC_OC_COMM_MB_CTL__W                                           1
#define    FEC_OC_COMM_MB_CTL__M                                           0x1
#define    FEC_OC_COMM_MB_CTL__PRE                                         0x0
#define      FEC_OC_COMM_MB_CTL_OFF                                        0x0
#define      FEC_OC_COMM_MB_CTL_ON                                         0x1
#define    FEC_OC_COMM_MB_OBS__B                                           1
#define    FEC_OC_COMM_MB_OBS__W                                           1
#define    FEC_OC_COMM_MB_OBS__M                                           0x2
#define    FEC_OC_COMM_MB_OBS__PRE                                         0x0
#define      FEC_OC_COMM_MB_OBS_OFF                                        0x0
#define      FEC_OC_COMM_MB_OBS_ON                                         0x2

#define  FEC_OC_COMM_INT_REQ__A                                            0x1C40003
#define  FEC_OC_COMM_INT_REQ__W                                            1
#define  FEC_OC_COMM_INT_REQ__M                                            0x1
#define  FEC_OC_COMM_INT_REQ__PRE                                          0x0
#define  FEC_OC_COMM_INT_STA__A                                            0x1C40005
#define  FEC_OC_COMM_INT_STA__W                                            8
#define  FEC_OC_COMM_INT_STA__M                                            0xFF
#define  FEC_OC_COMM_INT_STA__PRE                                          0x0

#define    FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B                             0
#define    FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W                             1
#define    FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M                             0x1
#define    FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE                           0x0

#define    FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B                             1
#define    FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W                             1
#define    FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M                             0x2
#define    FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE                           0x0

#define    FEC_OC_COMM_INT_STA_SNC_LOST_INT__B                             2
#define    FEC_OC_COMM_INT_STA_SNC_LOST_INT__W                             1
#define    FEC_OC_COMM_INT_STA_SNC_LOST_INT__M                             0x4
#define    FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE                           0x0

#define    FEC_OC_COMM_INT_STA_SNC_PAR_INT__B                              3
#define    FEC_OC_COMM_INT_STA_SNC_PAR_INT__W                              1
#define    FEC_OC_COMM_INT_STA_SNC_PAR_INT__M                              0x8
#define    FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE                            0x0

#define    FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B                            4
#define    FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W                            1
#define    FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M                            0x10
#define    FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE                          0x0

#define    FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B                           5
#define    FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W                           1
#define    FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M                           0x20
#define    FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE                         0x0

#define    FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B                              6
#define    FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W                              1
#define    FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M                              0x40
#define    FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE                            0x0

#define    FEC_OC_COMM_INT_STA_STAT_CHG_INT__B                             7
#define    FEC_OC_COMM_INT_STA_STAT_CHG_INT__W                             1
#define    FEC_OC_COMM_INT_STA_STAT_CHG_INT__M                             0x80
#define    FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE                           0x0

#define  FEC_OC_COMM_INT_MSK__A                                            0x1C40006
#define  FEC_OC_COMM_INT_MSK__W                                            8
#define  FEC_OC_COMM_INT_MSK__M                                            0xFF
#define  FEC_OC_COMM_INT_MSK__PRE                                          0x0
#define    FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B                             0
#define    FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W                             1
#define    FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M                             0x1
#define    FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE                           0x0
#define    FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B                             1
#define    FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W                             1
#define    FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M                             0x2
#define    FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE                           0x0
#define    FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B                             2
#define    FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W                             1
#define    FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M                             0x4
#define    FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE                           0x0
#define    FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B                              3
#define    FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W                              1
#define    FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M                              0x8
#define    FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE                            0x0
#define    FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B                            4
#define    FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W                            1
#define    FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M                            0x10
#define    FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE                          0x0
#define    FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B                           5
#define    FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W                           1
#define    FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M                           0x20
#define    FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE                         0x0
#define    FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B                              6
#define    FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W                              1
#define    FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M                              0x40
#define    FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE                            0x0
#define    FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B                             7
#define    FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W                             1
#define    FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M                             0x80
#define    FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE                           0x0

#define  FEC_OC_COMM_INT_STM__A                                            0x1C40007
#define  FEC_OC_COMM_INT_STM__W                                            8
#define  FEC_OC_COMM_INT_STM__M                                            0xFF
#define  FEC_OC_COMM_INT_STM__PRE                                          0x0
#define    FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B                             0
#define    FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W                             1
#define    FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M                             0x1
#define    FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE                           0x0
#define    FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B                             1
#define    FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W                             1
#define    FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M                             0x2
#define    FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE                           0x0
#define    FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B                             2
#define    FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W                             1
#define    FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M                             0x4
#define    FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE                           0x0
#define    FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B                              3
#define    FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W                              1
#define    FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M                              0x8
#define    FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE                            0x0
#define    FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B                            4
#define    FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W                            1
#define    FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M                            0x10
#define    FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE                          0x0
#define    FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B                           5
#define    FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W                           1
#define    FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M                           0x20
#define    FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE                         0x0
#define    FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B                              6
#define    FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W                              1
#define    FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M                              0x40
#define    FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE                            0x0
#define    FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B                             7
#define    FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W                             1
#define    FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M                             0x80
#define    FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE                           0x0

#define  FEC_OC_STATUS__A                                                  0x1C40010
#define  FEC_OC_STATUS__W                                                  5
#define  FEC_OC_STATUS__M                                                  0x1F
#define  FEC_OC_STATUS__PRE                                                0x0

#define    FEC_OC_STATUS_DPR_STATUS__B                                     0
#define    FEC_OC_STATUS_DPR_STATUS__W                                     1
#define    FEC_OC_STATUS_DPR_STATUS__M                                     0x1
#define    FEC_OC_STATUS_DPR_STATUS__PRE                                   0x0

#define    FEC_OC_STATUS_SNC_STATUS__B                                     1
#define    FEC_OC_STATUS_SNC_STATUS__W                                     2
#define    FEC_OC_STATUS_SNC_STATUS__M                                     0x6
#define    FEC_OC_STATUS_SNC_STATUS__PRE                                   0x0
#define      FEC_OC_STATUS_SNC_STATUS_HUNTING                              0x0
#define      FEC_OC_STATUS_SNC_STATUS_TRACKING                             0x2
#define      FEC_OC_STATUS_SNC_STATUS_LOCKED                               0x4

#define    FEC_OC_STATUS_FIFO_FULL__B                                      3
#define    FEC_OC_STATUS_FIFO_FULL__W                                      1
#define    FEC_OC_STATUS_FIFO_FULL__M                                      0x8
#define    FEC_OC_STATUS_FIFO_FULL__PRE                                    0x0

#define    FEC_OC_STATUS_FIFO_EMPTY__B                                     4
#define    FEC_OC_STATUS_FIFO_EMPTY__W                                     1
#define    FEC_OC_STATUS_FIFO_EMPTY__M                                     0x10
#define    FEC_OC_STATUS_FIFO_EMPTY__PRE                                   0x0

#define  FEC_OC_MODE__A                                                    0x1C40011
#define  FEC_OC_MODE__W                                                    4
#define  FEC_OC_MODE__M                                                    0xF
#define  FEC_OC_MODE__PRE                                                  0x0

#define    FEC_OC_MODE_PARITY__B                                           0
#define    FEC_OC_MODE_PARITY__W                                           1
#define    FEC_OC_MODE_PARITY__M                                           0x1
#define    FEC_OC_MODE_PARITY__PRE                                         0x0

#define    FEC_OC_MODE_TRANSPARENT__B                                      1
#define    FEC_OC_MODE_TRANSPARENT__W                                      1
#define    FEC_OC_MODE_TRANSPARENT__M                                      0x2
#define    FEC_OC_MODE_TRANSPARENT__PRE                                    0x0

#define    FEC_OC_MODE_CLEAR__B                                            2
#define    FEC_OC_MODE_CLEAR__W                                            1
#define    FEC_OC_MODE_CLEAR__M                                            0x4
#define    FEC_OC_MODE_CLEAR__PRE                                          0x0

#define    FEC_OC_MODE_RETAIN_FRAMING__B                                   3
#define    FEC_OC_MODE_RETAIN_FRAMING__W                                   1
#define    FEC_OC_MODE_RETAIN_FRAMING__M                                   0x8
#define    FEC_OC_MODE_RETAIN_FRAMING__PRE                                 0x0

#define  FEC_OC_DPR_MODE__A                                                0x1C40012
#define  FEC_OC_DPR_MODE__W                                                2
#define  FEC_OC_DPR_MODE__M                                                0x3
#define  FEC_OC_DPR_MODE__PRE                                              0x0

#define    FEC_OC_DPR_MODE_ERR_DISABLE__B                                  0
#define    FEC_OC_DPR_MODE_ERR_DISABLE__W                                  1
#define    FEC_OC_DPR_MODE_ERR_DISABLE__M                                  0x1
#define    FEC_OC_DPR_MODE_ERR_DISABLE__PRE                                0x0

#define    FEC_OC_DPR_MODE_NOSYNC_ENABLE__B                                1
#define    FEC_OC_DPR_MODE_NOSYNC_ENABLE__W                                1
#define    FEC_OC_DPR_MODE_NOSYNC_ENABLE__M                                0x2
#define    FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE                              0x0


#define  FEC_OC_DPR_UNLOCK__A                                              0x1C40013
#define  FEC_OC_DPR_UNLOCK__W                                              1
#define  FEC_OC_DPR_UNLOCK__M                                              0x1
#define  FEC_OC_DPR_UNLOCK__PRE                                            0x0
#define  FEC_OC_DTO_MODE__A                                                0x1C40014
#define  FEC_OC_DTO_MODE__W                                                3
#define  FEC_OC_DTO_MODE__M                                                0x7
#define  FEC_OC_DTO_MODE__PRE                                              0x0

#define    FEC_OC_DTO_MODE_DYNAMIC__B                                      0
#define    FEC_OC_DTO_MODE_DYNAMIC__W                                      1
#define    FEC_OC_DTO_MODE_DYNAMIC__M                                      0x1
#define    FEC_OC_DTO_MODE_DYNAMIC__PRE                                    0x0

#define    FEC_OC_DTO_MODE_DUTY_CYCLE__B                                   1
#define    FEC_OC_DTO_MODE_DUTY_CYCLE__W                                   1
#define    FEC_OC_DTO_MODE_DUTY_CYCLE__M                                   0x2
#define    FEC_OC_DTO_MODE_DUTY_CYCLE__PRE                                 0x0

#define    FEC_OC_DTO_MODE_OFFSET_ENABLE__B                                2
#define    FEC_OC_DTO_MODE_OFFSET_ENABLE__W                                1
#define    FEC_OC_DTO_MODE_OFFSET_ENABLE__M                                0x4
#define    FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE                              0x0


#define  FEC_OC_DTO_PERIOD__A                                              0x1C40015
#define  FEC_OC_DTO_PERIOD__W                                              8
#define  FEC_OC_DTO_PERIOD__M                                              0xFF
#define  FEC_OC_DTO_PERIOD__PRE                                            0x0
#define  FEC_OC_DTO_RATE_LO__A                                             0x1C40016
#define  FEC_OC_DTO_RATE_LO__W                                             16
#define  FEC_OC_DTO_RATE_LO__M                                             0xFFFF
#define  FEC_OC_DTO_RATE_LO__PRE                                           0x0

#define    FEC_OC_DTO_RATE_LO_RATE_LO__B                                   0
#define    FEC_OC_DTO_RATE_LO_RATE_LO__W                                   16
#define    FEC_OC_DTO_RATE_LO_RATE_LO__M                                   0xFFFF
#define    FEC_OC_DTO_RATE_LO_RATE_LO__PRE                                 0x0

#define  FEC_OC_DTO_RATE_HI__A                                             0x1C40017
#define  FEC_OC_DTO_RATE_HI__W                                             10
#define  FEC_OC_DTO_RATE_HI__M                                             0x3FF
#define  FEC_OC_DTO_RATE_HI__PRE                                           0xC0

#define    FEC_OC_DTO_RATE_HI_RATE_HI__B                                   0
#define    FEC_OC_DTO_RATE_HI_RATE_HI__W                                   10
#define    FEC_OC_DTO_RATE_HI_RATE_HI__M                                   0x3FF
#define    FEC_OC_DTO_RATE_HI_RATE_HI__PRE                                 0xC0

#define  FEC_OC_DTO_BURST_LEN__A                                           0x1C40018
#define  FEC_OC_DTO_BURST_LEN__W                                           8
#define  FEC_OC_DTO_BURST_LEN__M                                           0xFF
#define  FEC_OC_DTO_BURST_LEN__PRE                                         0xBC

#define    FEC_OC_DTO_BURST_LEN_BURST_LEN__B                               0
#define    FEC_OC_DTO_BURST_LEN_BURST_LEN__W                               8
#define    FEC_OC_DTO_BURST_LEN_BURST_LEN__M                               0xFF
#define    FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE                             0xBC

#define  FEC_OC_FCT_MODE__A                                                0x1C4001A
#define  FEC_OC_FCT_MODE__W                                                2
#define  FEC_OC_FCT_MODE__M                                                0x3
#define  FEC_OC_FCT_MODE__PRE                                              0x0

#define    FEC_OC_FCT_MODE_RAT_ENA__B                                      0
#define    FEC_OC_FCT_MODE_RAT_ENA__W                                      1
#define    FEC_OC_FCT_MODE_RAT_ENA__M                                      0x1
#define    FEC_OC_FCT_MODE_RAT_ENA__PRE                                    0x0

#define    FEC_OC_FCT_MODE_VIRT_ENA__B                                     1
#define    FEC_OC_FCT_MODE_VIRT_ENA__W                                     1
#define    FEC_OC_FCT_MODE_VIRT_ENA__M                                     0x2
#define    FEC_OC_FCT_MODE_VIRT_ENA__PRE                                   0x0

#define  FEC_OC_FCT_USAGE__A                                               0x1C4001B
#define  FEC_OC_FCT_USAGE__W                                               3
#define  FEC_OC_FCT_USAGE__M                                               0x7
#define  FEC_OC_FCT_USAGE__PRE                                             0x7

#define    FEC_OC_FCT_USAGE_USAGE__B                                       0
#define    FEC_OC_FCT_USAGE_USAGE__W                                       3
#define    FEC_OC_FCT_USAGE_USAGE__M                                       0x7
#define    FEC_OC_FCT_USAGE_USAGE__PRE                                     0x7

#define  FEC_OC_FCT_OCCUPATION__A                                          0x1C4001C
#define  FEC_OC_FCT_OCCUPATION__W                                          12
#define  FEC_OC_FCT_OCCUPATION__M                                          0xFFF
#define  FEC_OC_FCT_OCCUPATION__PRE                                        0x0

#define    FEC_OC_FCT_OCCUPATION_OCCUPATION__B                             0
#define    FEC_OC_FCT_OCCUPATION_OCCUPATION__W                             12
#define    FEC_OC_FCT_OCCUPATION_OCCUPATION__M                             0xFFF
#define    FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE                           0x0

#define  FEC_OC_TMD_MODE__A                                                0x1C4001E
#define  FEC_OC_TMD_MODE__W                                                3
#define  FEC_OC_TMD_MODE__M                                                0x7
#define  FEC_OC_TMD_MODE__PRE                                              0x4

#define    FEC_OC_TMD_MODE_MODE__B                                         0
#define    FEC_OC_TMD_MODE_MODE__W                                         3
#define    FEC_OC_TMD_MODE_MODE__M                                         0x7
#define    FEC_OC_TMD_MODE_MODE__PRE                                       0x4

#define  FEC_OC_TMD_COUNT__A                                               0x1C4001F
#define  FEC_OC_TMD_COUNT__W                                               10
#define  FEC_OC_TMD_COUNT__M                                               0x3FF
#define  FEC_OC_TMD_COUNT__PRE                                             0x1F4

#define    FEC_OC_TMD_COUNT_COUNT__B                                       0
#define    FEC_OC_TMD_COUNT_COUNT__W                                       10
#define    FEC_OC_TMD_COUNT_COUNT__M                                       0x3FF
#define    FEC_OC_TMD_COUNT_COUNT__PRE                                     0x1F4

#define  FEC_OC_TMD_HI_MARGIN__A                                           0x1C40020
#define  FEC_OC_TMD_HI_MARGIN__W                                           11
#define  FEC_OC_TMD_HI_MARGIN__M                                           0x7FF
#define  FEC_OC_TMD_HI_MARGIN__PRE                                         0x500

#define    FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B                               0
#define    FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W                               11
#define    FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M                               0x7FF
#define    FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE                             0x500

#define  FEC_OC_TMD_LO_MARGIN__A                                           0x1C40021
#define  FEC_OC_TMD_LO_MARGIN__W                                           11
#define  FEC_OC_TMD_LO_MARGIN__M                                           0x7FF
#define  FEC_OC_TMD_LO_MARGIN__PRE                                         0x300

#define    FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B                               0
#define    FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W                               11
#define    FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M                               0x7FF
#define    FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE                             0x300

#define  FEC_OC_TMD_CTL_UPD_RATE__A                                        0x1C40022
#define  FEC_OC_TMD_CTL_UPD_RATE__W                                        4
#define  FEC_OC_TMD_CTL_UPD_RATE__M                                        0xF
#define  FEC_OC_TMD_CTL_UPD_RATE__PRE                                      0x1

#define    FEC_OC_TMD_CTL_UPD_RATE_RATE__B                                 0
#define    FEC_OC_TMD_CTL_UPD_RATE_RATE__W                                 4
#define    FEC_OC_TMD_CTL_UPD_RATE_RATE__M                                 0xF
#define    FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE                               0x1

#define  FEC_OC_TMD_INT_UPD_RATE__A                                        0x1C40023
#define  FEC_OC_TMD_INT_UPD_RATE__W                                        4
#define  FEC_OC_TMD_INT_UPD_RATE__M                                        0xF
#define  FEC_OC_TMD_INT_UPD_RATE__PRE                                      0x4

#define    FEC_OC_TMD_INT_UPD_RATE_RATE__B                                 0
#define    FEC_OC_TMD_INT_UPD_RATE_RATE__W                                 4
#define    FEC_OC_TMD_INT_UPD_RATE_RATE__M                                 0xF
#define    FEC_OC_TMD_INT_UPD_RATE_RATE__PRE                               0x4

#define  FEC_OC_AVR_PARM_A__A                                              0x1C40026
#define  FEC_OC_AVR_PARM_A__W                                              4
#define  FEC_OC_AVR_PARM_A__M                                              0xF
#define  FEC_OC_AVR_PARM_A__PRE                                            0x6

#define    FEC_OC_AVR_PARM_A_PARM__B                                       0
#define    FEC_OC_AVR_PARM_A_PARM__W                                       4
#define    FEC_OC_AVR_PARM_A_PARM__M                                       0xF
#define    FEC_OC_AVR_PARM_A_PARM__PRE                                     0x6

#define  FEC_OC_AVR_PARM_B__A                                              0x1C40027
#define  FEC_OC_AVR_PARM_B__W                                              4
#define  FEC_OC_AVR_PARM_B__M                                              0xF
#define  FEC_OC_AVR_PARM_B__PRE                                            0x4

#define    FEC_OC_AVR_PARM_B_PARM__B                                       0
#define    FEC_OC_AVR_PARM_B_PARM__W                                       4
#define    FEC_OC_AVR_PARM_B_PARM__M                                       0xF
#define    FEC_OC_AVR_PARM_B_PARM__PRE                                     0x4

#define  FEC_OC_AVR_AVG_LO__A                                              0x1C40028
#define  FEC_OC_AVR_AVG_LO__W                                              16
#define  FEC_OC_AVR_AVG_LO__M                                              0xFFFF
#define  FEC_OC_AVR_AVG_LO__PRE                                            0x0

#define    FEC_OC_AVR_AVG_LO_AVG_LO__B                                     0
#define    FEC_OC_AVR_AVG_LO_AVG_LO__W                                     16
#define    FEC_OC_AVR_AVG_LO_AVG_LO__M                                     0xFFFF
#define    FEC_OC_AVR_AVG_LO_AVG_LO__PRE                                   0x0

#define  FEC_OC_AVR_AVG_HI__A                                              0x1C40029
#define  FEC_OC_AVR_AVG_HI__W                                              6
#define  FEC_OC_AVR_AVG_HI__M                                              0x3F
#define  FEC_OC_AVR_AVG_HI__PRE                                            0x0

#define    FEC_OC_AVR_AVG_HI_AVG_HI__B                                     0
#define    FEC_OC_AVR_AVG_HI_AVG_HI__W                                     6
#define    FEC_OC_AVR_AVG_HI_AVG_HI__M                                     0x3F
#define    FEC_OC_AVR_AVG_HI_AVG_HI__PRE                                   0x0

#define  FEC_OC_RCN_MODE__A                                                0x1C4002C
#define  FEC_OC_RCN_MODE__W                                                5
#define  FEC_OC_RCN_MODE__M                                                0x1F
#define  FEC_OC_RCN_MODE__PRE                                              0x1F

#define    FEC_OC_RCN_MODE_MODE__B                                         0
#define    FEC_OC_RCN_MODE_MODE__W                                         5
#define    FEC_OC_RCN_MODE_MODE__M                                         0x1F
#define    FEC_OC_RCN_MODE_MODE__PRE                                       0x1F

#define  FEC_OC_RCN_OCC_SETTLE__A                                          0x1C4002D
#define  FEC_OC_RCN_OCC_SETTLE__W                                          11
#define  FEC_OC_RCN_OCC_SETTLE__M                                          0x7FF
#define  FEC_OC_RCN_OCC_SETTLE__PRE                                        0x400

#define    FEC_OC_RCN_OCC_SETTLE_LEVEL__B                                  0
#define    FEC_OC_RCN_OCC_SETTLE_LEVEL__W                                  11
#define    FEC_OC_RCN_OCC_SETTLE_LEVEL__M                                  0x7FF
#define    FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE                                0x400

#define  FEC_OC_RCN_GAIN__A                                                0x1C4002E
#define  FEC_OC_RCN_GAIN__W                                                4
#define  FEC_OC_RCN_GAIN__M                                                0xF
#define  FEC_OC_RCN_GAIN__PRE                                              0xC

#define    FEC_OC_RCN_GAIN_GAIN__B                                         0
#define    FEC_OC_RCN_GAIN_GAIN__W                                         4
#define    FEC_OC_RCN_GAIN_GAIN__M                                         0xF
#define    FEC_OC_RCN_GAIN_GAIN__PRE                                       0xC

#define  FEC_OC_RCN_CTL_RATE_LO__A                                         0x1C40030
#define  FEC_OC_RCN_CTL_RATE_LO__W                                         16
#define  FEC_OC_RCN_CTL_RATE_LO__M                                         0xFFFF
#define  FEC_OC_RCN_CTL_RATE_LO__PRE                                       0x0

#define    FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B                                0
#define    FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W                                16
#define    FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M                                0xFFFF
#define    FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE                              0x0

#define  FEC_OC_RCN_CTL_RATE_HI__A                                         0x1C40031
#define  FEC_OC_RCN_CTL_RATE_HI__W                                         8
#define  FEC_OC_RCN_CTL_RATE_HI__M                                         0xFF
#define  FEC_OC_RCN_CTL_RATE_HI__PRE                                       0xC0

#define    FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B                                0
#define    FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W                                8
#define    FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M                                0xFF
#define    FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE                              0xC0

#define  FEC_OC_RCN_CTL_STEP_LO__A                                         0x1C40032
#define  FEC_OC_RCN_CTL_STEP_LO__W                                         16
#define  FEC_OC_RCN_CTL_STEP_LO__M                                         0xFFFF
#define  FEC_OC_RCN_CTL_STEP_LO__PRE                                       0x0

#define    FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B                                0
#define    FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W                                16
#define    FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M                                0xFFFF
#define    FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE                              0x0

#define  FEC_OC_RCN_CTL_STEP_HI__A                                         0x1C40033
#define  FEC_OC_RCN_CTL_STEP_HI__W                                         8
#define  FEC_OC_RCN_CTL_STEP_HI__M                                         0xFF
#define  FEC_OC_RCN_CTL_STEP_HI__PRE                                       0x8

#define    FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B                                0
#define    FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W                                8
#define    FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M                                0xFF
#define    FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE                              0x8

#define  FEC_OC_RCN_DTO_OFS_LO__A                                          0x1C40034
#define  FEC_OC_RCN_DTO_OFS_LO__W                                          16
#define  FEC_OC_RCN_DTO_OFS_LO__M                                          0xFFFF
#define  FEC_OC_RCN_DTO_OFS_LO__PRE                                        0x0

#define    FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B                                 0
#define    FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W                                 16
#define    FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M                                 0xFFFF
#define    FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE                               0x0

#define  FEC_OC_RCN_DTO_OFS_HI__A                                          0x1C40035
#define  FEC_OC_RCN_DTO_OFS_HI__W                                          8
#define  FEC_OC_RCN_DTO_OFS_HI__M                                          0xFF
#define  FEC_OC_RCN_DTO_OFS_HI__PRE                                        0x0

#define    FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B                                 0
#define    FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W                                 8
#define    FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M                                 0xFF
#define    FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE                               0x0

#define  FEC_OC_RCN_DTO_RATE_LO__A                                         0x1C40036
#define  FEC_OC_RCN_DTO_RATE_LO__W                                         16
#define  FEC_OC_RCN_DTO_RATE_LO__M                                         0xFFFF
#define  FEC_OC_RCN_DTO_RATE_LO__PRE                                       0x0

#define    FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B                                0
#define    FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W                                16
#define    FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M                                0xFFFF
#define    FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE                              0x0

#define  FEC_OC_RCN_DTO_RATE_HI__A                                         0x1C40037
#define  FEC_OC_RCN_DTO_RATE_HI__W                                         8
#define  FEC_OC_RCN_DTO_RATE_HI__M                                         0xFF
#define  FEC_OC_RCN_DTO_RATE_HI__PRE                                       0x0

#define    FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B                                0
#define    FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W                                8
#define    FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M                                0xFF
#define    FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE                              0x0

#define  FEC_OC_RCN_RATE_CLIP_LO__A                                        0x1C40038
#define  FEC_OC_RCN_RATE_CLIP_LO__W                                        16
#define  FEC_OC_RCN_RATE_CLIP_LO__M                                        0xFFFF
#define  FEC_OC_RCN_RATE_CLIP_LO__PRE                                      0x0

#define    FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B                              0
#define    FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W                              16
#define    FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M                              0xFFFF
#define    FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE                            0x0

#define  FEC_OC_RCN_RATE_CLIP_HI__A                                        0x1C40039
#define  FEC_OC_RCN_RATE_CLIP_HI__W                                        8
#define  FEC_OC_RCN_RATE_CLIP_HI__M                                        0xFF
#define  FEC_OC_RCN_RATE_CLIP_HI__PRE                                      0xF0

#define    FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B                              0
#define    FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W                              8
#define    FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M                              0xFF
#define    FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE                            0xF0

#define  FEC_OC_RCN_DYN_RATE_LO__A                                         0x1C4003A
#define  FEC_OC_RCN_DYN_RATE_LO__W                                         16
#define  FEC_OC_RCN_DYN_RATE_LO__M                                         0xFFFF
#define  FEC_OC_RCN_DYN_RATE_LO__PRE                                       0x0

#define    FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B                               0
#define    FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W                               16
#define    FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M                               0xFFFF
#define    FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE                             0x0

#define  FEC_OC_RCN_DYN_RATE_HI__A                                         0x1C4003B
#define  FEC_OC_RCN_DYN_RATE_HI__W                                         8
#define  FEC_OC_RCN_DYN_RATE_HI__M                                         0xFF
#define  FEC_OC_RCN_DYN_RATE_HI__PRE                                       0x0

#define    FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B                               0
#define    FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W                               8
#define    FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M                               0xFF
#define    FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE                             0x0

#define  FEC_OC_SNC_MODE__A                                                0x1C40040
#define  FEC_OC_SNC_MODE__W                                                5
#define  FEC_OC_SNC_MODE__M                                                0x1F
#define  FEC_OC_SNC_MODE__PRE                                              0x0

#define    FEC_OC_SNC_MODE_UNLOCK_ENABLE__B                                0
#define    FEC_OC_SNC_MODE_UNLOCK_ENABLE__W                                1
#define    FEC_OC_SNC_MODE_UNLOCK_ENABLE__M                                0x1
#define    FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE                              0x0

#define    FEC_OC_SNC_MODE_ERROR_CTL__B                                    1
#define    FEC_OC_SNC_MODE_ERROR_CTL__W                                    2
#define    FEC_OC_SNC_MODE_ERROR_CTL__M                                    0x6
#define    FEC_OC_SNC_MODE_ERROR_CTL__PRE                                  0x0

#define    FEC_OC_SNC_MODE_CORR_DISABLE__B                                 3
#define    FEC_OC_SNC_MODE_CORR_DISABLE__W                                 1
#define    FEC_OC_SNC_MODE_CORR_DISABLE__M                                 0x8
#define    FEC_OC_SNC_MODE_CORR_DISABLE__PRE                               0x0

#define    FEC_OC_SNC_MODE_SHUTDOWN__B                                     4
#define    FEC_OC_SNC_MODE_SHUTDOWN__W                                     1
#define    FEC_OC_SNC_MODE_SHUTDOWN__M                                     0x10
#define    FEC_OC_SNC_MODE_SHUTDOWN__PRE                                   0x0

#define  FEC_OC_SNC_LWM__A                                                 0x1C40041
#define  FEC_OC_SNC_LWM__W                                                 4
#define  FEC_OC_SNC_LWM__M                                                 0xF
#define  FEC_OC_SNC_LWM__PRE                                               0x3

#define    FEC_OC_SNC_LWM_MARK__B                                          0
#define    FEC_OC_SNC_LWM_MARK__W                                          4
#define    FEC_OC_SNC_LWM_MARK__M                                          0xF
#define    FEC_OC_SNC_LWM_MARK__PRE                                        0x3

#define  FEC_OC_SNC_HWM__A                                                 0x1C40042
#define  FEC_OC_SNC_HWM__W                                                 4
#define  FEC_OC_SNC_HWM__M                                                 0xF
#define  FEC_OC_SNC_HWM__PRE                                               0x5

#define    FEC_OC_SNC_HWM_MARK__B                                          0
#define    FEC_OC_SNC_HWM_MARK__W                                          4
#define    FEC_OC_SNC_HWM_MARK__M                                          0xF
#define    FEC_OC_SNC_HWM_MARK__PRE                                        0x5

#define  FEC_OC_SNC_UNLOCK__A                                              0x1C40043
#define  FEC_OC_SNC_UNLOCK__W                                              1
#define  FEC_OC_SNC_UNLOCK__M                                              0x1
#define  FEC_OC_SNC_UNLOCK__PRE                                            0x0

#define    FEC_OC_SNC_UNLOCK_RESTART__B                                    0
#define    FEC_OC_SNC_UNLOCK_RESTART__W                                    1
#define    FEC_OC_SNC_UNLOCK_RESTART__M                                    0x1
#define    FEC_OC_SNC_UNLOCK_RESTART__PRE                                  0x0

#define  FEC_OC_SNC_LOCK_COUNT__A                                          0x1C40044
#define  FEC_OC_SNC_LOCK_COUNT__W                                          12
#define  FEC_OC_SNC_LOCK_COUNT__M                                          0xFFF
#define  FEC_OC_SNC_LOCK_COUNT__PRE                                        0x0

#define    FEC_OC_SNC_LOCK_COUNT_COUNT__B                                  0
#define    FEC_OC_SNC_LOCK_COUNT_COUNT__W                                  12
#define    FEC_OC_SNC_LOCK_COUNT_COUNT__M                                  0xFFF
#define    FEC_OC_SNC_LOCK_COUNT_COUNT__PRE                                0x0

#define  FEC_OC_SNC_FAIL_COUNT__A                                          0x1C40045
#define  FEC_OC_SNC_FAIL_COUNT__W                                          12
#define  FEC_OC_SNC_FAIL_COUNT__M                                          0xFFF
#define  FEC_OC_SNC_FAIL_COUNT__PRE                                        0x0

#define    FEC_OC_SNC_FAIL_COUNT_COUNT__B                                  0
#define    FEC_OC_SNC_FAIL_COUNT_COUNT__W                                  12
#define    FEC_OC_SNC_FAIL_COUNT_COUNT__M                                  0xFFF
#define    FEC_OC_SNC_FAIL_COUNT_COUNT__PRE                                0x0

#define  FEC_OC_SNC_FAIL_PERIOD__A                                         0x1C40046
#define  FEC_OC_SNC_FAIL_PERIOD__W                                         16
#define  FEC_OC_SNC_FAIL_PERIOD__M                                         0xFFFF
#define  FEC_OC_SNC_FAIL_PERIOD__PRE                                       0x1171

#define    FEC_OC_SNC_FAIL_PERIOD_PERIOD__B                                0
#define    FEC_OC_SNC_FAIL_PERIOD_PERIOD__W                                16
#define    FEC_OC_SNC_FAIL_PERIOD_PERIOD__M                                0xFFFF
#define    FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE                              0x1171

#define  FEC_OC_EMS_MODE__A                                                0x1C40047
#define  FEC_OC_EMS_MODE__W                                                2
#define  FEC_OC_EMS_MODE__M                                                0x3
#define  FEC_OC_EMS_MODE__PRE                                              0x0

#define    FEC_OC_EMS_MODE_MODE__B                                         0
#define    FEC_OC_EMS_MODE_MODE__W                                         2
#define    FEC_OC_EMS_MODE_MODE__M                                         0x3
#define    FEC_OC_EMS_MODE_MODE__PRE                                       0x0

#define  FEC_OC_IPR_MODE__A                                                0x1C40048
#define  FEC_OC_IPR_MODE__W                                                12
#define  FEC_OC_IPR_MODE__M                                                0xFFF
#define  FEC_OC_IPR_MODE__PRE                                              0x0

#define    FEC_OC_IPR_MODE_SERIAL__B                                       0
#define    FEC_OC_IPR_MODE_SERIAL__W                                       1
#define    FEC_OC_IPR_MODE_SERIAL__M                                       0x1
#define    FEC_OC_IPR_MODE_SERIAL__PRE                                     0x0

#define    FEC_OC_IPR_MODE_REVERSE_ORDER__B                                1
#define    FEC_OC_IPR_MODE_REVERSE_ORDER__W                                1
#define    FEC_OC_IPR_MODE_REVERSE_ORDER__M                                0x2
#define    FEC_OC_IPR_MODE_REVERSE_ORDER__PRE                              0x0

#define    FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B                             2
#define    FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W                             1
#define    FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M                             0x4
#define    FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE                           0x0

#define    FEC_OC_IPR_MODE_MCLK_DIS_PAR__B                                 3
#define    FEC_OC_IPR_MODE_MCLK_DIS_PAR__W                                 1
#define    FEC_OC_IPR_MODE_MCLK_DIS_PAR__M                                 0x8
#define    FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE                               0x0

#define    FEC_OC_IPR_MODE_MVAL_DIS_PAR__B                                 4
#define    FEC_OC_IPR_MODE_MVAL_DIS_PAR__W                                 1
#define    FEC_OC_IPR_MODE_MVAL_DIS_PAR__M                                 0x10
#define    FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE                               0x0

#define    FEC_OC_IPR_MODE_MERR_DIS_PAR__B                                 5
#define    FEC_OC_IPR_MODE_MERR_DIS_PAR__W                                 1
#define    FEC_OC_IPR_MODE_MERR_DIS_PAR__M                                 0x20
#define    FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE                               0x0

#define    FEC_OC_IPR_MODE_MD_DIS_PAR__B                                   6
#define    FEC_OC_IPR_MODE_MD_DIS_PAR__W                                   1
#define    FEC_OC_IPR_MODE_MD_DIS_PAR__M                                   0x40
#define    FEC_OC_IPR_MODE_MD_DIS_PAR__PRE                                 0x0

#define    FEC_OC_IPR_MODE_MCLK_DIS_ERR__B                                 7
#define    FEC_OC_IPR_MODE_MCLK_DIS_ERR__W                                 1
#define    FEC_OC_IPR_MODE_MCLK_DIS_ERR__M                                 0x80
#define    FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE                               0x0

#define    FEC_OC_IPR_MODE_MVAL_DIS_ERR__B                                 8
#define    FEC_OC_IPR_MODE_MVAL_DIS_ERR__W                                 1
#define    FEC_OC_IPR_MODE_MVAL_DIS_ERR__M                                 0x100
#define    FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE                               0x0

#define    FEC_OC_IPR_MODE_MERR_DIS_ERR__B                                 9
#define    FEC_OC_IPR_MODE_MERR_DIS_ERR__W                                 1
#define    FEC_OC_IPR_MODE_MERR_DIS_ERR__M                                 0x200
#define    FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE                               0x0

#define    FEC_OC_IPR_MODE_MD_DIS_ERR__B                                   10
#define    FEC_OC_IPR_MODE_MD_DIS_ERR__W                                   1
#define    FEC_OC_IPR_MODE_MD_DIS_ERR__M                                   0x400
#define    FEC_OC_IPR_MODE_MD_DIS_ERR__PRE                                 0x0

#define    FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B                                11
#define    FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W                                1
#define    FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M                                0x800
#define    FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE                              0x0

#define  FEC_OC_IPR_INVERT__A                                              0x1C40049
#define  FEC_OC_IPR_INVERT__W                                              12
#define  FEC_OC_IPR_INVERT__M                                              0xFFF
#define  FEC_OC_IPR_INVERT__PRE                                            0x0

#define    FEC_OC_IPR_INVERT_MD0__B                                        0
#define    FEC_OC_IPR_INVERT_MD0__W                                        1
#define    FEC_OC_IPR_INVERT_MD0__M                                        0x1
#define    FEC_OC_IPR_INVERT_MD0__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD1__B                                        1
#define    FEC_OC_IPR_INVERT_MD1__W                                        1
#define    FEC_OC_IPR_INVERT_MD1__M                                        0x2
#define    FEC_OC_IPR_INVERT_MD1__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD2__B                                        2
#define    FEC_OC_IPR_INVERT_MD2__W                                        1
#define    FEC_OC_IPR_INVERT_MD2__M                                        0x4
#define    FEC_OC_IPR_INVERT_MD2__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD3__B                                        3
#define    FEC_OC_IPR_INVERT_MD3__W                                        1
#define    FEC_OC_IPR_INVERT_MD3__M                                        0x8
#define    FEC_OC_IPR_INVERT_MD3__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD4__B                                        4
#define    FEC_OC_IPR_INVERT_MD4__W                                        1
#define    FEC_OC_IPR_INVERT_MD4__M                                        0x10
#define    FEC_OC_IPR_INVERT_MD4__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD5__B                                        5
#define    FEC_OC_IPR_INVERT_MD5__W                                        1
#define    FEC_OC_IPR_INVERT_MD5__M                                        0x20
#define    FEC_OC_IPR_INVERT_MD5__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD6__B                                        6
#define    FEC_OC_IPR_INVERT_MD6__W                                        1
#define    FEC_OC_IPR_INVERT_MD6__M                                        0x40
#define    FEC_OC_IPR_INVERT_MD6__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MD7__B                                        7
#define    FEC_OC_IPR_INVERT_MD7__W                                        1
#define    FEC_OC_IPR_INVERT_MD7__M                                        0x80
#define    FEC_OC_IPR_INVERT_MD7__PRE                                      0x0

#define    FEC_OC_IPR_INVERT_MERR__B                                       8
#define    FEC_OC_IPR_INVERT_MERR__W                                       1
#define    FEC_OC_IPR_INVERT_MERR__M                                       0x100
#define    FEC_OC_IPR_INVERT_MERR__PRE                                     0x0

#define    FEC_OC_IPR_INVERT_MSTRT__B                                      9
#define    FEC_OC_IPR_INVERT_MSTRT__W                                      1
#define    FEC_OC_IPR_INVERT_MSTRT__M                                      0x200
#define    FEC_OC_IPR_INVERT_MSTRT__PRE                                    0x0

#define    FEC_OC_IPR_INVERT_MVAL__B                                       10
#define    FEC_OC_IPR_INVERT_MVAL__W                                       1
#define    FEC_OC_IPR_INVERT_MVAL__M                                       0x400
#define    FEC_OC_IPR_INVERT_MVAL__PRE                                     0x0

#define    FEC_OC_IPR_INVERT_MCLK__B                                       11
#define    FEC_OC_IPR_INVERT_MCLK__W                                       1
#define    FEC_OC_IPR_INVERT_MCLK__M                                       0x800
#define    FEC_OC_IPR_INVERT_MCLK__PRE                                     0x0

#define  FEC_OC_OCR_MODE__A                                                0x1C40050
#define  FEC_OC_OCR_MODE__W                                                4
#define  FEC_OC_OCR_MODE__M                                                0xF
#define  FEC_OC_OCR_MODE__PRE                                              0x0

#define    FEC_OC_OCR_MODE_MB_SELECT__B                                    0
#define    FEC_OC_OCR_MODE_MB_SELECT__W                                    1
#define    FEC_OC_OCR_MODE_MB_SELECT__M                                    0x1
#define    FEC_OC_OCR_MODE_MB_SELECT__PRE                                  0x0

#define    FEC_OC_OCR_MODE_GRAB_ENABLE__B                                  1
#define    FEC_OC_OCR_MODE_GRAB_ENABLE__W                                  1
#define    FEC_OC_OCR_MODE_GRAB_ENABLE__M                                  0x2
#define    FEC_OC_OCR_MODE_GRAB_ENABLE__PRE                                0x0

#define    FEC_OC_OCR_MODE_GRAB_SELECT__B                                  2
#define    FEC_OC_OCR_MODE_GRAB_SELECT__W                                  1
#define    FEC_OC_OCR_MODE_GRAB_SELECT__M                                  0x4
#define    FEC_OC_OCR_MODE_GRAB_SELECT__PRE                                0x0

#define    FEC_OC_OCR_MODE_GRAB_COUNTED__B                                 3
#define    FEC_OC_OCR_MODE_GRAB_COUNTED__W                                 1
#define    FEC_OC_OCR_MODE_GRAB_COUNTED__M                                 0x8
#define    FEC_OC_OCR_MODE_GRAB_COUNTED__PRE                               0x0

#define  FEC_OC_OCR_RATE__A                                                0x1C40051
#define  FEC_OC_OCR_RATE__W                                                4
#define  FEC_OC_OCR_RATE__M                                                0xF
#define  FEC_OC_OCR_RATE__PRE                                              0x0

#define    FEC_OC_OCR_RATE_RATE__B                                         0
#define    FEC_OC_OCR_RATE_RATE__W                                         4
#define    FEC_OC_OCR_RATE_RATE__M                                         0xF
#define    FEC_OC_OCR_RATE_RATE__PRE                                       0x0

#define  FEC_OC_OCR_INVERT__A                                              0x1C40052
#define  FEC_OC_OCR_INVERT__W                                              12
#define  FEC_OC_OCR_INVERT__M                                              0xFFF
#define  FEC_OC_OCR_INVERT__PRE                                            0x800

#define    FEC_OC_OCR_INVERT_INVERT__B                                     0
#define    FEC_OC_OCR_INVERT_INVERT__W                                     12
#define    FEC_OC_OCR_INVERT_INVERT__M                                     0xFFF
#define    FEC_OC_OCR_INVERT_INVERT__PRE                                   0x800

#define  FEC_OC_OCR_GRAB_COUNT__A                                          0x1C40053
#define  FEC_OC_OCR_GRAB_COUNT__W                                          16
#define  FEC_OC_OCR_GRAB_COUNT__M                                          0xFFFF
#define  FEC_OC_OCR_GRAB_COUNT__PRE                                        0x0

#define    FEC_OC_OCR_GRAB_COUNT_COUNT__B                                  0
#define    FEC_OC_OCR_GRAB_COUNT_COUNT__W                                  16
#define    FEC_OC_OCR_GRAB_COUNT_COUNT__M                                  0xFFFF
#define    FEC_OC_OCR_GRAB_COUNT_COUNT__PRE                                0x0

#define  FEC_OC_OCR_GRAB_SYNC__A                                           0x1C40054
#define  FEC_OC_OCR_GRAB_SYNC__W                                           8
#define  FEC_OC_OCR_GRAB_SYNC__M                                           0xFF
#define  FEC_OC_OCR_GRAB_SYNC__PRE                                         0x0

#define    FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B                                0
#define    FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W                                3
#define    FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M                                0x7
#define    FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE                              0x0

#define    FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B                                 3
#define    FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W                                 4
#define    FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M                                 0x78
#define    FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE                               0x0

#define    FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B                               7
#define    FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W                               1
#define    FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M                               0x80
#define    FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE                             0x0

#define  FEC_OC_OCR_GRAB_RD0__A                                            0x1C40055
#define  FEC_OC_OCR_GRAB_RD0__W                                            10
#define  FEC_OC_OCR_GRAB_RD0__M                                            0x3FF
#define  FEC_OC_OCR_GRAB_RD0__PRE                                          0x0

#define    FEC_OC_OCR_GRAB_RD0_DATA__B                                     0
#define    FEC_OC_OCR_GRAB_RD0_DATA__W                                     10
#define    FEC_OC_OCR_GRAB_RD0_DATA__M                                     0x3FF
#define    FEC_OC_OCR_GRAB_RD0_DATA__PRE                                   0x0

#define  FEC_OC_OCR_GRAB_RD1__A                                            0x1C40056
#define  FEC_OC_OCR_GRAB_RD1__W                                            10
#define  FEC_OC_OCR_GRAB_RD1__M                                            0x3FF
#define  FEC_OC_OCR_GRAB_RD1__PRE                                          0x0

#define    FEC_OC_OCR_GRAB_RD1_DATA__B                                     0
#define    FEC_OC_OCR_GRAB_RD1_DATA__W                                     10
#define    FEC_OC_OCR_GRAB_RD1_DATA__M                                     0x3FF
#define    FEC_OC_OCR_GRAB_RD1_DATA__PRE                                   0x0

#define  FEC_OC_OCR_GRAB_RD2__A                                            0x1C40057
#define  FEC_OC_OCR_GRAB_RD2__W                                            10
#define  FEC_OC_OCR_GRAB_RD2__M                                            0x3FF
#define  FEC_OC_OCR_GRAB_RD2__PRE                                          0x0

#define    FEC_OC_OCR_GRAB_RD2_DATA__B                                     0
#define    FEC_OC_OCR_GRAB_RD2_DATA__W                                     10
#define    FEC_OC_OCR_GRAB_RD2_DATA__M                                     0x3FF
#define    FEC_OC_OCR_GRAB_RD2_DATA__PRE                                   0x0

#define  FEC_OC_OCR_GRAB_RD3__A                                            0x1C40058
#define  FEC_OC_OCR_GRAB_RD3__W                                            10
#define  FEC_OC_OCR_GRAB_RD3__M                                            0x3FF
#define  FEC_OC_OCR_GRAB_RD3__PRE                                          0x0

#define    FEC_OC_OCR_GRAB_RD3_DATA__B                                     0
#define    FEC_OC_OCR_GRAB_RD3_DATA__W                                     10
#define    FEC_OC_OCR_GRAB_RD3_DATA__M                                     0x3FF
#define    FEC_OC_OCR_GRAB_RD3_DATA__PRE                                   0x0

#define  FEC_OC_OCR_GRAB_RD4__A                                            0x1C40059
#define  FEC_OC_OCR_GRAB_RD4__W                                            10
#define  FEC_OC_OCR_GRAB_RD4__M                                            0x3FF
#define  FEC_OC_OCR_GRAB_RD4__PRE                                          0x0

#define    FEC_OC_OCR_GRAB_RD4_DATA__B                                     0
#define    FEC_OC_OCR_GRAB_RD4_DATA__W                                     10
#define    FEC_OC_OCR_GRAB_RD4_DATA__M                                     0x3FF
#define    FEC_OC_OCR_GRAB_RD4_DATA__PRE                                   0x0

#define  FEC_OC_OCR_GRAB_RD5__A                                            0x1C4005A
#define  FEC_OC_OCR_GRAB_RD5__W                                            10
#define  FEC_OC_OCR_GRAB_RD5__M                                            0x3FF
#define  FEC_OC_OCR_GRAB_RD5__PRE                                          0x0

#define    FEC_OC_OCR_GRAB_RD5_DATA__B                                     0
#define    FEC_OC_OCR_GRAB_RD5_DATA__W                                     10
#define    FEC_OC_OCR_GRAB_RD5_DATA__M                                     0x3FF
#define    FEC_OC_OCR_GRAB_RD5_DATA__PRE                                   0x0



#define  FEC_DI_RAM__A                                                     0x1C50000



#define  FEC_RS_RAM__A                                                     0x1C60000



#define  FEC_OC_RAM__A                                                     0x1C70000





#define  IQM_COMM_EXEC__A                                                  0x1800000
#define  IQM_COMM_EXEC__W                                                  2
#define  IQM_COMM_EXEC__M                                                  0x3
#define  IQM_COMM_EXEC__PRE                                                0x0
#define    IQM_COMM_EXEC_B__B                                              0
#define    IQM_COMM_EXEC_B__W                                              2
#define    IQM_COMM_EXEC_B__M                                              0x3
#define    IQM_COMM_EXEC_B__PRE                                            0x0
#define      IQM_COMM_EXEC_B_STOP                                          0x0
#define      IQM_COMM_EXEC_B_ACTIVE                                        0x1
#define      IQM_COMM_EXEC_B_HOLD                                          0x2

#define  IQM_COMM_MB__A                                                    0x1800002
#define  IQM_COMM_MB__W                                                    16
#define  IQM_COMM_MB__M                                                    0xFFFF
#define  IQM_COMM_MB__PRE                                                  0x0
#define    IQM_COMM_MB_B__B                                                0
#define    IQM_COMM_MB_B__W                                                16
#define    IQM_COMM_MB_B__M                                                0xFFFF
#define    IQM_COMM_MB_B__PRE                                              0x0

#define  IQM_COMM_INT_REQ__A                                               0x1800003
#define  IQM_COMM_INT_REQ__W                                               3
#define  IQM_COMM_INT_REQ__M                                               0x7
#define  IQM_COMM_INT_REQ__PRE                                             0x0

#define    IQM_COMM_INT_REQ_AF_REQ__B                                      0
#define    IQM_COMM_INT_REQ_AF_REQ__W                                      1
#define    IQM_COMM_INT_REQ_AF_REQ__M                                      0x1
#define    IQM_COMM_INT_REQ_AF_REQ__PRE                                    0x0

#define    IQM_COMM_INT_REQ_CF_REQ__B                                      1
#define    IQM_COMM_INT_REQ_CF_REQ__W                                      1
#define    IQM_COMM_INT_REQ_CF_REQ__M                                      0x2
#define    IQM_COMM_INT_REQ_CF_REQ__PRE                                    0x0

#define    IQM_COMM_INT_REQ_CW_REQ__B                                      2
#define    IQM_COMM_INT_REQ_CW_REQ__W                                      1
#define    IQM_COMM_INT_REQ_CW_REQ__M                                      0x4
#define    IQM_COMM_INT_REQ_CW_REQ__PRE                                    0x0

#define  IQM_COMM_INT_STA__A                                               0x1800005
#define  IQM_COMM_INT_STA__W                                               16
#define  IQM_COMM_INT_STA__M                                               0xFFFF
#define  IQM_COMM_INT_STA__PRE                                             0x0
#define    IQM_COMM_INT_STA_B__B                                           0
#define    IQM_COMM_INT_STA_B__W                                           16
#define    IQM_COMM_INT_STA_B__M                                           0xFFFF
#define    IQM_COMM_INT_STA_B__PRE                                         0x0

#define  IQM_COMM_INT_MSK__A                                               0x1800006
#define  IQM_COMM_INT_MSK__W                                               16
#define  IQM_COMM_INT_MSK__M                                               0xFFFF
#define  IQM_COMM_INT_MSK__PRE                                             0x0
#define    IQM_COMM_INT_MSK_B__B                                           0
#define    IQM_COMM_INT_MSK_B__W                                           16
#define    IQM_COMM_INT_MSK_B__M                                           0xFFFF
#define    IQM_COMM_INT_MSK_B__PRE                                         0x0

#define  IQM_COMM_INT_STM__A                                               0x1800007
#define  IQM_COMM_INT_STM__W                                               16
#define  IQM_COMM_INT_STM__M                                               0xFFFF
#define  IQM_COMM_INT_STM__PRE                                             0x0
#define    IQM_COMM_INT_STM_B__B                                           0
#define    IQM_COMM_INT_STM_B__W                                           16
#define    IQM_COMM_INT_STM_B__M                                           0xFFFF
#define    IQM_COMM_INT_STM_B__PRE                                         0x0



#define  IQM_FS_COMM_EXEC__A                                               0x1820000
#define  IQM_FS_COMM_EXEC__W                                               2
#define  IQM_FS_COMM_EXEC__M                                               0x3
#define  IQM_FS_COMM_EXEC__PRE                                             0x0
#define    IQM_FS_COMM_EXEC_STOP                                           0x0
#define    IQM_FS_COMM_EXEC_ACTIVE                                         0x1
#define    IQM_FS_COMM_EXEC_HOLD                                           0x2

#define  IQM_FS_COMM_MB__A                                                 0x1820002
#define  IQM_FS_COMM_MB__W                                                 4
#define  IQM_FS_COMM_MB__M                                                 0xF
#define  IQM_FS_COMM_MB__PRE                                               0x0
#define    IQM_FS_COMM_MB_CTL__B                                           0
#define    IQM_FS_COMM_MB_CTL__W                                           1
#define    IQM_FS_COMM_MB_CTL__M                                           0x1
#define    IQM_FS_COMM_MB_CTL__PRE                                         0x0
#define      IQM_FS_COMM_MB_CTL_CTL_OFF                                    0x0
#define      IQM_FS_COMM_MB_CTL_CTL_ON                                     0x1
#define    IQM_FS_COMM_MB_OBS__B                                           1
#define    IQM_FS_COMM_MB_OBS__W                                           1
#define    IQM_FS_COMM_MB_OBS__M                                           0x2
#define    IQM_FS_COMM_MB_OBS__PRE                                         0x0
#define      IQM_FS_COMM_MB_OBS_OBS_OFF                                    0x0
#define      IQM_FS_COMM_MB_OBS_OBS_ON                                     0x2
#define    IQM_FS_COMM_MB_CTL_MUX__B                                       2
#define    IQM_FS_COMM_MB_CTL_MUX__W                                       1
#define    IQM_FS_COMM_MB_CTL_MUX__M                                       0x4
#define    IQM_FS_COMM_MB_CTL_MUX__PRE                                     0x0
#define    IQM_FS_COMM_MB_OBS_MUX__B                                       3
#define    IQM_FS_COMM_MB_OBS_MUX__W                                       1
#define    IQM_FS_COMM_MB_OBS_MUX__M                                       0x8
#define    IQM_FS_COMM_MB_OBS_MUX__PRE                                     0x0

#define  IQM_FS_RATE_OFS_LO__A                                             0x1820010
#define  IQM_FS_RATE_OFS_LO__W                                             16
#define  IQM_FS_RATE_OFS_LO__M                                             0xFFFF
#define  IQM_FS_RATE_OFS_LO__PRE                                           0x0
#define    IQM_FS_RATE_OFS_LO_B__B                                         0
#define    IQM_FS_RATE_OFS_LO_B__W                                         16
#define    IQM_FS_RATE_OFS_LO_B__M                                         0xFFFF
#define    IQM_FS_RATE_OFS_LO_B__PRE                                       0x0

#define  IQM_FS_RATE_OFS_HI__A                                             0x1820011
#define  IQM_FS_RATE_OFS_HI__W                                             12
#define  IQM_FS_RATE_OFS_HI__M                                             0xFFF
#define  IQM_FS_RATE_OFS_HI__PRE                                           0x0
#define    IQM_FS_RATE_OFS_HI_B__B                                         0
#define    IQM_FS_RATE_OFS_HI_B__W                                         12
#define    IQM_FS_RATE_OFS_HI_B__M                                         0xFFF
#define    IQM_FS_RATE_OFS_HI_B__PRE                                       0x0

#define  IQM_FS_RATE_LO__A                                                 0x1820012
#define  IQM_FS_RATE_LO__W                                                 16
#define  IQM_FS_RATE_LO__M                                                 0xFFFF
#define  IQM_FS_RATE_LO__PRE                                               0x0
#define    IQM_FS_RATE_LO_B__B                                             0
#define    IQM_FS_RATE_LO_B__W                                             16
#define    IQM_FS_RATE_LO_B__M                                             0xFFFF
#define    IQM_FS_RATE_LO_B__PRE                                           0x0

#define  IQM_FS_RATE_HI__A                                                 0x1820013
#define  IQM_FS_RATE_HI__W                                                 12
#define  IQM_FS_RATE_HI__M                                                 0xFFF
#define  IQM_FS_RATE_HI__PRE                                               0x0
#define    IQM_FS_RATE_HI_B__B                                             0
#define    IQM_FS_RATE_HI_B__W                                             12
#define    IQM_FS_RATE_HI_B__M                                             0xFFF
#define    IQM_FS_RATE_HI_B__PRE                                           0x0

#define  IQM_FS_ADJ_SEL__A                                                 0x1820014
#define  IQM_FS_ADJ_SEL__W                                                 2
#define  IQM_FS_ADJ_SEL__M                                                 0x3
#define  IQM_FS_ADJ_SEL__PRE                                               0x0

#define    IQM_FS_ADJ_SEL_B__B                                             0
#define    IQM_FS_ADJ_SEL_B__W                                             2
#define    IQM_FS_ADJ_SEL_B__M                                             0x3
#define    IQM_FS_ADJ_SEL_B__PRE                                           0x0
#define      IQM_FS_ADJ_SEL_B_OFF                                          0x0
#define      IQM_FS_ADJ_SEL_B_QAM                                          0x1
#define      IQM_FS_ADJ_SEL_B_VSB                                          0x2



#define  IQM_FD_COMM_EXEC__A                                               0x1830000
#define  IQM_FD_COMM_EXEC__W                                               2
#define  IQM_FD_COMM_EXEC__M                                               0x3
#define  IQM_FD_COMM_EXEC__PRE                                             0x0
#define    IQM_FD_COMM_EXEC_STOP                                           0x0
#define    IQM_FD_COMM_EXEC_ACTIVE                                         0x1
#define    IQM_FD_COMM_EXEC_HOLD                                           0x2

#define  IQM_FD_COMM_MB__A                                                 0x1830002
#define  IQM_FD_COMM_MB__W                                                 2
#define  IQM_FD_COMM_MB__M                                                 0x3
#define  IQM_FD_COMM_MB__PRE                                               0x0
#define    IQM_FD_COMM_MB_CTL__B                                           0
#define    IQM_FD_COMM_MB_CTL__W                                           1
#define    IQM_FD_COMM_MB_CTL__M                                           0x1
#define    IQM_FD_COMM_MB_CTL__PRE                                         0x0
#define      IQM_FD_COMM_MB_CTL_CTL_OFF                                    0x0
#define      IQM_FD_COMM_MB_CTL_CTL_ON                                     0x1
#define    IQM_FD_COMM_MB_OBS__B                                           1
#define    IQM_FD_COMM_MB_OBS__W                                           1
#define    IQM_FD_COMM_MB_OBS__M                                           0x2
#define    IQM_FD_COMM_MB_OBS__PRE                                         0x0
#define      IQM_FD_COMM_MB_OBS_OBS_OFF                                    0x0
#define      IQM_FD_COMM_MB_OBS_OBS_ON                                     0x2

#define  IQM_FD_RATESEL__A                                                 0x1830010
#define  IQM_FD_RATESEL__W                                                 2
#define  IQM_FD_RATESEL__M                                                 0x3
#define  IQM_FD_RATESEL__PRE                                               0x0
#define    IQM_FD_RATESEL_B__B                                             0
#define    IQM_FD_RATESEL_B__W                                             2
#define    IQM_FD_RATESEL_B__M                                             0x3
#define    IQM_FD_RATESEL_B__PRE                                           0x0
#define      IQM_FD_RATESEL_B_DS0                                          0x0
#define      IQM_FD_RATESEL_B_DS1                                          0x1
#define      IQM_FD_RATESEL_B_DS2                                          0x2
#define      IQM_FD_RATESEL_B_DS3                                          0x3



#define  IQM_RC_COMM_EXEC__A                                               0x1840000
#define  IQM_RC_COMM_EXEC__W                                               2
#define  IQM_RC_COMM_EXEC__M                                               0x3
#define  IQM_RC_COMM_EXEC__PRE                                             0x0
#define    IQM_RC_COMM_EXEC_STOP                                           0x0
#define    IQM_RC_COMM_EXEC_ACTIVE                                         0x1
#define    IQM_RC_COMM_EXEC_HOLD                                           0x2

#define  IQM_RC_COMM_MB__A                                                 0x1840002
#define  IQM_RC_COMM_MB__W                                                 2
#define  IQM_RC_COMM_MB__M                                                 0x3
#define  IQM_RC_COMM_MB__PRE                                               0x0
#define    IQM_RC_COMM_MB_CTL__B                                           0
#define    IQM_RC_COMM_MB_CTL__W                                           1
#define    IQM_RC_COMM_MB_CTL__M                                           0x1
#define    IQM_RC_COMM_MB_CTL__PRE                                         0x0
#define      IQM_RC_COMM_MB_CTL_CTL_OFF                                    0x0
#define      IQM_RC_COMM_MB_CTL_CTL_ON                                     0x1
#define    IQM_RC_COMM_MB_OBS__B                                           1
#define    IQM_RC_COMM_MB_OBS__W                                           1
#define    IQM_RC_COMM_MB_OBS__M                                           0x2
#define    IQM_RC_COMM_MB_OBS__PRE                                         0x0
#define      IQM_RC_COMM_MB_OBS_OBS_OFF                                    0x0
#define      IQM_RC_COMM_MB_OBS_OBS_ON                                     0x2

#define  IQM_RC_RATE_OFS_LO__A                                             0x1840010
#define  IQM_RC_RATE_OFS_LO__W                                             16
#define  IQM_RC_RATE_OFS_LO__M                                             0xFFFF
#define  IQM_RC_RATE_OFS_LO__PRE                                           0x0
#define    IQM_RC_RATE_OFS_LO_B__B                                         0
#define    IQM_RC_RATE_OFS_LO_B__W                                         16
#define    IQM_RC_RATE_OFS_LO_B__M                                         0xFFFF
#define    IQM_RC_RATE_OFS_LO_B__PRE                                       0x0

#define  IQM_RC_RATE_OFS_HI__A                                             0x1840011
#define  IQM_RC_RATE_OFS_HI__W                                             8
#define  IQM_RC_RATE_OFS_HI__M                                             0xFF
#define  IQM_RC_RATE_OFS_HI__PRE                                           0x0
#define    IQM_RC_RATE_OFS_HI_B__B                                         0
#define    IQM_RC_RATE_OFS_HI_B__W                                         8
#define    IQM_RC_RATE_OFS_HI_B__M                                         0xFF
#define    IQM_RC_RATE_OFS_HI_B__PRE                                       0x0

#define  IQM_RC_RATE_LO__A                                                 0x1840012
#define  IQM_RC_RATE_LO__W                                                 16
#define  IQM_RC_RATE_LO__M                                                 0xFFFF
#define  IQM_RC_RATE_LO__PRE                                               0x0
#define    IQM_RC_RATE_LO_B__B                                             0
#define    IQM_RC_RATE_LO_B__W                                             16
#define    IQM_RC_RATE_LO_B__M                                             0xFFFF
#define    IQM_RC_RATE_LO_B__PRE                                           0x0

#define  IQM_RC_RATE_HI__A                                                 0x1840013
#define  IQM_RC_RATE_HI__W                                                 8
#define  IQM_RC_RATE_HI__M                                                 0xFF
#define  IQM_RC_RATE_HI__PRE                                               0x0
#define    IQM_RC_RATE_HI_B__B                                             0
#define    IQM_RC_RATE_HI_B__W                                             8
#define    IQM_RC_RATE_HI_B__M                                             0xFF
#define    IQM_RC_RATE_HI_B__PRE                                           0x0

#define  IQM_RC_ADJ_SEL__A                                                 0x1840014
#define  IQM_RC_ADJ_SEL__W                                                 2
#define  IQM_RC_ADJ_SEL__M                                                 0x3
#define  IQM_RC_ADJ_SEL__PRE                                               0x0

#define    IQM_RC_ADJ_SEL_B__B                                             0
#define    IQM_RC_ADJ_SEL_B__W                                             2
#define    IQM_RC_ADJ_SEL_B__M                                             0x3
#define    IQM_RC_ADJ_SEL_B__PRE                                           0x0
#define      IQM_RC_ADJ_SEL_B_OFF                                          0x0
#define      IQM_RC_ADJ_SEL_B_QAM                                          0x1
#define      IQM_RC_ADJ_SEL_B_VSB                                          0x2

#define  IQM_RC_CROUT_ENA__A                                               0x1840015
#define  IQM_RC_CROUT_ENA__W                                               1
#define  IQM_RC_CROUT_ENA__M                                               0x1
#define  IQM_RC_CROUT_ENA__PRE                                             0x0

#define    IQM_RC_CROUT_ENA_ENA__B                                         0
#define    IQM_RC_CROUT_ENA_ENA__W                                         1
#define    IQM_RC_CROUT_ENA_ENA__M                                         0x1
#define    IQM_RC_CROUT_ENA_ENA__PRE                                       0x0

#define  IQM_RC_STRETCH__A                                                 0x1840016
#define  IQM_RC_STRETCH__W                                                 5
#define  IQM_RC_STRETCH__M                                                 0x1F
#define  IQM_RC_STRETCH__PRE                                               0x0

#define    IQM_RC_STRETCH_B__B                                             0
#define    IQM_RC_STRETCH_B__W                                             5
#define    IQM_RC_STRETCH_B__M                                             0x1F
#define    IQM_RC_STRETCH_B__PRE                                           0x0



#define  IQM_RT_COMM_EXEC__A                                               0x1850000
#define  IQM_RT_COMM_EXEC__W                                               2
#define  IQM_RT_COMM_EXEC__M                                               0x3
#define  IQM_RT_COMM_EXEC__PRE                                             0x0
#define    IQM_RT_COMM_EXEC_STOP                                           0x0
#define    IQM_RT_COMM_EXEC_ACTIVE                                         0x1
#define    IQM_RT_COMM_EXEC_HOLD                                           0x2

#define  IQM_RT_COMM_MB__A                                                 0x1850002
#define  IQM_RT_COMM_MB__W                                                 2
#define  IQM_RT_COMM_MB__M                                                 0x3
#define  IQM_RT_COMM_MB__PRE                                               0x0
#define    IQM_RT_COMM_MB_CTL__B                                           0
#define    IQM_RT_COMM_MB_CTL__W                                           1
#define    IQM_RT_COMM_MB_CTL__M                                           0x1
#define    IQM_RT_COMM_MB_CTL__PRE                                         0x0
#define      IQM_RT_COMM_MB_CTL_CTL_OFF                                    0x0
#define      IQM_RT_COMM_MB_CTL_CTL_ON                                     0x1
#define    IQM_RT_COMM_MB_OBS__B                                           1
#define    IQM_RT_COMM_MB_OBS__W                                           1
#define    IQM_RT_COMM_MB_OBS__M                                           0x2
#define    IQM_RT_COMM_MB_OBS__PRE                                         0x0
#define      IQM_RT_COMM_MB_OBS_OBS_OFF                                    0x0
#define      IQM_RT_COMM_MB_OBS_OBS_ON                                     0x2

#define  IQM_RT_ACTIVE__A                                                  0x1850010
#define  IQM_RT_ACTIVE__W                                                  2
#define  IQM_RT_ACTIVE__M                                                  0x3
#define  IQM_RT_ACTIVE__PRE                                                0x0

#define    IQM_RT_ACTIVE_ACTIVE_RT__B                                      0
#define    IQM_RT_ACTIVE_ACTIVE_RT__W                                      1
#define    IQM_RT_ACTIVE_ACTIVE_RT__M                                      0x1
#define    IQM_RT_ACTIVE_ACTIVE_RT__PRE                                    0x0
#define      IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF                           0x0
#define      IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON                            0x1

#define    IQM_RT_ACTIVE_ACTIVE_CR__B                                      1
#define    IQM_RT_ACTIVE_ACTIVE_CR__W                                      1
#define    IQM_RT_ACTIVE_ACTIVE_CR__M                                      0x2
#define    IQM_RT_ACTIVE_ACTIVE_CR__PRE                                    0x0
#define      IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF                            0x0
#define      IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON                             0x2


#define  IQM_RT_LO_INCR__A                                                 0x1850011
#define  IQM_RT_LO_INCR__W                                                 12
#define  IQM_RT_LO_INCR__M                                                 0xFFF
#define  IQM_RT_LO_INCR__PRE                                               0x588
#define    IQM_RT_LO_INCR_FM                                               0x0
#define    IQM_RT_LO_INCR_MN                                               0x588

#define  IQM_RT_ROT_BP__A                                                  0x1850012
#define  IQM_RT_ROT_BP__W                                                  3
#define  IQM_RT_ROT_BP__M                                                  0x7
#define  IQM_RT_ROT_BP__PRE                                                0x0

#define    IQM_RT_ROT_BP_ROT_OFF__B                                        0
#define    IQM_RT_ROT_BP_ROT_OFF__W                                        1
#define    IQM_RT_ROT_BP_ROT_OFF__M                                        0x1
#define    IQM_RT_ROT_BP_ROT_OFF__PRE                                      0x0
#define      IQM_RT_ROT_BP_ROT_OFF_ACTIVE                                  0x0
#define      IQM_RT_ROT_BP_ROT_OFF_OFF                                     0x1

#define    IQM_RT_ROT_BP_ROT_BPF__B                                        1
#define    IQM_RT_ROT_BP_ROT_BPF__W                                        1
#define    IQM_RT_ROT_BP_ROT_BPF__M                                        0x2
#define    IQM_RT_ROT_BP_ROT_BPF__PRE                                      0x0

#define    IQM_RT_ROT_BP_MIX_BP__B                                         2
#define    IQM_RT_ROT_BP_MIX_BP__W                                         1
#define    IQM_RT_ROT_BP_MIX_BP__M                                         0x4
#define    IQM_RT_ROT_BP_MIX_BP__PRE                                       0x0


#define  IQM_RT_LP_BP__A                                                   0x1850013
#define  IQM_RT_LP_BP__W                                                   1
#define  IQM_RT_LP_BP__M                                                   0x1
#define  IQM_RT_LP_BP__PRE                                                 0x0

#define  IQM_RT_DELAY__A                                                   0x1850014
#define  IQM_RT_DELAY__W                                                   7
#define  IQM_RT_DELAY__M                                                   0x7F
#define  IQM_RT_DELAY__PRE                                                 0x45



#define  IQM_CF_COMM_EXEC__A                                               0x1860000
#define  IQM_CF_COMM_EXEC__W                                               2
#define  IQM_CF_COMM_EXEC__M                                               0x3
#define  IQM_CF_COMM_EXEC__PRE                                             0x0
#define    IQM_CF_COMM_EXEC_STOP                                           0x0
#define    IQM_CF_COMM_EXEC_ACTIVE                                         0x1
#define    IQM_CF_COMM_EXEC_HOLD                                           0x2

#define  IQM_CF_COMM_MB__A                                                 0x1860002
#define  IQM_CF_COMM_MB__W                                                 2
#define  IQM_CF_COMM_MB__M                                                 0x3
#define  IQM_CF_COMM_MB__PRE                                               0x0
#define    IQM_CF_COMM_MB_CTL__B                                           0
#define    IQM_CF_COMM_MB_CTL__W                                           1
#define    IQM_CF_COMM_MB_CTL__M                                           0x1
#define    IQM_CF_COMM_MB_CTL__PRE                                         0x0
#define      IQM_CF_COMM_MB_CTL_CTL_OFF                                    0x0
#define      IQM_CF_COMM_MB_CTL_CTL_ON                                     0x1
#define    IQM_CF_COMM_MB_OBS__B                                           1
#define    IQM_CF_COMM_MB_OBS__W                                           1
#define    IQM_CF_COMM_MB_OBS__M                                           0x2
#define    IQM_CF_COMM_MB_OBS__PRE                                         0x0
#define      IQM_CF_COMM_MB_OBS_OBS_OFF                                    0x0
#define      IQM_CF_COMM_MB_OBS_OBS_ON                                     0x2

#define  IQM_CF_COMM_INT_REQ__A                                            0x1860003
#define  IQM_CF_COMM_INT_REQ__W                                            1
#define  IQM_CF_COMM_INT_REQ__M                                            0x1
#define  IQM_CF_COMM_INT_REQ__PRE                                          0x0
#define  IQM_CF_COMM_INT_STA__A                                            0x1860005
#define  IQM_CF_COMM_INT_STA__W                                            2
#define  IQM_CF_COMM_INT_STA__M                                            0x3
#define  IQM_CF_COMM_INT_STA__PRE                                          0x0
#define    IQM_CF_COMM_INT_STA_PM__B                                       0
#define    IQM_CF_COMM_INT_STA_PM__W                                       1
#define    IQM_CF_COMM_INT_STA_PM__M                                       0x1
#define    IQM_CF_COMM_INT_STA_PM__PRE                                     0x0
#define    IQM_CF_COMM_INT_STA_INC__B                                      1
#define    IQM_CF_COMM_INT_STA_INC__W                                      1
#define    IQM_CF_COMM_INT_STA_INC__M                                      0x2
#define    IQM_CF_COMM_INT_STA_INC__PRE                                    0x0

#define  IQM_CF_COMM_INT_MSK__A                                            0x1860006
#define  IQM_CF_COMM_INT_MSK__W                                            2
#define  IQM_CF_COMM_INT_MSK__M                                            0x3
#define  IQM_CF_COMM_INT_MSK__PRE                                          0x0
#define    IQM_CF_COMM_INT_MSK_PM__B                                       0
#define    IQM_CF_COMM_INT_MSK_PM__W                                       1
#define    IQM_CF_COMM_INT_MSK_PM__M                                       0x1
#define    IQM_CF_COMM_INT_MSK_PM__PRE                                     0x0
#define    IQM_CF_COMM_INT_MSK_INC__B                                      1
#define    IQM_CF_COMM_INT_MSK_INC__W                                      1
#define    IQM_CF_COMM_INT_MSK_INC__M                                      0x2
#define    IQM_CF_COMM_INT_MSK_INC__PRE                                    0x0

#define  IQM_CF_COMM_INT_STM__A                                            0x1860007
#define  IQM_CF_COMM_INT_STM__W                                            2
#define  IQM_CF_COMM_INT_STM__M                                            0x3
#define  IQM_CF_COMM_INT_STM__PRE                                          0x0
#define    IQM_CF_COMM_INT_STM_PM__B                                       0
#define    IQM_CF_COMM_INT_STM_PM__W                                       1
#define    IQM_CF_COMM_INT_STM_PM__M                                       0x1
#define    IQM_CF_COMM_INT_STM_PM__PRE                                     0x0
#define    IQM_CF_COMM_INT_STM_INC__B                                      1
#define    IQM_CF_COMM_INT_STM_INC__W                                      1
#define    IQM_CF_COMM_INT_STM_INC__M                                      0x2
#define    IQM_CF_COMM_INT_STM_INC__PRE                                    0x0

#define  IQM_CF_SYMMETRIC__A                                               0x1860010
#define  IQM_CF_SYMMETRIC__W                                               2
#define  IQM_CF_SYMMETRIC__M                                               0x3
#define  IQM_CF_SYMMETRIC__PRE                                             0x0

#define    IQM_CF_SYMMETRIC_RE__B                                          0
#define    IQM_CF_SYMMETRIC_RE__W                                          1
#define    IQM_CF_SYMMETRIC_RE__M                                          0x1
#define    IQM_CF_SYMMETRIC_RE__PRE                                        0x0

#define    IQM_CF_SYMMETRIC_IM__B                                          1
#define    IQM_CF_SYMMETRIC_IM__W                                          1
#define    IQM_CF_SYMMETRIC_IM__M                                          0x2
#define    IQM_CF_SYMMETRIC_IM__PRE                                        0x0

#define  IQM_CF_MIDTAP__A                                                  0x1860011
#define  IQM_CF_MIDTAP__W                                                  3
#define  IQM_CF_MIDTAP__M                                                  0x7
#define  IQM_CF_MIDTAP__PRE                                                0x3

#define    IQM_CF_MIDTAP_RE__B                                             0
#define    IQM_CF_MIDTAP_RE__W                                             1
#define    IQM_CF_MIDTAP_RE__M                                             0x1
#define    IQM_CF_MIDTAP_RE__PRE                                           0x1

#define    IQM_CF_MIDTAP_IM__B                                             1
#define    IQM_CF_MIDTAP_IM__W                                             1
#define    IQM_CF_MIDTAP_IM__M                                             0x2
#define    IQM_CF_MIDTAP_IM__PRE                                           0x2

#define    IQM_CF_MIDTAP_SCALE__B                                          2
#define    IQM_CF_MIDTAP_SCALE__W                                          1
#define    IQM_CF_MIDTAP_SCALE__M                                          0x4
#define    IQM_CF_MIDTAP_SCALE__PRE                                        0x0

#define  IQM_CF_OUT_ENA__A                                                 0x1860012
#define  IQM_CF_OUT_ENA__W                                                 3
#define  IQM_CF_OUT_ENA__M                                                 0x7
#define  IQM_CF_OUT_ENA__PRE                                               0x0

#define    IQM_CF_OUT_ENA_ATV__B                                           0
#define    IQM_CF_OUT_ENA_ATV__W                                           1
#define    IQM_CF_OUT_ENA_ATV__M                                           0x1
#define    IQM_CF_OUT_ENA_ATV__PRE                                         0x0

#define    IQM_CF_OUT_ENA_QAM__B                                           1
#define    IQM_CF_OUT_ENA_QAM__W                                           1
#define    IQM_CF_OUT_ENA_QAM__M                                           0x2
#define    IQM_CF_OUT_ENA_QAM__PRE                                         0x0

#define    IQM_CF_OUT_ENA_OFDM__B                                          2
#define    IQM_CF_OUT_ENA_OFDM__W                                          1
#define    IQM_CF_OUT_ENA_OFDM__M                                          0x4
#define    IQM_CF_OUT_ENA_OFDM__PRE                                        0x0

#define  IQM_CF_ADJ_SEL__A                                                 0x1860013
#define  IQM_CF_ADJ_SEL__W                                                 2
#define  IQM_CF_ADJ_SEL__M                                                 0x3
#define  IQM_CF_ADJ_SEL__PRE                                               0x0

#define    IQM_CF_ADJ_SEL_B__B                                             0
#define    IQM_CF_ADJ_SEL_B__W                                             2
#define    IQM_CF_ADJ_SEL_B__M                                             0x3
#define    IQM_CF_ADJ_SEL_B__PRE                                           0x0

#define  IQM_CF_SCALE__A                                                   0x1860014
#define  IQM_CF_SCALE__W                                                   14
#define  IQM_CF_SCALE__M                                                   0x3FFF
#define  IQM_CF_SCALE__PRE                                                 0x400
#define    IQM_CF_SCALE_B__B                                               0
#define    IQM_CF_SCALE_B__W                                               14
#define    IQM_CF_SCALE_B__M                                               0x3FFF
#define    IQM_CF_SCALE_B__PRE                                             0x400

#define  IQM_CF_SCALE_SH__A                                                0x1860015
#define  IQM_CF_SCALE_SH__W                                                2
#define  IQM_CF_SCALE_SH__M                                                0x3
#define  IQM_CF_SCALE_SH__PRE                                              0x0

#define    IQM_CF_SCALE_SH_B__B                                            0
#define    IQM_CF_SCALE_SH_B__W                                            2
#define    IQM_CF_SCALE_SH_B__M                                            0x3
#define    IQM_CF_SCALE_SH_B__PRE                                          0x0

#define  IQM_CF_AMP__A                                                     0x1860016
#define  IQM_CF_AMP__W                                                     14
#define  IQM_CF_AMP__M                                                     0x3FFF
#define  IQM_CF_AMP__PRE                                                   0x0

#define    IQM_CF_AMP_B__B                                                 0
#define    IQM_CF_AMP_B__W                                                 14
#define    IQM_CF_AMP_B__M                                                 0x3FFF
#define    IQM_CF_AMP_B__PRE                                               0x0

#define  IQM_CF_POW_MEAS_LEN__A                                            0x1860017
#define  IQM_CF_POW_MEAS_LEN__W                                            3
#define  IQM_CF_POW_MEAS_LEN__M                                            0x7
#define  IQM_CF_POW_MEAS_LEN__PRE                                          0x2

#define    IQM_CF_POW_MEAS_LEN_B__B                                        0
#define    IQM_CF_POW_MEAS_LEN_B__W                                        3
#define    IQM_CF_POW_MEAS_LEN_B__M                                        0x7
#define    IQM_CF_POW_MEAS_LEN_B__PRE                                      0x2

#define  IQM_CF_POW__A                                                     0x1860018
#define  IQM_CF_POW__W                                                     16
#define  IQM_CF_POW__M                                                     0xFFFF
#define  IQM_CF_POW__PRE                                                   0x2
#define    IQM_CF_POW_B__B                                                 0
#define    IQM_CF_POW_B__W                                                 16
#define    IQM_CF_POW_B__M                                                 0xFFFF
#define    IQM_CF_POW_B__PRE                                               0x2

#define  IQM_CF_DS_ENA__A                                                  0x1860019
#define  IQM_CF_DS_ENA__W                                                  3
#define  IQM_CF_DS_ENA__M                                                  0x7
#define  IQM_CF_DS_ENA__PRE                                                0x4

#define    IQM_CF_DS_ENA_ATV__B                                            0
#define    IQM_CF_DS_ENA_ATV__W                                            1
#define    IQM_CF_DS_ENA_ATV__M                                            0x1
#define    IQM_CF_DS_ENA_ATV__PRE                                          0x0

#define    IQM_CF_DS_ENA_QAM__B                                            1
#define    IQM_CF_DS_ENA_QAM__W                                            1
#define    IQM_CF_DS_ENA_QAM__M                                            0x2
#define    IQM_CF_DS_ENA_QAM__PRE                                          0x0

#define    IQM_CF_DS_ENA_VSB__B                                            2
#define    IQM_CF_DS_ENA_VSB__W                                            1
#define    IQM_CF_DS_ENA_VSB__M                                            0x4
#define    IQM_CF_DS_ENA_VSB__PRE                                          0x4


#define  IQM_CF_POW_UPD__A                                                 0x186001A
#define  IQM_CF_POW_UPD__W                                                 1
#define  IQM_CF_POW_UPD__M                                                 0x1
#define  IQM_CF_POW_UPD__PRE                                               0x0
#define  IQM_CF_TAP_RE0__A                                                 0x1860020
#define  IQM_CF_TAP_RE0__W                                                 7
#define  IQM_CF_TAP_RE0__M                                                 0x7F
#define  IQM_CF_TAP_RE0__PRE                                               0x2
#define    IQM_CF_TAP_RE0_B__B                                             0
#define    IQM_CF_TAP_RE0_B__W                                             7
#define    IQM_CF_TAP_RE0_B__M                                             0x7F
#define    IQM_CF_TAP_RE0_B__PRE                                           0x2

#define  IQM_CF_TAP_RE1__A                                                 0x1860021
#define  IQM_CF_TAP_RE1__W                                                 7
#define  IQM_CF_TAP_RE1__M                                                 0x7F
#define  IQM_CF_TAP_RE1__PRE                                               0x2
#define    IQM_CF_TAP_RE1_B__B                                             0
#define    IQM_CF_TAP_RE1_B__W                                             7
#define    IQM_CF_TAP_RE1_B__M                                             0x7F
#define    IQM_CF_TAP_RE1_B__PRE                                           0x2

#define  IQM_CF_TAP_RE2__A                                                 0x1860022
#define  IQM_CF_TAP_RE2__W                                                 7
#define  IQM_CF_TAP_RE2__M                                                 0x7F
#define  IQM_CF_TAP_RE2__PRE                                               0x2
#define    IQM_CF_TAP_RE2_B__B                                             0
#define    IQM_CF_TAP_RE2_B__W                                             7
#define    IQM_CF_TAP_RE2_B__M                                             0x7F
#define    IQM_CF_TAP_RE2_B__PRE                                           0x2

#define  IQM_CF_TAP_RE3__A                                                 0x1860023
#define  IQM_CF_TAP_RE3__W                                                 7
#define  IQM_CF_TAP_RE3__M                                                 0x7F
#define  IQM_CF_TAP_RE3__PRE                                               0x2
#define    IQM_CF_TAP_RE3_B__B                                             0
#define    IQM_CF_TAP_RE3_B__W                                             7
#define    IQM_CF_TAP_RE3_B__M                                             0x7F
#define    IQM_CF_TAP_RE3_B__PRE                                           0x2

#define  IQM_CF_TAP_RE4__A                                                 0x1860024
#define  IQM_CF_TAP_RE4__W                                                 7
#define  IQM_CF_TAP_RE4__M                                                 0x7F
#define  IQM_CF_TAP_RE4__PRE                                               0x2
#define    IQM_CF_TAP_RE4_B__B                                             0
#define    IQM_CF_TAP_RE4_B__W                                             7
#define    IQM_CF_TAP_RE4_B__M                                             0x7F
#define    IQM_CF_TAP_RE4_B__PRE                                           0x2

#define  IQM_CF_TAP_RE5__A                                                 0x1860025
#define  IQM_CF_TAP_RE5__W                                                 7
#define  IQM_CF_TAP_RE5__M                                                 0x7F
#define  IQM_CF_TAP_RE5__PRE                                               0x2
#define    IQM_CF_TAP_RE5_B__B                                             0
#define    IQM_CF_TAP_RE5_B__W                                             7
#define    IQM_CF_TAP_RE5_B__M                                             0x7F
#define    IQM_CF_TAP_RE5_B__PRE                                           0x2

#define  IQM_CF_TAP_RE6__A                                                 0x1860026
#define  IQM_CF_TAP_RE6__W                                                 7
#define  IQM_CF_TAP_RE6__M                                                 0x7F
#define  IQM_CF_TAP_RE6__PRE                                               0x2
#define    IQM_CF_TAP_RE6_B__B                                             0
#define    IQM_CF_TAP_RE6_B__W                                             7
#define    IQM_CF_TAP_RE6_B__M                                             0x7F
#define    IQM_CF_TAP_RE6_B__PRE                                           0x2

#define  IQM_CF_TAP_RE7__A                                                 0x1860027
#define  IQM_CF_TAP_RE7__W                                                 9
#define  IQM_CF_TAP_RE7__M                                                 0x1FF
#define  IQM_CF_TAP_RE7__PRE                                               0x2
#define    IQM_CF_TAP_RE7_B__B                                             0
#define    IQM_CF_TAP_RE7_B__W                                             9
#define    IQM_CF_TAP_RE7_B__M                                             0x1FF
#define    IQM_CF_TAP_RE7_B__PRE                                           0x2

#define  IQM_CF_TAP_RE8__A                                                 0x1860028
#define  IQM_CF_TAP_RE8__W                                                 9
#define  IQM_CF_TAP_RE8__M                                                 0x1FF
#define  IQM_CF_TAP_RE8__PRE                                               0x2
#define    IQM_CF_TAP_RE8_B__B                                             0
#define    IQM_CF_TAP_RE8_B__W                                             9
#define    IQM_CF_TAP_RE8_B__M                                             0x1FF
#define    IQM_CF_TAP_RE8_B__PRE                                           0x2

#define  IQM_CF_TAP_RE9__A                                                 0x1860029
#define  IQM_CF_TAP_RE9__W                                                 9
#define  IQM_CF_TAP_RE9__M                                                 0x1FF
#define  IQM_CF_TAP_RE9__PRE                                               0x2
#define    IQM_CF_TAP_RE9_B__B                                             0
#define    IQM_CF_TAP_RE9_B__W                                             9
#define    IQM_CF_TAP_RE9_B__M                                             0x1FF
#define    IQM_CF_TAP_RE9_B__PRE                                           0x2

#define  IQM_CF_TAP_RE10__A                                                0x186002A
#define  IQM_CF_TAP_RE10__W                                                9
#define  IQM_CF_TAP_RE10__M                                                0x1FF
#define  IQM_CF_TAP_RE10__PRE                                              0x2
#define    IQM_CF_TAP_RE10_B__B                                            0
#define    IQM_CF_TAP_RE10_B__W                                            9
#define    IQM_CF_TAP_RE10_B__M                                            0x1FF
#define    IQM_CF_TAP_RE10_B__PRE                                          0x2

#define  IQM_CF_TAP_RE11__A                                                0x186002B
#define  IQM_CF_TAP_RE11__W                                                9
#define  IQM_CF_TAP_RE11__M                                                0x1FF
#define  IQM_CF_TAP_RE11__PRE                                              0x2
#define    IQM_CF_TAP_RE11_B__B                                            0
#define    IQM_CF_TAP_RE11_B__W                                            9
#define    IQM_CF_TAP_RE11_B__M                                            0x1FF
#define    IQM_CF_TAP_RE11_B__PRE                                          0x2

#define  IQM_CF_TAP_RE12__A                                                0x186002C
#define  IQM_CF_TAP_RE12__W                                                9
#define  IQM_CF_TAP_RE12__M                                                0x1FF
#define  IQM_CF_TAP_RE12__PRE                                              0x2
#define    IQM_CF_TAP_RE12_B__B                                            0
#define    IQM_CF_TAP_RE12_B__W                                            9
#define    IQM_CF_TAP_RE12_B__M                                            0x1FF
#define    IQM_CF_TAP_RE12_B__PRE                                          0x2

#define  IQM_CF_TAP_RE13__A                                                0x186002D
#define  IQM_CF_TAP_RE13__W                                                9
#define  IQM_CF_TAP_RE13__M                                                0x1FF
#define  IQM_CF_TAP_RE13__PRE                                              0x2
#define    IQM_CF_TAP_RE13_B__B                                            0
#define    IQM_CF_TAP_RE13_B__W                                            9
#define    IQM_CF_TAP_RE13_B__M                                            0x1FF
#define    IQM_CF_TAP_RE13_B__PRE                                          0x2

#define  IQM_CF_TAP_RE14__A                                                0x186002E
#define  IQM_CF_TAP_RE14__W                                                9
#define  IQM_CF_TAP_RE14__M                                                0x1FF
#define  IQM_CF_TAP_RE14__PRE                                              0x2
#define    IQM_CF_TAP_RE14_B__B                                            0
#define    IQM_CF_TAP_RE14_B__W                                            9
#define    IQM_CF_TAP_RE14_B__M                                            0x1FF
#define    IQM_CF_TAP_RE14_B__PRE                                          0x2

#define  IQM_CF_TAP_RE15__A                                                0x186002F
#define  IQM_CF_TAP_RE15__W                                                9
#define  IQM_CF_TAP_RE15__M                                                0x1FF
#define  IQM_CF_TAP_RE15__PRE                                              0x2
#define    IQM_CF_TAP_RE15_B__B                                            0
#define    IQM_CF_TAP_RE15_B__W                                            9
#define    IQM_CF_TAP_RE15_B__M                                            0x1FF
#define    IQM_CF_TAP_RE15_B__PRE                                          0x2

#define  IQM_CF_TAP_RE16__A                                                0x1860030
#define  IQM_CF_TAP_RE16__W                                                9
#define  IQM_CF_TAP_RE16__M                                                0x1FF
#define  IQM_CF_TAP_RE16__PRE                                              0x2
#define    IQM_CF_TAP_RE16_B__B                                            0
#define    IQM_CF_TAP_RE16_B__W                                            9
#define    IQM_CF_TAP_RE16_B__M                                            0x1FF
#define    IQM_CF_TAP_RE16_B__PRE                                          0x2

#define  IQM_CF_TAP_RE17__A                                                0x1860031
#define  IQM_CF_TAP_RE17__W                                                9
#define  IQM_CF_TAP_RE17__M                                                0x1FF
#define  IQM_CF_TAP_RE17__PRE                                              0x2
#define    IQM_CF_TAP_RE17_B__B                                            0
#define    IQM_CF_TAP_RE17_B__W                                            9
#define    IQM_CF_TAP_RE17_B__M                                            0x1FF
#define    IQM_CF_TAP_RE17_B__PRE                                          0x2

#define  IQM_CF_TAP_RE18__A                                                0x1860032
#define  IQM_CF_TAP_RE18__W                                                9
#define  IQM_CF_TAP_RE18__M                                                0x1FF
#define  IQM_CF_TAP_RE18__PRE                                              0x2
#define    IQM_CF_TAP_RE18_B__B                                            0
#define    IQM_CF_TAP_RE18_B__W                                            9
#define    IQM_CF_TAP_RE18_B__M                                            0x1FF
#define    IQM_CF_TAP_RE18_B__PRE                                          0x2

#define  IQM_CF_TAP_RE19__A                                                0x1860033
#define  IQM_CF_TAP_RE19__W                                                9
#define  IQM_CF_TAP_RE19__M                                                0x1FF
#define  IQM_CF_TAP_RE19__PRE                                              0x2
#define    IQM_CF_TAP_RE19_B__B                                            0
#define    IQM_CF_TAP_RE19_B__W                                            9
#define    IQM_CF_TAP_RE19_B__M                                            0x1FF
#define    IQM_CF_TAP_RE19_B__PRE                                          0x2

#define  IQM_CF_TAP_RE20__A                                                0x1860034
#define  IQM_CF_TAP_RE20__W                                                9
#define  IQM_CF_TAP_RE20__M                                                0x1FF
#define  IQM_CF_TAP_RE20__PRE                                              0x2
#define    IQM_CF_TAP_RE20_B__B                                            0
#define    IQM_CF_TAP_RE20_B__W                                            9
#define    IQM_CF_TAP_RE20_B__M                                            0x1FF
#define    IQM_CF_TAP_RE20_B__PRE                                          0x2

#define  IQM_CF_TAP_RE21__A                                                0x1860035
#define  IQM_CF_TAP_RE21__W                                                11
#define  IQM_CF_TAP_RE21__M                                                0x7FF
#define  IQM_CF_TAP_RE21__PRE                                              0x2
#define    IQM_CF_TAP_RE21_B__B                                            0
#define    IQM_CF_TAP_RE21_B__W                                            11
#define    IQM_CF_TAP_RE21_B__M                                            0x7FF
#define    IQM_CF_TAP_RE21_B__PRE                                          0x2

#define  IQM_CF_TAP_RE22__A                                                0x1860036
#define  IQM_CF_TAP_RE22__W                                                11
#define  IQM_CF_TAP_RE22__M                                                0x7FF
#define  IQM_CF_TAP_RE22__PRE                                              0x2
#define    IQM_CF_TAP_RE22_B__B                                            0
#define    IQM_CF_TAP_RE22_B__W                                            11
#define    IQM_CF_TAP_RE22_B__M                                            0x7FF
#define    IQM_CF_TAP_RE22_B__PRE                                          0x2

#define  IQM_CF_TAP_RE23__A                                                0x1860037
#define  IQM_CF_TAP_RE23__W                                                11
#define  IQM_CF_TAP_RE23__M                                                0x7FF
#define  IQM_CF_TAP_RE23__PRE                                              0x2
#define    IQM_CF_TAP_RE23_B__B                                            0
#define    IQM_CF_TAP_RE23_B__W                                            11
#define    IQM_CF_TAP_RE23_B__M                                            0x7FF
#define    IQM_CF_TAP_RE23_B__PRE                                          0x2

#define  IQM_CF_TAP_RE24__A                                                0x1860038
#define  IQM_CF_TAP_RE24__W                                                11
#define  IQM_CF_TAP_RE24__M                                                0x7FF
#define  IQM_CF_TAP_RE24__PRE                                              0x2
#define    IQM_CF_TAP_RE24_B__B                                            0
#define    IQM_CF_TAP_RE24_B__W                                            11
#define    IQM_CF_TAP_RE24_B__M                                            0x7FF
#define    IQM_CF_TAP_RE24_B__PRE                                          0x2

#define  IQM_CF_TAP_RE25__A                                                0x1860039
#define  IQM_CF_TAP_RE25__W                                                11
#define  IQM_CF_TAP_RE25__M                                                0x7FF
#define  IQM_CF_TAP_RE25__PRE                                              0x2
#define    IQM_CF_TAP_RE25_B__B                                            0
#define    IQM_CF_TAP_RE25_B__W                                            11
#define    IQM_CF_TAP_RE25_B__M                                            0x7FF
#define    IQM_CF_TAP_RE25_B__PRE                                          0x2

#define  IQM_CF_TAP_RE26__A                                                0x186003A
#define  IQM_CF_TAP_RE26__W                                                11
#define  IQM_CF_TAP_RE26__M                                                0x7FF
#define  IQM_CF_TAP_RE26__PRE                                              0x2
#define    IQM_CF_TAP_RE26_B__B                                            0
#define    IQM_CF_TAP_RE26_B__W                                            11
#define    IQM_CF_TAP_RE26_B__M                                            0x7FF
#define    IQM_CF_TAP_RE26_B__PRE                                          0x2

#define  IQM_CF_TAP_RE27__A                                                0x186003B
#define  IQM_CF_TAP_RE27__W                                                11
#define  IQM_CF_TAP_RE27__M                                                0x7FF
#define  IQM_CF_TAP_RE27__PRE                                              0x2
#define    IQM_CF_TAP_RE27_B__B                                            0
#define    IQM_CF_TAP_RE27_B__W                                            11
#define    IQM_CF_TAP_RE27_B__M                                            0x7FF
#define    IQM_CF_TAP_RE27_B__PRE                                          0x2

#define  IQM_CF_TAP_IM0__A                                                 0x1860040
#define  IQM_CF_TAP_IM0__W                                                 7
#define  IQM_CF_TAP_IM0__M                                                 0x7F
#define  IQM_CF_TAP_IM0__PRE                                               0x2
#define    IQM_CF_TAP_IM0_B__B                                             0
#define    IQM_CF_TAP_IM0_B__W                                             7
#define    IQM_CF_TAP_IM0_B__M                                             0x7F
#define    IQM_CF_TAP_IM0_B__PRE                                           0x2

#define  IQM_CF_TAP_IM1__A                                                 0x1860041
#define  IQM_CF_TAP_IM1__W                                                 7
#define  IQM_CF_TAP_IM1__M                                                 0x7F
#define  IQM_CF_TAP_IM1__PRE                                               0x2
#define    IQM_CF_TAP_IM1_B__B                                             0
#define    IQM_CF_TAP_IM1_B__W                                             7
#define    IQM_CF_TAP_IM1_B__M                                             0x7F
#define    IQM_CF_TAP_IM1_B__PRE                                           0x2

#define  IQM_CF_TAP_IM2__A                                                 0x1860042
#define  IQM_CF_TAP_IM2__W                                                 7
#define  IQM_CF_TAP_IM2__M                                                 0x7F
#define  IQM_CF_TAP_IM2__PRE                                               0x2
#define    IQM_CF_TAP_IM2_B__B                                             0
#define    IQM_CF_TAP_IM2_B__W                                             7
#define    IQM_CF_TAP_IM2_B__M                                             0x7F
#define    IQM_CF_TAP_IM2_B__PRE                                           0x2

#define  IQM_CF_TAP_IM3__A                                                 0x1860043
#define  IQM_CF_TAP_IM3__W                                                 7
#define  IQM_CF_TAP_IM3__M                                                 0x7F
#define  IQM_CF_TAP_IM3__PRE                                               0x2
#define    IQM_CF_TAP_IM3_B__B                                             0
#define    IQM_CF_TAP_IM3_B__W                                             7
#define    IQM_CF_TAP_IM3_B__M                                             0x7F
#define    IQM_CF_TAP_IM3_B__PRE                                           0x2

#define  IQM_CF_TAP_IM4__A                                                 0x1860044
#define  IQM_CF_TAP_IM4__W                                                 7
#define  IQM_CF_TAP_IM4__M                                                 0x7F
#define  IQM_CF_TAP_IM4__PRE                                               0x2
#define    IQM_CF_TAP_IM4_B__B                                             0
#define    IQM_CF_TAP_IM4_B__W                                             7
#define    IQM_CF_TAP_IM4_B__M                                             0x7F
#define    IQM_CF_TAP_IM4_B__PRE                                           0x2

#define  IQM_CF_TAP_IM5__A                                                 0x1860045
#define  IQM_CF_TAP_IM5__W                                                 7
#define  IQM_CF_TAP_IM5__M                                                 0x7F
#define  IQM_CF_TAP_IM5__PRE                                               0x2
#define    IQM_CF_TAP_IM5_B__B                                             0
#define    IQM_CF_TAP_IM5_B__W                                             7
#define    IQM_CF_TAP_IM5_B__M                                             0x7F
#define    IQM_CF_TAP_IM5_B__PRE                                           0x2

#define  IQM_CF_TAP_IM6__A                                                 0x1860046
#define  IQM_CF_TAP_IM6__W                                                 7
#define  IQM_CF_TAP_IM6__M                                                 0x7F
#define  IQM_CF_TAP_IM6__PRE                                               0x2
#define    IQM_CF_TAP_IM6_B__B                                             0
#define    IQM_CF_TAP_IM6_B__W                                             7
#define    IQM_CF_TAP_IM6_B__M                                             0x7F
#define    IQM_CF_TAP_IM6_B__PRE                                           0x2

#define  IQM_CF_TAP_IM7__A                                                 0x1860047
#define  IQM_CF_TAP_IM7__W                                                 9
#define  IQM_CF_TAP_IM7__M                                                 0x1FF
#define  IQM_CF_TAP_IM7__PRE                                               0x2
#define    IQM_CF_TAP_IM7_B__B                                             0
#define    IQM_CF_TAP_IM7_B__W                                             9
#define    IQM_CF_TAP_IM7_B__M                                             0x1FF
#define    IQM_CF_TAP_IM7_B__PRE                                           0x2

#define  IQM_CF_TAP_IM8__A                                                 0x1860048
#define  IQM_CF_TAP_IM8__W                                                 9
#define  IQM_CF_TAP_IM8__M                                                 0x1FF
#define  IQM_CF_TAP_IM8__PRE                                               0x2
#define    IQM_CF_TAP_IM8_B__B                                             0
#define    IQM_CF_TAP_IM8_B__W                                             9
#define    IQM_CF_TAP_IM8_B__M                                             0x1FF
#define    IQM_CF_TAP_IM8_B__PRE                                           0x2

#define  IQM_CF_TAP_IM9__A                                                 0x1860049
#define  IQM_CF_TAP_IM9__W                                                 9
#define  IQM_CF_TAP_IM9__M                                                 0x1FF
#define  IQM_CF_TAP_IM9__PRE                                               0x2
#define    IQM_CF_TAP_IM9_B__B                                             0
#define    IQM_CF_TAP_IM9_B__W                                             9
#define    IQM_CF_TAP_IM9_B__M                                             0x1FF
#define    IQM_CF_TAP_IM9_B__PRE                                           0x2

#define  IQM_CF_TAP_IM10__A                                                0x186004A
#define  IQM_CF_TAP_IM10__W                                                9
#define  IQM_CF_TAP_IM10__M                                                0x1FF
#define  IQM_CF_TAP_IM10__PRE                                              0x2
#define    IQM_CF_TAP_IM10_B__B                                            0
#define    IQM_CF_TAP_IM10_B__W                                            9
#define    IQM_CF_TAP_IM10_B__M                                            0x1FF
#define    IQM_CF_TAP_IM10_B__PRE                                          0x2

#define  IQM_CF_TAP_IM11__A                                                0x186004B
#define  IQM_CF_TAP_IM11__W                                                9
#define  IQM_CF_TAP_IM11__M                                                0x1FF
#define  IQM_CF_TAP_IM11__PRE                                              0x2
#define    IQM_CF_TAP_IM11_B__B                                            0
#define    IQM_CF_TAP_IM11_B__W                                            9
#define    IQM_CF_TAP_IM11_B__M                                            0x1FF
#define    IQM_CF_TAP_IM11_B__PRE                                          0x2

#define  IQM_CF_TAP_IM12__A                                                0x186004C
#define  IQM_CF_TAP_IM12__W                                                9
#define  IQM_CF_TAP_IM12__M                                                0x1FF
#define  IQM_CF_TAP_IM12__PRE                                              0x2
#define    IQM_CF_TAP_IM12_B__B                                            0
#define    IQM_CF_TAP_IM12_B__W                                            9
#define    IQM_CF_TAP_IM12_B__M                                            0x1FF
#define    IQM_CF_TAP_IM12_B__PRE                                          0x2

#define  IQM_CF_TAP_IM13__A                                                0x186004D
#define  IQM_CF_TAP_IM13__W                                                9
#define  IQM_CF_TAP_IM13__M                                                0x1FF
#define  IQM_CF_TAP_IM13__PRE                                              0x2
#define    IQM_CF_TAP_IM13_B__B                                            0
#define    IQM_CF_TAP_IM13_B__W                                            9
#define    IQM_CF_TAP_IM13_B__M                                            0x1FF
#define    IQM_CF_TAP_IM13_B__PRE                                          0x2

#define  IQM_CF_TAP_IM14__A                                                0x186004E
#define  IQM_CF_TAP_IM14__W                                                9
#define  IQM_CF_TAP_IM14__M                                                0x1FF
#define  IQM_CF_TAP_IM14__PRE                                              0x2
#define    IQM_CF_TAP_IM14_B__B                                            0
#define    IQM_CF_TAP_IM14_B__W                                            9
#define    IQM_CF_TAP_IM14_B__M                                            0x1FF
#define    IQM_CF_TAP_IM14_B__PRE                                          0x2

#define  IQM_CF_TAP_IM15__A                                                0x186004F
#define  IQM_CF_TAP_IM15__W                                                9
#define  IQM_CF_TAP_IM15__M                                                0x1FF
#define  IQM_CF_TAP_IM15__PRE                                              0x2
#define    IQM_CF_TAP_IM15_B__B                                            0
#define    IQM_CF_TAP_IM15_B__W                                            9
#define    IQM_CF_TAP_IM15_B__M                                            0x1FF
#define    IQM_CF_TAP_IM15_B__PRE                                          0x2

#define  IQM_CF_TAP_IM16__A                                                0x1860050
#define  IQM_CF_TAP_IM16__W                                                9
#define  IQM_CF_TAP_IM16__M                                                0x1FF
#define  IQM_CF_TAP_IM16__PRE                                              0x2
#define    IQM_CF_TAP_IM16_B__B                                            0
#define    IQM_CF_TAP_IM16_B__W                                            9
#define    IQM_CF_TAP_IM16_B__M                                            0x1FF
#define    IQM_CF_TAP_IM16_B__PRE                                          0x2

#define  IQM_CF_TAP_IM17__A                                                0x1860051
#define  IQM_CF_TAP_IM17__W                                                9
#define  IQM_CF_TAP_IM17__M                                                0x1FF
#define  IQM_CF_TAP_IM17__PRE                                              0x2
#define    IQM_CF_TAP_IM17_B__B                                            0
#define    IQM_CF_TAP_IM17_B__W                                            9
#define    IQM_CF_TAP_IM17_B__M                                            0x1FF
#define    IQM_CF_TAP_IM17_B__PRE                                          0x2

#define  IQM_CF_TAP_IM18__A                                                0x1860052
#define  IQM_CF_TAP_IM18__W                                                9
#define  IQM_CF_TAP_IM18__M                                                0x1FF
#define  IQM_CF_TAP_IM18__PRE                                              0x2
#define    IQM_CF_TAP_IM18_B__B                                            0
#define    IQM_CF_TAP_IM18_B__W                                            9
#define    IQM_CF_TAP_IM18_B__M                                            0x1FF
#define    IQM_CF_TAP_IM18_B__PRE                                          0x2

#define  IQM_CF_TAP_IM19__A                                                0x1860053
#define  IQM_CF_TAP_IM19__W                                                9
#define  IQM_CF_TAP_IM19__M                                                0x1FF
#define  IQM_CF_TAP_IM19__PRE                                              0x2
#define    IQM_CF_TAP_IM19_B__B                                            0
#define    IQM_CF_TAP_IM19_B__W                                            9
#define    IQM_CF_TAP_IM19_B__M                                            0x1FF
#define    IQM_CF_TAP_IM19_B__PRE                                          0x2

#define  IQM_CF_TAP_IM20__A                                                0x1860054
#define  IQM_CF_TAP_IM20__W                                                9
#define  IQM_CF_TAP_IM20__M                                                0x1FF
#define  IQM_CF_TAP_IM20__PRE                                              0x2
#define    IQM_CF_TAP_IM20_B__B                                            0
#define    IQM_CF_TAP_IM20_B__W                                            9
#define    IQM_CF_TAP_IM20_B__M                                            0x1FF
#define    IQM_CF_TAP_IM20_B__PRE                                          0x2

#define  IQM_CF_TAP_IM21__A                                                0x1860055
#define  IQM_CF_TAP_IM21__W                                                11
#define  IQM_CF_TAP_IM21__M                                                0x7FF
#define  IQM_CF_TAP_IM21__PRE                                              0x2
#define    IQM_CF_TAP_IM21_B__B                                            0
#define    IQM_CF_TAP_IM21_B__W                                            11
#define    IQM_CF_TAP_IM21_B__M                                            0x7FF
#define    IQM_CF_TAP_IM21_B__PRE                                          0x2

#define  IQM_CF_TAP_IM22__A                                                0x1860056
#define  IQM_CF_TAP_IM22__W                                                11
#define  IQM_CF_TAP_IM22__M                                                0x7FF
#define  IQM_CF_TAP_IM22__PRE                                              0x2
#define    IQM_CF_TAP_IM22_B__B                                            0
#define    IQM_CF_TAP_IM22_B__W                                            11
#define    IQM_CF_TAP_IM22_B__M                                            0x7FF
#define    IQM_CF_TAP_IM22_B__PRE                                          0x2

#define  IQM_CF_TAP_IM23__A                                                0x1860057
#define  IQM_CF_TAP_IM23__W                                                11
#define  IQM_CF_TAP_IM23__M                                                0x7FF
#define  IQM_CF_TAP_IM23__PRE                                              0x2
#define    IQM_CF_TAP_IM23_B__B                                            0
#define    IQM_CF_TAP_IM23_B__W                                            11
#define    IQM_CF_TAP_IM23_B__M                                            0x7FF
#define    IQM_CF_TAP_IM23_B__PRE                                          0x2

#define  IQM_CF_TAP_IM24__A                                                0x1860058
#define  IQM_CF_TAP_IM24__W                                                11
#define  IQM_CF_TAP_IM24__M                                                0x7FF
#define  IQM_CF_TAP_IM24__PRE                                              0x2
#define    IQM_CF_TAP_IM24_B__B                                            0
#define    IQM_CF_TAP_IM24_B__W                                            11
#define    IQM_CF_TAP_IM24_B__M                                            0x7FF
#define    IQM_CF_TAP_IM24_B__PRE                                          0x2

#define  IQM_CF_TAP_IM25__A                                                0x1860059
#define  IQM_CF_TAP_IM25__W                                                11
#define  IQM_CF_TAP_IM25__M                                                0x7FF
#define  IQM_CF_TAP_IM25__PRE                                              0x2
#define    IQM_CF_TAP_IM25_B__B                                            0
#define    IQM_CF_TAP_IM25_B__W                                            11
#define    IQM_CF_TAP_IM25_B__M                                            0x7FF
#define    IQM_CF_TAP_IM25_B__PRE                                          0x2

#define  IQM_CF_TAP_IM26__A                                                0x186005A
#define  IQM_CF_TAP_IM26__W                                                11
#define  IQM_CF_TAP_IM26__M                                                0x7FF
#define  IQM_CF_TAP_IM26__PRE                                              0x2
#define    IQM_CF_TAP_IM26_B__B                                            0
#define    IQM_CF_TAP_IM26_B__W                                            11
#define    IQM_CF_TAP_IM26_B__M                                            0x7FF
#define    IQM_CF_TAP_IM26_B__PRE                                          0x2

#define  IQM_CF_TAP_IM27__A                                                0x186005B
#define  IQM_CF_TAP_IM27__W                                                11
#define  IQM_CF_TAP_IM27__M                                                0x7FF
#define  IQM_CF_TAP_IM27__PRE                                              0x2
#define    IQM_CF_TAP_IM27_B__B                                            0
#define    IQM_CF_TAP_IM27_B__W                                            11
#define    IQM_CF_TAP_IM27_B__M                                            0x7FF
#define    IQM_CF_TAP_IM27_B__PRE                                          0x2


#define  IQM_CF_CLP_VAL__A                                                 0x1860060
#define  IQM_CF_CLP_VAL__W                                                 9
#define  IQM_CF_CLP_VAL__M                                                 0x1FF
#define  IQM_CF_CLP_VAL__PRE                                               0x3C

#define  IQM_CF_DATATH__A                                                  0x1860061
#define  IQM_CF_DATATH__W                                                  10
#define  IQM_CF_DATATH__M                                                  0x3FF
#define  IQM_CF_DATATH__PRE                                                0x180

#define  IQM_CF_PKDTH__A                                                   0x1860062
#define  IQM_CF_PKDTH__W                                                   5
#define  IQM_CF_PKDTH__M                                                   0x1F
#define  IQM_CF_PKDTH__PRE                                                 0x1

#define  IQM_CF_WND_LEN__A                                                 0x1860063
#define  IQM_CF_WND_LEN__W                                                 4
#define  IQM_CF_WND_LEN__M                                                 0xF
#define  IQM_CF_WND_LEN__PRE                                               0x1

#define  IQM_CF_DET_LCT__A                                                 0x1860064
#define  IQM_CF_DET_LCT__W                                                 1
#define  IQM_CF_DET_LCT__M                                                 0x1
#define  IQM_CF_DET_LCT__PRE                                               0x1

#define  IQM_CF_SNS_LEN__A                                                 0x1860065
#define  IQM_CF_SNS_LEN__W                                                 16
#define  IQM_CF_SNS_LEN__M                                                 0xFFFF
#define  IQM_CF_SNS_LEN__PRE                                               0x0

#define  IQM_CF_SNS_SENSE__A                                               0x1860066
#define  IQM_CF_SNS_SENSE__W                                               16
#define  IQM_CF_SNS_SENSE__M                                               0xFFFF
#define  IQM_CF_SNS_SENSE__PRE                                             0x0

#define  IQM_CF_BYPASSDET__A                                               0x1860067
#define  IQM_CF_BYPASSDET__W                                               1
#define  IQM_CF_BYPASSDET__M                                               0x1
#define  IQM_CF_BYPASSDET__PRE                                             0x0

#define  IQM_CF_UPD_ENA__A                                                 0x1860068
#define  IQM_CF_UPD_ENA__W                                                 1
#define  IQM_CF_UPD_ENA__M                                                 0x1
#define  IQM_CF_UPD_ENA__PRE                                               0x0
#define    IQM_CF_UPD_ENA_DISABLE                                          0x0
#define    IQM_CF_UPD_ENA_ENABLE                                           0x1



#define  IQM_AF_COMM_EXEC__A                                               0x1870000
#define  IQM_AF_COMM_EXEC__W                                               2
#define  IQM_AF_COMM_EXEC__M                                               0x3
#define  IQM_AF_COMM_EXEC__PRE                                             0x0
#define    IQM_AF_COMM_EXEC_STOP                                           0x0
#define    IQM_AF_COMM_EXEC_ACTIVE                                         0x1
#define    IQM_AF_COMM_EXEC_HOLD                                           0x2

#define  IQM_AF_COMM_MB__A                                                 0x1870002
#define  IQM_AF_COMM_MB__W                                                 8
#define  IQM_AF_COMM_MB__M                                                 0xFF
#define  IQM_AF_COMM_MB__PRE                                               0x0
#define    IQM_AF_COMM_MB_CTL__B                                           0
#define    IQM_AF_COMM_MB_CTL__W                                           1
#define    IQM_AF_COMM_MB_CTL__M                                           0x1
#define    IQM_AF_COMM_MB_CTL__PRE                                         0x0
#define      IQM_AF_COMM_MB_CTL_CTL_OFF                                    0x0
#define      IQM_AF_COMM_MB_CTL_CTL_ON                                     0x1
#define    IQM_AF_COMM_MB_OBS__B                                           1
#define    IQM_AF_COMM_MB_OBS__W                                           1
#define    IQM_AF_COMM_MB_OBS__M                                           0x2
#define    IQM_AF_COMM_MB_OBS__PRE                                         0x0
#define      IQM_AF_COMM_MB_OBS_OBS_OFF                                    0x0
#define      IQM_AF_COMM_MB_OBS_OBS_ON                                     0x2
#define    IQM_AF_COMM_MB_MUX_CTRL__B                                      2
#define    IQM_AF_COMM_MB_MUX_CTRL__W                                      3
#define    IQM_AF_COMM_MB_MUX_CTRL__M                                      0x1C
#define    IQM_AF_COMM_MB_MUX_CTRL__PRE                                    0x0
#define      IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT                         0x0
#define      IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT                           0x4
#define      IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT                        0x8
#define      IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT                         0xC
#define      IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT                         0x10
#define      IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN                            0x14
#define    IQM_AF_COMM_MB_MUX_OBS__B                                       5
#define    IQM_AF_COMM_MB_MUX_OBS__W                                       3
#define    IQM_AF_COMM_MB_MUX_OBS__M                                       0xE0
#define    IQM_AF_COMM_MB_MUX_OBS__PRE                                     0x0
#define      IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT                          0x0
#define      IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT                            0x20
#define      IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT                         0x40
#define      IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT                          0x60
#define      IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT                          0x80
#define      IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN                             0xA0

#define  IQM_AF_COMM_INT_REQ__A                                            0x1870003
#define  IQM_AF_COMM_INT_REQ__W                                            1
#define  IQM_AF_COMM_INT_REQ__M                                            0x1
#define  IQM_AF_COMM_INT_REQ__PRE                                          0x0
#define  IQM_AF_COMM_INT_STA__A                                            0x1870005
#define  IQM_AF_COMM_INT_STA__W                                            3
#define  IQM_AF_COMM_INT_STA__M                                            0x7
#define  IQM_AF_COMM_INT_STA__PRE                                          0x0
#define    IQM_AF_COMM_INT_STA_CLP_INT_STA__B                              0
#define    IQM_AF_COMM_INT_STA_CLP_INT_STA__W                              1
#define    IQM_AF_COMM_INT_STA_CLP_INT_STA__M                              0x1
#define    IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE                            0x0
#define    IQM_AF_COMM_INT_STA_SNS_INT_STA__B                              1
#define    IQM_AF_COMM_INT_STA_SNS_INT_STA__W                              1
#define    IQM_AF_COMM_INT_STA_SNS_INT_STA__M                              0x2
#define    IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE                            0x0
#define    IQM_AF_COMM_INT_STA_ISNS_INT_STA__B                             2
#define    IQM_AF_COMM_INT_STA_ISNS_INT_STA__W                             1
#define    IQM_AF_COMM_INT_STA_ISNS_INT_STA__M                             0x4
#define    IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE                           0x0

#define  IQM_AF_COMM_INT_MSK__A                                            0x1870006
#define  IQM_AF_COMM_INT_MSK__W                                            3
#define  IQM_AF_COMM_INT_MSK__M                                            0x7
#define  IQM_AF_COMM_INT_MSK__PRE                                          0x0
#define    IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B                              0
#define    IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W                              1
#define    IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M                              0x1
#define    IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE                            0x0
#define    IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B                              1
#define    IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W                              1
#define    IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M                              0x2
#define    IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE                            0x0
#define    IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B                             2
#define    IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W                             1
#define    IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M                             0x4
#define    IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE                           0x0

#define  IQM_AF_COMM_INT_STM__A                                            0x1870007
#define  IQM_AF_COMM_INT_STM__W                                            3
#define  IQM_AF_COMM_INT_STM__M                                            0x7
#define  IQM_AF_COMM_INT_STM__PRE                                          0x0
#define    IQM_AF_COMM_INT_STM_CLP_INT_STA__B                              0
#define    IQM_AF_COMM_INT_STM_CLP_INT_STA__W                              1
#define    IQM_AF_COMM_INT_STM_CLP_INT_STA__M                              0x1
#define    IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE                            0x0
#define    IQM_AF_COMM_INT_STM_SNS_INT_STA__B                              1
#define    IQM_AF_COMM_INT_STM_SNS_INT_STA__W                              1
#define    IQM_AF_COMM_INT_STM_SNS_INT_STA__M                              0x2
#define    IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE                            0x0
#define    IQM_AF_COMM_INT_STM_ISNS_INT_STA__B                             2
#define    IQM_AF_COMM_INT_STM_ISNS_INT_STA__W                             1
#define    IQM_AF_COMM_INT_STM_ISNS_INT_STA__M                             0x4
#define    IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE                           0x0


#define  IQM_AF_FDB_SEL__A                                                 0x1870010
#define  IQM_AF_FDB_SEL__W                                                 2
#define  IQM_AF_FDB_SEL__M                                                 0x3
#define  IQM_AF_FDB_SEL__PRE                                               0x0
#define  IQM_AF_CLKNEG__A                                                  0x1870012
#define  IQM_AF_CLKNEG__W                                                  2
#define  IQM_AF_CLKNEG__M                                                  0x3
#define  IQM_AF_CLKNEG__PRE                                                0x0

#define    IQM_AF_CLKNEG_CLKNEGPEAK__B                                     0
#define    IQM_AF_CLKNEG_CLKNEGPEAK__W                                     1
#define    IQM_AF_CLKNEG_CLKNEGPEAK__M                                     0x1
#define    IQM_AF_CLKNEG_CLKNEGPEAK__PRE                                   0x0
#define      IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS                     0x0
#define      IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG                     0x1

#define    IQM_AF_CLKNEG_CLKNEGDATA__B                                     1
#define    IQM_AF_CLKNEG_CLKNEGDATA__W                                     1
#define    IQM_AF_CLKNEG_CLKNEGDATA__M                                     0x2
#define    IQM_AF_CLKNEG_CLKNEGDATA__PRE                                   0x0
#define      IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS                     0x0
#define      IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG                     0x2


#define  IQM_AF_MON_IN_MUX__A                                              0x1870013
#define  IQM_AF_MON_IN_MUX__W                                              2
#define  IQM_AF_MON_IN_MUX__M                                              0x3
#define  IQM_AF_MON_IN_MUX__PRE                                            0x0

#define  IQM_AF_MON_IN5__A                                                 0x1870014
#define  IQM_AF_MON_IN5__W                                                 10
#define  IQM_AF_MON_IN5__M                                                 0x3FF
#define  IQM_AF_MON_IN5__PRE                                               0x0

#define  IQM_AF_MON_IN4__A                                                 0x1870015
#define  IQM_AF_MON_IN4__W                                                 10
#define  IQM_AF_MON_IN4__M                                                 0x3FF
#define  IQM_AF_MON_IN4__PRE                                               0x0

#define  IQM_AF_MON_IN3__A                                                 0x1870016
#define  IQM_AF_MON_IN3__W                                                 10
#define  IQM_AF_MON_IN3__M                                                 0x3FF
#define  IQM_AF_MON_IN3__PRE                                               0x0

#define  IQM_AF_MON_IN2__A                                                 0x1870017
#define  IQM_AF_MON_IN2__W                                                 10
#define  IQM_AF_MON_IN2__M                                                 0x3FF
#define  IQM_AF_MON_IN2__PRE                                               0x0

#define  IQM_AF_MON_IN1__A                                                 0x1870018
#define  IQM_AF_MON_IN1__W                                                 10
#define  IQM_AF_MON_IN1__M                                                 0x3FF
#define  IQM_AF_MON_IN1__PRE                                               0x0

#define  IQM_AF_MON_IN0__A                                                 0x1870019
#define  IQM_AF_MON_IN0__W                                                 10
#define  IQM_AF_MON_IN0__M                                                 0x3FF
#define  IQM_AF_MON_IN0__PRE                                               0x0

#define  IQM_AF_MON_IN_VAL__A                                              0x187001A
#define  IQM_AF_MON_IN_VAL__W                                              1
#define  IQM_AF_MON_IN_VAL__M                                              0x1
#define  IQM_AF_MON_IN_VAL__PRE                                            0x0

#define  IQM_AF_START_LOCK__A                                              0x187001B
#define  IQM_AF_START_LOCK__W                                              1
#define  IQM_AF_START_LOCK__M                                              0x1
#define  IQM_AF_START_LOCK__PRE                                            0x0

#define  IQM_AF_PHASE0__A                                                  0x187001C
#define  IQM_AF_PHASE0__W                                                  7
#define  IQM_AF_PHASE0__M                                                  0x7F
#define  IQM_AF_PHASE0__PRE                                                0x0

#define  IQM_AF_PHASE1__A                                                  0x187001D
#define  IQM_AF_PHASE1__W                                                  7
#define  IQM_AF_PHASE1__M                                                  0x7F
#define  IQM_AF_PHASE1__PRE                                                0x0

#define  IQM_AF_PHASE2__A                                                  0x187001E
#define  IQM_AF_PHASE2__W                                                  7
#define  IQM_AF_PHASE2__M                                                  0x7F
#define  IQM_AF_PHASE2__PRE                                                0x0

#define  IQM_AF_SCU_PHASE__A                                               0x187001F
#define  IQM_AF_SCU_PHASE__W                                               2
#define  IQM_AF_SCU_PHASE__M                                               0x3
#define  IQM_AF_SCU_PHASE__PRE                                             0x0

#define  IQM_AF_SYNC_SEL__A                                                0x1870020
#define  IQM_AF_SYNC_SEL__W                                                2
#define  IQM_AF_SYNC_SEL__M                                                0x3
#define  IQM_AF_SYNC_SEL__PRE                                              0x0
#define  IQM_AF_ADC_CONF__A                                                0x1870021
#define  IQM_AF_ADC_CONF__W                                                4
#define  IQM_AF_ADC_CONF__M                                                0xF
#define  IQM_AF_ADC_CONF__PRE                                              0x0

#define    IQM_AF_ADC_CONF_ADC_SIGN__B                                     0
#define    IQM_AF_ADC_CONF_ADC_SIGN__W                                     1
#define    IQM_AF_ADC_CONF_ADC_SIGN__M                                     0x1
#define    IQM_AF_ADC_CONF_ADC_SIGN__PRE                                   0x0
#define      IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED                           0x0
#define      IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED                         0x1

#define    IQM_AF_ADC_CONF_BITREVERSE_ADC__B                               1
#define    IQM_AF_ADC_CONF_BITREVERSE_ADC__W                               1
#define    IQM_AF_ADC_CONF_BITREVERSE_ADC__M                               0x2
#define    IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE                             0x0
#define      IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL                     0x0
#define      IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED                0x2

#define    IQM_AF_ADC_CONF_BITREVERSE_NSSI__B                              2
#define    IQM_AF_ADC_CONF_BITREVERSE_NSSI__W                              1
#define    IQM_AF_ADC_CONF_BITREVERSE_NSSI__M                              0x4
#define    IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE                            0x0
#define      IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL              0x0
#define      IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED         0x4

#define    IQM_AF_ADC_CONF_BITREVERSE_NSSR__B                              3
#define    IQM_AF_ADC_CONF_BITREVERSE_NSSR__W                              1
#define    IQM_AF_ADC_CONF_BITREVERSE_NSSR__M                              0x8
#define    IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE                            0x0
#define      IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL              0x0
#define      IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED         0x8


#define  IQM_AF_CLP_CLIP__A                                                0x1870022
#define  IQM_AF_CLP_CLIP__W                                                16
#define  IQM_AF_CLP_CLIP__M                                                0xFFFF
#define  IQM_AF_CLP_CLIP__PRE                                              0x0

#define  IQM_AF_CLP_LEN__A                                                 0x1870023
#define  IQM_AF_CLP_LEN__W                                                 16
#define  IQM_AF_CLP_LEN__M                                                 0xFFFF
#define  IQM_AF_CLP_LEN__PRE                                               0x0

#define  IQM_AF_CLP_TH__A                                                  0x1870024
#define  IQM_AF_CLP_TH__W                                                  9
#define  IQM_AF_CLP_TH__M                                                  0x1FF
#define  IQM_AF_CLP_TH__PRE                                                0x0

#define  IQM_AF_DCF_BYPASS__A                                              0x1870025
#define  IQM_AF_DCF_BYPASS__W                                              1
#define  IQM_AF_DCF_BYPASS__M                                              0x1
#define  IQM_AF_DCF_BYPASS__PRE                                            0x0
#define    IQM_AF_DCF_BYPASS_ACTIVE                                        0x0
#define    IQM_AF_DCF_BYPASS_BYPASS                                        0x1


#define  IQM_AF_SNS_LEN__A                                                 0x1870026
#define  IQM_AF_SNS_LEN__W                                                 16
#define  IQM_AF_SNS_LEN__M                                                 0xFFFF
#define  IQM_AF_SNS_LEN__PRE                                               0x0

#define  IQM_AF_SNS_SENSE__A                                               0x1870027
#define  IQM_AF_SNS_SENSE__W                                               16
#define  IQM_AF_SNS_SENSE__M                                               0xFFFF
#define  IQM_AF_SNS_SENSE__PRE                                             0x0

#define  IQM_AF_AGC_IF__A                                                  0x1870028
#define  IQM_AF_AGC_IF__W                                                  15
#define  IQM_AF_AGC_IF__M                                                  0x7FFF
#define  IQM_AF_AGC_IF__PRE                                                0x0

#define  IQM_AF_AGC_RF__A                                                  0x1870029
#define  IQM_AF_AGC_RF__W                                                  15
#define  IQM_AF_AGC_RF__M                                                  0x7FFF
#define  IQM_AF_AGC_RF__PRE                                                0x0

#define  IQM_AF_PDREF__A                                                   0x187002B
#define  IQM_AF_PDREF__W                                                   5
#define  IQM_AF_PDREF__M                                                   0x1F
#define  IQM_AF_PDREF__PRE                                                 0x0
#define  IQM_AF_STDBY__A                                                   0x187002C
#define  IQM_AF_STDBY__W                                                   6
#define  IQM_AF_STDBY__M                                                   0x3F
#define  IQM_AF_STDBY__PRE                                                 0x3E

#define    IQM_AF_STDBY_STDBY_BIAS__B                                      0
#define    IQM_AF_STDBY_STDBY_BIAS__W                                      1
#define    IQM_AF_STDBY_STDBY_BIAS__M                                      0x1
#define    IQM_AF_STDBY_STDBY_BIAS__PRE                                    0x0
#define      IQM_AF_STDBY_STDBY_BIAS_ACTIVE                                0x0
#define      IQM_AF_STDBY_STDBY_BIAS_STANDBY                               0x1

#define    IQM_AF_STDBY_STDBY_ADC__B                                       1
#define    IQM_AF_STDBY_STDBY_ADC__W                                       1
#define    IQM_AF_STDBY_STDBY_ADC__M                                       0x2
#define    IQM_AF_STDBY_STDBY_ADC__PRE                                     0x2
#define      IQM_AF_STDBY_STDBY_ADC_ACTIVE                                 0x0
#define      IQM_AF_STDBY_STDBY_ADC_STANDBY                                0x2

#define    IQM_AF_STDBY_STDBY_AMP__B                                       2
#define    IQM_AF_STDBY_STDBY_AMP__W                                       1
#define    IQM_AF_STDBY_STDBY_AMP__M                                       0x4
#define    IQM_AF_STDBY_STDBY_AMP__PRE                                     0x4
#define      IQM_AF_STDBY_STDBY_AMP_ACTIVE                                 0x0
#define      IQM_AF_STDBY_STDBY_AMP_STANDBY                                0x4

#define    IQM_AF_STDBY_STDBY_PD__B                                        3
#define    IQM_AF_STDBY_STDBY_PD__W                                        1
#define    IQM_AF_STDBY_STDBY_PD__M                                        0x8
#define    IQM_AF_STDBY_STDBY_PD__PRE                                      0x8
#define      IQM_AF_STDBY_STDBY_PD_ACTIVE                                  0x0
#define      IQM_AF_STDBY_STDBY_PD_STANDBY                                 0x8

#define    IQM_AF_STDBY_STDBY_TAGC_IF__B                                   4
#define    IQM_AF_STDBY_STDBY_TAGC_IF__W                                   1
#define    IQM_AF_STDBY_STDBY_TAGC_IF__M                                   0x10
#define    IQM_AF_STDBY_STDBY_TAGC_IF__PRE                                 0x10
#define      IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE                             0x0
#define      IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY                            0x10

#define    IQM_AF_STDBY_STDBY_TAGC_RF__B                                   5
#define    IQM_AF_STDBY_STDBY_TAGC_RF__W                                   1
#define    IQM_AF_STDBY_STDBY_TAGC_RF__M                                   0x20
#define    IQM_AF_STDBY_STDBY_TAGC_RF__PRE                                 0x20
#define      IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE                             0x0
#define      IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY                            0x20


#define  IQM_AF_AMUX__A                                                    0x187002D
#define  IQM_AF_AMUX__W                                                    1
#define  IQM_AF_AMUX__M                                                    0x1
#define  IQM_AF_AMUX__PRE                                                  0x0
#define    IQM_AF_AMUX_SIGNAL2LOWPASS                                      0x0
#define    IQM_AF_AMUX_SIGNAL2ADC                                          0x1


#define  IQM_AF_TST_AFEMAIN__A                                             0x187002E
#define  IQM_AF_TST_AFEMAIN__W                                             8
#define  IQM_AF_TST_AFEMAIN__M                                             0xFF
#define  IQM_AF_TST_AFEMAIN__PRE                                           0x0

#define  IQM_AF_UPD_SEL__A                                                 0x187002F
#define  IQM_AF_UPD_SEL__W                                                 1
#define  IQM_AF_UPD_SEL__M                                                 0x1
#define  IQM_AF_UPD_SEL__PRE                                               0x0

#define  IQM_AF_INC_DATATH__A                                              0x1870030
#define  IQM_AF_INC_DATATH__W                                              9
#define  IQM_AF_INC_DATATH__M                                              0x1FF
#define  IQM_AF_INC_DATATH__PRE                                            0x180

#define  IQM_AF_INC_PKDTH__A                                               0x1870031
#define  IQM_AF_INC_PKDTH__W                                               5
#define  IQM_AF_INC_PKDTH__M                                               0x1F
#define  IQM_AF_INC_PKDTH__PRE                                             0x3

#define  IQM_AF_INC_WND_LEN__A                                             0x1870032
#define  IQM_AF_INC_WND_LEN__W                                             4
#define  IQM_AF_INC_WND_LEN__M                                             0xF
#define  IQM_AF_INC_WND_LEN__PRE                                           0xA

#define  IQM_AF_INC_DLY__A                                                 0x1870033
#define  IQM_AF_INC_DLY__W                                                 7
#define  IQM_AF_INC_DLY__M                                                 0x7F
#define  IQM_AF_INC_DLY__PRE                                               0x14

#define  IQM_AF_INC_LCT__A                                                 0x1870034
#define  IQM_AF_INC_LCT__W                                                 1
#define  IQM_AF_INC_LCT__M                                                 0x1
#define  IQM_AF_INC_LCT__PRE                                               0x1

#define  IQM_AF_INC_CLP_VAL__A                                             0x1870035
#define  IQM_AF_INC_CLP_VAL__W                                             9
#define  IQM_AF_INC_CLP_VAL__M                                             0x1FF
#define  IQM_AF_INC_CLP_VAL__PRE                                           0x3C

#define  IQM_AF_INC_BYPASS__A                                              0x1870036
#define  IQM_AF_INC_BYPASS__W                                              1
#define  IQM_AF_INC_BYPASS__M                                              0x1
#define  IQM_AF_INC_BYPASS__PRE                                            0x1

#define  IQM_AF_INC_MODE_SEL__A                                            0x1870037
#define  IQM_AF_INC_MODE_SEL__W                                            2
#define  IQM_AF_INC_MODE_SEL__M                                            0x3
#define  IQM_AF_INC_MODE_SEL__PRE                                          0x1

#define  IQM_AF_INC_A_DLY__A                                               0x1870038
#define  IQM_AF_INC_A_DLY__W                                               6
#define  IQM_AF_INC_A_DLY__M                                               0x3F
#define  IQM_AF_INC_A_DLY__PRE                                             0xF

#define  IQM_AF_ISNS_LEN__A                                                0x1870039
#define  IQM_AF_ISNS_LEN__W                                                16
#define  IQM_AF_ISNS_LEN__M                                                0xFFFF
#define  IQM_AF_ISNS_LEN__PRE                                              0x0

#define  IQM_AF_ISNS_SENSE__A                                              0x187003A
#define  IQM_AF_ISNS_SENSE__W                                              16
#define  IQM_AF_ISNS_SENSE__M                                              0xFFFF
#define  IQM_AF_ISNS_SENSE__PRE                                            0x0
#define  IQM_AF_CMP_STATE__A                                               0x187003B
#define  IQM_AF_CMP_STATE__W                                               7
#define  IQM_AF_CMP_STATE__M                                               0x7F
#define  IQM_AF_CMP_STATE__PRE                                             0x0

#define    IQM_AF_CMP_STATE_STATE__B                                       0
#define    IQM_AF_CMP_STATE_STATE__W                                       2
#define    IQM_AF_CMP_STATE_STATE__M                                       0x3
#define    IQM_AF_CMP_STATE_STATE__PRE                                     0x0

#define    IQM_AF_CMP_STATE_ENABLE_CORING__B                               2
#define    IQM_AF_CMP_STATE_ENABLE_CORING__W                               1
#define    IQM_AF_CMP_STATE_ENABLE_CORING__M                               0x4
#define    IQM_AF_CMP_STATE_ENABLE_CORING__PRE                             0x0

#define    IQM_AF_CMP_STATE_FILTERGAIN__B                                  3
#define    IQM_AF_CMP_STATE_FILTERGAIN__W                                  2
#define    IQM_AF_CMP_STATE_FILTERGAIN__M                                  0x18
#define    IQM_AF_CMP_STATE_FILTERGAIN__PRE                                0x0
#define      IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128                      0x0
#define      IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64                       0x8
#define      IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32                       0x10
#define      IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16                       0x18

#define    IQM_AF_CMP_STATE_KEEPCOEFF__B                                   5
#define    IQM_AF_CMP_STATE_KEEPCOEFF__W                                   1
#define    IQM_AF_CMP_STATE_KEEPCOEFF__M                                   0x20
#define    IQM_AF_CMP_STATE_KEEPCOEFF__PRE                                 0x0

#define    IQM_AF_CMP_STATE_SEG64__B                                       6
#define    IQM_AF_CMP_STATE_SEG64__W                                       1
#define    IQM_AF_CMP_STATE_SEG64__M                                       0x40
#define    IQM_AF_CMP_STATE_SEG64__PRE                                     0x0
#define      IQM_AF_CMP_STATE_SEG64_SEG32                                  0x0
#define      IQM_AF_CMP_STATE_SEG64_SEG64                                  0x40


#define  IQM_AF_CMP_DC_OUT__A                                              0x187003C
#define  IQM_AF_CMP_DC_OUT__W                                              12
#define  IQM_AF_CMP_DC_OUT__M                                              0xFFF
#define  IQM_AF_CMP_DC_OUT__PRE                                            0x0
#define  IQM_AF_CMP_DC_IN__A                                               0x187003D
#define  IQM_AF_CMP_DC_IN__W                                               13
#define  IQM_AF_CMP_DC_IN__M                                               0x1FFF
#define  IQM_AF_CMP_DC_IN__PRE                                             0x0

#define    IQM_AF_CMP_DC_IN_DC__B                                          0
#define    IQM_AF_CMP_DC_IN_DC__W                                          12
#define    IQM_AF_CMP_DC_IN_DC__M                                          0xFFF
#define    IQM_AF_CMP_DC_IN_DC__PRE                                        0x0
#define    IQM_AF_CMP_DC_IN_DC_EN__B                                       12
#define    IQM_AF_CMP_DC_IN_DC_EN__W                                       1
#define    IQM_AF_CMP_DC_IN_DC_EN__M                                       0x1000
#define    IQM_AF_CMP_DC_IN_DC_EN__PRE                                     0x0
#define      IQM_AF_CMP_DC_IN_DC_EN_DISABLE                                0x0
#define      IQM_AF_CMP_DC_IN_DC_EN_ENABLE                                 0x1000


#define  IQM_AF_CMP_AMP__A                                                 0x187003E
#define  IQM_AF_CMP_AMP__W                                                 10
#define  IQM_AF_CMP_AMP__M                                                 0x3FF
#define  IQM_AF_CMP_AMP__PRE                                               0x0
#define  IQM_AF_CMP_DN_AVG__A                                              0x187003F
#define  IQM_AF_CMP_DN_AVG__W                                              8
#define  IQM_AF_CMP_DN_AVG__M                                              0xFF
#define  IQM_AF_CMP_DN_AVG__PRE                                            0x0

#define    IQM_AF_CMP_DN_AVG_DN_AVG__B                                     0
#define    IQM_AF_CMP_DN_AVG_DN_AVG__W                                     8
#define    IQM_AF_CMP_DN_AVG_DN_AVG__M                                     0xFF
#define    IQM_AF_CMP_DN_AVG_DN_AVG__PRE                                   0x0


#define  IQM_AF_CMP_ACTIVE__A                                              0x1870040
#define  IQM_AF_CMP_ACTIVE__W                                              1
#define  IQM_AF_CMP_ACTIVE__M                                              0x1
#define  IQM_AF_CMP_ACTIVE__PRE                                            0x0
#define  IQM_AF_CMP_MEM0__A                                                0x1870080
#define  IQM_AF_CMP_MEM0__W                                                13
#define  IQM_AF_CMP_MEM0__M                                                0x1FFF
#define  IQM_AF_CMP_MEM0__PRE                                              0x0

#define    IQM_AF_CMP_MEM0_COEF__B                                         0
#define    IQM_AF_CMP_MEM0_COEF__W                                         13
#define    IQM_AF_CMP_MEM0_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM0_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM1__A                                                0x1870081
#define  IQM_AF_CMP_MEM1__W                                                13
#define  IQM_AF_CMP_MEM1__M                                                0x1FFF
#define  IQM_AF_CMP_MEM1__PRE                                              0x0

#define    IQM_AF_CMP_MEM1_COEF__B                                         0
#define    IQM_AF_CMP_MEM1_COEF__W                                         13
#define    IQM_AF_CMP_MEM1_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM1_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM2__A                                                0x1870082
#define  IQM_AF_CMP_MEM2__W                                                13
#define  IQM_AF_CMP_MEM2__M                                                0x1FFF
#define  IQM_AF_CMP_MEM2__PRE                                              0x0

#define    IQM_AF_CMP_MEM2_COEF__B                                         0
#define    IQM_AF_CMP_MEM2_COEF__W                                         13
#define    IQM_AF_CMP_MEM2_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM2_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM3__A                                                0x1870083
#define  IQM_AF_CMP_MEM3__W                                                13
#define  IQM_AF_CMP_MEM3__M                                                0x1FFF
#define  IQM_AF_CMP_MEM3__PRE                                              0x0

#define    IQM_AF_CMP_MEM3_COEF__B                                         0
#define    IQM_AF_CMP_MEM3_COEF__W                                         13
#define    IQM_AF_CMP_MEM3_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM3_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM4__A                                                0x1870084
#define  IQM_AF_CMP_MEM4__W                                                13
#define  IQM_AF_CMP_MEM4__M                                                0x1FFF
#define  IQM_AF_CMP_MEM4__PRE                                              0x0

#define    IQM_AF_CMP_MEM4_COEF__B                                         0
#define    IQM_AF_CMP_MEM4_COEF__W                                         13
#define    IQM_AF_CMP_MEM4_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM4_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM5__A                                                0x1870085
#define  IQM_AF_CMP_MEM5__W                                                13
#define  IQM_AF_CMP_MEM5__M                                                0x1FFF
#define  IQM_AF_CMP_MEM5__PRE                                              0x0

#define    IQM_AF_CMP_MEM5_COEF__B                                         0
#define    IQM_AF_CMP_MEM5_COEF__W                                         13
#define    IQM_AF_CMP_MEM5_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM5_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM6__A                                                0x1870086
#define  IQM_AF_CMP_MEM6__W                                                13
#define  IQM_AF_CMP_MEM6__M                                                0x1FFF
#define  IQM_AF_CMP_MEM6__PRE                                              0x0

#define    IQM_AF_CMP_MEM6_COEF__B                                         0
#define    IQM_AF_CMP_MEM6_COEF__W                                         13
#define    IQM_AF_CMP_MEM6_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM6_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM7__A                                                0x1870087
#define  IQM_AF_CMP_MEM7__W                                                13
#define  IQM_AF_CMP_MEM7__M                                                0x1FFF
#define  IQM_AF_CMP_MEM7__PRE                                              0x0

#define    IQM_AF_CMP_MEM7_COEF__B                                         0
#define    IQM_AF_CMP_MEM7_COEF__W                                         13
#define    IQM_AF_CMP_MEM7_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM7_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM8__A                                                0x1870088
#define  IQM_AF_CMP_MEM8__W                                                13
#define  IQM_AF_CMP_MEM8__M                                                0x1FFF
#define  IQM_AF_CMP_MEM8__PRE                                              0x0

#define    IQM_AF_CMP_MEM8_COEF__B                                         0
#define    IQM_AF_CMP_MEM8_COEF__W                                         13
#define    IQM_AF_CMP_MEM8_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM8_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM9__A                                                0x1870089
#define  IQM_AF_CMP_MEM9__W                                                13
#define  IQM_AF_CMP_MEM9__M                                                0x1FFF
#define  IQM_AF_CMP_MEM9__PRE                                              0x0

#define    IQM_AF_CMP_MEM9_COEF__B                                         0
#define    IQM_AF_CMP_MEM9_COEF__W                                         13
#define    IQM_AF_CMP_MEM9_COEF__M                                         0x1FFF
#define    IQM_AF_CMP_MEM9_COEF__PRE                                       0x0

#define  IQM_AF_CMP_MEM10__A                                               0x187008A
#define  IQM_AF_CMP_MEM10__W                                               13
#define  IQM_AF_CMP_MEM10__M                                               0x1FFF
#define  IQM_AF_CMP_MEM10__PRE                                             0x0

#define    IQM_AF_CMP_MEM10_COEF__B                                        0
#define    IQM_AF_CMP_MEM10_COEF__W                                        13
#define    IQM_AF_CMP_MEM10_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM10_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM11__A                                               0x187008B
#define  IQM_AF_CMP_MEM11__W                                               13
#define  IQM_AF_CMP_MEM11__M                                               0x1FFF
#define  IQM_AF_CMP_MEM11__PRE                                             0x0

#define    IQM_AF_CMP_MEM11_COEF__B                                        0
#define    IQM_AF_CMP_MEM11_COEF__W                                        13
#define    IQM_AF_CMP_MEM11_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM11_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM12__A                                               0x187008C
#define  IQM_AF_CMP_MEM12__W                                               13
#define  IQM_AF_CMP_MEM12__M                                               0x1FFF
#define  IQM_AF_CMP_MEM12__PRE                                             0x0

#define    IQM_AF_CMP_MEM12_COEF__B                                        0
#define    IQM_AF_CMP_MEM12_COEF__W                                        13
#define    IQM_AF_CMP_MEM12_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM12_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM13__A                                               0x187008D
#define  IQM_AF_CMP_MEM13__W                                               13
#define  IQM_AF_CMP_MEM13__M                                               0x1FFF
#define  IQM_AF_CMP_MEM13__PRE                                             0x0

#define    IQM_AF_CMP_MEM13_COEF__B                                        0
#define    IQM_AF_CMP_MEM13_COEF__W                                        13
#define    IQM_AF_CMP_MEM13_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM13_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM14__A                                               0x187008E
#define  IQM_AF_CMP_MEM14__W                                               13
#define  IQM_AF_CMP_MEM14__M                                               0x1FFF
#define  IQM_AF_CMP_MEM14__PRE                                             0x0

#define    IQM_AF_CMP_MEM14_COEF__B                                        0
#define    IQM_AF_CMP_MEM14_COEF__W                                        13
#define    IQM_AF_CMP_MEM14_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM14_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM15__A                                               0x187008F
#define  IQM_AF_CMP_MEM15__W                                               13
#define  IQM_AF_CMP_MEM15__M                                               0x1FFF
#define  IQM_AF_CMP_MEM15__PRE                                             0x0

#define    IQM_AF_CMP_MEM15_COEF__B                                        0
#define    IQM_AF_CMP_MEM15_COEF__W                                        13
#define    IQM_AF_CMP_MEM15_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM15_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM16__A                                               0x1870090
#define  IQM_AF_CMP_MEM16__W                                               13
#define  IQM_AF_CMP_MEM16__M                                               0x1FFF
#define  IQM_AF_CMP_MEM16__PRE                                             0x0

#define    IQM_AF_CMP_MEM16_COEF__B                                        0
#define    IQM_AF_CMP_MEM16_COEF__W                                        13
#define    IQM_AF_CMP_MEM16_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM16_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM17__A                                               0x1870091
#define  IQM_AF_CMP_MEM17__W                                               13
#define  IQM_AF_CMP_MEM17__M                                               0x1FFF
#define  IQM_AF_CMP_MEM17__PRE                                             0x0

#define    IQM_AF_CMP_MEM17_COEF__B                                        0
#define    IQM_AF_CMP_MEM17_COEF__W                                        13
#define    IQM_AF_CMP_MEM17_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM17_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM18__A                                               0x1870092
#define  IQM_AF_CMP_MEM18__W                                               13
#define  IQM_AF_CMP_MEM18__M                                               0x1FFF
#define  IQM_AF_CMP_MEM18__PRE                                             0x0

#define    IQM_AF_CMP_MEM18_COEF__B                                        0
#define    IQM_AF_CMP_MEM18_COEF__W                                        13
#define    IQM_AF_CMP_MEM18_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM18_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM19__A                                               0x1870093
#define  IQM_AF_CMP_MEM19__W                                               13
#define  IQM_AF_CMP_MEM19__M                                               0x1FFF
#define  IQM_AF_CMP_MEM19__PRE                                             0x0

#define    IQM_AF_CMP_MEM19_COEF__B                                        0
#define    IQM_AF_CMP_MEM19_COEF__W                                        13
#define    IQM_AF_CMP_MEM19_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM19_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM20__A                                               0x1870094
#define  IQM_AF_CMP_MEM20__W                                               13
#define  IQM_AF_CMP_MEM20__M                                               0x1FFF
#define  IQM_AF_CMP_MEM20__PRE                                             0x0

#define    IQM_AF_CMP_MEM20_COEF__B                                        0
#define    IQM_AF_CMP_MEM20_COEF__W                                        13
#define    IQM_AF_CMP_MEM20_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM20_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM21__A                                               0x1870095
#define  IQM_AF_CMP_MEM21__W                                               13
#define  IQM_AF_CMP_MEM21__M                                               0x1FFF
#define  IQM_AF_CMP_MEM21__PRE                                             0x0

#define    IQM_AF_CMP_MEM21_COEF__B                                        0
#define    IQM_AF_CMP_MEM21_COEF__W                                        13
#define    IQM_AF_CMP_MEM21_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM21_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM22__A                                               0x1870096
#define  IQM_AF_CMP_MEM22__W                                               13
#define  IQM_AF_CMP_MEM22__M                                               0x1FFF
#define  IQM_AF_CMP_MEM22__PRE                                             0x0

#define    IQM_AF_CMP_MEM22_COEF__B                                        0
#define    IQM_AF_CMP_MEM22_COEF__W                                        13
#define    IQM_AF_CMP_MEM22_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM22_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM23__A                                               0x1870097
#define  IQM_AF_CMP_MEM23__W                                               13
#define  IQM_AF_CMP_MEM23__M                                               0x1FFF
#define  IQM_AF_CMP_MEM23__PRE                                             0x0

#define    IQM_AF_CMP_MEM23_COEF__B                                        0
#define    IQM_AF_CMP_MEM23_COEF__W                                        13
#define    IQM_AF_CMP_MEM23_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM23_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM24__A                                               0x1870098
#define  IQM_AF_CMP_MEM24__W                                               13
#define  IQM_AF_CMP_MEM24__M                                               0x1FFF
#define  IQM_AF_CMP_MEM24__PRE                                             0x0

#define    IQM_AF_CMP_MEM24_COEF__B                                        0
#define    IQM_AF_CMP_MEM24_COEF__W                                        13
#define    IQM_AF_CMP_MEM24_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM24_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM25__A                                               0x1870099
#define  IQM_AF_CMP_MEM25__W                                               13
#define  IQM_AF_CMP_MEM25__M                                               0x1FFF
#define  IQM_AF_CMP_MEM25__PRE                                             0x0

#define    IQM_AF_CMP_MEM25_COEF__B                                        0
#define    IQM_AF_CMP_MEM25_COEF__W                                        13
#define    IQM_AF_CMP_MEM25_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM25_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM26__A                                               0x187009A
#define  IQM_AF_CMP_MEM26__W                                               13
#define  IQM_AF_CMP_MEM26__M                                               0x1FFF
#define  IQM_AF_CMP_MEM26__PRE                                             0x0

#define    IQM_AF_CMP_MEM26_COEF__B                                        0
#define    IQM_AF_CMP_MEM26_COEF__W                                        13
#define    IQM_AF_CMP_MEM26_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM26_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM27__A                                               0x187009B
#define  IQM_AF_CMP_MEM27__W                                               13
#define  IQM_AF_CMP_MEM27__M                                               0x1FFF
#define  IQM_AF_CMP_MEM27__PRE                                             0x0

#define    IQM_AF_CMP_MEM27_COEF__B                                        0
#define    IQM_AF_CMP_MEM27_COEF__W                                        13
#define    IQM_AF_CMP_MEM27_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM27_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM28__A                                               0x187009C
#define  IQM_AF_CMP_MEM28__W                                               13
#define  IQM_AF_CMP_MEM28__M                                               0x1FFF
#define  IQM_AF_CMP_MEM28__PRE                                             0x0

#define    IQM_AF_CMP_MEM28_COEF__B                                        0
#define    IQM_AF_CMP_MEM28_COEF__W                                        13
#define    IQM_AF_CMP_MEM28_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM28_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM29__A                                               0x187009D
#define  IQM_AF_CMP_MEM29__W                                               13
#define  IQM_AF_CMP_MEM29__M                                               0x1FFF
#define  IQM_AF_CMP_MEM29__PRE                                             0x0

#define    IQM_AF_CMP_MEM29_COEF__B                                        0
#define    IQM_AF_CMP_MEM29_COEF__W                                        13
#define    IQM_AF_CMP_MEM29_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM29_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM30__A                                               0x187009E
#define  IQM_AF_CMP_MEM30__W                                               13
#define  IQM_AF_CMP_MEM30__M                                               0x1FFF
#define  IQM_AF_CMP_MEM30__PRE                                             0x0

#define    IQM_AF_CMP_MEM30_COEF__B                                        0
#define    IQM_AF_CMP_MEM30_COEF__W                                        13
#define    IQM_AF_CMP_MEM30_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM30_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM31__A                                               0x187009F
#define  IQM_AF_CMP_MEM31__W                                               13
#define  IQM_AF_CMP_MEM31__M                                               0x1FFF
#define  IQM_AF_CMP_MEM31__PRE                                             0x0

#define    IQM_AF_CMP_MEM31_COEF__B                                        0
#define    IQM_AF_CMP_MEM31_COEF__W                                        13
#define    IQM_AF_CMP_MEM31_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM31_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM32__A                                               0x18700A0
#define  IQM_AF_CMP_MEM32__W                                               13
#define  IQM_AF_CMP_MEM32__M                                               0x1FFF
#define  IQM_AF_CMP_MEM32__PRE                                             0x0

#define    IQM_AF_CMP_MEM32_COEF__B                                        0
#define    IQM_AF_CMP_MEM32_COEF__W                                        13
#define    IQM_AF_CMP_MEM32_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM32_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM33__A                                               0x18700A1
#define  IQM_AF_CMP_MEM33__W                                               13
#define  IQM_AF_CMP_MEM33__M                                               0x1FFF
#define  IQM_AF_CMP_MEM33__PRE                                             0x0

#define    IQM_AF_CMP_MEM33_COEF__B                                        0
#define    IQM_AF_CMP_MEM33_COEF__W                                        13
#define    IQM_AF_CMP_MEM33_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM33_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM34__A                                               0x18700A2
#define  IQM_AF_CMP_MEM34__W                                               13
#define  IQM_AF_CMP_MEM34__M                                               0x1FFF
#define  IQM_AF_CMP_MEM34__PRE                                             0x0

#define    IQM_AF_CMP_MEM34_COEF__B                                        0
#define    IQM_AF_CMP_MEM34_COEF__W                                        13
#define    IQM_AF_CMP_MEM34_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM34_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM35__A                                               0x18700A3
#define  IQM_AF_CMP_MEM35__W                                               13
#define  IQM_AF_CMP_MEM35__M                                               0x1FFF
#define  IQM_AF_CMP_MEM35__PRE                                             0x0

#define    IQM_AF_CMP_MEM35_COEF__B                                        0
#define    IQM_AF_CMP_MEM35_COEF__W                                        13
#define    IQM_AF_CMP_MEM35_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM35_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM36__A                                               0x18700A4
#define  IQM_AF_CMP_MEM36__W                                               13
#define  IQM_AF_CMP_MEM36__M                                               0x1FFF
#define  IQM_AF_CMP_MEM36__PRE                                             0x0

#define    IQM_AF_CMP_MEM36_COEF__B                                        0
#define    IQM_AF_CMP_MEM36_COEF__W                                        13
#define    IQM_AF_CMP_MEM36_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM36_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM37__A                                               0x18700A5
#define  IQM_AF_CMP_MEM37__W                                               13
#define  IQM_AF_CMP_MEM37__M                                               0x1FFF
#define  IQM_AF_CMP_MEM37__PRE                                             0x0

#define    IQM_AF_CMP_MEM37_COEF__B                                        0
#define    IQM_AF_CMP_MEM37_COEF__W                                        13
#define    IQM_AF_CMP_MEM37_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM37_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM38__A                                               0x18700A6
#define  IQM_AF_CMP_MEM38__W                                               13
#define  IQM_AF_CMP_MEM38__M                                               0x1FFF
#define  IQM_AF_CMP_MEM38__PRE                                             0x0

#define    IQM_AF_CMP_MEM38_COEF__B                                        0
#define    IQM_AF_CMP_MEM38_COEF__W                                        13
#define    IQM_AF_CMP_MEM38_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM38_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM39__A                                               0x18700A7
#define  IQM_AF_CMP_MEM39__W                                               13
#define  IQM_AF_CMP_MEM39__M                                               0x1FFF
#define  IQM_AF_CMP_MEM39__PRE                                             0x0

#define    IQM_AF_CMP_MEM39_COEF__B                                        0
#define    IQM_AF_CMP_MEM39_COEF__W                                        13
#define    IQM_AF_CMP_MEM39_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM39_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM40__A                                               0x18700A8
#define  IQM_AF_CMP_MEM40__W                                               13
#define  IQM_AF_CMP_MEM40__M                                               0x1FFF
#define  IQM_AF_CMP_MEM40__PRE                                             0x0

#define    IQM_AF_CMP_MEM40_COEF__B                                        0
#define    IQM_AF_CMP_MEM40_COEF__W                                        13
#define    IQM_AF_CMP_MEM40_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM40_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM41__A                                               0x18700A9
#define  IQM_AF_CMP_MEM41__W                                               13
#define  IQM_AF_CMP_MEM41__M                                               0x1FFF
#define  IQM_AF_CMP_MEM41__PRE                                             0x0

#define    IQM_AF_CMP_MEM41_COEF__B                                        0
#define    IQM_AF_CMP_MEM41_COEF__W                                        13
#define    IQM_AF_CMP_MEM41_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM41_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM42__A                                               0x18700AA
#define  IQM_AF_CMP_MEM42__W                                               13
#define  IQM_AF_CMP_MEM42__M                                               0x1FFF
#define  IQM_AF_CMP_MEM42__PRE                                             0x0

#define    IQM_AF_CMP_MEM42_COEF__B                                        0
#define    IQM_AF_CMP_MEM42_COEF__W                                        13
#define    IQM_AF_CMP_MEM42_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM42_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM43__A                                               0x18700AB
#define  IQM_AF_CMP_MEM43__W                                               13
#define  IQM_AF_CMP_MEM43__M                                               0x1FFF
#define  IQM_AF_CMP_MEM43__PRE                                             0x0

#define    IQM_AF_CMP_MEM43_COEF__B                                        0
#define    IQM_AF_CMP_MEM43_COEF__W                                        13
#define    IQM_AF_CMP_MEM43_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM43_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM44__A                                               0x18700AC
#define  IQM_AF_CMP_MEM44__W                                               13
#define  IQM_AF_CMP_MEM44__M                                               0x1FFF
#define  IQM_AF_CMP_MEM44__PRE                                             0x0

#define    IQM_AF_CMP_MEM44_COEF__B                                        0
#define    IQM_AF_CMP_MEM44_COEF__W                                        13
#define    IQM_AF_CMP_MEM44_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM44_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM45__A                                               0x18700AD
#define  IQM_AF_CMP_MEM45__W                                               13
#define  IQM_AF_CMP_MEM45__M                                               0x1FFF
#define  IQM_AF_CMP_MEM45__PRE                                             0x0

#define    IQM_AF_CMP_MEM45_COEF__B                                        0
#define    IQM_AF_CMP_MEM45_COEF__W                                        13
#define    IQM_AF_CMP_MEM45_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM45_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM46__A                                               0x18700AE
#define  IQM_AF_CMP_MEM46__W                                               13
#define  IQM_AF_CMP_MEM46__M                                               0x1FFF
#define  IQM_AF_CMP_MEM46__PRE                                             0x0

#define    IQM_AF_CMP_MEM46_COEF__B                                        0
#define    IQM_AF_CMP_MEM46_COEF__W                                        13
#define    IQM_AF_CMP_MEM46_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM46_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM47__A                                               0x18700AF
#define  IQM_AF_CMP_MEM47__W                                               13
#define  IQM_AF_CMP_MEM47__M                                               0x1FFF
#define  IQM_AF_CMP_MEM47__PRE                                             0x0

#define    IQM_AF_CMP_MEM47_COEF__B                                        0
#define    IQM_AF_CMP_MEM47_COEF__W                                        13
#define    IQM_AF_CMP_MEM47_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM47_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM48__A                                               0x18700B0
#define  IQM_AF_CMP_MEM48__W                                               13
#define  IQM_AF_CMP_MEM48__M                                               0x1FFF
#define  IQM_AF_CMP_MEM48__PRE                                             0x0

#define    IQM_AF_CMP_MEM48_COEF__B                                        0
#define    IQM_AF_CMP_MEM48_COEF__W                                        13
#define    IQM_AF_CMP_MEM48_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM48_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM49__A                                               0x18700B1
#define  IQM_AF_CMP_MEM49__W                                               13
#define  IQM_AF_CMP_MEM49__M                                               0x1FFF
#define  IQM_AF_CMP_MEM49__PRE                                             0x0

#define    IQM_AF_CMP_MEM49_COEF__B                                        0
#define    IQM_AF_CMP_MEM49_COEF__W                                        13
#define    IQM_AF_CMP_MEM49_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM49_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM50__A                                               0x18700B2
#define  IQM_AF_CMP_MEM50__W                                               13
#define  IQM_AF_CMP_MEM50__M                                               0x1FFF
#define  IQM_AF_CMP_MEM50__PRE                                             0x0

#define    IQM_AF_CMP_MEM50_COEF__B                                        0
#define    IQM_AF_CMP_MEM50_COEF__W                                        13
#define    IQM_AF_CMP_MEM50_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM50_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM51__A                                               0x18700B3
#define  IQM_AF_CMP_MEM51__W                                               13
#define  IQM_AF_CMP_MEM51__M                                               0x1FFF
#define  IQM_AF_CMP_MEM51__PRE                                             0x0

#define    IQM_AF_CMP_MEM51_COEF__B                                        0
#define    IQM_AF_CMP_MEM51_COEF__W                                        13
#define    IQM_AF_CMP_MEM51_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM51_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM52__A                                               0x18700B4
#define  IQM_AF_CMP_MEM52__W                                               13
#define  IQM_AF_CMP_MEM52__M                                               0x1FFF
#define  IQM_AF_CMP_MEM52__PRE                                             0x0

#define    IQM_AF_CMP_MEM52_COEF__B                                        0
#define    IQM_AF_CMP_MEM52_COEF__W                                        13
#define    IQM_AF_CMP_MEM52_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM52_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM53__A                                               0x18700B5
#define  IQM_AF_CMP_MEM53__W                                               13
#define  IQM_AF_CMP_MEM53__M                                               0x1FFF
#define  IQM_AF_CMP_MEM53__PRE                                             0x0

#define    IQM_AF_CMP_MEM53_COEF__B                                        0
#define    IQM_AF_CMP_MEM53_COEF__W                                        13
#define    IQM_AF_CMP_MEM53_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM53_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM54__A                                               0x18700B6
#define  IQM_AF_CMP_MEM54__W                                               13
#define  IQM_AF_CMP_MEM54__M                                               0x1FFF
#define  IQM_AF_CMP_MEM54__PRE                                             0x0

#define    IQM_AF_CMP_MEM54_COEF__B                                        0
#define    IQM_AF_CMP_MEM54_COEF__W                                        13
#define    IQM_AF_CMP_MEM54_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM54_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM55__A                                               0x18700B7
#define  IQM_AF_CMP_MEM55__W                                               13
#define  IQM_AF_CMP_MEM55__M                                               0x1FFF
#define  IQM_AF_CMP_MEM55__PRE                                             0x0

#define    IQM_AF_CMP_MEM55_COEF__B                                        0
#define    IQM_AF_CMP_MEM55_COEF__W                                        13
#define    IQM_AF_CMP_MEM55_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM55_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM56__A                                               0x18700B8
#define  IQM_AF_CMP_MEM56__W                                               13
#define  IQM_AF_CMP_MEM56__M                                               0x1FFF
#define  IQM_AF_CMP_MEM56__PRE                                             0x0

#define    IQM_AF_CMP_MEM56_COEF__B                                        0
#define    IQM_AF_CMP_MEM56_COEF__W                                        13
#define    IQM_AF_CMP_MEM56_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM56_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM57__A                                               0x18700B9
#define  IQM_AF_CMP_MEM57__W                                               13
#define  IQM_AF_CMP_MEM57__M                                               0x1FFF
#define  IQM_AF_CMP_MEM57__PRE                                             0x0

#define    IQM_AF_CMP_MEM57_COEF__B                                        0
#define    IQM_AF_CMP_MEM57_COEF__W                                        13
#define    IQM_AF_CMP_MEM57_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM57_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM58__A                                               0x18700BA
#define  IQM_AF_CMP_MEM58__W                                               13
#define  IQM_AF_CMP_MEM58__M                                               0x1FFF
#define  IQM_AF_CMP_MEM58__PRE                                             0x0

#define    IQM_AF_CMP_MEM58_COEF__B                                        0
#define    IQM_AF_CMP_MEM58_COEF__W                                        13
#define    IQM_AF_CMP_MEM58_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM58_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM59__A                                               0x18700BB
#define  IQM_AF_CMP_MEM59__W                                               13
#define  IQM_AF_CMP_MEM59__M                                               0x1FFF
#define  IQM_AF_CMP_MEM59__PRE                                             0x0

#define    IQM_AF_CMP_MEM59_COEF__B                                        0
#define    IQM_AF_CMP_MEM59_COEF__W                                        13
#define    IQM_AF_CMP_MEM59_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM59_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM60__A                                               0x18700BC
#define  IQM_AF_CMP_MEM60__W                                               13
#define  IQM_AF_CMP_MEM60__M                                               0x1FFF
#define  IQM_AF_CMP_MEM60__PRE                                             0x0

#define    IQM_AF_CMP_MEM60_COEF__B                                        0
#define    IQM_AF_CMP_MEM60_COEF__W                                        13
#define    IQM_AF_CMP_MEM60_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM60_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM61__A                                               0x18700BD
#define  IQM_AF_CMP_MEM61__W                                               13
#define  IQM_AF_CMP_MEM61__M                                               0x1FFF
#define  IQM_AF_CMP_MEM61__PRE                                             0x0

#define    IQM_AF_CMP_MEM61_COEF__B                                        0
#define    IQM_AF_CMP_MEM61_COEF__W                                        13
#define    IQM_AF_CMP_MEM61_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM61_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM62__A                                               0x18700BE
#define  IQM_AF_CMP_MEM62__W                                               13
#define  IQM_AF_CMP_MEM62__M                                               0x1FFF
#define  IQM_AF_CMP_MEM62__PRE                                             0x0

#define    IQM_AF_CMP_MEM62_COEF__B                                        0
#define    IQM_AF_CMP_MEM62_COEF__W                                        13
#define    IQM_AF_CMP_MEM62_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM62_COEF__PRE                                      0x0

#define  IQM_AF_CMP_MEM63__A                                               0x18700BF
#define  IQM_AF_CMP_MEM63__W                                               13
#define  IQM_AF_CMP_MEM63__M                                               0x1FFF
#define  IQM_AF_CMP_MEM63__PRE                                             0x0

#define    IQM_AF_CMP_MEM63_COEF__B                                        0
#define    IQM_AF_CMP_MEM63_COEF__W                                        13
#define    IQM_AF_CMP_MEM63_COEF__M                                        0x1FFF
#define    IQM_AF_CMP_MEM63_COEF__PRE                                      0x0



#define  IQM_RT_RAM__A                                                     0x1880000

#define    IQM_RT_RAM_DLY__B                                               0
#define    IQM_RT_RAM_DLY__W                                               13
#define    IQM_RT_RAM_DLY__M                                               0x1FFF
#define    IQM_RT_RAM_DLY__PRE                                             0x0





#define  OFDM_CE_COMM_EXEC__A                                              0x2C00000
#define  OFDM_CE_COMM_EXEC__W                                              3
#define  OFDM_CE_COMM_EXEC__M                                              0x7
#define  OFDM_CE_COMM_EXEC__PRE                                            0x0
#define    OFDM_CE_COMM_EXEC_STOP                                          0x0
#define    OFDM_CE_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_CE_COMM_EXEC_HOLD                                          0x2
#define    OFDM_CE_COMM_EXEC_STEP                                          0x3
#define    OFDM_CE_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_CE_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_CE_COMM_STATE__A                                             0x2C00001
#define  OFDM_CE_COMM_STATE__W                                             16
#define  OFDM_CE_COMM_STATE__M                                             0xFFFF
#define  OFDM_CE_COMM_STATE__PRE                                           0x0
#define  OFDM_CE_COMM_MB__A                                                0x2C00002
#define  OFDM_CE_COMM_MB__W                                                16
#define  OFDM_CE_COMM_MB__M                                                0xFFFF
#define  OFDM_CE_COMM_MB__PRE                                              0x0
#define  OFDM_CE_COMM_INT_REQ__A                                           0x2C00004
#define  OFDM_CE_COMM_INT_REQ__W                                           16
#define  OFDM_CE_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_CE_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_CE_COMM_INT_REQ_TOP_REQ__B                                 2
#define    OFDM_CE_COMM_INT_REQ_TOP_REQ__W                                 1
#define    OFDM_CE_COMM_INT_REQ_TOP_REQ__M                                 0x4
#define    OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE                               0x0

#define  OFDM_CE_COMM_INT_STA__A                                           0x2C00005
#define  OFDM_CE_COMM_INT_STA__W                                           16
#define  OFDM_CE_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_CE_COMM_INT_STA__PRE                                         0x0
#define  OFDM_CE_COMM_INT_MSK__A                                           0x2C00006
#define  OFDM_CE_COMM_INT_MSK__W                                           16
#define  OFDM_CE_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_CE_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_CE_COMM_INT_STM__A                                           0x2C00007
#define  OFDM_CE_COMM_INT_STM__W                                           16
#define  OFDM_CE_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_CE_COMM_INT_STM__PRE                                         0x0
#define    OFDM_CE_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_CE_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_CE_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_CE_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_CE_TOP_COMM_EXEC__A                                          0x2C10000
#define  OFDM_CE_TOP_COMM_EXEC__W                                          3
#define  OFDM_CE_TOP_COMM_EXEC__M                                          0x7
#define  OFDM_CE_TOP_COMM_EXEC__PRE                                        0x0
#define    OFDM_CE_TOP_COMM_EXEC_STOP                                      0x0
#define    OFDM_CE_TOP_COMM_EXEC_ACTIVE                                    0x1
#define    OFDM_CE_TOP_COMM_EXEC_HOLD                                      0x2
#define    OFDM_CE_TOP_COMM_EXEC_STEP                                      0x3

#define  OFDM_CE_TOP_COMM_MB__A                                            0x2C10002
#define  OFDM_CE_TOP_COMM_MB__W                                            4
#define  OFDM_CE_TOP_COMM_MB__M                                            0xF
#define  OFDM_CE_TOP_COMM_MB__PRE                                          0x0
#define    OFDM_CE_TOP_COMM_MB_CTL__B                                      0
#define    OFDM_CE_TOP_COMM_MB_CTL__W                                      1
#define    OFDM_CE_TOP_COMM_MB_CTL__M                                      0x1
#define    OFDM_CE_TOP_COMM_MB_CTL__PRE                                    0x0
#define      OFDM_CE_TOP_COMM_MB_CTL_OFF                                   0x0
#define      OFDM_CE_TOP_COMM_MB_CTL_ON                                    0x1
#define    OFDM_CE_TOP_COMM_MB_OBS__B                                      1
#define    OFDM_CE_TOP_COMM_MB_OBS__W                                      1
#define    OFDM_CE_TOP_COMM_MB_OBS__M                                      0x2
#define    OFDM_CE_TOP_COMM_MB_OBS__PRE                                    0x0
#define      OFDM_CE_TOP_COMM_MB_OBS_OFF                                   0x0
#define      OFDM_CE_TOP_COMM_MB_OBS_ON                                    0x2
#define    OFDM_CE_TOP_COMM_MB_OBS_SEL__B                                  2
#define    OFDM_CE_TOP_COMM_MB_OBS_SEL__W                                  2
#define    OFDM_CE_TOP_COMM_MB_OBS_SEL__M                                  0xC
#define    OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE                                0x0
#define      OFDM_CE_TOP_COMM_MB_OBS_SEL_FI                                0x0
#define      OFDM_CE_TOP_COMM_MB_OBS_SEL_TP                                0x4
#define      OFDM_CE_TOP_COMM_MB_OBS_SEL_TI                                0x8
#define      OFDM_CE_TOP_COMM_MB_OBS_SEL_FR                                0xC

#define  OFDM_CE_TOP_COMM_INT_REQ__A                                       0x2C10004
#define  OFDM_CE_TOP_COMM_INT_REQ__W                                       1
#define  OFDM_CE_TOP_COMM_INT_REQ__M                                       0x1
#define  OFDM_CE_TOP_COMM_INT_REQ__PRE                                     0x0
#define  OFDM_CE_TOP_COMM_INT_STA__A                                       0x2C10005
#define  OFDM_CE_TOP_COMM_INT_STA__W                                       3
#define  OFDM_CE_TOP_COMM_INT_STA__M                                       0x7
#define  OFDM_CE_TOP_COMM_INT_STA__PRE                                     0x0
#define    OFDM_CE_TOP_COMM_INT_STA_CE_PE__B                               0
#define    OFDM_CE_TOP_COMM_INT_STA_CE_PE__W                               1
#define    OFDM_CE_TOP_COMM_INT_STA_CE_PE__M                               0x1
#define    OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE                             0x0
#define    OFDM_CE_TOP_COMM_INT_STA_CE_IR__B                               1
#define    OFDM_CE_TOP_COMM_INT_STA_CE_IR__W                               1
#define    OFDM_CE_TOP_COMM_INT_STA_CE_IR__M                               0x2
#define    OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE                             0x0
#define    OFDM_CE_TOP_COMM_INT_STA_CE_FI__B                               2
#define    OFDM_CE_TOP_COMM_INT_STA_CE_FI__W                               1
#define    OFDM_CE_TOP_COMM_INT_STA_CE_FI__M                               0x4
#define    OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE                             0x0

#define  OFDM_CE_TOP_COMM_INT_MSK__A                                       0x2C10006
#define  OFDM_CE_TOP_COMM_INT_MSK__W                                       3
#define  OFDM_CE_TOP_COMM_INT_MSK__M                                       0x7
#define  OFDM_CE_TOP_COMM_INT_MSK__PRE                                     0x0
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B                               0
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W                               1
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M                               0x1
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE                             0x0
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B                               1
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W                               1
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M                               0x2
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE                             0x0
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B                               2
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W                               1
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M                               0x4
#define    OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE                             0x0

#define  OFDM_CE_TOP_COMM_INT_STM__A                                       0x2C10007
#define  OFDM_CE_TOP_COMM_INT_STM__W                                       3
#define  OFDM_CE_TOP_COMM_INT_STM__M                                       0x7
#define  OFDM_CE_TOP_COMM_INT_STM__PRE                                     0x0
#define    OFDM_CE_TOP_COMM_INT_STM_CE_PE__B                               0
#define    OFDM_CE_TOP_COMM_INT_STM_CE_PE__W                               1
#define    OFDM_CE_TOP_COMM_INT_STM_CE_PE__M                               0x1
#define    OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE                             0x0
#define    OFDM_CE_TOP_COMM_INT_STM_CE_IR__B                               1
#define    OFDM_CE_TOP_COMM_INT_STM_CE_IR__W                               1
#define    OFDM_CE_TOP_COMM_INT_STM_CE_IR__M                               0x2
#define    OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE                             0x0
#define    OFDM_CE_TOP_COMM_INT_STM_CE_FI__B                               2
#define    OFDM_CE_TOP_COMM_INT_STM_CE_FI__W                               1
#define    OFDM_CE_TOP_COMM_INT_STM_CE_FI__M                               0x4
#define    OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE                             0x0


#define  OFDM_CE_TOP_MODE_2K__A                                            0x2C10010
#define  OFDM_CE_TOP_MODE_2K__W                                            1
#define  OFDM_CE_TOP_MODE_2K__M                                            0x1
#define  OFDM_CE_TOP_MODE_2K__PRE                                          0x0

#define  OFDM_CE_TOP_TAPSET__A                                             0x2C10011
#define  OFDM_CE_TOP_TAPSET__W                                             4
#define  OFDM_CE_TOP_TAPSET__M                                             0xF
#define  OFDM_CE_TOP_TAPSET__PRE                                           0x1
#define  OFDM_CE_TOP_AVG_POW__A                                            0x2C10012
#define  OFDM_CE_TOP_AVG_POW__W                                            8
#define  OFDM_CE_TOP_AVG_POW__M                                            0xFF
#define  OFDM_CE_TOP_AVG_POW__PRE                                          0x65
#define  OFDM_CE_TOP_MAX_POW__A                                            0x2C10013
#define  OFDM_CE_TOP_MAX_POW__W                                            8
#define  OFDM_CE_TOP_MAX_POW__M                                            0xFF
#define  OFDM_CE_TOP_MAX_POW__PRE                                          0x80
#define  OFDM_CE_TOP_ATT__A                                                0x2C10014
#define  OFDM_CE_TOP_ATT__W                                                8
#define  OFDM_CE_TOP_ATT__M                                                0xFF
#define  OFDM_CE_TOP_ATT__PRE                                              0x70
#define  OFDM_CE_TOP_NRED__A                                               0x2C10015
#define  OFDM_CE_TOP_NRED__W                                               6
#define  OFDM_CE_TOP_NRED__M                                               0x3F
#define  OFDM_CE_TOP_NRED__PRE                                             0x9

#define  OFDM_CE_TOP_PU_SIGN__A                                            0x2C10020
#define  OFDM_CE_TOP_PU_SIGN__W                                            1
#define  OFDM_CE_TOP_PU_SIGN__M                                            0x1
#define  OFDM_CE_TOP_PU_SIGN__PRE                                          0x0

#define  OFDM_CE_TOP_PU_MIX__A                                             0x2C10021
#define  OFDM_CE_TOP_PU_MIX__W                                             1
#define  OFDM_CE_TOP_PU_MIX__M                                             0x1
#define  OFDM_CE_TOP_PU_MIX__PRE                                           0x0
#define  OFDM_CE_TOP_PB_PILOT_REQ__A                                       0x2C10030
#define  OFDM_CE_TOP_PB_PILOT_REQ__W                                       15
#define  OFDM_CE_TOP_PB_PILOT_REQ__M                                       0x7FFF
#define  OFDM_CE_TOP_PB_PILOT_REQ__PRE                                     0x0
#define    OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B                        12
#define    OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W                        3
#define    OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M                        0x7000
#define    OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE                      0x0
#define    OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B                           0
#define    OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W                           12
#define    OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M                           0xFFF
#define    OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE                         0x0


#define  OFDM_CE_TOP_PB_PILOT_REQ_VALID__A                                 0x2C10031
#define  OFDM_CE_TOP_PB_PILOT_REQ_VALID__W                                 1
#define  OFDM_CE_TOP_PB_PILOT_REQ_VALID__M                                 0x1
#define  OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE                               0x0

#define  OFDM_CE_TOP_PB_FREEZE__A                                          0x2C10032
#define  OFDM_CE_TOP_PB_FREEZE__W                                          1
#define  OFDM_CE_TOP_PB_FREEZE__M                                          0x1
#define  OFDM_CE_TOP_PB_FREEZE__PRE                                        0x0

#define  OFDM_CE_TOP_PB_PILOT_EXP__A                                       0x2C10038
#define  OFDM_CE_TOP_PB_PILOT_EXP__W                                       4
#define  OFDM_CE_TOP_PB_PILOT_EXP__M                                       0xF
#define  OFDM_CE_TOP_PB_PILOT_EXP__PRE                                     0x0

#define  OFDM_CE_TOP_PB_PILOT_REAL__A                                      0x2C10039
#define  OFDM_CE_TOP_PB_PILOT_REAL__W                                      10
#define  OFDM_CE_TOP_PB_PILOT_REAL__M                                      0x3FF
#define  OFDM_CE_TOP_PB_PILOT_REAL__PRE                                    0x0

#define  OFDM_CE_TOP_PB_PILOT_IMAG__A                                      0x2C1003A
#define  OFDM_CE_TOP_PB_PILOT_IMAG__W                                      10
#define  OFDM_CE_TOP_PB_PILOT_IMAG__M                                      0x3FF
#define  OFDM_CE_TOP_PB_PILOT_IMAG__PRE                                    0x0

#define  OFDM_CE_TOP_PB_SMBNR__A                                           0x2C1003B
#define  OFDM_CE_TOP_PB_SMBNR__W                                           5
#define  OFDM_CE_TOP_PB_SMBNR__M                                           0x1F
#define  OFDM_CE_TOP_PB_SMBNR__PRE                                         0x0

#define  OFDM_CE_TOP_NE_PILOT_REQ__A                                       0x2C10040
#define  OFDM_CE_TOP_NE_PILOT_REQ__W                                       12
#define  OFDM_CE_TOP_NE_PILOT_REQ__M                                       0xFFF
#define  OFDM_CE_TOP_NE_PILOT_REQ__PRE                                     0x0
#define  OFDM_CE_TOP_NE_PILOT_REQ_VALID__A                                 0x2C10041
#define  OFDM_CE_TOP_NE_PILOT_REQ_VALID__W                                 2
#define  OFDM_CE_TOP_NE_PILOT_REQ_VALID__M                                 0x3
#define  OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE                               0x0
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B                   1
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W                   1
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M                   0x2
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE                 0x0
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B                    0
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W                    1
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M                    0x1
#define    OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE                  0x0


#define  OFDM_CE_TOP_NE_PILOT_DATA__A                                      0x2C10042
#define  OFDM_CE_TOP_NE_PILOT_DATA__W                                      10
#define  OFDM_CE_TOP_NE_PILOT_DATA__M                                      0x3FF
#define  OFDM_CE_TOP_NE_PILOT_DATA__PRE                                    0x0
#define  OFDM_CE_TOP_NE_ERR_SELECT__A                                      0x2C10043
#define  OFDM_CE_TOP_NE_ERR_SELECT__W                                      5
#define  OFDM_CE_TOP_NE_ERR_SELECT__M                                      0x1F
#define  OFDM_CE_TOP_NE_ERR_SELECT__PRE                                    0x7

#define    OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B                            4
#define    OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W                            1
#define    OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M                            0x10
#define    OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE                          0x0

#define    OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B                          3
#define    OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W                          1
#define    OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M                          0x8
#define    OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE                        0x0

#define    OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B                          2
#define    OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W                          1
#define    OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M                          0x4
#define    OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE                        0x4

#define    OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B                          1
#define    OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W                          1
#define    OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M                          0x2
#define    OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE                        0x2

#define    OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B                          0
#define    OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W                          1
#define    OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M                          0x1
#define    OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE                        0x1


#define  OFDM_CE_TOP_NE_TD_CAL__A                                          0x2C10044
#define  OFDM_CE_TOP_NE_TD_CAL__W                                          9
#define  OFDM_CE_TOP_NE_TD_CAL__M                                          0x1FF
#define  OFDM_CE_TOP_NE_TD_CAL__PRE                                        0x1E8

#define  OFDM_CE_TOP_NE_FD_CAL__A                                          0x2C10045
#define  OFDM_CE_TOP_NE_FD_CAL__W                                          9
#define  OFDM_CE_TOP_NE_FD_CAL__M                                          0x1FF
#define  OFDM_CE_TOP_NE_FD_CAL__PRE                                        0x1D9

#define  OFDM_CE_TOP_NE_MIXAVG__A                                          0x2C10046
#define  OFDM_CE_TOP_NE_MIXAVG__W                                          3
#define  OFDM_CE_TOP_NE_MIXAVG__M                                          0x7
#define  OFDM_CE_TOP_NE_MIXAVG__PRE                                        0x6

#define  OFDM_CE_TOP_NE_NUPD_OFS__A                                        0x2C10047
#define  OFDM_CE_TOP_NE_NUPD_OFS__W                                        4
#define  OFDM_CE_TOP_NE_NUPD_OFS__M                                        0xF
#define  OFDM_CE_TOP_NE_NUPD_OFS__PRE                                      0x4
#define  OFDM_CE_TOP_NE_TD_POW__A                                          0x2C10048
#define  OFDM_CE_TOP_NE_TD_POW__W                                          15
#define  OFDM_CE_TOP_NE_TD_POW__M                                          0x7FFF
#define  OFDM_CE_TOP_NE_TD_POW__PRE                                        0x0

#define    OFDM_CE_TOP_NE_TD_POW_EXPONENT__B                               10
#define    OFDM_CE_TOP_NE_TD_POW_EXPONENT__W                               5
#define    OFDM_CE_TOP_NE_TD_POW_EXPONENT__M                               0x7C00
#define    OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE                             0x0

#define    OFDM_CE_TOP_NE_TD_POW_MANTISSA__B                               0
#define    OFDM_CE_TOP_NE_TD_POW_MANTISSA__W                               10
#define    OFDM_CE_TOP_NE_TD_POW_MANTISSA__M                               0x3FF
#define    OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE                             0x0

#define  OFDM_CE_TOP_NE_FD_POW__A                                          0x2C10049
#define  OFDM_CE_TOP_NE_FD_POW__W                                          15
#define  OFDM_CE_TOP_NE_FD_POW__M                                          0x7FFF
#define  OFDM_CE_TOP_NE_FD_POW__PRE                                        0x0

#define    OFDM_CE_TOP_NE_FD_POW_EXPONENT__B                               10
#define    OFDM_CE_TOP_NE_FD_POW_EXPONENT__W                               5
#define    OFDM_CE_TOP_NE_FD_POW_EXPONENT__M                               0x7C00
#define    OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE                             0x0

#define    OFDM_CE_TOP_NE_FD_POW_MANTISSA__B                               0
#define    OFDM_CE_TOP_NE_FD_POW_MANTISSA__W                               10
#define    OFDM_CE_TOP_NE_FD_POW_MANTISSA__M                               0x3FF
#define    OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE                             0x0


#define  OFDM_CE_TOP_NE_NEXP_AVG__A                                        0x2C1004A
#define  OFDM_CE_TOP_NE_NEXP_AVG__W                                        8
#define  OFDM_CE_TOP_NE_NEXP_AVG__M                                        0xFF
#define  OFDM_CE_TOP_NE_NEXP_AVG__PRE                                      0x0

#define  OFDM_CE_TOP_NE_OFFSET__A                                          0x2C1004B
#define  OFDM_CE_TOP_NE_OFFSET__W                                          9
#define  OFDM_CE_TOP_NE_OFFSET__M                                          0x1FF
#define  OFDM_CE_TOP_NE_OFFSET__PRE                                        0x0

#define  OFDM_CE_TOP_NE_NUPD_TRH__A                                        0x2C1004C
#define  OFDM_CE_TOP_NE_NUPD_TRH__W                                        5
#define  OFDM_CE_TOP_NE_NUPD_TRH__M                                        0x1F
#define  OFDM_CE_TOP_NE_NUPD_TRH__PRE                                      0x14

#define  OFDM_CE_TOP_PE_NEXP_OFFS__A                                       0x2C10050
#define  OFDM_CE_TOP_PE_NEXP_OFFS__W                                       8
#define  OFDM_CE_TOP_PE_NEXP_OFFS__M                                       0xFF
#define  OFDM_CE_TOP_PE_NEXP_OFFS__PRE                                     0x0

#define  OFDM_CE_TOP_PE_TIMESHIFT__A                                       0x2C10051
#define  OFDM_CE_TOP_PE_TIMESHIFT__W                                       14
#define  OFDM_CE_TOP_PE_TIMESHIFT__M                                       0x3FFF
#define  OFDM_CE_TOP_PE_TIMESHIFT__PRE                                     0x0

#define  OFDM_CE_TOP_PE_DIF_REAL_L__A                                      0x2C10052
#define  OFDM_CE_TOP_PE_DIF_REAL_L__W                                      16
#define  OFDM_CE_TOP_PE_DIF_REAL_L__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_DIF_REAL_L__PRE                                    0x0

#define  OFDM_CE_TOP_PE_DIF_IMAG_L__A                                      0x2C10053
#define  OFDM_CE_TOP_PE_DIF_IMAG_L__W                                      16
#define  OFDM_CE_TOP_PE_DIF_IMAG_L__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_DIF_IMAG_L__PRE                                    0x0

#define  OFDM_CE_TOP_PE_DIF_REAL_R__A                                      0x2C10054
#define  OFDM_CE_TOP_PE_DIF_REAL_R__W                                      16
#define  OFDM_CE_TOP_PE_DIF_REAL_R__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_DIF_REAL_R__PRE                                    0x0

#define  OFDM_CE_TOP_PE_DIF_IMAG_R__A                                      0x2C10055
#define  OFDM_CE_TOP_PE_DIF_IMAG_R__W                                      16
#define  OFDM_CE_TOP_PE_DIF_IMAG_R__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_DIF_IMAG_R__PRE                                    0x0

#define  OFDM_CE_TOP_PE_ABS_REAL_L__A                                      0x2C10056
#define  OFDM_CE_TOP_PE_ABS_REAL_L__W                                      16
#define  OFDM_CE_TOP_PE_ABS_REAL_L__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_ABS_REAL_L__PRE                                    0x0

#define  OFDM_CE_TOP_PE_ABS_IMAG_L__A                                      0x2C10057
#define  OFDM_CE_TOP_PE_ABS_IMAG_L__W                                      16
#define  OFDM_CE_TOP_PE_ABS_IMAG_L__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_ABS_IMAG_L__PRE                                    0x0

#define  OFDM_CE_TOP_PE_ABS_REAL_R__A                                      0x2C10058
#define  OFDM_CE_TOP_PE_ABS_REAL_R__W                                      16
#define  OFDM_CE_TOP_PE_ABS_REAL_R__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_ABS_REAL_R__PRE                                    0x0

#define  OFDM_CE_TOP_PE_ABS_IMAG_R__A                                      0x2C10059
#define  OFDM_CE_TOP_PE_ABS_IMAG_R__W                                      16
#define  OFDM_CE_TOP_PE_ABS_IMAG_R__M                                      0xFFFF
#define  OFDM_CE_TOP_PE_ABS_IMAG_R__PRE                                    0x0

#define  OFDM_CE_TOP_PE_ABS_EXP_L__A                                       0x2C1005A
#define  OFDM_CE_TOP_PE_ABS_EXP_L__W                                       5
#define  OFDM_CE_TOP_PE_ABS_EXP_L__M                                       0x1F
#define  OFDM_CE_TOP_PE_ABS_EXP_L__PRE                                     0x0

#define  OFDM_CE_TOP_PE_ABS_EXP_R__A                                       0x2C1005B
#define  OFDM_CE_TOP_PE_ABS_EXP_R__W                                       5
#define  OFDM_CE_TOP_PE_ABS_EXP_R__M                                       0x1F
#define  OFDM_CE_TOP_PE_ABS_EXP_R__PRE                                     0x0

#define  OFDM_CE_TOP_TP_UPDATE_MODE__A                                     0x2C10060
#define  OFDM_CE_TOP_TP_UPDATE_MODE__W                                     1
#define  OFDM_CE_TOP_TP_UPDATE_MODE__M                                     0x1
#define  OFDM_CE_TOP_TP_UPDATE_MODE__PRE                                   0x0

#define  OFDM_CE_TOP_TP_LMS_TAP_ON__A                                      0x2C10061
#define  OFDM_CE_TOP_TP_LMS_TAP_ON__W                                      1
#define  OFDM_CE_TOP_TP_LMS_TAP_ON__M                                      0x1
#define  OFDM_CE_TOP_TP_LMS_TAP_ON__PRE                                    0x0

#define  OFDM_CE_TOP_TP_A0_TAP_NEW__A                                      0x2C10064
#define  OFDM_CE_TOP_TP_A0_TAP_NEW__W                                      10
#define  OFDM_CE_TOP_TP_A0_TAP_NEW__M                                      0x3FF
#define  OFDM_CE_TOP_TP_A0_TAP_NEW__PRE                                    0x100

#define  OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A                                0x2C10065
#define  OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W                                1
#define  OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M                                0x1
#define  OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE                              0x0

#define  OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A                                  0x2C10066
#define  OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W                                  5
#define  OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M                                  0x1F
#define  OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE                                0xE

#define  OFDM_CE_TOP_TP_A0_TAP_CURR__A                                     0x2C10067
#define  OFDM_CE_TOP_TP_A0_TAP_CURR__W                                     10
#define  OFDM_CE_TOP_TP_A0_TAP_CURR__M                                     0x3FF
#define  OFDM_CE_TOP_TP_A0_TAP_CURR__PRE                                   0x0

#define  OFDM_CE_TOP_TP_A1_TAP_NEW__A                                      0x2C10068
#define  OFDM_CE_TOP_TP_A1_TAP_NEW__W                                      10
#define  OFDM_CE_TOP_TP_A1_TAP_NEW__M                                      0x3FF
#define  OFDM_CE_TOP_TP_A1_TAP_NEW__PRE                                    0x0

#define  OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A                                0x2C10069
#define  OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W                                1
#define  OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M                                0x1
#define  OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE                              0x0

#define  OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A                                  0x2C1006A
#define  OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W                                  5
#define  OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M                                  0x1F
#define  OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE                                0xA

#define  OFDM_CE_TOP_TP_A1_TAP_CURR__A                                     0x2C1006B
#define  OFDM_CE_TOP_TP_A1_TAP_CURR__W                                     10
#define  OFDM_CE_TOP_TP_A1_TAP_CURR__M                                     0x3FF
#define  OFDM_CE_TOP_TP_A1_TAP_CURR__PRE                                   0x0
#define  OFDM_CE_TOP_TP_DOPP_ENERGY__A                                     0x2C1006C
#define  OFDM_CE_TOP_TP_DOPP_ENERGY__W                                     15
#define  OFDM_CE_TOP_TP_DOPP_ENERGY__M                                     0x7FFF
#define  OFDM_CE_TOP_TP_DOPP_ENERGY__PRE                                   0x0

#define    OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B                          10
#define    OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W                          5
#define    OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M                          0x7C00
#define    OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE                        0x0

#define    OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B                          0
#define    OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W                          10
#define    OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M                          0x3FF
#define    OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE                        0x0

#define  OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A                                0x2C1006D
#define  OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W                                15
#define  OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M                                0x7FFF
#define  OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE                              0x0

#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B                     10
#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W                     5
#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M                     0x7C00
#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE                   0x0

#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B                     0
#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W                     10
#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M                     0x3FF
#define    OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE                   0x0

#define  OFDM_CE_TOP_TP_A0_TAP_ENERGY__A                                   0x2C1006E
#define  OFDM_CE_TOP_TP_A0_TAP_ENERGY__W                                   15
#define  OFDM_CE_TOP_TP_A0_TAP_ENERGY__M                                   0x7FFF
#define  OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE                                 0x0

#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B                        10
#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W                        5
#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M                        0x7C00
#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE                      0x0

#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B                        0
#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W                        10
#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M                        0x3FF
#define    OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE                      0x0

#define  OFDM_CE_TOP_TP_A1_TAP_ENERGY__A                                   0x2C1006F
#define  OFDM_CE_TOP_TP_A1_TAP_ENERGY__W                                   15
#define  OFDM_CE_TOP_TP_A1_TAP_ENERGY__M                                   0x7FFF
#define  OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE                                 0x0

#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B                        10
#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W                        5
#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M                        0x7C00
#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE                      0x0

#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B                        0
#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W                        10
#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M                        0x3FF
#define    OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE                      0x0


#define  OFDM_CE_TOP_TI_SYM_CNT__A                                         0x2C10072
#define  OFDM_CE_TOP_TI_SYM_CNT__W                                         6
#define  OFDM_CE_TOP_TI_SYM_CNT__M                                         0x3F
#define  OFDM_CE_TOP_TI_SYM_CNT__PRE                                       0x20

#define  OFDM_CE_TOP_TI_PHN_ENABLE__A                                      0x2C10073
#define  OFDM_CE_TOP_TI_PHN_ENABLE__W                                      1
#define  OFDM_CE_TOP_TI_PHN_ENABLE__M                                      0x1
#define  OFDM_CE_TOP_TI_PHN_ENABLE__PRE                                    0x1

#define  OFDM_CE_TOP_TI_SHIFT__A                                           0x2C10074
#define  OFDM_CE_TOP_TI_SHIFT__W                                           2
#define  OFDM_CE_TOP_TI_SHIFT__M                                           0x3
#define  OFDM_CE_TOP_TI_SHIFT__PRE                                         0x0

#define  OFDM_CE_TOP_TI_SLOW__A                                            0x2C10075
#define  OFDM_CE_TOP_TI_SLOW__W                                            1
#define  OFDM_CE_TOP_TI_SLOW__M                                            0x1
#define  OFDM_CE_TOP_TI_SLOW__PRE                                          0x1

#define  OFDM_CE_TOP_TI_MGAIN__A                                           0x2C10076
#define  OFDM_CE_TOP_TI_MGAIN__W                                           8
#define  OFDM_CE_TOP_TI_MGAIN__M                                           0xFF
#define  OFDM_CE_TOP_TI_MGAIN__PRE                                         0x0

#define  OFDM_CE_TOP_TI_ACCU1__A                                           0x2C10077
#define  OFDM_CE_TOP_TI_ACCU1__W                                           8
#define  OFDM_CE_TOP_TI_ACCU1__M                                           0xFF
#define  OFDM_CE_TOP_TI_ACCU1__PRE                                         0x0

#define  OFDM_CE_TOP_NI_PER_LEFT__A                                        0x2C100B0
#define  OFDM_CE_TOP_NI_PER_LEFT__W                                        5
#define  OFDM_CE_TOP_NI_PER_LEFT__M                                        0x1F
#define  OFDM_CE_TOP_NI_PER_LEFT__PRE                                      0xE

#define  OFDM_CE_TOP_NI_PER_RIGHT__A                                       0x2C100B1
#define  OFDM_CE_TOP_NI_PER_RIGHT__W                                       5
#define  OFDM_CE_TOP_NI_PER_RIGHT__M                                       0x1F
#define  OFDM_CE_TOP_NI_PER_RIGHT__PRE                                     0x7

#define  OFDM_CE_TOP_NI_POS_LR__A                                          0x2C100B2
#define  OFDM_CE_TOP_NI_POS_LR__W                                          9
#define  OFDM_CE_TOP_NI_POS_LR__M                                          0x1FF
#define  OFDM_CE_TOP_NI_POS_LR__PRE                                        0xA0

#define  OFDM_CE_TOP_FI_SHT_INCR__A                                        0x2C10090
#define  OFDM_CE_TOP_FI_SHT_INCR__W                                        9
#define  OFDM_CE_TOP_FI_SHT_INCR__M                                        0x1FF
#define  OFDM_CE_TOP_FI_SHT_INCR__PRE                                      0x1E

#define  OFDM_CE_TOP_FI_EXP_NORM__A                                        0x2C10091
#define  OFDM_CE_TOP_FI_EXP_NORM__W                                        4
#define  OFDM_CE_TOP_FI_EXP_NORM__M                                        0xF
#define  OFDM_CE_TOP_FI_EXP_NORM__PRE                                      0xC

#define  OFDM_CE_TOP_FI_SUPR_VAL__A                                        0x2C10092
#define  OFDM_CE_TOP_FI_SUPR_VAL__W                                        1
#define  OFDM_CE_TOP_FI_SUPR_VAL__M                                        0x1
#define  OFDM_CE_TOP_FI_SUPR_VAL__PRE                                      0x0

#define  OFDM_CE_TOP_IR_INPUTSEL__A                                        0x2C100A0
#define  OFDM_CE_TOP_IR_INPUTSEL__W                                        1
#define  OFDM_CE_TOP_IR_INPUTSEL__M                                        0x1
#define  OFDM_CE_TOP_IR_INPUTSEL__PRE                                      0x0

#define  OFDM_CE_TOP_IR_STARTPOS__A                                        0x2C100A1
#define  OFDM_CE_TOP_IR_STARTPOS__W                                        8
#define  OFDM_CE_TOP_IR_STARTPOS__M                                        0xFF
#define  OFDM_CE_TOP_IR_STARTPOS__PRE                                      0x0

#define  OFDM_CE_TOP_IR_NEXP_THRES__A                                      0x2C100A2
#define  OFDM_CE_TOP_IR_NEXP_THRES__W                                      8
#define  OFDM_CE_TOP_IR_NEXP_THRES__M                                      0xFF
#define  OFDM_CE_TOP_IR_NEXP_THRES__PRE                                    0xFF

#define  OFDM_CE_TOP_IR_LENGTH__A                                          0x2C100A3
#define  OFDM_CE_TOP_IR_LENGTH__W                                          4
#define  OFDM_CE_TOP_IR_LENGTH__M                                          0xF
#define  OFDM_CE_TOP_IR_LENGTH__PRE                                        0x9

#define  OFDM_CE_TOP_IR_FREQ__A                                            0x2C100A4
#define  OFDM_CE_TOP_IR_FREQ__W                                            11
#define  OFDM_CE_TOP_IR_FREQ__M                                            0x7FF
#define  OFDM_CE_TOP_IR_FREQ__PRE                                          0x0

#define  OFDM_CE_TOP_IR_FREQINC__A                                         0x2C100A5
#define  OFDM_CE_TOP_IR_FREQINC__W                                         11
#define  OFDM_CE_TOP_IR_FREQINC__M                                         0x7FF
#define  OFDM_CE_TOP_IR_FREQINC__PRE                                       0x4

#define  OFDM_CE_TOP_IR_KAISINC__A                                         0x2C100A6
#define  OFDM_CE_TOP_IR_KAISINC__W                                         15
#define  OFDM_CE_TOP_IR_KAISINC__M                                         0x7FFF
#define  OFDM_CE_TOP_IR_KAISINC__PRE                                       0x100

#define  OFDM_CE_TOP_IR_CTL__A                                             0x2C100A7
#define  OFDM_CE_TOP_IR_CTL__W                                             3
#define  OFDM_CE_TOP_IR_CTL__M                                             0x7
#define  OFDM_CE_TOP_IR_CTL__PRE                                           0x0

#define  OFDM_CE_TOP_IR_REAL__A                                            0x2C100A8
#define  OFDM_CE_TOP_IR_REAL__W                                            16
#define  OFDM_CE_TOP_IR_REAL__M                                            0xFFFF
#define  OFDM_CE_TOP_IR_REAL__PRE                                          0x0

#define  OFDM_CE_TOP_IR_IMAG__A                                            0x2C100A9
#define  OFDM_CE_TOP_IR_IMAG__W                                            16
#define  OFDM_CE_TOP_IR_IMAG__M                                            0xFFFF
#define  OFDM_CE_TOP_IR_IMAG__PRE                                          0x0

#define  OFDM_CE_TOP_IR_INDEX__A                                           0x2C100AA
#define  OFDM_CE_TOP_IR_INDEX__W                                           12
#define  OFDM_CE_TOP_IR_INDEX__M                                           0xFFF
#define  OFDM_CE_TOP_IR_INDEX__PRE                                         0x0



#define  OFDM_CE_FR_COMM_EXEC__A                                           0x2C20000
#define  OFDM_CE_FR_COMM_EXEC__W                                           3
#define  OFDM_CE_FR_COMM_EXEC__M                                           0x7
#define  OFDM_CE_FR_COMM_EXEC__PRE                                         0x0
#define    OFDM_CE_FR_COMM_EXEC_STOP                                       0x0
#define    OFDM_CE_FR_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_CE_FR_COMM_EXEC_HOLD                                       0x2
#define    OFDM_CE_FR_COMM_EXEC_STEP                                       0x3


#define  OFDM_CE_FR_TREAL00__A                                             0x2C20010
#define  OFDM_CE_FR_TREAL00__W                                             11
#define  OFDM_CE_FR_TREAL00__M                                             0x7FF
#define  OFDM_CE_FR_TREAL00__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG00__A                                             0x2C20011
#define  OFDM_CE_FR_TIMAG00__W                                             11
#define  OFDM_CE_FR_TIMAG00__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG00__PRE                                           0x0

#define  OFDM_CE_FR_TREAL01__A                                             0x2C20012
#define  OFDM_CE_FR_TREAL01__W                                             11
#define  OFDM_CE_FR_TREAL01__M                                             0x7FF
#define  OFDM_CE_FR_TREAL01__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG01__A                                             0x2C20013
#define  OFDM_CE_FR_TIMAG01__W                                             11
#define  OFDM_CE_FR_TIMAG01__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG01__PRE                                           0x0

#define  OFDM_CE_FR_TREAL02__A                                             0x2C20014
#define  OFDM_CE_FR_TREAL02__W                                             11
#define  OFDM_CE_FR_TREAL02__M                                             0x7FF
#define  OFDM_CE_FR_TREAL02__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG02__A                                             0x2C20015
#define  OFDM_CE_FR_TIMAG02__W                                             11
#define  OFDM_CE_FR_TIMAG02__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG02__PRE                                           0x0

#define  OFDM_CE_FR_TREAL03__A                                             0x2C20016
#define  OFDM_CE_FR_TREAL03__W                                             11
#define  OFDM_CE_FR_TREAL03__M                                             0x7FF
#define  OFDM_CE_FR_TREAL03__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG03__A                                             0x2C20017
#define  OFDM_CE_FR_TIMAG03__W                                             11
#define  OFDM_CE_FR_TIMAG03__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG03__PRE                                           0x0

#define  OFDM_CE_FR_TREAL04__A                                             0x2C20018
#define  OFDM_CE_FR_TREAL04__W                                             11
#define  OFDM_CE_FR_TREAL04__M                                             0x7FF
#define  OFDM_CE_FR_TREAL04__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG04__A                                             0x2C20019
#define  OFDM_CE_FR_TIMAG04__W                                             11
#define  OFDM_CE_FR_TIMAG04__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG04__PRE                                           0x0

#define  OFDM_CE_FR_TREAL05__A                                             0x2C2001A
#define  OFDM_CE_FR_TREAL05__W                                             11
#define  OFDM_CE_FR_TREAL05__M                                             0x7FF
#define  OFDM_CE_FR_TREAL05__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG05__A                                             0x2C2001B
#define  OFDM_CE_FR_TIMAG05__W                                             11
#define  OFDM_CE_FR_TIMAG05__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG05__PRE                                           0x0

#define  OFDM_CE_FR_TREAL06__A                                             0x2C2001C
#define  OFDM_CE_FR_TREAL06__W                                             11
#define  OFDM_CE_FR_TREAL06__M                                             0x7FF
#define  OFDM_CE_FR_TREAL06__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG06__A                                             0x2C2001D
#define  OFDM_CE_FR_TIMAG06__W                                             11
#define  OFDM_CE_FR_TIMAG06__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG06__PRE                                           0x0

#define  OFDM_CE_FR_TREAL07__A                                             0x2C2001E
#define  OFDM_CE_FR_TREAL07__W                                             11
#define  OFDM_CE_FR_TREAL07__M                                             0x7FF
#define  OFDM_CE_FR_TREAL07__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG07__A                                             0x2C2001F
#define  OFDM_CE_FR_TIMAG07__W                                             11
#define  OFDM_CE_FR_TIMAG07__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG07__PRE                                           0x0

#define  OFDM_CE_FR_TREAL08__A                                             0x2C20020
#define  OFDM_CE_FR_TREAL08__W                                             11
#define  OFDM_CE_FR_TREAL08__M                                             0x7FF
#define  OFDM_CE_FR_TREAL08__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG08__A                                             0x2C20021
#define  OFDM_CE_FR_TIMAG08__W                                             11
#define  OFDM_CE_FR_TIMAG08__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG08__PRE                                           0x0

#define  OFDM_CE_FR_TREAL09__A                                             0x2C20022
#define  OFDM_CE_FR_TREAL09__W                                             11
#define  OFDM_CE_FR_TREAL09__M                                             0x7FF
#define  OFDM_CE_FR_TREAL09__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG09__A                                             0x2C20023
#define  OFDM_CE_FR_TIMAG09__W                                             11
#define  OFDM_CE_FR_TIMAG09__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG09__PRE                                           0x0

#define  OFDM_CE_FR_TREAL10__A                                             0x2C20024
#define  OFDM_CE_FR_TREAL10__W                                             11
#define  OFDM_CE_FR_TREAL10__M                                             0x7FF
#define  OFDM_CE_FR_TREAL10__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG10__A                                             0x2C20025
#define  OFDM_CE_FR_TIMAG10__W                                             11
#define  OFDM_CE_FR_TIMAG10__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG10__PRE                                           0x0

#define  OFDM_CE_FR_TREAL11__A                                             0x2C20026
#define  OFDM_CE_FR_TREAL11__W                                             11
#define  OFDM_CE_FR_TREAL11__M                                             0x7FF
#define  OFDM_CE_FR_TREAL11__PRE                                           0x52

#define  OFDM_CE_FR_TIMAG11__A                                             0x2C20027
#define  OFDM_CE_FR_TIMAG11__W                                             11
#define  OFDM_CE_FR_TIMAG11__M                                             0x7FF
#define  OFDM_CE_FR_TIMAG11__PRE                                           0x0

#define  OFDM_CE_FR_MID_TAP__A                                             0x2C20028
#define  OFDM_CE_FR_MID_TAP__W                                             11
#define  OFDM_CE_FR_MID_TAP__M                                             0x7FF
#define  OFDM_CE_FR_MID_TAP__PRE                                           0x51

#define  OFDM_CE_FR_SQS_G00__A                                             0x2C20029
#define  OFDM_CE_FR_SQS_G00__W                                             8
#define  OFDM_CE_FR_SQS_G00__M                                             0xFF
#define  OFDM_CE_FR_SQS_G00__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G01__A                                             0x2C2002A
#define  OFDM_CE_FR_SQS_G01__W                                             8
#define  OFDM_CE_FR_SQS_G01__M                                             0xFF
#define  OFDM_CE_FR_SQS_G01__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G02__A                                             0x2C2002B
#define  OFDM_CE_FR_SQS_G02__W                                             8
#define  OFDM_CE_FR_SQS_G02__M                                             0xFF
#define  OFDM_CE_FR_SQS_G02__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G03__A                                             0x2C2002C
#define  OFDM_CE_FR_SQS_G03__W                                             8
#define  OFDM_CE_FR_SQS_G03__M                                             0xFF
#define  OFDM_CE_FR_SQS_G03__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G04__A                                             0x2C2002D
#define  OFDM_CE_FR_SQS_G04__W                                             8
#define  OFDM_CE_FR_SQS_G04__M                                             0xFF
#define  OFDM_CE_FR_SQS_G04__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G05__A                                             0x2C2002E
#define  OFDM_CE_FR_SQS_G05__W                                             8
#define  OFDM_CE_FR_SQS_G05__M                                             0xFF
#define  OFDM_CE_FR_SQS_G05__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G06__A                                             0x2C2002F
#define  OFDM_CE_FR_SQS_G06__W                                             8
#define  OFDM_CE_FR_SQS_G06__M                                             0xFF
#define  OFDM_CE_FR_SQS_G06__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G07__A                                             0x2C20030
#define  OFDM_CE_FR_SQS_G07__W                                             8
#define  OFDM_CE_FR_SQS_G07__M                                             0xFF
#define  OFDM_CE_FR_SQS_G07__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G08__A                                             0x2C20031
#define  OFDM_CE_FR_SQS_G08__W                                             8
#define  OFDM_CE_FR_SQS_G08__M                                             0xFF
#define  OFDM_CE_FR_SQS_G08__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G09__A                                             0x2C20032
#define  OFDM_CE_FR_SQS_G09__W                                             8
#define  OFDM_CE_FR_SQS_G09__M                                             0xFF
#define  OFDM_CE_FR_SQS_G09__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G10__A                                             0x2C20033
#define  OFDM_CE_FR_SQS_G10__W                                             8
#define  OFDM_CE_FR_SQS_G10__M                                             0xFF
#define  OFDM_CE_FR_SQS_G10__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G11__A                                             0x2C20034
#define  OFDM_CE_FR_SQS_G11__W                                             8
#define  OFDM_CE_FR_SQS_G11__M                                             0xFF
#define  OFDM_CE_FR_SQS_G11__PRE                                           0xB

#define  OFDM_CE_FR_SQS_G12__A                                             0x2C20035
#define  OFDM_CE_FR_SQS_G12__W                                             8
#define  OFDM_CE_FR_SQS_G12__M                                             0xFF
#define  OFDM_CE_FR_SQS_G12__PRE                                           0x5

#define  OFDM_CE_FR_RIO_G00__A                                             0x2C20036
#define  OFDM_CE_FR_RIO_G00__W                                             9
#define  OFDM_CE_FR_RIO_G00__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G00__PRE                                           0x1FF

#define  OFDM_CE_FR_RIO_G01__A                                             0x2C20037
#define  OFDM_CE_FR_RIO_G01__W                                             9
#define  OFDM_CE_FR_RIO_G01__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G01__PRE                                           0x190

#define  OFDM_CE_FR_RIO_G02__A                                             0x2C20038
#define  OFDM_CE_FR_RIO_G02__W                                             9
#define  OFDM_CE_FR_RIO_G02__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G02__PRE                                           0x10B

#define  OFDM_CE_FR_RIO_G03__A                                             0x2C20039
#define  OFDM_CE_FR_RIO_G03__W                                             9
#define  OFDM_CE_FR_RIO_G03__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G03__PRE                                           0xC8

#define  OFDM_CE_FR_RIO_G04__A                                             0x2C2003A
#define  OFDM_CE_FR_RIO_G04__W                                             9
#define  OFDM_CE_FR_RIO_G04__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G04__PRE                                           0xA0

#define  OFDM_CE_FR_RIO_G05__A                                             0x2C2003B
#define  OFDM_CE_FR_RIO_G05__W                                             9
#define  OFDM_CE_FR_RIO_G05__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G05__PRE                                           0x85

#define  OFDM_CE_FR_RIO_G06__A                                             0x2C2003C
#define  OFDM_CE_FR_RIO_G06__W                                             9
#define  OFDM_CE_FR_RIO_G06__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G06__PRE                                           0x72

#define  OFDM_CE_FR_RIO_G07__A                                             0x2C2003D
#define  OFDM_CE_FR_RIO_G07__W                                             9
#define  OFDM_CE_FR_RIO_G07__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G07__PRE                                           0x64

#define  OFDM_CE_FR_RIO_G08__A                                             0x2C2003E
#define  OFDM_CE_FR_RIO_G08__W                                             9
#define  OFDM_CE_FR_RIO_G08__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G08__PRE                                           0x59

#define  OFDM_CE_FR_RIO_G09__A                                             0x2C2003F
#define  OFDM_CE_FR_RIO_G09__W                                             9
#define  OFDM_CE_FR_RIO_G09__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G09__PRE                                           0x50

#define  OFDM_CE_FR_RIO_G10__A                                             0x2C20040
#define  OFDM_CE_FR_RIO_G10__W                                             9
#define  OFDM_CE_FR_RIO_G10__M                                             0x1FF
#define  OFDM_CE_FR_RIO_G10__PRE                                           0x49
#define  OFDM_CE_FR_MODE__A                                                0x2C20041
#define  OFDM_CE_FR_MODE__W                                                9
#define  OFDM_CE_FR_MODE__M                                                0x1FF
#define  OFDM_CE_FR_MODE__PRE                                              0xDE

#define    OFDM_CE_FR_MODE_UPDATE_ENABLE__B                                0
#define    OFDM_CE_FR_MODE_UPDATE_ENABLE__W                                1
#define    OFDM_CE_FR_MODE_UPDATE_ENABLE__M                                0x1
#define    OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE                              0x0

#define    OFDM_CE_FR_MODE_ERROR_SHIFT__B                                  1
#define    OFDM_CE_FR_MODE_ERROR_SHIFT__W                                  1
#define    OFDM_CE_FR_MODE_ERROR_SHIFT__M                                  0x2
#define    OFDM_CE_FR_MODE_ERROR_SHIFT__PRE                                0x2

#define    OFDM_CE_FR_MODE_NEXP_UPDATE__B                                  2
#define    OFDM_CE_FR_MODE_NEXP_UPDATE__W                                  1
#define    OFDM_CE_FR_MODE_NEXP_UPDATE__M                                  0x4
#define    OFDM_CE_FR_MODE_NEXP_UPDATE__PRE                                0x4

#define    OFDM_CE_FR_MODE_MANUAL_SHIFT__B                                 3
#define    OFDM_CE_FR_MODE_MANUAL_SHIFT__W                                 1
#define    OFDM_CE_FR_MODE_MANUAL_SHIFT__M                                 0x8
#define    OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE                               0x8

#define    OFDM_CE_FR_MODE_SQUASH_MODE__B                                  4
#define    OFDM_CE_FR_MODE_SQUASH_MODE__W                                  1
#define    OFDM_CE_FR_MODE_SQUASH_MODE__M                                  0x10
#define    OFDM_CE_FR_MODE_SQUASH_MODE__PRE                                0x10

#define    OFDM_CE_FR_MODE_UPDATE_MODE__B                                  5
#define    OFDM_CE_FR_MODE_UPDATE_MODE__W                                  1
#define    OFDM_CE_FR_MODE_UPDATE_MODE__M                                  0x20
#define    OFDM_CE_FR_MODE_UPDATE_MODE__PRE                                0x0

#define    OFDM_CE_FR_MODE_MID_MODE__B                                     6
#define    OFDM_CE_FR_MODE_MID_MODE__W                                     1
#define    OFDM_CE_FR_MODE_MID_MODE__M                                     0x40
#define    OFDM_CE_FR_MODE_MID_MODE__PRE                                   0x40

#define    OFDM_CE_FR_MODE_NOISE_MODE__B                                   7
#define    OFDM_CE_FR_MODE_NOISE_MODE__W                                   1
#define    OFDM_CE_FR_MODE_NOISE_MODE__M                                   0x80
#define    OFDM_CE_FR_MODE_NOISE_MODE__PRE                                 0x80

#define    OFDM_CE_FR_MODE_NOTCH_MODE__B                                   8
#define    OFDM_CE_FR_MODE_NOTCH_MODE__W                                   1
#define    OFDM_CE_FR_MODE_NOTCH_MODE__M                                   0x100
#define    OFDM_CE_FR_MODE_NOTCH_MODE__PRE                                 0x0


#define  OFDM_CE_FR_SQS_TRH__A                                             0x2C20042
#define  OFDM_CE_FR_SQS_TRH__W                                             8
#define  OFDM_CE_FR_SQS_TRH__M                                             0xFF
#define  OFDM_CE_FR_SQS_TRH__PRE                                           0x80

#define  OFDM_CE_FR_RIO_GAIN__A                                            0x2C20043
#define  OFDM_CE_FR_RIO_GAIN__W                                            3
#define  OFDM_CE_FR_RIO_GAIN__M                                            0x7
#define  OFDM_CE_FR_RIO_GAIN__PRE                                          0x7
#define  OFDM_CE_FR_BYPASS__A                                              0x2C20044
#define  OFDM_CE_FR_BYPASS__W                                              10
#define  OFDM_CE_FR_BYPASS__M                                              0x3FF
#define  OFDM_CE_FR_BYPASS__PRE                                            0x13B

#define    OFDM_CE_FR_BYPASS_RUN_IN__B                                     0
#define    OFDM_CE_FR_BYPASS_RUN_IN__W                                     4
#define    OFDM_CE_FR_BYPASS_RUN_IN__M                                     0xF
#define    OFDM_CE_FR_BYPASS_RUN_IN__PRE                                   0xB

#define    OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B                                4
#define    OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W                                5
#define    OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M                                0x1F0
#define    OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE                              0x130

#define    OFDM_CE_FR_BYPASS_TOTAL__B                                      9
#define    OFDM_CE_FR_BYPASS_TOTAL__W                                      1
#define    OFDM_CE_FR_BYPASS_TOTAL__M                                      0x200
#define    OFDM_CE_FR_BYPASS_TOTAL__PRE                                    0x0


#define  OFDM_CE_FR_PM_SET__A                                              0x2C20045
#define  OFDM_CE_FR_PM_SET__W                                              4
#define  OFDM_CE_FR_PM_SET__M                                              0xF
#define  OFDM_CE_FR_PM_SET__PRE                                            0xD

#define  OFDM_CE_FR_ERR_SH__A                                              0x2C20046
#define  OFDM_CE_FR_ERR_SH__W                                              4
#define  OFDM_CE_FR_ERR_SH__M                                              0xF
#define  OFDM_CE_FR_ERR_SH__PRE                                            0x4

#define  OFDM_CE_FR_MAN_SH__A                                              0x2C20047
#define  OFDM_CE_FR_MAN_SH__W                                              4
#define  OFDM_CE_FR_MAN_SH__M                                              0xF
#define  OFDM_CE_FR_MAN_SH__PRE                                            0x7

#define  OFDM_CE_FR_TAP_SH__A                                              0x2C20048
#define  OFDM_CE_FR_TAP_SH__W                                              3
#define  OFDM_CE_FR_TAP_SH__M                                              0x7
#define  OFDM_CE_FR_TAP_SH__PRE                                            0x3

#define  OFDM_CE_FR_CLIP__A                                                0x2C20049
#define  OFDM_CE_FR_CLIP__W                                                9
#define  OFDM_CE_FR_CLIP__M                                                0x1FF
#define  OFDM_CE_FR_CLIP__PRE                                              0x49

#define  OFDM_CE_FR_LEAK_UPD__A                                            0x2C2004A
#define  OFDM_CE_FR_LEAK_UPD__W                                            3
#define  OFDM_CE_FR_LEAK_UPD__M                                            0x7
#define  OFDM_CE_FR_LEAK_UPD__PRE                                          0x0

#define  OFDM_CE_FR_LEAK_SH__A                                             0x2C2004B
#define  OFDM_CE_FR_LEAK_SH__W                                             3
#define  OFDM_CE_FR_LEAK_SH__M                                             0x7
#define  OFDM_CE_FR_LEAK_SH__PRE                                           0x1



#define  OFDM_CE_NE_RAM__A                                                 0x2C30000



#define  OFDM_CE_PB_RAM__A                                                 0x2C40000





#define  OFDM_CP_COMM_EXEC__A                                              0x2800000
#define  OFDM_CP_COMM_EXEC__W                                              3
#define  OFDM_CP_COMM_EXEC__M                                              0x7
#define  OFDM_CP_COMM_EXEC__PRE                                            0x0
#define    OFDM_CP_COMM_EXEC_STOP                                          0x0
#define    OFDM_CP_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_CP_COMM_EXEC_HOLD                                          0x2
#define    OFDM_CP_COMM_EXEC_STEP                                          0x3
#define    OFDM_CP_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_CP_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_CP_COMM_STATE__A                                             0x2800001
#define  OFDM_CP_COMM_STATE__W                                             16
#define  OFDM_CP_COMM_STATE__M                                             0xFFFF
#define  OFDM_CP_COMM_STATE__PRE                                           0x0
#define  OFDM_CP_COMM_MB__A                                                0x2800002
#define  OFDM_CP_COMM_MB__W                                                16
#define  OFDM_CP_COMM_MB__M                                                0xFFFF
#define  OFDM_CP_COMM_MB__PRE                                              0x0
#define  OFDM_CP_COMM_INT_REQ__A                                           0x2800004
#define  OFDM_CP_COMM_INT_REQ__W                                           16
#define  OFDM_CP_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_CP_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_CP_COMM_INT_REQ_TOP_REQ__B                                 1
#define    OFDM_CP_COMM_INT_REQ_TOP_REQ__W                                 1
#define    OFDM_CP_COMM_INT_REQ_TOP_REQ__M                                 0x2
#define    OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE                               0x0

#define  OFDM_CP_COMM_INT_STA__A                                           0x2800005
#define  OFDM_CP_COMM_INT_STA__W                                           16
#define  OFDM_CP_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_CP_COMM_INT_STA__PRE                                         0x0
#define  OFDM_CP_COMM_INT_MSK__A                                           0x2800006
#define  OFDM_CP_COMM_INT_MSK__W                                           16
#define  OFDM_CP_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_CP_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_CP_COMM_INT_STM__A                                           0x2800007
#define  OFDM_CP_COMM_INT_STM__W                                           16
#define  OFDM_CP_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_CP_COMM_INT_STM__PRE                                         0x0
#define    OFDM_CP_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_CP_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_CP_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_CP_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_CP_TOP_COMM_EXEC__A                                          0x2810000
#define  OFDM_CP_TOP_COMM_EXEC__W                                          3
#define  OFDM_CP_TOP_COMM_EXEC__M                                          0x7
#define  OFDM_CP_TOP_COMM_EXEC__PRE                                        0x0
#define    OFDM_CP_TOP_COMM_EXEC_STOP                                      0x0
#define    OFDM_CP_TOP_COMM_EXEC_ACTIVE                                    0x1
#define    OFDM_CP_TOP_COMM_EXEC_HOLD                                      0x2
#define    OFDM_CP_TOP_COMM_EXEC_STEP                                      0x3

#define  OFDM_CP_TOP_COMM_MB__A                                            0x2810002
#define  OFDM_CP_TOP_COMM_MB__W                                            3
#define  OFDM_CP_TOP_COMM_MB__M                                            0x7
#define  OFDM_CP_TOP_COMM_MB__PRE                                          0x0
#define    OFDM_CP_TOP_COMM_MB_CTL__B                                      0
#define    OFDM_CP_TOP_COMM_MB_CTL__W                                      1
#define    OFDM_CP_TOP_COMM_MB_CTL__M                                      0x1
#define    OFDM_CP_TOP_COMM_MB_CTL__PRE                                    0x0
#define      OFDM_CP_TOP_COMM_MB_CTL_OFF                                   0x0
#define      OFDM_CP_TOP_COMM_MB_CTL_ON                                    0x1
#define    OFDM_CP_TOP_COMM_MB_OBS__B                                      1
#define    OFDM_CP_TOP_COMM_MB_OBS__W                                      1
#define    OFDM_CP_TOP_COMM_MB_OBS__M                                      0x2
#define    OFDM_CP_TOP_COMM_MB_OBS__PRE                                    0x0
#define      OFDM_CP_TOP_COMM_MB_OBS_OFF                                   0x0
#define      OFDM_CP_TOP_COMM_MB_OBS_ON                                    0x2
#define    OFDM_CP_TOP_COMM_MB_OBS_MUX__B                                  2
#define    OFDM_CP_TOP_COMM_MB_OBS_MUX__W                                  1
#define    OFDM_CP_TOP_COMM_MB_OBS_MUX__M                                  0x4
#define    OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE                                0x0
#define      OFDM_CP_TOP_COMM_MB_OBS_MUX_CE                                0x0
#define      OFDM_CP_TOP_COMM_MB_OBS_MUX_DL                                0x4

#define  OFDM_CP_TOP_COMM_INT_REQ__A                                       0x2810004
#define  OFDM_CP_TOP_COMM_INT_REQ__W                                       1
#define  OFDM_CP_TOP_COMM_INT_REQ__M                                       0x1
#define  OFDM_CP_TOP_COMM_INT_REQ__PRE                                     0x0
#define  OFDM_CP_TOP_COMM_INT_STA__A                                       0x2810005
#define  OFDM_CP_TOP_COMM_INT_STA__W                                       1
#define  OFDM_CP_TOP_COMM_INT_STA__M                                       0x1
#define  OFDM_CP_TOP_COMM_INT_STA__PRE                                     0x0
#define    OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B                            0
#define    OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W                            1
#define    OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M                            0x1
#define    OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE                          0x0

#define  OFDM_CP_TOP_COMM_INT_MSK__A                                       0x2810006
#define  OFDM_CP_TOP_COMM_INT_MSK__W                                       1
#define  OFDM_CP_TOP_COMM_INT_MSK__M                                       0x1
#define  OFDM_CP_TOP_COMM_INT_MSK__PRE                                     0x0
#define    OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B                            0
#define    OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W                            1
#define    OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M                            0x1
#define    OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE                          0x0

#define  OFDM_CP_TOP_COMM_INT_STM__A                                       0x2810007
#define  OFDM_CP_TOP_COMM_INT_STM__W                                       1
#define  OFDM_CP_TOP_COMM_INT_STM__M                                       0x1
#define  OFDM_CP_TOP_COMM_INT_STM__PRE                                     0x0
#define    OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B                            0
#define    OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W                            1
#define    OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M                            0x1
#define    OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE                          0x0


#define  OFDM_CP_TOP_MODE_2K__A                                            0x2810010
#define  OFDM_CP_TOP_MODE_2K__W                                            1
#define  OFDM_CP_TOP_MODE_2K__M                                            0x1
#define  OFDM_CP_TOP_MODE_2K__PRE                                          0x0

#define  OFDM_CP_TOP_INTERVAL__A                                           0x2810011
#define  OFDM_CP_TOP_INTERVAL__W                                           4
#define  OFDM_CP_TOP_INTERVAL__M                                           0xF
#define  OFDM_CP_TOP_INTERVAL__PRE                                         0x5
#define  OFDM_CP_TOP_DETECT_ENA__A                                         0x2810012
#define  OFDM_CP_TOP_DETECT_ENA__W                                         2
#define  OFDM_CP_TOP_DETECT_ENA__M                                         0x3
#define  OFDM_CP_TOP_DETECT_ENA__PRE                                       0x0

#define    OFDM_CP_TOP_DETECT_ENA_SCATTERED__B                             0
#define    OFDM_CP_TOP_DETECT_ENA_SCATTERED__W                             1
#define    OFDM_CP_TOP_DETECT_ENA_SCATTERED__M                             0x1
#define    OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE                           0x0

#define    OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B                            1
#define    OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W                            1
#define    OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M                            0x2
#define    OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE                          0x0

#define  OFDM_CP_TOP_FIX__A                                                0x2810013
#define  OFDM_CP_TOP_FIX__W                                                4
#define  OFDM_CP_TOP_FIX__M                                                0xF
#define  OFDM_CP_TOP_FIX__PRE                                              0xF

#define    OFDM_CP_TOP_FIX_RT_SPD_MIX__B                                   0
#define    OFDM_CP_TOP_FIX_RT_SPD_MIX__W                                   1
#define    OFDM_CP_TOP_FIX_RT_SPD_MIX__M                                   0x1
#define    OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE                                 0x1
#define      OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE                            0x0
#define      OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE                             0x1

#define    OFDM_CP_TOP_FIX_RT_SPD_ADD__B                                   1
#define    OFDM_CP_TOP_FIX_RT_SPD_ADD__W                                   1
#define    OFDM_CP_TOP_FIX_RT_SPD_ADD__M                                   0x2
#define    OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE                                 0x2
#define      OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE                            0x0
#define      OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE                             0x2

#define    OFDM_CP_TOP_FIX_RT_SPD_CLP__B                                   2
#define    OFDM_CP_TOP_FIX_RT_SPD_CLP__W                                   1
#define    OFDM_CP_TOP_FIX_RT_SPD_CLP__M                                   0x4
#define    OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE                                 0x4
#define      OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE                            0x0
#define      OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE                             0x4

#define    OFDM_CP_TOP_FIX_RT_SPD_SSH__B                                   3
#define    OFDM_CP_TOP_FIX_RT_SPD_SSH__W                                   1
#define    OFDM_CP_TOP_FIX_RT_SPD_SSH__M                                   0x8
#define    OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE                                 0x8
#define      OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE                            0x0
#define      OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE                             0x8

#define  OFDM_CP_TOP_BR_SMB_NR__A                                          0x2810021
#define  OFDM_CP_TOP_BR_SMB_NR__W                                          4
#define  OFDM_CP_TOP_BR_SMB_NR__M                                          0xF
#define  OFDM_CP_TOP_BR_SMB_NR__PRE                                        0x0

#define    OFDM_CP_TOP_BR_SMB_NR_SMB__B                                    0
#define    OFDM_CP_TOP_BR_SMB_NR_SMB__W                                    2
#define    OFDM_CP_TOP_BR_SMB_NR_SMB__M                                    0x3
#define    OFDM_CP_TOP_BR_SMB_NR_SMB__PRE                                  0x0

#define    OFDM_CP_TOP_BR_SMB_NR_VAL__B                                    2
#define    OFDM_CP_TOP_BR_SMB_NR_VAL__W                                    1
#define    OFDM_CP_TOP_BR_SMB_NR_VAL__M                                    0x4
#define    OFDM_CP_TOP_BR_SMB_NR_VAL__PRE                                  0x0

#define    OFDM_CP_TOP_BR_SMB_NR_OFFSET__B                                 3
#define    OFDM_CP_TOP_BR_SMB_NR_OFFSET__W                                 1
#define    OFDM_CP_TOP_BR_SMB_NR_OFFSET__M                                 0x8
#define    OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE                               0x0


#define  OFDM_CP_TOP_BR_CP_SMB_NR__A                                       0x2810022
#define  OFDM_CP_TOP_BR_CP_SMB_NR__W                                       2
#define  OFDM_CP_TOP_BR_CP_SMB_NR__M                                       0x3
#define  OFDM_CP_TOP_BR_CP_SMB_NR__PRE                                     0x0

#define  OFDM_CP_TOP_BR_SPL_OFFSET__A                                      0x2810023
#define  OFDM_CP_TOP_BR_SPL_OFFSET__W                                      4
#define  OFDM_CP_TOP_BR_SPL_OFFSET__M                                      0xF
#define  OFDM_CP_TOP_BR_SPL_OFFSET__PRE                                    0x8

#define  OFDM_CP_TOP_BR_STR_DEL__A                                         0x2810024
#define  OFDM_CP_TOP_BR_STR_DEL__W                                         10
#define  OFDM_CP_TOP_BR_STR_DEL__M                                         0x3FF
#define  OFDM_CP_TOP_BR_STR_DEL__PRE                                       0xA

#define  OFDM_CP_TOP_BR_EXP_ADJ__A                                         0x2810025
#define  OFDM_CP_TOP_BR_EXP_ADJ__W                                         5
#define  OFDM_CP_TOP_BR_EXP_ADJ__M                                         0x1F
#define  OFDM_CP_TOP_BR_EXP_ADJ__PRE                                       0x10

#define  OFDM_CP_TOP_RT_ANG_INC0__A                                        0x2810030
#define  OFDM_CP_TOP_RT_ANG_INC0__W                                        16
#define  OFDM_CP_TOP_RT_ANG_INC0__M                                        0xFFFF
#define  OFDM_CP_TOP_RT_ANG_INC0__PRE                                      0x0

#define  OFDM_CP_TOP_RT_ANG_INC1__A                                        0x2810031
#define  OFDM_CP_TOP_RT_ANG_INC1__W                                        8
#define  OFDM_CP_TOP_RT_ANG_INC1__M                                        0xFF
#define  OFDM_CP_TOP_RT_ANG_INC1__PRE                                      0x0

#define  OFDM_CP_TOP_RT_SPD_EXP_MARG__A                                    0x2810032
#define  OFDM_CP_TOP_RT_SPD_EXP_MARG__W                                    5
#define  OFDM_CP_TOP_RT_SPD_EXP_MARG__M                                    0x1F
#define  OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE                                  0x5

#define  OFDM_CP_TOP_RT_DETECT_TRH__A                                      0x2810033
#define  OFDM_CP_TOP_RT_DETECT_TRH__W                                      2
#define  OFDM_CP_TOP_RT_DETECT_TRH__M                                      0x3
#define  OFDM_CP_TOP_RT_DETECT_TRH__PRE                                    0x3

#define  OFDM_CP_TOP_RT_SPD_RELIABLE__A                                    0x2810034
#define  OFDM_CP_TOP_RT_SPD_RELIABLE__W                                    3
#define  OFDM_CP_TOP_RT_SPD_RELIABLE__M                                    0x7
#define  OFDM_CP_TOP_RT_SPD_RELIABLE__PRE                                  0x0

#define  OFDM_CP_TOP_RT_SPD_DIRECTION__A                                   0x2810035
#define  OFDM_CP_TOP_RT_SPD_DIRECTION__W                                   1
#define  OFDM_CP_TOP_RT_SPD_DIRECTION__M                                   0x1
#define  OFDM_CP_TOP_RT_SPD_DIRECTION__PRE                                 0x0

#define  OFDM_CP_TOP_RT_SPD_MOD__A                                         0x2810036
#define  OFDM_CP_TOP_RT_SPD_MOD__W                                         2
#define  OFDM_CP_TOP_RT_SPD_MOD__M                                         0x3
#define  OFDM_CP_TOP_RT_SPD_MOD__PRE                                       0x0

#define  OFDM_CP_TOP_RT_SPD_SMB__A                                         0x2810037
#define  OFDM_CP_TOP_RT_SPD_SMB__W                                         2
#define  OFDM_CP_TOP_RT_SPD_SMB__M                                         0x3
#define  OFDM_CP_TOP_RT_SPD_SMB__PRE                                       0x0
#define  OFDM_CP_TOP_RT_CPD_MODE__A                                        0x2810038
#define  OFDM_CP_TOP_RT_CPD_MODE__W                                        3
#define  OFDM_CP_TOP_RT_CPD_MODE__M                                        0x7
#define  OFDM_CP_TOP_RT_CPD_MODE__PRE                                      0x0

#define    OFDM_CP_TOP_RT_CPD_MODE_MOD3__B                                 0
#define    OFDM_CP_TOP_RT_CPD_MODE_MOD3__W                                 2
#define    OFDM_CP_TOP_RT_CPD_MODE_MOD3__M                                 0x3
#define    OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE                               0x0

#define    OFDM_CP_TOP_RT_CPD_MODE_ADD__B                                  2
#define    OFDM_CP_TOP_RT_CPD_MODE_ADD__W                                  1
#define    OFDM_CP_TOP_RT_CPD_MODE_ADD__M                                  0x4
#define    OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE                                0x0


#define  OFDM_CP_TOP_RT_CPD_RELIABLE__A                                    0x2810039
#define  OFDM_CP_TOP_RT_CPD_RELIABLE__W                                    3
#define  OFDM_CP_TOP_RT_CPD_RELIABLE__M                                    0x7
#define  OFDM_CP_TOP_RT_CPD_RELIABLE__PRE                                  0x0

#define  OFDM_CP_TOP_RT_CPD_BIN__A                                         0x281003A
#define  OFDM_CP_TOP_RT_CPD_BIN__W                                         5
#define  OFDM_CP_TOP_RT_CPD_BIN__M                                         0x1F
#define  OFDM_CP_TOP_RT_CPD_BIN__PRE                                       0x0

#define  OFDM_CP_TOP_RT_CPD_MAX__A                                         0x281003B
#define  OFDM_CP_TOP_RT_CPD_MAX__W                                         4
#define  OFDM_CP_TOP_RT_CPD_MAX__M                                         0xF
#define  OFDM_CP_TOP_RT_CPD_MAX__PRE                                       0x0
#define  OFDM_CP_TOP_RT_SUPR_VAL__A                                        0x281003C
#define  OFDM_CP_TOP_RT_SUPR_VAL__W                                        2
#define  OFDM_CP_TOP_RT_SUPR_VAL__M                                        0x3
#define  OFDM_CP_TOP_RT_SUPR_VAL__PRE                                      0x0

#define    OFDM_CP_TOP_RT_SUPR_VAL_CE__B                                   0
#define    OFDM_CP_TOP_RT_SUPR_VAL_CE__W                                   1
#define    OFDM_CP_TOP_RT_SUPR_VAL_CE__M                                   0x1
#define    OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE                                 0x0

#define    OFDM_CP_TOP_RT_SUPR_VAL_DL__B                                   1
#define    OFDM_CP_TOP_RT_SUPR_VAL_DL__W                                   1
#define    OFDM_CP_TOP_RT_SUPR_VAL_DL__M                                   0x2
#define    OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE                                 0x0


#define  OFDM_CP_TOP_RT_EXP_AVE__A                                         0x281003D
#define  OFDM_CP_TOP_RT_EXP_AVE__W                                         5
#define  OFDM_CP_TOP_RT_EXP_AVE__M                                         0x1F
#define  OFDM_CP_TOP_RT_EXP_AVE__PRE                                       0x0

#define  OFDM_CP_TOP_RT_CPD_EXP_MARG__A                                    0x281003E
#define  OFDM_CP_TOP_RT_CPD_EXP_MARG__W                                    5
#define  OFDM_CP_TOP_RT_CPD_EXP_MARG__M                                    0x1F
#define  OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE                                  0x3

#define  OFDM_CP_TOP_AC_NEXP_OFFS__A                                       0x2810040
#define  OFDM_CP_TOP_AC_NEXP_OFFS__W                                       8
#define  OFDM_CP_TOP_AC_NEXP_OFFS__M                                       0xFF
#define  OFDM_CP_TOP_AC_NEXP_OFFS__PRE                                     0x0

#define  OFDM_CP_TOP_AC_AVER_POW__A                                        0x2810041
#define  OFDM_CP_TOP_AC_AVER_POW__W                                        8
#define  OFDM_CP_TOP_AC_AVER_POW__M                                        0xFF
#define  OFDM_CP_TOP_AC_AVER_POW__PRE                                      0x5F

#define  OFDM_CP_TOP_AC_MAX_POW__A                                         0x2810042
#define  OFDM_CP_TOP_AC_MAX_POW__W                                         8
#define  OFDM_CP_TOP_AC_MAX_POW__M                                         0xFF
#define  OFDM_CP_TOP_AC_MAX_POW__PRE                                       0x7A

#define  OFDM_CP_TOP_AC_WEIGHT_MAN__A                                      0x2810043
#define  OFDM_CP_TOP_AC_WEIGHT_MAN__W                                      6
#define  OFDM_CP_TOP_AC_WEIGHT_MAN__M                                      0x3F
#define  OFDM_CP_TOP_AC_WEIGHT_MAN__PRE                                    0x31

#define  OFDM_CP_TOP_AC_WEIGHT_EXP__A                                      0x2810044
#define  OFDM_CP_TOP_AC_WEIGHT_EXP__W                                      5
#define  OFDM_CP_TOP_AC_WEIGHT_EXP__M                                      0x1F
#define  OFDM_CP_TOP_AC_WEIGHT_EXP__PRE                                    0x10

#define  OFDM_CP_TOP_AC_GAIN_MAN__A                                        0x2810045
#define  OFDM_CP_TOP_AC_GAIN_MAN__W                                        16
#define  OFDM_CP_TOP_AC_GAIN_MAN__M                                        0xFFFF
#define  OFDM_CP_TOP_AC_GAIN_MAN__PRE                                      0x0

#define  OFDM_CP_TOP_AC_GAIN_EXP__A                                        0x2810046
#define  OFDM_CP_TOP_AC_GAIN_EXP__W                                        5
#define  OFDM_CP_TOP_AC_GAIN_EXP__M                                        0x1F
#define  OFDM_CP_TOP_AC_GAIN_EXP__PRE                                      0x0

#define  OFDM_CP_TOP_AC_AMP_MODE__A                                        0x2810047
#define  OFDM_CP_TOP_AC_AMP_MODE__W                                        2
#define  OFDM_CP_TOP_AC_AMP_MODE__M                                        0x3
#define  OFDM_CP_TOP_AC_AMP_MODE__PRE                                      0x2
#define    OFDM_CP_TOP_AC_AMP_MODE_NEW                                     0x0
#define    OFDM_CP_TOP_AC_AMP_MODE_OLD                                     0x1
#define    OFDM_CP_TOP_AC_AMP_MODE_FIXED                                   0x2

#define  OFDM_CP_TOP_AC_AMP_FIX__A                                         0x2810048
#define  OFDM_CP_TOP_AC_AMP_FIX__W                                         14
#define  OFDM_CP_TOP_AC_AMP_FIX__M                                         0x3FFF
#define  OFDM_CP_TOP_AC_AMP_FIX__PRE                                       0x0

#define    OFDM_CP_TOP_AC_AMP_FIX_MAN__B                                   0
#define    OFDM_CP_TOP_AC_AMP_FIX_MAN__W                                   10
#define    OFDM_CP_TOP_AC_AMP_FIX_MAN__M                                   0x3FF
#define    OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE                                 0x0

#define    OFDM_CP_TOP_AC_AMP_FIX_EXP__B                                   10
#define    OFDM_CP_TOP_AC_AMP_FIX_EXP__W                                   4
#define    OFDM_CP_TOP_AC_AMP_FIX_EXP__M                                   0x3C00
#define    OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE                                 0x0

#define  OFDM_CP_TOP_AC_AMP_READ__A                                        0x2810049
#define  OFDM_CP_TOP_AC_AMP_READ__W                                        14
#define  OFDM_CP_TOP_AC_AMP_READ__M                                        0x3FFF
#define  OFDM_CP_TOP_AC_AMP_READ__PRE                                      0x0

#define    OFDM_CP_TOP_AC_AMP_READ_MAN__B                                  0
#define    OFDM_CP_TOP_AC_AMP_READ_MAN__W                                  10
#define    OFDM_CP_TOP_AC_AMP_READ_MAN__M                                  0x3FF
#define    OFDM_CP_TOP_AC_AMP_READ_MAN__PRE                                0x0

#define    OFDM_CP_TOP_AC_AMP_READ_EXP__B                                  10
#define    OFDM_CP_TOP_AC_AMP_READ_EXP__W                                  4
#define    OFDM_CP_TOP_AC_AMP_READ_EXP__M                                  0x3C00
#define    OFDM_CP_TOP_AC_AMP_READ_EXP__PRE                                0x0


#define  OFDM_CP_TOP_AC_ANG_MODE__A                                        0x281004A
#define  OFDM_CP_TOP_AC_ANG_MODE__W                                        2
#define  OFDM_CP_TOP_AC_ANG_MODE__M                                        0x3
#define  OFDM_CP_TOP_AC_ANG_MODE__PRE                                      0x3
#define    OFDM_CP_TOP_AC_ANG_MODE_NEW                                     0x0
#define    OFDM_CP_TOP_AC_ANG_MODE_OLD                                     0x1
#define    OFDM_CP_TOP_AC_ANG_MODE_NO_INT                                  0x2
#define    OFDM_CP_TOP_AC_ANG_MODE_OFFSET                                  0x3


#define  OFDM_CP_TOP_AC_ANG_OFFS__A                                        0x281004B
#define  OFDM_CP_TOP_AC_ANG_OFFS__W                                        16
#define  OFDM_CP_TOP_AC_ANG_OFFS__M                                        0xFFFF
#define  OFDM_CP_TOP_AC_ANG_OFFS__PRE                                      0x0

#define  OFDM_CP_TOP_AC_ANG_READ__A                                        0x281004C
#define  OFDM_CP_TOP_AC_ANG_READ__W                                        16
#define  OFDM_CP_TOP_AC_ANG_READ__M                                        0xFFFF
#define  OFDM_CP_TOP_AC_ANG_READ__PRE                                      0x0

#define  OFDM_CP_TOP_AC_ACCU_REAL0__A                                      0x2810060
#define  OFDM_CP_TOP_AC_ACCU_REAL0__W                                      8
#define  OFDM_CP_TOP_AC_ACCU_REAL0__M                                      0xFF
#define  OFDM_CP_TOP_AC_ACCU_REAL0__PRE                                    0x0

#define  OFDM_CP_TOP_AC_ACCU_IMAG0__A                                      0x2810061
#define  OFDM_CP_TOP_AC_ACCU_IMAG0__W                                      8
#define  OFDM_CP_TOP_AC_ACCU_IMAG0__M                                      0xFF
#define  OFDM_CP_TOP_AC_ACCU_IMAG0__PRE                                    0x0

#define  OFDM_CP_TOP_AC_ACCU_REAL1__A                                      0x2810062
#define  OFDM_CP_TOP_AC_ACCU_REAL1__W                                      8
#define  OFDM_CP_TOP_AC_ACCU_REAL1__M                                      0xFF
#define  OFDM_CP_TOP_AC_ACCU_REAL1__PRE                                    0x0

#define  OFDM_CP_TOP_AC_ACCU_IMAG1__A                                      0x2810063
#define  OFDM_CP_TOP_AC_ACCU_IMAG1__W                                      8
#define  OFDM_CP_TOP_AC_ACCU_IMAG1__M                                      0xFF
#define  OFDM_CP_TOP_AC_ACCU_IMAG1__PRE                                    0x0

#define  OFDM_CP_TOP_DL_MB_WR_ADDR__A                                      0x2810050
#define  OFDM_CP_TOP_DL_MB_WR_ADDR__W                                      15
#define  OFDM_CP_TOP_DL_MB_WR_ADDR__M                                      0x7FFF
#define  OFDM_CP_TOP_DL_MB_WR_ADDR__PRE                                    0x0
#define  OFDM_CP_TOP_DL_MB_WR_CTR__A                                       0x2810051
#define  OFDM_CP_TOP_DL_MB_WR_CTR__W                                       5
#define  OFDM_CP_TOP_DL_MB_WR_CTR__M                                       0x1F
#define  OFDM_CP_TOP_DL_MB_WR_CTR__PRE                                     0x0

#define    OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B                                2
#define    OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W                                3
#define    OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M                                0x1C
#define    OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE                              0x0

#define    OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B                                 1
#define    OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W                                 1
#define    OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M                                 0x2
#define    OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE                               0x0

#define    OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B                                 0
#define    OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W                                 1
#define    OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M                                 0x1
#define    OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE                               0x0


#define  OFDM_CP_TOP_DL_MB_RD_ADDR__A                                      0x2810052
#define  OFDM_CP_TOP_DL_MB_RD_ADDR__W                                      15
#define  OFDM_CP_TOP_DL_MB_RD_ADDR__M                                      0x7FFF
#define  OFDM_CP_TOP_DL_MB_RD_ADDR__PRE                                    0x0
#define  OFDM_CP_TOP_DL_MB_RD_CTR__A                                       0x2810053
#define  OFDM_CP_TOP_DL_MB_RD_CTR__W                                       11
#define  OFDM_CP_TOP_DL_MB_RD_CTR__M                                       0x7FF
#define  OFDM_CP_TOP_DL_MB_RD_CTR__PRE                                     0x0

#define    OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B                                10
#define    OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W                                1
#define    OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M                                0x400
#define    OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE                              0x0

#define    OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B                              8
#define    OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W                              2
#define    OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M                              0x300
#define    OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE                            0x0

#define    OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B                               5
#define    OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W                               3
#define    OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M                               0xE0
#define    OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE                             0x0

#define    OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B                                2
#define    OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W                                3
#define    OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M                                0x1C
#define    OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE                              0x0

#define    OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B                                 1
#define    OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W                                 1
#define    OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M                                 0x2
#define    OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE                               0x0

#define    OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B                                 0
#define    OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W                                 1
#define    OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M                                 0x1
#define    OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE                               0x0



#define  OFDM_CP_BR_BUF_CPL_RAM__A                                         0x2820000



#define  OFDM_CP_BR_BUF_DAT_RAM__A                                         0x2830000



#define  OFDM_CP_DL_0_RAM__A                                               0x2840000



#define  OFDM_CP_DL_1_RAM__A                                               0x2850000



#define  OFDM_CP_DL_2_RAM__A                                               0x2860000





#define  OFDM_EC_COMM_EXEC__A                                              0x3400000
#define  OFDM_EC_COMM_EXEC__W                                              3
#define  OFDM_EC_COMM_EXEC__M                                              0x7
#define  OFDM_EC_COMM_EXEC__PRE                                            0x0
#define    OFDM_EC_COMM_EXEC_STOP                                          0x0
#define    OFDM_EC_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_EC_COMM_EXEC_HOLD                                          0x2
#define    OFDM_EC_COMM_EXEC_STEP                                          0x3
#define    OFDM_EC_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_EC_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_EC_COMM_STATE__A                                             0x3400001
#define  OFDM_EC_COMM_STATE__W                                             16
#define  OFDM_EC_COMM_STATE__M                                             0xFFFF
#define  OFDM_EC_COMM_STATE__PRE                                           0x0
#define  OFDM_EC_COMM_MB__A                                                0x3400002
#define  OFDM_EC_COMM_MB__W                                                16
#define  OFDM_EC_COMM_MB__M                                                0xFFFF
#define  OFDM_EC_COMM_MB__PRE                                              0x0
#define  OFDM_EC_COMM_INT_REQ__A                                           0x3400004
#define  OFDM_EC_COMM_INT_REQ__W                                           16
#define  OFDM_EC_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_EC_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_EC_COMM_INT_REQ_VD_REQ__B                                  4
#define    OFDM_EC_COMM_INT_REQ_VD_REQ__W                                  1
#define    OFDM_EC_COMM_INT_REQ_VD_REQ__M                                  0x10
#define    OFDM_EC_COMM_INT_REQ_VD_REQ__PRE                                0x0
#define    OFDM_EC_COMM_INT_REQ_SY_REQ__B                                  5
#define    OFDM_EC_COMM_INT_REQ_SY_REQ__W                                  1
#define    OFDM_EC_COMM_INT_REQ_SY_REQ__M                                  0x20
#define    OFDM_EC_COMM_INT_REQ_SY_REQ__PRE                                0x0

#define  OFDM_EC_COMM_INT_STA__A                                           0x3400005
#define  OFDM_EC_COMM_INT_STA__W                                           16
#define  OFDM_EC_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_EC_COMM_INT_STA__PRE                                         0x0
#define  OFDM_EC_COMM_INT_MSK__A                                           0x3400006
#define  OFDM_EC_COMM_INT_MSK__W                                           16
#define  OFDM_EC_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_EC_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_EC_COMM_INT_STM__A                                           0x3400007
#define  OFDM_EC_COMM_INT_STM__W                                           16
#define  OFDM_EC_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_EC_COMM_INT_STM__PRE                                         0x0
#define    OFDM_EC_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_EC_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_EC_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_EC_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_EC_SB_COMM_EXEC__A                                           0x3410000
#define  OFDM_EC_SB_COMM_EXEC__W                                           3
#define  OFDM_EC_SB_COMM_EXEC__M                                           0x7
#define  OFDM_EC_SB_COMM_EXEC__PRE                                         0x0
#define    OFDM_EC_SB_COMM_EXEC_STOP                                       0x0
#define    OFDM_EC_SB_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_EC_SB_COMM_EXEC_HOLD                                       0x2
#define    OFDM_EC_SB_COMM_EXEC_STEP                                       0x3

#define  OFDM_EC_SB_COMM_STATE__A                                          0x3410001
#define  OFDM_EC_SB_COMM_STATE__W                                          4
#define  OFDM_EC_SB_COMM_STATE__M                                          0xF
#define  OFDM_EC_SB_COMM_STATE__PRE                                        0x0
#define  OFDM_EC_SB_COMM_MB__A                                             0x3410002
#define  OFDM_EC_SB_COMM_MB__W                                             2
#define  OFDM_EC_SB_COMM_MB__M                                             0x3
#define  OFDM_EC_SB_COMM_MB__PRE                                           0x0
#define    OFDM_EC_SB_COMM_MB_CTL__B                                       0
#define    OFDM_EC_SB_COMM_MB_CTL__W                                       1
#define    OFDM_EC_SB_COMM_MB_CTL__M                                       0x1
#define    OFDM_EC_SB_COMM_MB_CTL__PRE                                     0x0
#define      OFDM_EC_SB_COMM_MB_CTL_OFF                                    0x0
#define      OFDM_EC_SB_COMM_MB_CTL_ON                                     0x1
#define    OFDM_EC_SB_COMM_MB_OBS__B                                       1
#define    OFDM_EC_SB_COMM_MB_OBS__W                                       1
#define    OFDM_EC_SB_COMM_MB_OBS__M                                       0x2
#define    OFDM_EC_SB_COMM_MB_OBS__PRE                                     0x0
#define      OFDM_EC_SB_COMM_MB_OBS_OFF                                    0x0
#define      OFDM_EC_SB_COMM_MB_OBS_ON                                     0x2


#define  OFDM_EC_SB_TR_MODE__A                                             0x3410010
#define  OFDM_EC_SB_TR_MODE__W                                             1
#define  OFDM_EC_SB_TR_MODE__M                                             0x1
#define  OFDM_EC_SB_TR_MODE__PRE                                           0x0
#define    OFDM_EC_SB_TR_MODE_8K                                           0x0
#define    OFDM_EC_SB_TR_MODE_2K                                           0x1


#define  OFDM_EC_SB_CONST__A                                               0x3410011
#define  OFDM_EC_SB_CONST__W                                               2
#define  OFDM_EC_SB_CONST__M                                               0x3
#define  OFDM_EC_SB_CONST__PRE                                             0x2
#define    OFDM_EC_SB_CONST_QPSK                                           0x0
#define    OFDM_EC_SB_CONST_16QAM                                          0x1
#define    OFDM_EC_SB_CONST_64QAM                                          0x2


#define  OFDM_EC_SB_ALPHA__A                                               0x3410012
#define  OFDM_EC_SB_ALPHA__W                                               3
#define  OFDM_EC_SB_ALPHA__M                                               0x7
#define  OFDM_EC_SB_ALPHA__PRE                                             0x0
#define    OFDM_EC_SB_ALPHA_NH                                             0x0
#define    OFDM_EC_SB_ALPHA_H1                                             0x1
#define    OFDM_EC_SB_ALPHA_H2                                             0x2
#define    OFDM_EC_SB_ALPHA_H4                                             0x3


#define  OFDM_EC_SB_PRIOR__A                                               0x3410013
#define  OFDM_EC_SB_PRIOR__W                                               1
#define  OFDM_EC_SB_PRIOR__M                                               0x1
#define  OFDM_EC_SB_PRIOR__PRE                                             0x0
#define    OFDM_EC_SB_PRIOR_HI                                             0x0
#define    OFDM_EC_SB_PRIOR_LO                                             0x1


#define  OFDM_EC_SB_CSI_HI__A                                              0x3410014
#define  OFDM_EC_SB_CSI_HI__W                                              5
#define  OFDM_EC_SB_CSI_HI__M                                              0x1F
#define  OFDM_EC_SB_CSI_HI__PRE                                            0x18
#define    OFDM_EC_SB_CSI_HI_MAX                                           0x1F
#define    OFDM_EC_SB_CSI_HI_MIN                                           0x0
#define    OFDM_EC_SB_CSI_HI_TAG                                           0x0


#define  OFDM_EC_SB_CSI_LO__A                                              0x3410015
#define  OFDM_EC_SB_CSI_LO__W                                              5
#define  OFDM_EC_SB_CSI_LO__M                                              0x1F
#define  OFDM_EC_SB_CSI_LO__PRE                                            0xC
#define    OFDM_EC_SB_CSI_LO_MAX                                           0x1F
#define    OFDM_EC_SB_CSI_LO_MIN                                           0x0
#define    OFDM_EC_SB_CSI_LO_TAG                                           0x0


#define  OFDM_EC_SB_SMB_TGL__A                                             0x3410016
#define  OFDM_EC_SB_SMB_TGL__W                                             1
#define  OFDM_EC_SB_SMB_TGL__M                                             0x1
#define  OFDM_EC_SB_SMB_TGL__PRE                                           0x1
#define    OFDM_EC_SB_SMB_TGL_OFF                                          0x0
#define    OFDM_EC_SB_SMB_TGL_ON                                           0x1


#define  OFDM_EC_SB_SNR_HI__A                                              0x3410017
#define  OFDM_EC_SB_SNR_HI__W                                              7
#define  OFDM_EC_SB_SNR_HI__M                                              0x7F
#define  OFDM_EC_SB_SNR_HI__PRE                                            0x7F
#define    OFDM_EC_SB_SNR_HI_MAX                                           0x7F
#define    OFDM_EC_SB_SNR_HI_MIN                                           0x0
#define    OFDM_EC_SB_SNR_HI_TAG                                           0x0


#define  OFDM_EC_SB_SNR_MID__A                                             0x3410018
#define  OFDM_EC_SB_SNR_MID__W                                             7
#define  OFDM_EC_SB_SNR_MID__M                                             0x7F
#define  OFDM_EC_SB_SNR_MID__PRE                                           0x7F
#define    OFDM_EC_SB_SNR_MID_MAX                                          0x7F
#define    OFDM_EC_SB_SNR_MID_MIN                                          0x0
#define    OFDM_EC_SB_SNR_MID_TAG                                          0x0


#define  OFDM_EC_SB_SNR_LO__A                                              0x3410019
#define  OFDM_EC_SB_SNR_LO__W                                              7
#define  OFDM_EC_SB_SNR_LO__M                                              0x7F
#define  OFDM_EC_SB_SNR_LO__PRE                                            0x7F
#define    OFDM_EC_SB_SNR_LO_MAX                                           0x7F
#define    OFDM_EC_SB_SNR_LO_MIN                                           0x0
#define    OFDM_EC_SB_SNR_LO_TAG                                           0x0


#define  OFDM_EC_SB_SCALE_MSB__A                                           0x341001A
#define  OFDM_EC_SB_SCALE_MSB__W                                           6
#define  OFDM_EC_SB_SCALE_MSB__M                                           0x3F
#define  OFDM_EC_SB_SCALE_MSB__PRE                                         0x30
#define    OFDM_EC_SB_SCALE_MSB_MAX                                        0x3F


#define  OFDM_EC_SB_SCALE_BIT2__A                                          0x341001B
#define  OFDM_EC_SB_SCALE_BIT2__W                                          6
#define  OFDM_EC_SB_SCALE_BIT2__M                                          0x3F
#define  OFDM_EC_SB_SCALE_BIT2__PRE                                        0xC
#define    OFDM_EC_SB_SCALE_BIT2_MAX                                       0x3F


#define  OFDM_EC_SB_SCALE_LSB__A                                           0x341001C
#define  OFDM_EC_SB_SCALE_LSB__W                                           6
#define  OFDM_EC_SB_SCALE_LSB__M                                           0x3F
#define  OFDM_EC_SB_SCALE_LSB__PRE                                         0x3
#define    OFDM_EC_SB_SCALE_LSB_MAX                                        0x3F


#define  OFDM_EC_SB_CSI_OFS0__A                                            0x341001D
#define  OFDM_EC_SB_CSI_OFS0__W                                            4
#define  OFDM_EC_SB_CSI_OFS0__M                                            0xF
#define  OFDM_EC_SB_CSI_OFS0__PRE                                          0x1

#define  OFDM_EC_SB_CSI_OFS1__A                                            0x341001E
#define  OFDM_EC_SB_CSI_OFS1__W                                            4
#define  OFDM_EC_SB_CSI_OFS1__M                                            0xF
#define  OFDM_EC_SB_CSI_OFS1__PRE                                          0x1

#define  OFDM_EC_SB_CSI_OFS2__A                                            0x341001F
#define  OFDM_EC_SB_CSI_OFS2__W                                            4
#define  OFDM_EC_SB_CSI_OFS2__M                                            0xF
#define  OFDM_EC_SB_CSI_OFS2__PRE                                          0x1

#define  OFDM_EC_SB_MAX0__A                                                0x3410020
#define  OFDM_EC_SB_MAX0__W                                                6
#define  OFDM_EC_SB_MAX0__M                                                0x3F
#define  OFDM_EC_SB_MAX0__PRE                                              0x3F

#define  OFDM_EC_SB_MAX1__A                                                0x3410021
#define  OFDM_EC_SB_MAX1__W                                                6
#define  OFDM_EC_SB_MAX1__M                                                0x3F
#define  OFDM_EC_SB_MAX1__PRE                                              0x3F
#define    OFDM_EC_SB_MAX1_INIT                                            0x3F


#define  OFDM_EC_SB_MAX2__A                                                0x3410022
#define  OFDM_EC_SB_MAX2__W                                                6
#define  OFDM_EC_SB_MAX2__M                                                0x3F
#define  OFDM_EC_SB_MAX2__PRE                                              0x3F

#define  OFDM_EC_SB_CSI_DIS__A                                             0x3410023
#define  OFDM_EC_SB_CSI_DIS__W                                             1
#define  OFDM_EC_SB_CSI_DIS__M                                             0x1
#define  OFDM_EC_SB_CSI_DIS__PRE                                           0x0



#define  OFDM_EC_VD_COMM_EXEC__A                                           0x3420000
#define  OFDM_EC_VD_COMM_EXEC__W                                           3
#define  OFDM_EC_VD_COMM_EXEC__M                                           0x7
#define  OFDM_EC_VD_COMM_EXEC__PRE                                         0x0
#define    OFDM_EC_VD_COMM_EXEC_STOP                                       0x0
#define    OFDM_EC_VD_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_EC_VD_COMM_EXEC_HOLD                                       0x2
#define    OFDM_EC_VD_COMM_EXEC_STEP                                       0x3

#define  OFDM_EC_VD_COMM_STATE__A                                          0x3420001
#define  OFDM_EC_VD_COMM_STATE__W                                          4
#define  OFDM_EC_VD_COMM_STATE__M                                          0xF
#define  OFDM_EC_VD_COMM_STATE__PRE                                        0x0
#define  OFDM_EC_VD_COMM_MB__A                                             0x3420002
#define  OFDM_EC_VD_COMM_MB__W                                             2
#define  OFDM_EC_VD_COMM_MB__M                                             0x3
#define  OFDM_EC_VD_COMM_MB__PRE                                           0x0
#define    OFDM_EC_VD_COMM_MB_CTL__B                                       0
#define    OFDM_EC_VD_COMM_MB_CTL__W                                       1
#define    OFDM_EC_VD_COMM_MB_CTL__M                                       0x1
#define    OFDM_EC_VD_COMM_MB_CTL__PRE                                     0x0
#define      OFDM_EC_VD_COMM_MB_CTL_OFF                                    0x0
#define      OFDM_EC_VD_COMM_MB_CTL_ON                                     0x1
#define    OFDM_EC_VD_COMM_MB_OBS__B                                       1
#define    OFDM_EC_VD_COMM_MB_OBS__W                                       1
#define    OFDM_EC_VD_COMM_MB_OBS__M                                       0x2
#define    OFDM_EC_VD_COMM_MB_OBS__PRE                                     0x0
#define      OFDM_EC_VD_COMM_MB_OBS_OFF                                    0x0
#define      OFDM_EC_VD_COMM_MB_OBS_ON                                     0x2

#define  OFDM_EC_VD_COMM_INT_REQ__A                                        0x3420003
#define  OFDM_EC_VD_COMM_INT_REQ__W                                        1
#define  OFDM_EC_VD_COMM_INT_REQ__M                                        0x1
#define  OFDM_EC_VD_COMM_INT_REQ__PRE                                      0x0
#define  OFDM_EC_VD_COMM_INT_STA__A                                        0x3420005
#define  OFDM_EC_VD_COMM_INT_STA__W                                        1
#define  OFDM_EC_VD_COMM_INT_STA__M                                        0x1
#define  OFDM_EC_VD_COMM_INT_STA__PRE                                      0x0
#define    OFDM_EC_VD_COMM_INT_STA_BER_RDY__B                              0
#define    OFDM_EC_VD_COMM_INT_STA_BER_RDY__W                              1
#define    OFDM_EC_VD_COMM_INT_STA_BER_RDY__M                              0x1
#define    OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE                            0x0

#define  OFDM_EC_VD_COMM_INT_MSK__A                                        0x3420006
#define  OFDM_EC_VD_COMM_INT_MSK__W                                        1
#define  OFDM_EC_VD_COMM_INT_MSK__M                                        0x1
#define  OFDM_EC_VD_COMM_INT_MSK__PRE                                      0x0
#define    OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B                              0
#define    OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W                              1
#define    OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M                              0x1
#define    OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE                            0x0

#define  OFDM_EC_VD_COMM_INT_STM__A                                        0x3420007
#define  OFDM_EC_VD_COMM_INT_STM__W                                        1
#define  OFDM_EC_VD_COMM_INT_STM__M                                        0x1
#define  OFDM_EC_VD_COMM_INT_STM__PRE                                      0x0
#define    OFDM_EC_VD_COMM_INT_STM_BER_RDY__B                              0
#define    OFDM_EC_VD_COMM_INT_STM_BER_RDY__W                              1
#define    OFDM_EC_VD_COMM_INT_STM_BER_RDY__M                              0x1
#define    OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE                            0x0


#define  OFDM_EC_VD_FORCE__A                                               0x3420010
#define  OFDM_EC_VD_FORCE__W                                               2
#define  OFDM_EC_VD_FORCE__M                                               0x3
#define  OFDM_EC_VD_FORCE__PRE                                             0x2
#define    OFDM_EC_VD_FORCE_FREE                                           0x0
#define    OFDM_EC_VD_FORCE_PROP                                           0x1
#define    OFDM_EC_VD_FORCE_FORCED                                         0x2
#define    OFDM_EC_VD_FORCE_FIXED                                          0x3


#define  OFDM_EC_VD_SET_CODERATE__A                                        0x3420011
#define  OFDM_EC_VD_SET_CODERATE__W                                        3
#define  OFDM_EC_VD_SET_CODERATE__M                                        0x7
#define  OFDM_EC_VD_SET_CODERATE__PRE                                      0x1
#define    OFDM_EC_VD_SET_CODERATE_C1_2                                    0x0
#define    OFDM_EC_VD_SET_CODERATE_C2_3                                    0x1
#define    OFDM_EC_VD_SET_CODERATE_C3_4                                    0x2
#define    OFDM_EC_VD_SET_CODERATE_C5_6                                    0x3
#define    OFDM_EC_VD_SET_CODERATE_C7_8                                    0x4


#define  OFDM_EC_VD_REQ_SMB_CNT__A                                         0x3420012
#define  OFDM_EC_VD_REQ_SMB_CNT__W                                         16
#define  OFDM_EC_VD_REQ_SMB_CNT__M                                         0xFFFF
#define  OFDM_EC_VD_REQ_SMB_CNT__PRE                                       0x1

#define  OFDM_EC_VD_REQ_BIT_CNT__A                                         0x3420013
#define  OFDM_EC_VD_REQ_BIT_CNT__W                                         16
#define  OFDM_EC_VD_REQ_BIT_CNT__M                                         0xFFFF
#define  OFDM_EC_VD_REQ_BIT_CNT__PRE                                       0xFFF

#define  OFDM_EC_VD_RLK_ENA__A                                             0x3420014
#define  OFDM_EC_VD_RLK_ENA__W                                             1
#define  OFDM_EC_VD_RLK_ENA__M                                             0x1
#define  OFDM_EC_VD_RLK_ENA__PRE                                           0x1
#define    OFDM_EC_VD_RLK_ENA_OFF                                          0x0
#define    OFDM_EC_VD_RLK_ENA_ON                                           0x1


#define  OFDM_EC_VD_VAL__A                                                 0x3420015
#define  OFDM_EC_VD_VAL__W                                                 2
#define  OFDM_EC_VD_VAL__M                                                 0x3
#define  OFDM_EC_VD_VAL__PRE                                               0x0
#define    OFDM_EC_VD_VAL_CODE                                             0x1
#define    OFDM_EC_VD_VAL_CNT                                              0x2


#define  OFDM_EC_VD_GET_CODERATE__A                                        0x3420016
#define  OFDM_EC_VD_GET_CODERATE__W                                        3
#define  OFDM_EC_VD_GET_CODERATE__M                                        0x7
#define  OFDM_EC_VD_GET_CODERATE__PRE                                      0x0
#define    OFDM_EC_VD_GET_CODERATE_C1_2                                    0x0
#define    OFDM_EC_VD_GET_CODERATE_C2_3                                    0x1
#define    OFDM_EC_VD_GET_CODERATE_C3_4                                    0x2
#define    OFDM_EC_VD_GET_CODERATE_C5_6                                    0x3
#define    OFDM_EC_VD_GET_CODERATE_C7_8                                    0x4


#define  OFDM_EC_VD_ERR_BIT_CNT__A                                         0x3420017
#define  OFDM_EC_VD_ERR_BIT_CNT__W                                         16
#define  OFDM_EC_VD_ERR_BIT_CNT__M                                         0xFFFF
#define  OFDM_EC_VD_ERR_BIT_CNT__PRE                                       0xFFFF

#define  OFDM_EC_VD_IN_BIT_CNT__A                                          0x3420018
#define  OFDM_EC_VD_IN_BIT_CNT__W                                          16
#define  OFDM_EC_VD_IN_BIT_CNT__M                                          0xFFFF
#define  OFDM_EC_VD_IN_BIT_CNT__PRE                                        0x0

#define  OFDM_EC_VD_STS__A                                                 0x3420019
#define  OFDM_EC_VD_STS__W                                                 1
#define  OFDM_EC_VD_STS__M                                                 0x1
#define  OFDM_EC_VD_STS__PRE                                               0x0
#define    OFDM_EC_VD_STS_NO_LOCK                                          0x0
#define    OFDM_EC_VD_STS_IN_LOCK                                          0x1


#define  OFDM_EC_VD_RLK_CNT__A                                             0x342001A
#define  OFDM_EC_VD_RLK_CNT__W                                             16
#define  OFDM_EC_VD_RLK_CNT__M                                             0xFFFF
#define  OFDM_EC_VD_RLK_CNT__PRE                                           0x0



#define  OFDM_EC_SY_COMM_EXEC__A                                           0x3430000
#define  OFDM_EC_SY_COMM_EXEC__W                                           2
#define  OFDM_EC_SY_COMM_EXEC__M                                           0x3
#define  OFDM_EC_SY_COMM_EXEC__PRE                                         0x0
#define    OFDM_EC_SY_COMM_EXEC_STOP                                       0x0
#define    OFDM_EC_SY_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_EC_SY_COMM_EXEC_HOLD                                       0x2
#define    OFDM_EC_SY_COMM_EXEC_STEP                                       0x3

#define  OFDM_EC_SY_COMM_MB__A                                             0x3430002
#define  OFDM_EC_SY_COMM_MB__W                                             2
#define  OFDM_EC_SY_COMM_MB__M                                             0x3
#define  OFDM_EC_SY_COMM_MB__PRE                                           0x0
#define    OFDM_EC_SY_COMM_MB_CTL__B                                       0
#define    OFDM_EC_SY_COMM_MB_CTL__W                                       1
#define    OFDM_EC_SY_COMM_MB_CTL__M                                       0x1
#define    OFDM_EC_SY_COMM_MB_CTL__PRE                                     0x0
#define      OFDM_EC_SY_COMM_MB_CTL_OFF                                    0x0
#define      OFDM_EC_SY_COMM_MB_CTL_ON                                     0x1
#define    OFDM_EC_SY_COMM_MB_OBS__B                                       1
#define    OFDM_EC_SY_COMM_MB_OBS__W                                       1
#define    OFDM_EC_SY_COMM_MB_OBS__M                                       0x2
#define    OFDM_EC_SY_COMM_MB_OBS__PRE                                     0x0
#define      OFDM_EC_SY_COMM_MB_OBS_OFF                                    0x0
#define      OFDM_EC_SY_COMM_MB_OBS_ON                                     0x2

#define  OFDM_EC_SY_COMM_INT_REQ__A                                        0x3430003
#define  OFDM_EC_SY_COMM_INT_REQ__W                                        1
#define  OFDM_EC_SY_COMM_INT_REQ__M                                        0x1
#define  OFDM_EC_SY_COMM_INT_REQ__PRE                                      0x0
#define  OFDM_EC_SY_COMM_INT_STA__A                                        0x3430005
#define  OFDM_EC_SY_COMM_INT_STA__W                                        3
#define  OFDM_EC_SY_COMM_INT_STA__M                                        0x7
#define  OFDM_EC_SY_COMM_INT_STA__PRE                                      0x0

#define    OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B                             0
#define    OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W                             1
#define    OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M                             0x1
#define    OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE                           0x0

#define    OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B                           1
#define    OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W                           1
#define    OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M                           0x2
#define    OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE                         0x0

#define    OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B                          2
#define    OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W                          1
#define    OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M                          0x4
#define    OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE                        0x0

#define  OFDM_EC_SY_COMM_INT_MSK__A                                        0x3430006
#define  OFDM_EC_SY_COMM_INT_MSK__W                                        3
#define  OFDM_EC_SY_COMM_INT_MSK__M                                        0x7
#define  OFDM_EC_SY_COMM_INT_MSK__PRE                                      0x0
#define    OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B                             0
#define    OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W                             1
#define    OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M                             0x1
#define    OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE                           0x0
#define    OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B                           1
#define    OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W                           1
#define    OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M                           0x2
#define    OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE                         0x0
#define    OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B                          2
#define    OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W                          1
#define    OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M                          0x4
#define    OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE                        0x0

#define  OFDM_EC_SY_COMM_INT_STM__A                                        0x3430007
#define  OFDM_EC_SY_COMM_INT_STM__W                                        3
#define  OFDM_EC_SY_COMM_INT_STM__M                                        0x7
#define  OFDM_EC_SY_COMM_INT_STM__PRE                                      0x0
#define    OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B                             0
#define    OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W                             1
#define    OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M                             0x1
#define    OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE                           0x0
#define    OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B                           1
#define    OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W                           1
#define    OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M                           0x2
#define    OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE                         0x0
#define    OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B                          2
#define    OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W                          1
#define    OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M                          0x4
#define    OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE                        0x0

#define  OFDM_EC_SY_STATUS__A                                              0x3430010
#define  OFDM_EC_SY_STATUS__W                                              2
#define  OFDM_EC_SY_STATUS__M                                              0x3
#define  OFDM_EC_SY_STATUS__PRE                                            0x0
#define    OFDM_EC_SY_STATUS_SYNC_STATE__B                                 0
#define    OFDM_EC_SY_STATUS_SYNC_STATE__W                                 2
#define    OFDM_EC_SY_STATUS_SYNC_STATE__M                                 0x3
#define    OFDM_EC_SY_STATUS_SYNC_STATE__PRE                               0x0
#define      OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING                          0x0
#define      OFDM_EC_SY_STATUS_SYNC_STATE_TRYING                           0x1
#define      OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC                          0x2


#define  OFDM_EC_SY_TIMEOUT__A                                             0x3430011
#define  OFDM_EC_SY_TIMEOUT__W                                             16
#define  OFDM_EC_SY_TIMEOUT__M                                             0xFFFF
#define  OFDM_EC_SY_TIMEOUT__PRE                                           0x3A98

#define  OFDM_EC_SY_SYNC_LWM__A                                            0x3430012
#define  OFDM_EC_SY_SYNC_LWM__W                                            4
#define  OFDM_EC_SY_SYNC_LWM__M                                            0xF
#define  OFDM_EC_SY_SYNC_LWM__PRE                                          0x2

#define  OFDM_EC_SY_SYNC_AWM__A                                            0x3430013
#define  OFDM_EC_SY_SYNC_AWM__W                                            4
#define  OFDM_EC_SY_SYNC_AWM__M                                            0xF
#define  OFDM_EC_SY_SYNC_AWM__PRE                                          0x3

#define  OFDM_EC_SY_SYNC_HWM__A                                            0x3430014
#define  OFDM_EC_SY_SYNC_HWM__W                                            4
#define  OFDM_EC_SY_SYNC_HWM__M                                            0xF
#define  OFDM_EC_SY_SYNC_HWM__PRE                                          0x5

#define  OFDM_EC_SY_UNLOCK__A                                              0x3430015
#define  OFDM_EC_SY_UNLOCK__W                                              1
#define  OFDM_EC_SY_UNLOCK__M                                              0x1
#define  OFDM_EC_SY_UNLOCK__PRE                                            0x0



#define  OFDM_EC_SB_BD0_RAM__A                                             0x3440000



#define  OFDM_EC_SB_BD1_RAM__A                                             0x3450000



#define  OFDM_EC_SB_SD_RAM__A                                              0x3460000



#define  OFDM_EC_VD_RE_RAM__A                                              0x3470000



#define  OFDM_EC_VD_TB0_RAM__A                                             0x3480000



#define  OFDM_EC_VD_TB1_RAM__A                                             0x3490000



#define  OFDM_EC_VD_TB2_RAM__A                                             0x34A0000



#define  OFDM_EC_VD_TB3_RAM__A                                             0x34B0000





#define  OFDM_EQ_COMM_EXEC__A                                              0x3000000
#define  OFDM_EQ_COMM_EXEC__W                                              3
#define  OFDM_EQ_COMM_EXEC__M                                              0x7
#define  OFDM_EQ_COMM_EXEC__PRE                                            0x0
#define    OFDM_EQ_COMM_EXEC_STOP                                          0x0
#define    OFDM_EQ_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_EQ_COMM_EXEC_HOLD                                          0x2
#define    OFDM_EQ_COMM_EXEC_STEP                                          0x3
#define    OFDM_EQ_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_EQ_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_EQ_COMM_STATE__A                                             0x3000001
#define  OFDM_EQ_COMM_STATE__W                                             16
#define  OFDM_EQ_COMM_STATE__M                                             0xFFFF
#define  OFDM_EQ_COMM_STATE__PRE                                           0x0
#define  OFDM_EQ_COMM_MB__A                                                0x3000002
#define  OFDM_EQ_COMM_MB__W                                                16
#define  OFDM_EQ_COMM_MB__M                                                0xFFFF
#define  OFDM_EQ_COMM_MB__PRE                                              0x0
#define  OFDM_EQ_COMM_INT_REQ__A                                           0x3000004
#define  OFDM_EQ_COMM_INT_REQ__W                                           16
#define  OFDM_EQ_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_EQ_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_EQ_COMM_INT_REQ_TOP_REQ__B                                 3
#define    OFDM_EQ_COMM_INT_REQ_TOP_REQ__W                                 1
#define    OFDM_EQ_COMM_INT_REQ_TOP_REQ__M                                 0x8
#define    OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE                               0x0

#define  OFDM_EQ_COMM_INT_STA__A                                           0x3000005
#define  OFDM_EQ_COMM_INT_STA__W                                           16
#define  OFDM_EQ_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_EQ_COMM_INT_STA__PRE                                         0x0
#define  OFDM_EQ_COMM_INT_MSK__A                                           0x3000006
#define  OFDM_EQ_COMM_INT_MSK__W                                           16
#define  OFDM_EQ_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_EQ_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_EQ_COMM_INT_STM__A                                           0x3000007
#define  OFDM_EQ_COMM_INT_STM__W                                           16
#define  OFDM_EQ_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_EQ_COMM_INT_STM__PRE                                         0x0
#define    OFDM_EQ_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_EQ_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_EQ_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_EQ_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_EQ_TOP_COMM_EXEC__A                                          0x3010000
#define  OFDM_EQ_TOP_COMM_EXEC__W                                          3
#define  OFDM_EQ_TOP_COMM_EXEC__M                                          0x7
#define  OFDM_EQ_TOP_COMM_EXEC__PRE                                        0x0
#define    OFDM_EQ_TOP_COMM_EXEC_STOP                                      0x0
#define    OFDM_EQ_TOP_COMM_EXEC_ACTIVE                                    0x1
#define    OFDM_EQ_TOP_COMM_EXEC_HOLD                                      0x2
#define    OFDM_EQ_TOP_COMM_EXEC_STEP                                      0x3

#define  OFDM_EQ_TOP_COMM_STATE__A                                         0x3010001
#define  OFDM_EQ_TOP_COMM_STATE__W                                         4
#define  OFDM_EQ_TOP_COMM_STATE__M                                         0xF
#define  OFDM_EQ_TOP_COMM_STATE__PRE                                       0x0
#define  OFDM_EQ_TOP_COMM_MB__A                                            0x3010002
#define  OFDM_EQ_TOP_COMM_MB__W                                            6
#define  OFDM_EQ_TOP_COMM_MB__M                                            0x3F
#define  OFDM_EQ_TOP_COMM_MB__PRE                                          0x0
#define    OFDM_EQ_TOP_COMM_MB_CTL__B                                      0
#define    OFDM_EQ_TOP_COMM_MB_CTL__W                                      1
#define    OFDM_EQ_TOP_COMM_MB_CTL__M                                      0x1
#define    OFDM_EQ_TOP_COMM_MB_CTL__PRE                                    0x0
#define      OFDM_EQ_TOP_COMM_MB_CTL_OFF                                   0x0
#define      OFDM_EQ_TOP_COMM_MB_CTL_ON                                    0x1
#define    OFDM_EQ_TOP_COMM_MB_OBS__B                                      1
#define    OFDM_EQ_TOP_COMM_MB_OBS__W                                      1
#define    OFDM_EQ_TOP_COMM_MB_OBS__M                                      0x2
#define    OFDM_EQ_TOP_COMM_MB_OBS__PRE                                    0x0
#define      OFDM_EQ_TOP_COMM_MB_OBS_OFF                                   0x0
#define      OFDM_EQ_TOP_COMM_MB_OBS_ON                                    0x2
#define    OFDM_EQ_TOP_COMM_MB_CTL_MUX__B                                  2
#define    OFDM_EQ_TOP_COMM_MB_CTL_MUX__W                                  2
#define    OFDM_EQ_TOP_COMM_MB_CTL_MUX__M                                  0xC
#define    OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE                                0x0
#define      OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT                             0x0
#define      OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC                             0x4
#define      OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS                             0x8
#define    OFDM_EQ_TOP_COMM_MB_OBS_MUX__B                                  4
#define    OFDM_EQ_TOP_COMM_MB_OBS_MUX__W                                  2
#define    OFDM_EQ_TOP_COMM_MB_OBS_MUX__M                                  0x30
#define    OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE                                0x0
#define      OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT                             0x0
#define      OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC                             0x10
#define      OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS                             0x20
#define      OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN                             0x30

#define  OFDM_EQ_TOP_COMM_INT_REQ__A                                       0x3010004
#define  OFDM_EQ_TOP_COMM_INT_REQ__W                                       1
#define  OFDM_EQ_TOP_COMM_INT_REQ__M                                       0x1
#define  OFDM_EQ_TOP_COMM_INT_REQ__PRE                                     0x0
#define  OFDM_EQ_TOP_COMM_INT_STA__A                                       0x3010005
#define  OFDM_EQ_TOP_COMM_INT_STA__W                                       2
#define  OFDM_EQ_TOP_COMM_INT_STA__M                                       0x3
#define  OFDM_EQ_TOP_COMM_INT_STA__PRE                                     0x0
#define    OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B                             0
#define    OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W                             1
#define    OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M                             0x1
#define    OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE                           0x0
#define    OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B                             1
#define    OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W                             1
#define    OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M                             0x2
#define    OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE                           0x0

#define  OFDM_EQ_TOP_COMM_INT_MSK__A                                       0x3010006
#define  OFDM_EQ_TOP_COMM_INT_MSK__W                                       2
#define  OFDM_EQ_TOP_COMM_INT_MSK__M                                       0x3
#define  OFDM_EQ_TOP_COMM_INT_MSK__PRE                                     0x0
#define    OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B                             0
#define    OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W                             1
#define    OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M                             0x1
#define    OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE                           0x0
#define    OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B                             1
#define    OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W                             1
#define    OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M                             0x2
#define    OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE                           0x0

#define  OFDM_EQ_TOP_COMM_INT_STM__A                                       0x3010007
#define  OFDM_EQ_TOP_COMM_INT_STM__W                                       2
#define  OFDM_EQ_TOP_COMM_INT_STM__M                                       0x3
#define  OFDM_EQ_TOP_COMM_INT_STM__PRE                                     0x0
#define    OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B                             0
#define    OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W                             1
#define    OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M                             0x1
#define    OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE                           0x0
#define    OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B                             1
#define    OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W                             1
#define    OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M                             0x2
#define    OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE                           0x0

#define  OFDM_EQ_TOP_IS_MODE__A                                            0x3010014
#define  OFDM_EQ_TOP_IS_MODE__W                                            4
#define  OFDM_EQ_TOP_IS_MODE__M                                            0xF
#define  OFDM_EQ_TOP_IS_MODE__PRE                                          0x0

#define    OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B                              0
#define    OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W                              1
#define    OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M                              0x1
#define    OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE                            0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX       0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER       0x1

#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B                              1
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W                              1
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M                              0x2
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE                            0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE       0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO       0x2

#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B                          2
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W                          1
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M                          0x4
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE                        0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE                    0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE                   0x4

#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B                          3
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W                          1
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M                          0x8
#define    OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE                        0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE                    0x0
#define      OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE                   0x8


#define  OFDM_EQ_TOP_IS_GAIN_MAN__A                                        0x3010015
#define  OFDM_EQ_TOP_IS_GAIN_MAN__W                                        10
#define  OFDM_EQ_TOP_IS_GAIN_MAN__M                                        0x3FF
#define  OFDM_EQ_TOP_IS_GAIN_MAN__PRE                                      0x114

#define  OFDM_EQ_TOP_IS_GAIN_EXP__A                                        0x3010016
#define  OFDM_EQ_TOP_IS_GAIN_EXP__W                                        5
#define  OFDM_EQ_TOP_IS_GAIN_EXP__M                                        0x1F
#define  OFDM_EQ_TOP_IS_GAIN_EXP__PRE                                      0x5

#define  OFDM_EQ_TOP_IS_CLIP_EXP__A                                        0x3010017
#define  OFDM_EQ_TOP_IS_CLIP_EXP__W                                        5
#define  OFDM_EQ_TOP_IS_CLIP_EXP__M                                        0x1F
#define  OFDM_EQ_TOP_IS_CLIP_EXP__PRE                                      0x10
#define  OFDM_EQ_TOP_DV_MODE__A                                            0x301001E
#define  OFDM_EQ_TOP_DV_MODE__W                                            4
#define  OFDM_EQ_TOP_DV_MODE__M                                            0xF
#define  OFDM_EQ_TOP_DV_MODE__PRE                                          0xF

#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B                              0
#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W                              1
#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M                              0x1
#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE                            0x1
#define      OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS                           0x0
#define      OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA                           0x1

#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B                              1
#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W                              1
#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M                              0x2
#define    OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE                            0x2
#define      OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS                           0x0
#define      OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA                           0x2

#define    OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B                              2
#define    OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W                              1
#define    OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M                              0x4
#define    OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE                            0x4
#define      OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS                           0x0
#define      OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA                           0x4

#define    OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B                              3
#define    OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W                              1
#define    OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M                              0x8
#define    OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE                            0x8
#define      OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS                           0x0
#define      OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA                           0x8


#define  OFDM_EQ_TOP_DV_POS_CLIP_DAT__A                                    0x301001F
#define  OFDM_EQ_TOP_DV_POS_CLIP_DAT__W                                    16
#define  OFDM_EQ_TOP_DV_POS_CLIP_DAT__M                                    0xFFFF
#define  OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE                                  0x0
#define  OFDM_EQ_TOP_SN_MODE__A                                            0x3010028
#define  OFDM_EQ_TOP_SN_MODE__W                                            8
#define  OFDM_EQ_TOP_SN_MODE__M                                            0xFF
#define  OFDM_EQ_TOP_SN_MODE__PRE                                          0x18

#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B                            0
#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M                            0x1
#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE                          0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE                     0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE                      0x1

#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M                            0x2
#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE                          0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE                     0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE                      0x2

#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B                            2
#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M                            0x4
#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE                          0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE                     0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE                      0x4

#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B                            3
#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M                            0x8
#define    OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE                          0x8
#define      OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE                     0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE                      0x8

#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B                            4
#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M                            0x10
#define    OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE                          0x10
#define      OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE                     0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE                      0x10

#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B                            5
#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W                            1
#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M                            0x20
#define    OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE                          0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE                     0x0
#define      OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE                      0x20

#define    OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B                              6
#define    OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W                              1
#define    OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M                              0x40
#define    OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE                            0x0
#define      OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC                       0x0
#define      OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC                        0x40

#define    OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B                              7
#define    OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W                              1
#define    OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M                              0x80
#define    OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE                            0x0
#define      OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC                       0x0
#define      OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC                        0x80


#define  OFDM_EQ_TOP_SN_PFIX__A                                            0x3010029
#define  OFDM_EQ_TOP_SN_PFIX__W                                            8
#define  OFDM_EQ_TOP_SN_PFIX__M                                            0xFF
#define  OFDM_EQ_TOP_SN_PFIX__PRE                                          0x0

#define  OFDM_EQ_TOP_SN_CEGAIN__A                                          0x301002A
#define  OFDM_EQ_TOP_SN_CEGAIN__W                                          8
#define  OFDM_EQ_TOP_SN_CEGAIN__M                                          0xFF
#define  OFDM_EQ_TOP_SN_CEGAIN__PRE                                        0x30

#define  OFDM_EQ_TOP_SN_OFFSET__A                                          0x301002B
#define  OFDM_EQ_TOP_SN_OFFSET__W                                          6
#define  OFDM_EQ_TOP_SN_OFFSET__M                                          0x3F
#define  OFDM_EQ_TOP_SN_OFFSET__PRE                                        0x39

#define  OFDM_EQ_TOP_SN_NULLIFY__A                                         0x301002C
#define  OFDM_EQ_TOP_SN_NULLIFY__W                                         6
#define  OFDM_EQ_TOP_SN_NULLIFY__M                                         0x3F
#define  OFDM_EQ_TOP_SN_NULLIFY__PRE                                       0x0
#define  OFDM_EQ_TOP_SN_SQUASH__A                                          0x301002D
#define  OFDM_EQ_TOP_SN_SQUASH__W                                          10
#define  OFDM_EQ_TOP_SN_SQUASH__M                                          0x3FF
#define  OFDM_EQ_TOP_SN_SQUASH__PRE                                        0x7

#define    OFDM_EQ_TOP_SN_SQUASH_MAN__B                                    0
#define    OFDM_EQ_TOP_SN_SQUASH_MAN__W                                    6
#define    OFDM_EQ_TOP_SN_SQUASH_MAN__M                                    0x3F
#define    OFDM_EQ_TOP_SN_SQUASH_MAN__PRE                                  0x7

#define    OFDM_EQ_TOP_SN_SQUASH_EXP__B                                    6
#define    OFDM_EQ_TOP_SN_SQUASH_EXP__W                                    4
#define    OFDM_EQ_TOP_SN_SQUASH_EXP__M                                    0x3C0
#define    OFDM_EQ_TOP_SN_SQUASH_EXP__PRE                                  0x0

#define  OFDM_EQ_TOP_RC_SEL_CAR__A                                         0x3010032
#define  OFDM_EQ_TOP_RC_SEL_CAR__W                                         8
#define  OFDM_EQ_TOP_RC_SEL_CAR__M                                         0xFF
#define  OFDM_EQ_TOP_RC_SEL_CAR__PRE                                       0x2
#define    OFDM_EQ_TOP_RC_SEL_CAR_DIV__B                                   0
#define    OFDM_EQ_TOP_RC_SEL_CAR_DIV__W                                   1
#define    OFDM_EQ_TOP_RC_SEL_CAR_DIV__M                                   0x1
#define    OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE                                 0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF                                0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON                                 0x1

#define    OFDM_EQ_TOP_RC_SEL_CAR_PASS__B                                  1
#define    OFDM_EQ_TOP_RC_SEL_CAR_PASS__W                                  2
#define    OFDM_EQ_TOP_RC_SEL_CAR_PASS__M                                  0x6
#define    OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE                                0x2
#define      OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC                              0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE                              0x2
#define      OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI                             0x4
#define      OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC                              0x6

#define    OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B                                 3
#define    OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W                                 2
#define    OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M                                 0x18
#define    OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE                               0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC                             0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE                             0x8
#define      OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI                            0x10
#define      OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC                             0x18

#define    OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B                                  5
#define    OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W                                  2
#define    OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M                                  0x60
#define    OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE                                0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC                              0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE                              0x20
#define      OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI                             0x40
#define      OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC                              0x60

#define    OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B                               7
#define    OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W                               1
#define    OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M                               0x80
#define    OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE                             0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K                             0x0
#define      OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K                             0x80

#define  OFDM_EQ_TOP_RC_STS__A                                             0x3010033
#define  OFDM_EQ_TOP_RC_STS__W                                             16
#define  OFDM_EQ_TOP_RC_STS__M                                             0xFFFF
#define  OFDM_EQ_TOP_RC_STS__PRE                                           0x0

#define    OFDM_EQ_TOP_RC_STS_DIFF__B                                      0
#define    OFDM_EQ_TOP_RC_STS_DIFF__W                                      11
#define    OFDM_EQ_TOP_RC_STS_DIFF__M                                      0x7FF
#define    OFDM_EQ_TOP_RC_STS_DIFF__PRE                                    0x0

#define    OFDM_EQ_TOP_RC_STS_FIRST__B                                     11
#define    OFDM_EQ_TOP_RC_STS_FIRST__W                                     1
#define    OFDM_EQ_TOP_RC_STS_FIRST__M                                     0x800
#define    OFDM_EQ_TOP_RC_STS_FIRST__PRE                                   0x0
#define      OFDM_EQ_TOP_RC_STS_FIRST_A_CE                                 0x0
#define      OFDM_EQ_TOP_RC_STS_FIRST_B_DRI                                0x800

#define    OFDM_EQ_TOP_RC_STS_SELEC__B                                     12
#define    OFDM_EQ_TOP_RC_STS_SELEC__W                                     1
#define    OFDM_EQ_TOP_RC_STS_SELEC__M                                     0x1000
#define    OFDM_EQ_TOP_RC_STS_SELEC__PRE                                   0x0
#define      OFDM_EQ_TOP_RC_STS_SELEC_A_CE                                 0x0
#define      OFDM_EQ_TOP_RC_STS_SELEC_B_DRI                                0x1000

#define    OFDM_EQ_TOP_RC_STS_OVERFLOW__B                                  13
#define    OFDM_EQ_TOP_RC_STS_OVERFLOW__W                                  1
#define    OFDM_EQ_TOP_RC_STS_OVERFLOW__M                                  0x2000
#define    OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE                                0x0
#define      OFDM_EQ_TOP_RC_STS_OVERFLOW_NO                                0x0
#define      OFDM_EQ_TOP_RC_STS_OVERFLOW_YES                               0x2000

#define    OFDM_EQ_TOP_RC_STS_LOC_PRS__B                                   14
#define    OFDM_EQ_TOP_RC_STS_LOC_PRS__W                                   1
#define    OFDM_EQ_TOP_RC_STS_LOC_PRS__M                                   0x4000
#define    OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE                                 0x0
#define      OFDM_EQ_TOP_RC_STS_LOC_PRS_NO                                 0x0
#define      OFDM_EQ_TOP_RC_STS_LOC_PRS_YES                                0x4000

#define    OFDM_EQ_TOP_RC_STS_DRI_PRS__B                                   15
#define    OFDM_EQ_TOP_RC_STS_DRI_PRS__W                                   1
#define    OFDM_EQ_TOP_RC_STS_DRI_PRS__M                                   0x8000
#define    OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE                                 0x0
#define      OFDM_EQ_TOP_RC_STS_DRI_PRS_NO                                 0x0
#define      OFDM_EQ_TOP_RC_STS_DRI_PRS_YES                                0x8000


#define  OFDM_EQ_TOP_OT_CONST__A                                           0x3010046
#define  OFDM_EQ_TOP_OT_CONST__W                                           2
#define  OFDM_EQ_TOP_OT_CONST__M                                           0x3
#define  OFDM_EQ_TOP_OT_CONST__PRE                                         0x2

#define  OFDM_EQ_TOP_OT_ALPHA__A                                           0x3010047
#define  OFDM_EQ_TOP_OT_ALPHA__W                                           2
#define  OFDM_EQ_TOP_OT_ALPHA__M                                           0x3
#define  OFDM_EQ_TOP_OT_ALPHA__PRE                                         0x0

#define  OFDM_EQ_TOP_OT_QNT_THRES0__A                                      0x3010048
#define  OFDM_EQ_TOP_OT_QNT_THRES0__W                                      5
#define  OFDM_EQ_TOP_OT_QNT_THRES0__M                                      0x1F
#define  OFDM_EQ_TOP_OT_QNT_THRES0__PRE                                    0x1E

#define  OFDM_EQ_TOP_OT_QNT_THRES1__A                                      0x3010049
#define  OFDM_EQ_TOP_OT_QNT_THRES1__W                                      5
#define  OFDM_EQ_TOP_OT_QNT_THRES1__M                                      0x1F
#define  OFDM_EQ_TOP_OT_QNT_THRES1__PRE                                    0x1F

#define  OFDM_EQ_TOP_OT_CSI_STEP__A                                        0x301004A
#define  OFDM_EQ_TOP_OT_CSI_STEP__W                                        4
#define  OFDM_EQ_TOP_OT_CSI_STEP__M                                        0xF
#define  OFDM_EQ_TOP_OT_CSI_STEP__PRE                                      0x5

#define  OFDM_EQ_TOP_OT_CSI_OFFSET__A                                      0x301004B
#define  OFDM_EQ_TOP_OT_CSI_OFFSET__W                                      8
#define  OFDM_EQ_TOP_OT_CSI_OFFSET__M                                      0xFF
#define  OFDM_EQ_TOP_OT_CSI_OFFSET__PRE                                    0x5

#define  OFDM_EQ_TOP_OT_CSI_GAIN__A                                        0x301004C
#define  OFDM_EQ_TOP_OT_CSI_GAIN__W                                        8
#define  OFDM_EQ_TOP_OT_CSI_GAIN__M                                        0xFF
#define  OFDM_EQ_TOP_OT_CSI_GAIN__PRE                                      0x2B

#define  OFDM_EQ_TOP_OT_CSI_MEAN__A                                        0x301004D
#define  OFDM_EQ_TOP_OT_CSI_MEAN__W                                        7
#define  OFDM_EQ_TOP_OT_CSI_MEAN__M                                        0x7F
#define  OFDM_EQ_TOP_OT_CSI_MEAN__PRE                                      0x0

#define  OFDM_EQ_TOP_OT_CSI_VARIANCE__A                                    0x301004E
#define  OFDM_EQ_TOP_OT_CSI_VARIANCE__W                                    7
#define  OFDM_EQ_TOP_OT_CSI_VARIANCE__M                                    0x7F
#define  OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE                                  0x0

#define  OFDM_EQ_TOP_TD_TPS_INIT__A                                        0x3010050
#define  OFDM_EQ_TOP_TD_TPS_INIT__W                                        1
#define  OFDM_EQ_TOP_TD_TPS_INIT__M                                        0x1
#define  OFDM_EQ_TOP_TD_TPS_INIT__PRE                                      0x0
#define    OFDM_EQ_TOP_TD_TPS_INIT_POS                                     0x0
#define    OFDM_EQ_TOP_TD_TPS_INIT_NEG                                     0x1


#define  OFDM_EQ_TOP_TD_TPS_SYNC__A                                        0x3010051
#define  OFDM_EQ_TOP_TD_TPS_SYNC__W                                        16
#define  OFDM_EQ_TOP_TD_TPS_SYNC__M                                        0xFFFF
#define  OFDM_EQ_TOP_TD_TPS_SYNC__PRE                                      0x0
#define    OFDM_EQ_TOP_TD_TPS_SYNC_ODD                                     0x35EE
#define    OFDM_EQ_TOP_TD_TPS_SYNC_EVEN                                    0xCA11


#define  OFDM_EQ_TOP_TD_TPS_LEN__A                                         0x3010052
#define  OFDM_EQ_TOP_TD_TPS_LEN__W                                         6
#define  OFDM_EQ_TOP_TD_TPS_LEN__M                                         0x3F
#define  OFDM_EQ_TOP_TD_TPS_LEN__PRE                                       0x0
#define    OFDM_EQ_TOP_TD_TPS_LEN_DEF                                      0x17
#define    OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP                                   0x1F


#define  OFDM_EQ_TOP_TD_TPS_FRM_NMB__A                                     0x3010053
#define  OFDM_EQ_TOP_TD_TPS_FRM_NMB__W                                     2
#define  OFDM_EQ_TOP_TD_TPS_FRM_NMB__M                                     0x3
#define  OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE                                   0x0
#define    OFDM_EQ_TOP_TD_TPS_FRM_NMB_1                                    0x0
#define    OFDM_EQ_TOP_TD_TPS_FRM_NMB_2                                    0x1
#define    OFDM_EQ_TOP_TD_TPS_FRM_NMB_3                                    0x2
#define    OFDM_EQ_TOP_TD_TPS_FRM_NMB_4                                    0x3


#define  OFDM_EQ_TOP_TD_TPS_CONST__A                                       0x3010054
#define  OFDM_EQ_TOP_TD_TPS_CONST__W                                       2
#define  OFDM_EQ_TOP_TD_TPS_CONST__M                                       0x3
#define  OFDM_EQ_TOP_TD_TPS_CONST__PRE                                     0x0
#define    OFDM_EQ_TOP_TD_TPS_CONST_QPSK                                   0x0
#define    OFDM_EQ_TOP_TD_TPS_CONST_16QAM                                  0x1
#define    OFDM_EQ_TOP_TD_TPS_CONST_64QAM                                  0x2


#define  OFDM_EQ_TOP_TD_TPS_HINFO__A                                       0x3010055
#define  OFDM_EQ_TOP_TD_TPS_HINFO__W                                       3
#define  OFDM_EQ_TOP_TD_TPS_HINFO__M                                       0x7
#define  OFDM_EQ_TOP_TD_TPS_HINFO__PRE                                     0x0
#define    OFDM_EQ_TOP_TD_TPS_HINFO_NH                                     0x0
#define    OFDM_EQ_TOP_TD_TPS_HINFO_H1                                     0x1
#define    OFDM_EQ_TOP_TD_TPS_HINFO_H2                                     0x2
#define    OFDM_EQ_TOP_TD_TPS_HINFO_H4                                     0x3


#define  OFDM_EQ_TOP_TD_TPS_CODE_HP__A                                     0x3010056
#define  OFDM_EQ_TOP_TD_TPS_CODE_HP__W                                     3
#define  OFDM_EQ_TOP_TD_TPS_CODE_HP__M                                     0x7
#define  OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE                                   0x0
#define    OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2                                  0x0
#define    OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3                                  0x1
#define    OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4                                  0x2
#define    OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6                                  0x3
#define    OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8                                  0x4


#define  OFDM_EQ_TOP_TD_TPS_CODE_LP__A                                     0x3010057
#define  OFDM_EQ_TOP_TD_TPS_CODE_LP__W                                     3
#define  OFDM_EQ_TOP_TD_TPS_CODE_LP__M                                     0x7
#define  OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE                                   0x0
#define    OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2                                  0x0
#define    OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3                                  0x1
#define    OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4                                  0x2
#define    OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6                                  0x3
#define    OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8                                  0x4


#define  OFDM_EQ_TOP_TD_TPS_GUARD__A                                       0x3010058
#define  OFDM_EQ_TOP_TD_TPS_GUARD__W                                       2
#define  OFDM_EQ_TOP_TD_TPS_GUARD__M                                       0x3
#define  OFDM_EQ_TOP_TD_TPS_GUARD__PRE                                     0x0
#define    OFDM_EQ_TOP_TD_TPS_GUARD_32                                     0x0
#define    OFDM_EQ_TOP_TD_TPS_GUARD_16                                     0x1
#define    OFDM_EQ_TOP_TD_TPS_GUARD_08                                     0x2
#define    OFDM_EQ_TOP_TD_TPS_GUARD_04                                     0x3


#define  OFDM_EQ_TOP_TD_TPS_TR_MODE__A                                     0x3010059
#define  OFDM_EQ_TOP_TD_TPS_TR_MODE__W                                     2
#define  OFDM_EQ_TOP_TD_TPS_TR_MODE__M                                     0x3
#define  OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE                                   0x0
#define    OFDM_EQ_TOP_TD_TPS_TR_MODE_2K                                   0x0
#define    OFDM_EQ_TOP_TD_TPS_TR_MODE_8K                                   0x1


#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A                                  0x301005A
#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W                                  8
#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M                                  0xFF
#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE                                0x0

#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A                                  0x301005B
#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W                                  8
#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M                                  0xFF
#define  OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE                                0x0

#define  OFDM_EQ_TOP_TD_TPS_RSV__A                                         0x301005C
#define  OFDM_EQ_TOP_TD_TPS_RSV__W                                         6
#define  OFDM_EQ_TOP_TD_TPS_RSV__M                                         0x3F
#define  OFDM_EQ_TOP_TD_TPS_RSV__PRE                                       0x0

#define  OFDM_EQ_TOP_TD_TPS_BCH__A                                         0x301005D
#define  OFDM_EQ_TOP_TD_TPS_BCH__W                                         14
#define  OFDM_EQ_TOP_TD_TPS_BCH__M                                         0x3FFF
#define  OFDM_EQ_TOP_TD_TPS_BCH__PRE                                       0x0

#define  OFDM_EQ_TOP_TD_SQR_ERR_I__A                                       0x301005E
#define  OFDM_EQ_TOP_TD_SQR_ERR_I__W                                       16
#define  OFDM_EQ_TOP_TD_SQR_ERR_I__M                                       0xFFFF
#define  OFDM_EQ_TOP_TD_SQR_ERR_I__PRE                                     0x0

#define  OFDM_EQ_TOP_TD_SQR_ERR_Q__A                                       0x301005F
#define  OFDM_EQ_TOP_TD_SQR_ERR_Q__W                                       16
#define  OFDM_EQ_TOP_TD_SQR_ERR_Q__M                                       0xFFFF
#define  OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE                                     0x0

#define  OFDM_EQ_TOP_TD_SQR_ERR_EXP__A                                     0x3010060
#define  OFDM_EQ_TOP_TD_SQR_ERR_EXP__W                                     4
#define  OFDM_EQ_TOP_TD_SQR_ERR_EXP__M                                     0xF
#define  OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE                                   0x0

#define  OFDM_EQ_TOP_TD_REQ_SMB_CNT__A                                     0x3010061
#define  OFDM_EQ_TOP_TD_REQ_SMB_CNT__W                                     16
#define  OFDM_EQ_TOP_TD_REQ_SMB_CNT__M                                     0xFFFF
#define  OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE                                   0x200

#define  OFDM_EQ_TOP_TD_TPS_PWR_OFS__A                                     0x3010062
#define  OFDM_EQ_TOP_TD_TPS_PWR_OFS__W                                     10
#define  OFDM_EQ_TOP_TD_TPS_PWR_OFS__M                                     0x3FF
#define  OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE                                   0x19F





#define  OFDM_FE_COMM_EXEC__A                                              0x2000000
#define  OFDM_FE_COMM_EXEC__W                                              3
#define  OFDM_FE_COMM_EXEC__M                                              0x7
#define  OFDM_FE_COMM_EXEC__PRE                                            0x0
#define    OFDM_FE_COMM_EXEC_STOP                                          0x0
#define    OFDM_FE_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_FE_COMM_EXEC_HOLD                                          0x2
#define    OFDM_FE_COMM_EXEC_STEP                                          0x3

#define  OFDM_FE_COMM_STATE__A                                             0x2000001
#define  OFDM_FE_COMM_STATE__W                                             16
#define  OFDM_FE_COMM_STATE__M                                             0xFFFF
#define  OFDM_FE_COMM_STATE__PRE                                           0x0
#define  OFDM_FE_COMM_MB__A                                                0x2000002
#define  OFDM_FE_COMM_MB__W                                                16
#define  OFDM_FE_COMM_MB__M                                                0xFFFF
#define  OFDM_FE_COMM_MB__PRE                                              0x0
#define  OFDM_FE_COMM_INT_REQ__A                                           0x2000004
#define  OFDM_FE_COMM_INT_REQ__W                                           16
#define  OFDM_FE_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_FE_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_FE_COMM_INT_REQ_CU_REQ__B                                  0
#define    OFDM_FE_COMM_INT_REQ_CU_REQ__W                                  1
#define    OFDM_FE_COMM_INT_REQ_CU_REQ__M                                  0x1
#define    OFDM_FE_COMM_INT_REQ_CU_REQ__PRE                                0x0

#define  OFDM_FE_COMM_INT_STA__A                                           0x2000005
#define  OFDM_FE_COMM_INT_STA__W                                           16
#define  OFDM_FE_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_FE_COMM_INT_STA__PRE                                         0x0
#define  OFDM_FE_COMM_INT_MSK__A                                           0x2000006
#define  OFDM_FE_COMM_INT_MSK__W                                           16
#define  OFDM_FE_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_FE_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_FE_COMM_INT_STM__A                                           0x2000007
#define  OFDM_FE_COMM_INT_STM__W                                           16
#define  OFDM_FE_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_FE_COMM_INT_STM__PRE                                         0x0
#define    OFDM_FE_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_FE_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_FE_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_FE_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_FE_CU_COMM_EXEC__A                                           0x2010000
#define  OFDM_FE_CU_COMM_EXEC__W                                           3
#define  OFDM_FE_CU_COMM_EXEC__M                                           0x7
#define  OFDM_FE_CU_COMM_EXEC__PRE                                         0x0
#define    OFDM_FE_CU_COMM_EXEC_STOP                                       0x0
#define    OFDM_FE_CU_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_FE_CU_COMM_EXEC_HOLD                                       0x2
#define    OFDM_FE_CU_COMM_EXEC_STEP                                       0x3

#define  OFDM_FE_CU_COMM_STATE__A                                          0x2010001
#define  OFDM_FE_CU_COMM_STATE__W                                          4
#define  OFDM_FE_CU_COMM_STATE__M                                          0xF
#define  OFDM_FE_CU_COMM_STATE__PRE                                        0x0
#define  OFDM_FE_CU_COMM_MB__A                                             0x2010002
#define  OFDM_FE_CU_COMM_MB__W                                             2
#define  OFDM_FE_CU_COMM_MB__M                                             0x3
#define  OFDM_FE_CU_COMM_MB__PRE                                           0x0
#define    OFDM_FE_CU_COMM_MB_CTL__B                                       0
#define    OFDM_FE_CU_COMM_MB_CTL__W                                       1
#define    OFDM_FE_CU_COMM_MB_CTL__M                                       0x1
#define    OFDM_FE_CU_COMM_MB_CTL__PRE                                     0x0
#define      OFDM_FE_CU_COMM_MB_CTL_OFF                                    0x0
#define      OFDM_FE_CU_COMM_MB_CTL_ON                                     0x1
#define    OFDM_FE_CU_COMM_MB_OBS__B                                       1
#define    OFDM_FE_CU_COMM_MB_OBS__W                                       1
#define    OFDM_FE_CU_COMM_MB_OBS__M                                       0x2
#define    OFDM_FE_CU_COMM_MB_OBS__PRE                                     0x0
#define      OFDM_FE_CU_COMM_MB_OBS_OFF                                    0x0
#define      OFDM_FE_CU_COMM_MB_OBS_ON                                     0x2

#define  OFDM_FE_CU_COMM_INT_REQ__A                                        0x2010004
#define  OFDM_FE_CU_COMM_INT_REQ__W                                        1
#define  OFDM_FE_CU_COMM_INT_REQ__M                                        0x1
#define  OFDM_FE_CU_COMM_INT_REQ__PRE                                      0x0
#define  OFDM_FE_CU_COMM_INT_STA__A                                        0x2010005
#define  OFDM_FE_CU_COMM_INT_STA__W                                        4
#define  OFDM_FE_CU_COMM_INT_STA__M                                        0xF
#define  OFDM_FE_CU_COMM_INT_STA__PRE                                      0x0
#define    OFDM_FE_CU_COMM_INT_STA_FE_START__B                             0
#define    OFDM_FE_CU_COMM_INT_STA_FE_START__W                             1
#define    OFDM_FE_CU_COMM_INT_STA_FE_START__M                             0x1
#define    OFDM_FE_CU_COMM_INT_STA_FE_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_STA_FT_START__B                             1
#define    OFDM_FE_CU_COMM_INT_STA_FT_START__W                             1
#define    OFDM_FE_CU_COMM_INT_STA_FT_START__M                             0x2
#define    OFDM_FE_CU_COMM_INT_STA_FT_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_STA_SB_START__B                             2
#define    OFDM_FE_CU_COMM_INT_STA_SB_START__W                             1
#define    OFDM_FE_CU_COMM_INT_STA_SB_START__M                             0x4
#define    OFDM_FE_CU_COMM_INT_STA_SB_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_STA_NF_READY__B                             3
#define    OFDM_FE_CU_COMM_INT_STA_NF_READY__W                             1
#define    OFDM_FE_CU_COMM_INT_STA_NF_READY__M                             0x8
#define    OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE                           0x0

#define  OFDM_FE_CU_COMM_INT_MSK__A                                        0x2010006
#define  OFDM_FE_CU_COMM_INT_MSK__W                                        4
#define  OFDM_FE_CU_COMM_INT_MSK__M                                        0xF
#define  OFDM_FE_CU_COMM_INT_MSK__PRE                                      0x0
#define    OFDM_FE_CU_COMM_INT_MSK_FE_START__B                             0
#define    OFDM_FE_CU_COMM_INT_MSK_FE_START__W                             1
#define    OFDM_FE_CU_COMM_INT_MSK_FE_START__M                             0x1
#define    OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_MSK_FT_START__B                             1
#define    OFDM_FE_CU_COMM_INT_MSK_FT_START__W                             1
#define    OFDM_FE_CU_COMM_INT_MSK_FT_START__M                             0x2
#define    OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_MSK_SB_START__B                             2
#define    OFDM_FE_CU_COMM_INT_MSK_SB_START__W                             1
#define    OFDM_FE_CU_COMM_INT_MSK_SB_START__M                             0x4
#define    OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_MSK_NF_READY__B                             3
#define    OFDM_FE_CU_COMM_INT_MSK_NF_READY__W                             1
#define    OFDM_FE_CU_COMM_INT_MSK_NF_READY__M                             0x8
#define    OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE                           0x0

#define  OFDM_FE_CU_COMM_INT_STM__A                                        0x2010007
#define  OFDM_FE_CU_COMM_INT_STM__W                                        4
#define  OFDM_FE_CU_COMM_INT_STM__M                                        0xF
#define  OFDM_FE_CU_COMM_INT_STM__PRE                                      0x0
#define    OFDM_FE_CU_COMM_INT_STM_FE_START__B                             0
#define    OFDM_FE_CU_COMM_INT_STM_FE_START__W                             1
#define    OFDM_FE_CU_COMM_INT_STM_FE_START__M                             0x1
#define    OFDM_FE_CU_COMM_INT_STM_FE_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_STM_FT_START__B                             1
#define    OFDM_FE_CU_COMM_INT_STM_FT_START__W                             1
#define    OFDM_FE_CU_COMM_INT_STM_FT_START__M                             0x2
#define    OFDM_FE_CU_COMM_INT_STM_FT_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_STM_SB_START__B                             2
#define    OFDM_FE_CU_COMM_INT_STM_SB_START__W                             1
#define    OFDM_FE_CU_COMM_INT_STM_SB_START__M                             0x4
#define    OFDM_FE_CU_COMM_INT_STM_SB_START__PRE                           0x0
#define    OFDM_FE_CU_COMM_INT_STM_NF_READY__B                             3
#define    OFDM_FE_CU_COMM_INT_STM_NF_READY__W                             1
#define    OFDM_FE_CU_COMM_INT_STM_NF_READY__M                             0x8
#define    OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE                           0x0

#define  OFDM_FE_CU_MODE__A                                                0x2010010
#define  OFDM_FE_CU_MODE__W                                                8
#define  OFDM_FE_CU_MODE__M                                                0xFF
#define  OFDM_FE_CU_MODE__PRE                                              0x20

#define    OFDM_FE_CU_MODE_FFT__B                                          0
#define    OFDM_FE_CU_MODE_FFT__W                                          1
#define    OFDM_FE_CU_MODE_FFT__M                                          0x1
#define    OFDM_FE_CU_MODE_FFT__PRE                                        0x0
#define      OFDM_FE_CU_MODE_FFT_M8K                                       0x0
#define      OFDM_FE_CU_MODE_FFT_M2K                                       0x1

#define    OFDM_FE_CU_MODE_COR__B                                          1
#define    OFDM_FE_CU_MODE_COR__W                                          1
#define    OFDM_FE_CU_MODE_COR__M                                          0x2
#define    OFDM_FE_CU_MODE_COR__PRE                                        0x0
#define      OFDM_FE_CU_MODE_COR_OFF                                       0x0
#define      OFDM_FE_CU_MODE_COR_ON                                        0x2

#define    OFDM_FE_CU_MODE_IFD__B                                          2
#define    OFDM_FE_CU_MODE_IFD__W                                          1
#define    OFDM_FE_CU_MODE_IFD__M                                          0x4
#define    OFDM_FE_CU_MODE_IFD__PRE                                        0x0
#define      OFDM_FE_CU_MODE_IFD_ENABLE                                    0x0
#define      OFDM_FE_CU_MODE_IFD_DISABLE                                   0x4

#define    OFDM_FE_CU_MODE_SEL__B                                          3
#define    OFDM_FE_CU_MODE_SEL__W                                          1
#define    OFDM_FE_CU_MODE_SEL__M                                          0x8
#define    OFDM_FE_CU_MODE_SEL__PRE                                        0x0
#define      OFDM_FE_CU_MODE_SEL_COR                                       0x0
#define      OFDM_FE_CU_MODE_SEL_COR_NFC                                   0x8

#define    OFDM_FE_CU_MODE_FES__B                                          4
#define    OFDM_FE_CU_MODE_FES__W                                          1
#define    OFDM_FE_CU_MODE_FES__M                                          0x10
#define    OFDM_FE_CU_MODE_FES__PRE                                        0x0
#define      OFDM_FE_CU_MODE_FES_SEL_RST                                   0x0
#define      OFDM_FE_CU_MODE_FES_SEL_UPD                                   0x10
#define    OFDM_FE_CU_MODE_AVG__B                                          5
#define    OFDM_FE_CU_MODE_AVG__W                                          1
#define    OFDM_FE_CU_MODE_AVG__M                                          0x20
#define    OFDM_FE_CU_MODE_AVG__PRE                                        0x20
#define      OFDM_FE_CU_MODE_AVG_OFF                                       0x0
#define      OFDM_FE_CU_MODE_AVG_ON                                        0x20
#define    OFDM_FE_CU_MODE_SHF_ENA__B                                      6
#define    OFDM_FE_CU_MODE_SHF_ENA__W                                      1
#define    OFDM_FE_CU_MODE_SHF_ENA__M                                      0x40
#define    OFDM_FE_CU_MODE_SHF_ENA__PRE                                    0x0
#define      OFDM_FE_CU_MODE_SHF_ENA_OFF                                   0x0
#define      OFDM_FE_CU_MODE_SHF_ENA_ON                                    0x40
#define    OFDM_FE_CU_MODE_SHF_DIR__B                                      7
#define    OFDM_FE_CU_MODE_SHF_DIR__W                                      1
#define    OFDM_FE_CU_MODE_SHF_DIR__M                                      0x80
#define    OFDM_FE_CU_MODE_SHF_DIR__PRE                                    0x0
#define      OFDM_FE_CU_MODE_SHF_DIR_POS                                   0x0
#define      OFDM_FE_CU_MODE_SHF_DIR_NEG                                   0x80


#define  OFDM_FE_CU_FRM_CNT_RST__A                                         0x2010011
#define  OFDM_FE_CU_FRM_CNT_RST__W                                         15
#define  OFDM_FE_CU_FRM_CNT_RST__M                                         0x7FFF
#define  OFDM_FE_CU_FRM_CNT_RST__PRE                                       0x20FF

#define  OFDM_FE_CU_FRM_CNT_STR__A                                         0x2010012
#define  OFDM_FE_CU_FRM_CNT_STR__W                                         15
#define  OFDM_FE_CU_FRM_CNT_STR__M                                         0x7FFF
#define  OFDM_FE_CU_FRM_CNT_STR__PRE                                       0x1E

#define  OFDM_FE_CU_FRM_SMP_CNT__A                                         0x2010013
#define  OFDM_FE_CU_FRM_SMP_CNT__W                                         15
#define  OFDM_FE_CU_FRM_SMP_CNT__M                                         0x7FFF
#define  OFDM_FE_CU_FRM_SMP_CNT__PRE                                       0x0

#define  OFDM_FE_CU_FRM_SMB_CNT__A                                         0x2010014
#define  OFDM_FE_CU_FRM_SMB_CNT__W                                         16
#define  OFDM_FE_CU_FRM_SMB_CNT__M                                         0xFFFF
#define  OFDM_FE_CU_FRM_SMB_CNT__PRE                                       0x0

#define  OFDM_FE_CU_CMP_MAX_DAT__A                                         0x2010015
#define  OFDM_FE_CU_CMP_MAX_DAT__W                                         12
#define  OFDM_FE_CU_CMP_MAX_DAT__M                                         0xFFF
#define  OFDM_FE_CU_CMP_MAX_DAT__PRE                                       0x0

#define  OFDM_FE_CU_CMP_MAX_ADR__A                                         0x2010016
#define  OFDM_FE_CU_CMP_MAX_ADR__W                                         10
#define  OFDM_FE_CU_CMP_MAX_ADR__M                                         0x3FF
#define  OFDM_FE_CU_CMP_MAX_ADR__PRE                                       0x0

#define  OFDM_FE_CU_CMP_MAX_RE__A                                          0x2010017
#define  OFDM_FE_CU_CMP_MAX_RE__W                                          12
#define  OFDM_FE_CU_CMP_MAX_RE__M                                          0xFFF
#define  OFDM_FE_CU_CMP_MAX_RE__PRE                                        0x0

#define  OFDM_FE_CU_CMP_MAX_IM__A                                          0x2010018
#define  OFDM_FE_CU_CMP_MAX_IM__W                                          12
#define  OFDM_FE_CU_CMP_MAX_IM__M                                          0xFFF
#define  OFDM_FE_CU_CMP_MAX_IM__PRE                                        0x0

#define  OFDM_FE_CU_BUF_NFC_DEL__A                                         0x201001F
#define  OFDM_FE_CU_BUF_NFC_DEL__W                                         14
#define  OFDM_FE_CU_BUF_NFC_DEL__M                                         0x3FFF
#define  OFDM_FE_CU_BUF_NFC_DEL__PRE                                       0x0

#define  OFDM_FE_CU_CTR_NFC_ICR__A                                         0x2010020
#define  OFDM_FE_CU_CTR_NFC_ICR__W                                         5
#define  OFDM_FE_CU_CTR_NFC_ICR__M                                         0x1F
#define  OFDM_FE_CU_CTR_NFC_ICR__PRE                                       0x1

#define  OFDM_FE_CU_CTR_NFC_OCR__A                                         0x2010021
#define  OFDM_FE_CU_CTR_NFC_OCR__W                                         15
#define  OFDM_FE_CU_CTR_NFC_OCR__M                                         0x7FFF
#define  OFDM_FE_CU_CTR_NFC_OCR__PRE                                       0x61A8

#define  OFDM_FE_CU_CTR_NFC_CNT__A                                         0x2010022
#define  OFDM_FE_CU_CTR_NFC_CNT__W                                         15
#define  OFDM_FE_CU_CTR_NFC_CNT__M                                         0x7FFF
#define  OFDM_FE_CU_CTR_NFC_CNT__PRE                                       0x0

#define  OFDM_FE_CU_CTR_NFC_STS__A                                         0x2010023
#define  OFDM_FE_CU_CTR_NFC_STS__W                                         3
#define  OFDM_FE_CU_CTR_NFC_STS__M                                         0x7
#define  OFDM_FE_CU_CTR_NFC_STS__PRE                                       0x0
#define    OFDM_FE_CU_CTR_NFC_STS_RUN                                      0x0
#define    OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA                              0x1
#define    OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA                              0x2
#define    OFDM_FE_CU_CTR_NFC_STS_CNT_MAX                                  0x4


#define  OFDM_FE_CU_DIV_NFC_REA__A                                         0x2010024
#define  OFDM_FE_CU_DIV_NFC_REA__W                                         14
#define  OFDM_FE_CU_DIV_NFC_REA__M                                         0x3FFF
#define  OFDM_FE_CU_DIV_NFC_REA__PRE                                       0x0

#define  OFDM_FE_CU_DIV_NFC_IMA__A                                         0x2010025
#define  OFDM_FE_CU_DIV_NFC_IMA__W                                         14
#define  OFDM_FE_CU_DIV_NFC_IMA__M                                         0x3FFF
#define  OFDM_FE_CU_DIV_NFC_IMA__PRE                                       0x0

#define  OFDM_FE_CU_FRM_CNT_UPD__A                                         0x2010026
#define  OFDM_FE_CU_FRM_CNT_UPD__W                                         15
#define  OFDM_FE_CU_FRM_CNT_UPD__M                                         0x7FFF
#define  OFDM_FE_CU_FRM_CNT_UPD__PRE                                       0x20FF

#define  OFDM_FE_CU_DIV_NFC_CLP__A                                         0x2010027
#define  OFDM_FE_CU_DIV_NFC_CLP__W                                         2
#define  OFDM_FE_CU_DIV_NFC_CLP__M                                         0x3
#define  OFDM_FE_CU_DIV_NFC_CLP__PRE                                       0x0
#define    OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11                                 0x0
#define    OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12                                 0x1
#define    OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13                                 0x2
#define    OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14                                 0x3


#define  OFDM_FE_CU_CMP_MAX_32__A                                          0x2010028
#define  OFDM_FE_CU_CMP_MAX_32__W                                          12
#define  OFDM_FE_CU_CMP_MAX_32__M                                          0xFFF
#define  OFDM_FE_CU_CMP_MAX_32__PRE                                        0x0

#define  OFDM_FE_CU_CMP_MAX_16__A                                          0x2010029
#define  OFDM_FE_CU_CMP_MAX_16__W                                          12
#define  OFDM_FE_CU_CMP_MAX_16__M                                          0xFFF
#define  OFDM_FE_CU_CMP_MAX_16__PRE                                        0x0

#define  OFDM_FE_CU_CMP_MAX_8__A                                           0x201002A
#define  OFDM_FE_CU_CMP_MAX_8__W                                           12
#define  OFDM_FE_CU_CMP_MAX_8__M                                           0xFFF
#define  OFDM_FE_CU_CMP_MAX_8__PRE                                         0x0

#define  OFDM_FE_CU_CMP_MAX_4__A                                           0x201002B
#define  OFDM_FE_CU_CMP_MAX_4__W                                           12
#define  OFDM_FE_CU_CMP_MAX_4__M                                           0xFFF
#define  OFDM_FE_CU_CMP_MAX_4__PRE                                         0x0

#define  OFDM_FE_CU_CMP_SUM_32_RE__A                                       0x201002C
#define  OFDM_FE_CU_CMP_SUM_32_RE__W                                       14
#define  OFDM_FE_CU_CMP_SUM_32_RE__M                                       0x3FFF
#define  OFDM_FE_CU_CMP_SUM_32_RE__PRE                                     0x0

#define  OFDM_FE_CU_CMP_SUM_32_IM__A                                       0x201002D
#define  OFDM_FE_CU_CMP_SUM_32_IM__W                                       14
#define  OFDM_FE_CU_CMP_SUM_32_IM__M                                       0x3FFF
#define  OFDM_FE_CU_CMP_SUM_32_IM__PRE                                     0x0

#define  OFDM_FE_CU_CMP_SUM_16_RE__A                                       0x201002E
#define  OFDM_FE_CU_CMP_SUM_16_RE__W                                       14
#define  OFDM_FE_CU_CMP_SUM_16_RE__M                                       0x3FFF
#define  OFDM_FE_CU_CMP_SUM_16_RE__PRE                                     0x0

#define  OFDM_FE_CU_CMP_SUM_16_IM__A                                       0x201002F
#define  OFDM_FE_CU_CMP_SUM_16_IM__W                                       14
#define  OFDM_FE_CU_CMP_SUM_16_IM__M                                       0x3FFF
#define  OFDM_FE_CU_CMP_SUM_16_IM__PRE                                     0x0

#define  OFDM_FE_CU_CMP_SUM_8_RE__A                                        0x2010030
#define  OFDM_FE_CU_CMP_SUM_8_RE__W                                        14
#define  OFDM_FE_CU_CMP_SUM_8_RE__M                                        0x3FFF
#define  OFDM_FE_CU_CMP_SUM_8_RE__PRE                                      0x0

#define  OFDM_FE_CU_CMP_SUM_8_IM__A                                        0x2010031
#define  OFDM_FE_CU_CMP_SUM_8_IM__W                                        14
#define  OFDM_FE_CU_CMP_SUM_8_IM__M                                        0x3FFF
#define  OFDM_FE_CU_CMP_SUM_8_IM__PRE                                      0x0

#define  OFDM_FE_CU_CMP_SUM_4_RE__A                                        0x2010032
#define  OFDM_FE_CU_CMP_SUM_4_RE__W                                        14
#define  OFDM_FE_CU_CMP_SUM_4_RE__M                                        0x3FFF
#define  OFDM_FE_CU_CMP_SUM_4_RE__PRE                                      0x0

#define  OFDM_FE_CU_CMP_SUM_4_IM__A                                        0x2010033
#define  OFDM_FE_CU_CMP_SUM_4_IM__W                                        14
#define  OFDM_FE_CU_CMP_SUM_4_IM__M                                        0x3FFF
#define  OFDM_FE_CU_CMP_SUM_4_IM__PRE                                      0x0



#define  OFDM_FE_CU_BUF_RAM__A                                             0x2020000



#define  OFDM_FE_CU_CMP_RAM__A                                             0x2030000





#define  OFDM_FT_COMM_EXEC__A                                              0x2400000
#define  OFDM_FT_COMM_EXEC__W                                              3
#define  OFDM_FT_COMM_EXEC__M                                              0x7
#define  OFDM_FT_COMM_EXEC__PRE                                            0x0
#define    OFDM_FT_COMM_EXEC_STOP                                          0x0
#define    OFDM_FT_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_FT_COMM_EXEC_HOLD                                          0x2
#define    OFDM_FT_COMM_EXEC_STEP                                          0x3
#define    OFDM_FT_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_FT_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_FT_COMM_STATE__A                                             0x2400001
#define  OFDM_FT_COMM_STATE__W                                             16
#define  OFDM_FT_COMM_STATE__M                                             0xFFFF
#define  OFDM_FT_COMM_STATE__PRE                                           0x0
#define  OFDM_FT_COMM_MB__A                                                0x2400002
#define  OFDM_FT_COMM_MB__W                                                16
#define  OFDM_FT_COMM_MB__M                                                0xFFFF
#define  OFDM_FT_COMM_MB__PRE                                              0x0



#define  OFDM_FT_TOP_COMM_EXEC__A                                          0x2410000
#define  OFDM_FT_TOP_COMM_EXEC__W                                          3
#define  OFDM_FT_TOP_COMM_EXEC__M                                          0x7
#define  OFDM_FT_TOP_COMM_EXEC__PRE                                        0x0
#define    OFDM_FT_TOP_COMM_EXEC_STOP                                      0x0
#define    OFDM_FT_TOP_COMM_EXEC_ACTIVE                                    0x1
#define    OFDM_FT_TOP_COMM_EXEC_HOLD                                      0x2
#define    OFDM_FT_TOP_COMM_EXEC_STEP                                      0x3

#define  OFDM_FT_TOP_COMM_MB__A                                            0x2410002
#define  OFDM_FT_TOP_COMM_MB__W                                            2
#define  OFDM_FT_TOP_COMM_MB__M                                            0x3
#define  OFDM_FT_TOP_COMM_MB__PRE                                          0x0
#define    OFDM_FT_TOP_COMM_MB_CTL__B                                      0
#define    OFDM_FT_TOP_COMM_MB_CTL__W                                      1
#define    OFDM_FT_TOP_COMM_MB_CTL__M                                      0x1
#define    OFDM_FT_TOP_COMM_MB_CTL__PRE                                    0x0
#define      OFDM_FT_TOP_COMM_MB_CTL_OFF                                   0x0
#define      OFDM_FT_TOP_COMM_MB_CTL_ON                                    0x1
#define    OFDM_FT_TOP_COMM_MB_OBS__B                                      1
#define    OFDM_FT_TOP_COMM_MB_OBS__W                                      1
#define    OFDM_FT_TOP_COMM_MB_OBS__M                                      0x2
#define    OFDM_FT_TOP_COMM_MB_OBS__PRE                                    0x0
#define      OFDM_FT_TOP_COMM_MB_OBS_OFF                                   0x0
#define      OFDM_FT_TOP_COMM_MB_OBS_ON                                    0x2


#define  OFDM_FT_TOP_MODE_2K__A                                            0x2410010
#define  OFDM_FT_TOP_MODE_2K__W                                            1
#define  OFDM_FT_TOP_MODE_2K__M                                            0x1
#define  OFDM_FT_TOP_MODE_2K__PRE                                          0x0
#define    OFDM_FT_TOP_MODE_2K_MODE_8K                                     0x0
#define    OFDM_FT_TOP_MODE_2K_MODE_2K                                     0x1


#define  OFDM_FT_TOP_NORM_OFF__A                                           0x2410016
#define  OFDM_FT_TOP_NORM_OFF__W                                           4
#define  OFDM_FT_TOP_NORM_OFF__M                                           0xF
#define  OFDM_FT_TOP_NORM_OFF__PRE                                         0x2



#define  OFDM_FT_0TO2_0_RAM__A                                             0x2420000



#define  OFDM_FT_0TO2_1_RAM__A                                             0x2430000



#define  OFDM_FT_0TO2_2_RAM__A                                             0x2440000



#define  OFDM_FT_3TO7_0_RAM__A                                             0x2450000



#define  OFDM_FT_3TO7_1_RAM__A                                             0x2460000





#define  OFDM_LC_COMM_EXEC__A                                              0x3800000
#define  OFDM_LC_COMM_EXEC__W                                              3
#define  OFDM_LC_COMM_EXEC__M                                              0x7
#define  OFDM_LC_COMM_EXEC__PRE                                            0x0
#define    OFDM_LC_COMM_EXEC_STOP                                          0x0
#define    OFDM_LC_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_LC_COMM_EXEC_HOLD                                          0x2
#define    OFDM_LC_COMM_EXEC_STEP                                          0x3
#define    OFDM_LC_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_LC_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_LC_COMM_STATE__A                                             0x3800001
#define  OFDM_LC_COMM_STATE__W                                             16
#define  OFDM_LC_COMM_STATE__M                                             0xFFFF
#define  OFDM_LC_COMM_STATE__PRE                                           0x0
#define  OFDM_LC_COMM_MB__A                                                0x3800002
#define  OFDM_LC_COMM_MB__W                                                16
#define  OFDM_LC_COMM_MB__M                                                0xFFFF
#define  OFDM_LC_COMM_MB__PRE                                              0x0
#define  OFDM_LC_COMM_INT_REQ__A                                           0x3800004
#define  OFDM_LC_COMM_INT_REQ__W                                           16
#define  OFDM_LC_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_LC_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_LC_COMM_INT_REQ_CT_REQ__B                                  6
#define    OFDM_LC_COMM_INT_REQ_CT_REQ__W                                  1
#define    OFDM_LC_COMM_INT_REQ_CT_REQ__M                                  0x40
#define    OFDM_LC_COMM_INT_REQ_CT_REQ__PRE                                0x0

#define  OFDM_LC_COMM_INT_STA__A                                           0x3800005
#define  OFDM_LC_COMM_INT_STA__W                                           16
#define  OFDM_LC_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_LC_COMM_INT_STA__PRE                                         0x0
#define  OFDM_LC_COMM_INT_MSK__A                                           0x3800006
#define  OFDM_LC_COMM_INT_MSK__W                                           16
#define  OFDM_LC_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_LC_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_LC_COMM_INT_STM__A                                           0x3800007
#define  OFDM_LC_COMM_INT_STM__W                                           16
#define  OFDM_LC_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_LC_COMM_INT_STM__PRE                                         0x0
#define    OFDM_LC_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_LC_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_LC_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_LC_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_LC_CT_COMM_EXEC__A                                           0x3810000
#define  OFDM_LC_CT_COMM_EXEC__W                                           3
#define  OFDM_LC_CT_COMM_EXEC__M                                           0x7
#define  OFDM_LC_CT_COMM_EXEC__PRE                                         0x0
#define    OFDM_LC_CT_COMM_EXEC_STOP                                       0x0
#define    OFDM_LC_CT_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_LC_CT_COMM_EXEC_HOLD                                       0x2
#define    OFDM_LC_CT_COMM_EXEC_STEP                                       0x3


#define  OFDM_LC_CT_COMM_STATE__A                                          0x3810001
#define  OFDM_LC_CT_COMM_STATE__W                                          10
#define  OFDM_LC_CT_COMM_STATE__M                                          0x3FF
#define  OFDM_LC_CT_COMM_STATE__PRE                                        0x0
#define  OFDM_LC_CT_COMM_INT_REQ__A                                        0x3810004
#define  OFDM_LC_CT_COMM_INT_REQ__W                                        1
#define  OFDM_LC_CT_COMM_INT_REQ__M                                        0x1
#define  OFDM_LC_CT_COMM_INT_REQ__PRE                                      0x0
#define  OFDM_LC_CT_COMM_INT_STA__A                                        0x3810005
#define  OFDM_LC_CT_COMM_INT_STA__W                                        1
#define  OFDM_LC_CT_COMM_INT_STA__M                                        0x1
#define  OFDM_LC_CT_COMM_INT_STA__PRE                                      0x0
#define    OFDM_LC_CT_COMM_INT_STA_REQUEST__B                              0
#define    OFDM_LC_CT_COMM_INT_STA_REQUEST__W                              1
#define    OFDM_LC_CT_COMM_INT_STA_REQUEST__M                              0x1
#define    OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE                            0x0

#define  OFDM_LC_CT_COMM_INT_MSK__A                                        0x3810006
#define  OFDM_LC_CT_COMM_INT_MSK__W                                        1
#define  OFDM_LC_CT_COMM_INT_MSK__M                                        0x1
#define  OFDM_LC_CT_COMM_INT_MSK__PRE                                      0x0
#define    OFDM_LC_CT_COMM_INT_MSK_REQUEST__B                              0
#define    OFDM_LC_CT_COMM_INT_MSK_REQUEST__W                              1
#define    OFDM_LC_CT_COMM_INT_MSK_REQUEST__M                              0x1
#define    OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE                            0x0

#define  OFDM_LC_CT_COMM_INT_STM__A                                        0x3810007
#define  OFDM_LC_CT_COMM_INT_STM__W                                        1
#define  OFDM_LC_CT_COMM_INT_STM__M                                        0x1
#define  OFDM_LC_CT_COMM_INT_STM__PRE                                      0x0
#define    OFDM_LC_CT_COMM_INT_STM_REQUEST__B                              0
#define    OFDM_LC_CT_COMM_INT_STM_REQUEST__W                              1
#define    OFDM_LC_CT_COMM_INT_STM_REQUEST__M                              0x1
#define    OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE                            0x0


#define  OFDM_LC_CT_CTL_STK_0__A                                           0x3810010
#define  OFDM_LC_CT_CTL_STK_0__W                                           10
#define  OFDM_LC_CT_CTL_STK_0__M                                           0x3FF
#define  OFDM_LC_CT_CTL_STK_0__PRE                                         0x0

#define  OFDM_LC_CT_CTL_STK_1__A                                           0x3810011
#define  OFDM_LC_CT_CTL_STK_1__W                                           10
#define  OFDM_LC_CT_CTL_STK_1__M                                           0x3FF
#define  OFDM_LC_CT_CTL_STK_1__PRE                                         0x0

#define  OFDM_LC_CT_CTL_STK_2__A                                           0x3810012
#define  OFDM_LC_CT_CTL_STK_2__W                                           10
#define  OFDM_LC_CT_CTL_STK_2__M                                           0x3FF
#define  OFDM_LC_CT_CTL_STK_2__PRE                                         0x0

#define  OFDM_LC_CT_CTL_STK_3__A                                           0x3810013
#define  OFDM_LC_CT_CTL_STK_3__W                                           10
#define  OFDM_LC_CT_CTL_STK_3__M                                           0x3FF
#define  OFDM_LC_CT_CTL_STK_3__PRE                                         0x0

#define  OFDM_LC_CT_CTL_BPT_IDX__A                                         0x381001F
#define  OFDM_LC_CT_CTL_BPT_IDX__W                                         1
#define  OFDM_LC_CT_CTL_BPT_IDX__M                                         0x1
#define  OFDM_LC_CT_CTL_BPT_IDX__PRE                                       0x0

#define  OFDM_LC_CT_CTL_BPT__A                                             0x3810020
#define  OFDM_LC_CT_CTL_BPT__W                                             10
#define  OFDM_LC_CT_CTL_BPT__M                                             0x3FF
#define  OFDM_LC_CT_CTL_BPT__PRE                                           0x0



#define  OFDM_LC_RA_RAM__A                                                 0x3820000




#define  OFDM_LC_IF_RAM_TRP_BPT0_0__A                                      0x3830000
#define  OFDM_LC_IF_RAM_TRP_BPT0_0__W                                      12
#define  OFDM_LC_IF_RAM_TRP_BPT0_0__M                                      0xFFF
#define  OFDM_LC_IF_RAM_TRP_BPT0_0__PRE                                    0x0

#define  OFDM_LC_IF_RAM_TRP_BPT0_1__A                                      0x3830001
#define  OFDM_LC_IF_RAM_TRP_BPT0_1__W                                      12
#define  OFDM_LC_IF_RAM_TRP_BPT0_1__M                                      0xFFF
#define  OFDM_LC_IF_RAM_TRP_BPT0_1__PRE                                    0x0

#define  OFDM_LC_IF_RAM_TRP_STKU_0__A                                      0x3830002
#define  OFDM_LC_IF_RAM_TRP_STKU_0__W                                      12
#define  OFDM_LC_IF_RAM_TRP_STKU_0__M                                      0xFFF
#define  OFDM_LC_IF_RAM_TRP_STKU_0__PRE                                    0x0

#define  OFDM_LC_IF_RAM_TRP_STKU_1__A                                      0x3830004
#define  OFDM_LC_IF_RAM_TRP_STKU_1__W                                      12
#define  OFDM_LC_IF_RAM_TRP_STKU_1__M                                      0xFFF
#define  OFDM_LC_IF_RAM_TRP_STKU_1__PRE                                    0x0

#define  OFDM_LC_IF_RAM_TRP_WARM_0__A                                      0x3830006
#define  OFDM_LC_IF_RAM_TRP_WARM_0__W                                      12
#define  OFDM_LC_IF_RAM_TRP_WARM_0__M                                      0xFFF
#define  OFDM_LC_IF_RAM_TRP_WARM_0__PRE                                    0x0

#define  OFDM_LC_IF_RAM_TRP_WARM_1__A                                      0x3830007
#define  OFDM_LC_IF_RAM_TRP_WARM_1__W                                      12
#define  OFDM_LC_IF_RAM_TRP_WARM_1__M                                      0xFFF
#define  OFDM_LC_IF_RAM_TRP_WARM_1__PRE                                    0x0







#define  OFDM_LC_RA_RAM_PROC_DELAY_IF__A                                   0x3820006
#define  OFDM_LC_RA_RAM_PROC_DELAY_IF__W                                   16
#define  OFDM_LC_RA_RAM_PROC_DELAY_IF__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE                                 0xFFE6
#define  OFDM_LC_RA_RAM_PROC_DELAY_FS__A                                   0x3820007
#define  OFDM_LC_RA_RAM_PROC_DELAY_FS__W                                   16
#define  OFDM_LC_RA_RAM_PROC_DELAY_FS__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE                                 0xFFE3
#define  OFDM_LC_RA_RAM_LOCK_TH_CRMM__A                                    0x3820008
#define  OFDM_LC_RA_RAM_LOCK_TH_CRMM__W                                    16
#define  OFDM_LC_RA_RAM_LOCK_TH_CRMM__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE                                  0xC8
#define  OFDM_LC_RA_RAM_LOCK_TH_SRMM__A                                    0x3820009
#define  OFDM_LC_RA_RAM_LOCK_TH_SRMM__W                                    16
#define  OFDM_LC_RA_RAM_LOCK_TH_SRMM__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE                                  0x46
#define  OFDM_LC_RA_RAM_LOCK_COUNT__A                                      0x382000A
#define  OFDM_LC_RA_RAM_LOCK_COUNT__W                                      16
#define  OFDM_LC_RA_RAM_LOCK_COUNT__M                                      0xFFFF
#define  OFDM_LC_RA_RAM_LOCK_COUNT__PRE                                    0x0
#define  OFDM_LC_RA_RAM_CPRTOFS_NOM__A                                     0x382000B
#define  OFDM_LC_RA_RAM_CPRTOFS_NOM__W                                     16
#define  OFDM_LC_RA_RAM_CPRTOFS_NOM__M                                     0xFFFF
#define  OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE                                   0x0
#define  OFDM_LC_RA_RAM_IFINCR_NOM_L__A                                    0x382000C
#define  OFDM_LC_RA_RAM_IFINCR_NOM_L__W                                    16
#define  OFDM_LC_RA_RAM_IFINCR_NOM_L__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE                                  0x0
#define  OFDM_LC_RA_RAM_IFINCR_NOM_H__A                                    0x382000D
#define  OFDM_LC_RA_RAM_IFINCR_NOM_H__W                                    16
#define  OFDM_LC_RA_RAM_IFINCR_NOM_H__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE                                  0x0
#define  OFDM_LC_RA_RAM_FSINCR_NOM_L__A                                    0x382000E
#define  OFDM_LC_RA_RAM_FSINCR_NOM_L__W                                    16
#define  OFDM_LC_RA_RAM_FSINCR_NOM_L__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE                                  0x0
#define  OFDM_LC_RA_RAM_FSINCR_NOM_H__A                                    0x382000F
#define  OFDM_LC_RA_RAM_FSINCR_NOM_H__W                                    16
#define  OFDM_LC_RA_RAM_FSINCR_NOM_H__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE                                  0x0
#define  OFDM_LC_RA_RAM_MODE_2K__A                                         0x3820010
#define  OFDM_LC_RA_RAM_MODE_2K__W                                         16
#define  OFDM_LC_RA_RAM_MODE_2K__M                                         0xFFFF
#define  OFDM_LC_RA_RAM_MODE_2K__PRE                                       0x0
#define  OFDM_LC_RA_RAM_MODE_GUARD__A                                      0x3820011
#define  OFDM_LC_RA_RAM_MODE_GUARD__W                                      16
#define  OFDM_LC_RA_RAM_MODE_GUARD__M                                      0xFFFF
#define  OFDM_LC_RA_RAM_MODE_GUARD__PRE                                    0x0
#define    OFDM_LC_RA_RAM_MODE_GUARD_32                                    0x0
#define    OFDM_LC_RA_RAM_MODE_GUARD_16                                    0x1
#define    OFDM_LC_RA_RAM_MODE_GUARD_8                                     0x2
#define    OFDM_LC_RA_RAM_MODE_GUARD_4                                     0x3

#define  OFDM_LC_RA_RAM_MODE_ADJUST__A                                     0x3820012
#define  OFDM_LC_RA_RAM_MODE_ADJUST__W                                     16
#define  OFDM_LC_RA_RAM_MODE_ADJUST__M                                     0xFFFF
#define  OFDM_LC_RA_RAM_MODE_ADJUST__PRE                                   0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B                           0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W                           1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M                           0x1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE                         0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B                           1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W                           1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M                           0x2
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE                         0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B                              2
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W                              1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M                              0x4
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE                            0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B                             3
#define    OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W                             1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M                             0x8
#define    OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE                           0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B                             4
#define    OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W                             1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M                             0x10
#define    OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE                           0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B                          5
#define    OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W                          1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M                          0x20
#define    OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE                        0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B                             6
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W                             1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M                             0x40
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE                           0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B                             7
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W                             1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M                             0x80
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE                           0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B                             8
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W                             1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M                             0x100
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE                           0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B                        9
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W                        1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M                        0x200
#define    OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE                      0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B                       10
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W                       1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M                       0x400
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE                     0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B                       11
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W                       1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M                       0x800
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE                     0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B                      12
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W                      1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M                      0x1000
#define    OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE                    0x0
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B                      13
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W                      1
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M                      0x2000
#define    OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE                    0x0

#define  OFDM_LC_RA_RAM_RC_STS__A                                          0x3820014
#define  OFDM_LC_RA_RAM_RC_STS__W                                          16
#define  OFDM_LC_RA_RAM_RC_STS__M                                          0xFFFF
#define  OFDM_LC_RA_RAM_RC_STS__PRE                                        0x0
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A                              0x3820018
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W                              16
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M                              0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE                            0x0
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A                              0x3820019
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W                              16
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M                              0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE                            0x0
#define  OFDM_LC_RA_RAM_FILTER_SYM_SET__A                                  0x382001A
#define  OFDM_LC_RA_RAM_FILTER_SYM_SET__W                                  16
#define  OFDM_LC_RA_RAM_FILTER_SYM_SET__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE                                0x3E8
#define  OFDM_LC_RA_RAM_FILTER_SYM_CUR__A                                  0x382001B
#define  OFDM_LC_RA_RAM_FILTER_SYM_CUR__W                                  16
#define  OFDM_LC_RA_RAM_FILTER_SYM_CUR__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE                                0x0
#define  OFDM_LC_RA_RAM_DIVERSITY_DELAY__A                                 0x382001C
#define  OFDM_LC_RA_RAM_DIVERSITY_DELAY__W                                 16
#define  OFDM_LC_RA_RAM_DIVERSITY_DELAY__M                                 0xFFFF
#define  OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE                               0x3E8
#define  OFDM_LC_RA_RAM_MAX_ABS_EXP__A                                     0x382001D
#define  OFDM_LC_RA_RAM_MAX_ABS_EXP__W                                     16
#define  OFDM_LC_RA_RAM_MAX_ABS_EXP__M                                     0xFFFF
#define  OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE                                   0x10
#define  OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A                                  0x382001F
#define  OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W                                  16
#define  OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE                                0x0
#define  OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A                                  0x3820020
#define  OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W                                  16
#define  OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE                                0x0
#define  OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A                                  0x3820021
#define  OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W                                  16
#define  OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE                                0x0
#define  OFDM_LC_RA_RAM_ACTUAL_PHASE__A                                    0x3820022
#define  OFDM_LC_RA_RAM_ACTUAL_PHASE__W                                    16
#define  OFDM_LC_RA_RAM_ACTUAL_PHASE__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE                                  0x0
#define  OFDM_LC_RA_RAM_ACTUAL_DELAY__A                                    0x3820023
#define  OFDM_LC_RA_RAM_ACTUAL_DELAY__W                                    16
#define  OFDM_LC_RA_RAM_ACTUAL_DELAY__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE                                  0x0
#define  OFDM_LC_RA_RAM_ADJUST_CRMM__A                                     0x3820024
#define  OFDM_LC_RA_RAM_ADJUST_CRMM__W                                     16
#define  OFDM_LC_RA_RAM_ADJUST_CRMM__M                                     0xFFFF
#define  OFDM_LC_RA_RAM_ADJUST_CRMM__PRE                                   0x0
#define  OFDM_LC_RA_RAM_ADJUST_SRMM__A                                     0x3820025
#define  OFDM_LC_RA_RAM_ADJUST_SRMM__W                                     16
#define  OFDM_LC_RA_RAM_ADJUST_SRMM__M                                     0xFFFF
#define  OFDM_LC_RA_RAM_ADJUST_SRMM__PRE                                   0x0
#define  OFDM_LC_RA_RAM_ADJUST_PHASE__A                                    0x3820026
#define  OFDM_LC_RA_RAM_ADJUST_PHASE__W                                    16
#define  OFDM_LC_RA_RAM_ADJUST_PHASE__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_ADJUST_PHASE__PRE                                  0x0
#define  OFDM_LC_RA_RAM_ADJUST_DELAY__A                                    0x3820027
#define  OFDM_LC_RA_RAM_ADJUST_DELAY__W                                    16
#define  OFDM_LC_RA_RAM_ADJUST_DELAY__M                                    0xFFFF
#define  OFDM_LC_RA_RAM_ADJUST_DELAY__PRE                                  0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A                                 0x3820028
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W                                 16
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M                                 0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE                               0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A                                 0x3820029
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W                                 16
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M                                 0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE                               0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A                               0x382002A
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W                               16
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M                               0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE                             0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A                               0x382002B
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W                               16
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M                               0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE                             0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A                               0x382002C
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W                               16
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M                               0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE                             0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A                                0x382002D
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_BACKUP__A                                   0x382002E
#define  OFDM_LC_RA_RAM_FILTER_BACKUP__W                                   16
#define  OFDM_LC_RA_RAM_FILTER_BACKUP__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_BACKUP__PRE                                 0x4
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A                                  0x3820030
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W                                  16
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE                                0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A                                  0x3820031
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W                                  16
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE                                0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A                                0x3820032
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE                              0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A                                0x3820033
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE                              0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A                                0x3820034
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE                              0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A                                 0x3820035
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W                                 16
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M                                 0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE                               0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A                                  0x3820038
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W                                  16
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE                                0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A                                  0x3820039
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W                                  16
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE                                0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A                                0x382003A
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE                              0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A                                0x382003B
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE                              0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A                                0x382003C
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W                                16
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M                                0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE                              0x0
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A                                 0x382003D
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W                                 16
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M                                 0xFFFF
#define  OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE                               0x0
#define  OFDM_LC_RA_RAM_FILTER_CRMM_A__A                                   0x3820060
#define  OFDM_LC_RA_RAM_FILTER_CRMM_A__W                                   16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_A__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE                                 0x7
#define  OFDM_LC_RA_RAM_FILTER_CRMM_B__A                                   0x3820061
#define  OFDM_LC_RA_RAM_FILTER_CRMM_B__W                                   16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_B__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE                                 0x2
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A                                0x3820062
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W                                16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A                                0x3820063
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W                                16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A                                0x3820064
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W                                16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A                                0x3820065
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W                                16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A                               0x3820066
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W                               16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A                               0x3820067
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W                               16
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_SRMM_A__A                                   0x3820068
#define  OFDM_LC_RA_RAM_FILTER_SRMM_A__W                                   16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_A__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE                                 0x4
#define  OFDM_LC_RA_RAM_FILTER_SRMM_B__A                                   0x3820069
#define  OFDM_LC_RA_RAM_FILTER_SRMM_B__W                                   16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_B__M                                   0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE                                 0x1
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A                                0x382006A
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W                                16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A                                0x382006B
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W                                16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A                                0x382006C
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W                                16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A                                0x382006D
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W                                16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M                                0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE                              0x0
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A                               0x382006E
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W                               16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A                               0x382006F
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W                               16
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_PHASE_A__A                                  0x3820070
#define  OFDM_LC_RA_RAM_FILTER_PHASE_A__W                                  16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_A__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE                                0x4
#define  OFDM_LC_RA_RAM_FILTER_PHASE_B__A                                  0x3820071
#define  OFDM_LC_RA_RAM_FILTER_PHASE_B__W                                  16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_B__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE                                0x1
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A                               0x3820072
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W                               16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A                               0x3820073
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W                               16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A                               0x3820074
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W                               16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A                               0x3820075
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W                               16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A                              0x3820076
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W                              16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M                              0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE                            0x0
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A                              0x3820077
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W                              16
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M                              0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE                            0x0
#define  OFDM_LC_RA_RAM_FILTER_DELAY_A__A                                  0x3820078
#define  OFDM_LC_RA_RAM_FILTER_DELAY_A__W                                  16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_A__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE                                0x4
#define  OFDM_LC_RA_RAM_FILTER_DELAY_B__A                                  0x3820079
#define  OFDM_LC_RA_RAM_FILTER_DELAY_B__W                                  16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_B__M                                  0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE                                0x1
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A                               0x382007A
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W                               16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A                               0x382007B
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W                               16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A                               0x382007C
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W                               16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A                               0x382007D
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W                               16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M                               0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE                             0x0
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A                              0x382007E
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W                              16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M                              0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE                            0x0
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A                              0x382007F
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W                              16
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M                              0xFFFF
#define  OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE                            0x0





#define  OFDM_SC_COMM_EXEC__A                                              0x3C00000
#define  OFDM_SC_COMM_EXEC__W                                              3
#define  OFDM_SC_COMM_EXEC__M                                              0x7
#define  OFDM_SC_COMM_EXEC__PRE                                            0x0
#define    OFDM_SC_COMM_EXEC_STOP                                          0x0
#define    OFDM_SC_COMM_EXEC_ACTIVE                                        0x1
#define    OFDM_SC_COMM_EXEC_HOLD                                          0x2
#define    OFDM_SC_COMM_EXEC_STEP                                          0x3
#define    OFDM_SC_COMM_EXEC_BYPASS_STOP                                   0x4
#define    OFDM_SC_COMM_EXEC_BYPASS_HOLD                                   0x6

#define  OFDM_SC_COMM_STATE__A                                             0x3C00001
#define  OFDM_SC_COMM_STATE__W                                             16
#define  OFDM_SC_COMM_STATE__M                                             0xFFFF
#define  OFDM_SC_COMM_STATE__PRE                                           0x0
#define  OFDM_SC_COMM_MB__A                                                0x3C00002
#define  OFDM_SC_COMM_MB__W                                                16
#define  OFDM_SC_COMM_MB__M                                                0xFFFF
#define  OFDM_SC_COMM_MB__PRE                                              0x0
#define  OFDM_SC_COMM_INT_REQ__A                                           0x3C00004
#define  OFDM_SC_COMM_INT_REQ__W                                           16
#define  OFDM_SC_COMM_INT_REQ__M                                           0xFFFF
#define  OFDM_SC_COMM_INT_REQ__PRE                                         0x0
#define    OFDM_SC_COMM_INT_REQ_CT_REQ__B                                  7
#define    OFDM_SC_COMM_INT_REQ_CT_REQ__W                                  1
#define    OFDM_SC_COMM_INT_REQ_CT_REQ__M                                  0x80
#define    OFDM_SC_COMM_INT_REQ_CT_REQ__PRE                                0x0

#define  OFDM_SC_COMM_INT_STA__A                                           0x3C00005
#define  OFDM_SC_COMM_INT_STA__W                                           16
#define  OFDM_SC_COMM_INT_STA__M                                           0xFFFF
#define  OFDM_SC_COMM_INT_STA__PRE                                         0x0
#define  OFDM_SC_COMM_INT_MSK__A                                           0x3C00006
#define  OFDM_SC_COMM_INT_MSK__W                                           16
#define  OFDM_SC_COMM_INT_MSK__M                                           0xFFFF
#define  OFDM_SC_COMM_INT_MSK__PRE                                         0x0
#define  OFDM_SC_COMM_INT_STM__A                                           0x3C00007
#define  OFDM_SC_COMM_INT_STM__W                                           16
#define  OFDM_SC_COMM_INT_STM__M                                           0xFFFF
#define  OFDM_SC_COMM_INT_STM__PRE                                         0x0
#define    OFDM_SC_COMM_INT_STM_INT_MSK__B                                 0
#define    OFDM_SC_COMM_INT_STM_INT_MSK__W                                 16
#define    OFDM_SC_COMM_INT_STM_INT_MSK__M                                 0xFFFF
#define    OFDM_SC_COMM_INT_STM_INT_MSK__PRE                               0x0



#define  OFDM_SC_CT_COMM_EXEC__A                                           0x3C10000
#define  OFDM_SC_CT_COMM_EXEC__W                                           3
#define  OFDM_SC_CT_COMM_EXEC__M                                           0x7
#define  OFDM_SC_CT_COMM_EXEC__PRE                                         0x0
#define    OFDM_SC_CT_COMM_EXEC_STOP                                       0x0
#define    OFDM_SC_CT_COMM_EXEC_ACTIVE                                     0x1
#define    OFDM_SC_CT_COMM_EXEC_HOLD                                       0x2
#define    OFDM_SC_CT_COMM_EXEC_STEP                                       0x3


#define  OFDM_SC_CT_COMM_STATE__A                                          0x3C10001
#define  OFDM_SC_CT_COMM_STATE__W                                          10
#define  OFDM_SC_CT_COMM_STATE__M                                          0x3FF
#define  OFDM_SC_CT_COMM_STATE__PRE                                        0x0
#define  OFDM_SC_CT_COMM_INT_REQ__A                                        0x3C10004
#define  OFDM_SC_CT_COMM_INT_REQ__W                                        1
#define  OFDM_SC_CT_COMM_INT_REQ__M                                        0x1
#define  OFDM_SC_CT_COMM_INT_REQ__PRE                                      0x0
#define  OFDM_SC_CT_COMM_INT_STA__A                                        0x3C10005
#define  OFDM_SC_CT_COMM_INT_STA__W                                        1
#define  OFDM_SC_CT_COMM_INT_STA__M                                        0x1
#define  OFDM_SC_CT_COMM_INT_STA__PRE                                      0x0
#define    OFDM_SC_CT_COMM_INT_STA_REQUEST__B                              0
#define    OFDM_SC_CT_COMM_INT_STA_REQUEST__W                              1
#define    OFDM_SC_CT_COMM_INT_STA_REQUEST__M                              0x1
#define    OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE                            0x0

#define  OFDM_SC_CT_COMM_INT_MSK__A                                        0x3C10006
#define  OFDM_SC_CT_COMM_INT_MSK__W                                        1
#define  OFDM_SC_CT_COMM_INT_MSK__M                                        0x1
#define  OFDM_SC_CT_COMM_INT_MSK__PRE                                      0x0
#define    OFDM_SC_CT_COMM_INT_MSK_REQUEST__B                              0
#define    OFDM_SC_CT_COMM_INT_MSK_REQUEST__W                              1
#define    OFDM_SC_CT_COMM_INT_MSK_REQUEST__M                              0x1
#define    OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE                            0x0

#define  OFDM_SC_CT_COMM_INT_STM__A                                        0x3C10007
#define  OFDM_SC_CT_COMM_INT_STM__W                                        1
#define  OFDM_SC_CT_COMM_INT_STM__M                                        0x1
#define  OFDM_SC_CT_COMM_INT_STM__PRE                                      0x0
#define    OFDM_SC_CT_COMM_INT_STM_REQUEST__B                              0
#define    OFDM_SC_CT_COMM_INT_STM_REQUEST__W                              1
#define    OFDM_SC_CT_COMM_INT_STM_REQUEST__M                              0x1
#define    OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE                            0x0


#define  OFDM_SC_CT_CTL_STK_0__A                                           0x3C10010
#define  OFDM_SC_CT_CTL_STK_0__W                                           10
#define  OFDM_SC_CT_CTL_STK_0__M                                           0x3FF
#define  OFDM_SC_CT_CTL_STK_0__PRE                                         0x0

#define  OFDM_SC_CT_CTL_STK_1__A                                           0x3C10011
#define  OFDM_SC_CT_CTL_STK_1__W                                           10
#define  OFDM_SC_CT_CTL_STK_1__M                                           0x3FF
#define  OFDM_SC_CT_CTL_STK_1__PRE                                         0x0

#define  OFDM_SC_CT_CTL_STK_2__A                                           0x3C10012
#define  OFDM_SC_CT_CTL_STK_2__W                                           10
#define  OFDM_SC_CT_CTL_STK_2__M                                           0x3FF
#define  OFDM_SC_CT_CTL_STK_2__PRE                                         0x0

#define  OFDM_SC_CT_CTL_STK_3__A                                           0x3C10013
#define  OFDM_SC_CT_CTL_STK_3__W                                           10
#define  OFDM_SC_CT_CTL_STK_3__M                                           0x3FF
#define  OFDM_SC_CT_CTL_STK_3__PRE                                         0x0

#define  OFDM_SC_CT_CTL_BPT_IDX__A                                         0x3C1001F
#define  OFDM_SC_CT_CTL_BPT_IDX__W                                         1
#define  OFDM_SC_CT_CTL_BPT_IDX__M                                         0x1
#define  OFDM_SC_CT_CTL_BPT_IDX__PRE                                       0x0

#define  OFDM_SC_CT_CTL_BPT__A                                             0x3C10020
#define  OFDM_SC_CT_CTL_BPT__W                                             13
#define  OFDM_SC_CT_CTL_BPT__M                                             0x1FFF
#define  OFDM_SC_CT_CTL_BPT__PRE                                           0x0



#define  OFDM_SC_RA_RAM__A                                                 0x3C20000




#define  OFDM_SC_IF_RAM_TRP_RST_0__A                                       0x3C30000
#define  OFDM_SC_IF_RAM_TRP_RST_0__W                                       12
#define  OFDM_SC_IF_RAM_TRP_RST_0__M                                       0xFFF
#define  OFDM_SC_IF_RAM_TRP_RST_0__PRE                                     0x0

#define  OFDM_SC_IF_RAM_TRP_RST_1__A                                       0x3C30001
#define  OFDM_SC_IF_RAM_TRP_RST_1__W                                       12
#define  OFDM_SC_IF_RAM_TRP_RST_1__M                                       0xFFF
#define  OFDM_SC_IF_RAM_TRP_RST_1__PRE                                     0x0

#define  OFDM_SC_IF_RAM_TRP_BPT0_0__A                                      0x3C30002
#define  OFDM_SC_IF_RAM_TRP_BPT0_0__W                                      12
#define  OFDM_SC_IF_RAM_TRP_BPT0_0__M                                      0xFFF
#define  OFDM_SC_IF_RAM_TRP_BPT0_0__PRE                                    0x0

#define  OFDM_SC_IF_RAM_TRP_BPT0_1__A                                      0x3C30004
#define  OFDM_SC_IF_RAM_TRP_BPT0_1__W                                      12
#define  OFDM_SC_IF_RAM_TRP_BPT0_1__M                                      0xFFF
#define  OFDM_SC_IF_RAM_TRP_BPT0_1__PRE                                    0x0

#define  OFDM_SC_IF_RAM_TRP_STKU_0__A                                      0x3C30004
#define  OFDM_SC_IF_RAM_TRP_STKU_0__W                                      12
#define  OFDM_SC_IF_RAM_TRP_STKU_0__M                                      0xFFF
#define  OFDM_SC_IF_RAM_TRP_STKU_0__PRE                                    0x0

#define  OFDM_SC_IF_RAM_TRP_STKU_1__A                                      0x3C30005
#define  OFDM_SC_IF_RAM_TRP_STKU_1__W                                      12
#define  OFDM_SC_IF_RAM_TRP_STKU_1__M                                      0xFFF
#define  OFDM_SC_IF_RAM_TRP_STKU_1__PRE                                    0x0

#define  OFDM_SC_IF_RAM_VERSION_MA_MI__A                                   0x3C30FFE
#define  OFDM_SC_IF_RAM_VERSION_MA_MI__W                                   12
#define  OFDM_SC_IF_RAM_VERSION_MA_MI__M                                   0xFFF
#define  OFDM_SC_IF_RAM_VERSION_MA_MI__PRE                                 0x0

#define  OFDM_SC_IF_RAM_VERSION_PATCH__A                                   0x3C30FFF
#define  OFDM_SC_IF_RAM_VERSION_PATCH__W                                   12
#define  OFDM_SC_IF_RAM_VERSION_PATCH__M                                   0xFFF
#define  OFDM_SC_IF_RAM_VERSION_PATCH__PRE                                 0x0







#define  OFDM_SC_RA_RAM_PARAM0__A                                          0x3C20040
#define  OFDM_SC_RA_RAM_PARAM0__W                                          16
#define  OFDM_SC_RA_RAM_PARAM0__M                                          0xFFFF
#define  OFDM_SC_RA_RAM_PARAM0__PRE                                        0x0
#define  OFDM_SC_RA_RAM_PARAM1__A                                          0x3C20041
#define  OFDM_SC_RA_RAM_PARAM1__W                                          16
#define  OFDM_SC_RA_RAM_PARAM1__M                                          0xFFFF
#define  OFDM_SC_RA_RAM_PARAM1__PRE                                        0x0
#define  OFDM_SC_RA_RAM_CMD_ADDR__A                                        0x3C20042
#define  OFDM_SC_RA_RAM_CMD_ADDR__W                                        16
#define  OFDM_SC_RA_RAM_CMD_ADDR__M                                        0xFFFF
#define  OFDM_SC_RA_RAM_CMD_ADDR__PRE                                      0x0
#define  OFDM_SC_RA_RAM_CMD__A                                             0x3C20043
#define  OFDM_SC_RA_RAM_CMD__W                                             16
#define  OFDM_SC_RA_RAM_CMD__M                                             0xFFFF
#define  OFDM_SC_RA_RAM_CMD__PRE                                           0x0
#define    OFDM_SC_RA_RAM_CMD_NULL                                         0x0
#define    OFDM_SC_RA_RAM_CMD_PROC_START                                   0x1
#define    OFDM_SC_RA_RAM_CMD_PROC_TRIGGER                                 0x2
#define    OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM                               0x3
#define    OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM                                0x4
#define    OFDM_SC_RA_RAM_CMD_GET_OP_PARAM                                 0x5
#define    OFDM_SC_RA_RAM_CMD_USER_IO                                      0x6
#define    OFDM_SC_RA_RAM_CMD_SET_TIMER                                    0x7
#define    OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING                              0x8
#define    OFDM_SC_RA_RAM_CMD_MAX                                          0x9
#define    OFDM_SC_RA_RAM_CMD_LOCK__C                                      0x4

#define  OFDM_SC_RA_RAM_PROC_ACTIVATE__A                                   0x3C20044
#define  OFDM_SC_RA_RAM_PROC_ACTIVATE__W                                   16
#define  OFDM_SC_RA_RAM_PROC_ACTIVATE__M                                   0xFFFF
#define  OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE                                 0xFFFF
#define  OFDM_SC_RA_RAM_PROC_TERMINATED__A                                 0x3C20045
#define  OFDM_SC_RA_RAM_PROC_TERMINATED__W                                 16
#define  OFDM_SC_RA_RAM_PROC_TERMINATED__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_PROC_TERMINATED__PRE                               0x0
#define  OFDM_SC_RA_RAM_SW_EVENT__A                                        0x3C20046
#define  OFDM_SC_RA_RAM_SW_EVENT__W                                        14
#define  OFDM_SC_RA_RAM_SW_EVENT__M                                        0x3FFF
#define  OFDM_SC_RA_RAM_SW_EVENT__PRE                                      0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B                            0
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W                            1
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M                            0x1
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE                          0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN__B                                  1
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN__W                                  1
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN__M                                  0x2
#define    OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE                                0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B                            2
#define    OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W                            1
#define    OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M                            0x4
#define    OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE                          0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_FT_START__B                             3
#define    OFDM_SC_RA_RAM_SW_EVENT_FT_START__W                             1
#define    OFDM_SC_RA_RAM_SW_EVENT_FT_START__M                             0x8
#define    OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE                           0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_FI_START__B                             4
#define    OFDM_SC_RA_RAM_SW_EVENT_FI_START__W                             1
#define    OFDM_SC_RA_RAM_SW_EVENT_FI_START__M                             0x10
#define    OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE                           0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B                               5
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W                               1
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M                               0x20
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE                             0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B                               6
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W                               1
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M                               0x40
#define    OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE                             0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B                                7
#define    OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W                                1
#define    OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M                                0x80
#define    OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE                              0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B                                8
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W                                1
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M                                0x100
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE                              0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B                                9
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W                                1
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M                                0x200
#define    OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE                              0x0
#define    OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B                             12
#define    OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W                             1
#define    OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M                             0x1000
#define    OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE                           0x0

#define  OFDM_SC_RA_RAM_LOCKTRACK__A                                       0x3C20047
#define  OFDM_SC_RA_RAM_LOCKTRACK__W                                       16
#define  OFDM_SC_RA_RAM_LOCKTRACK__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_LOCKTRACK__PRE                                     0x0
#define    OFDM_SC_RA_RAM_LOCKTRACK_NULL                                   0x0
#define    OFDM_SC_RA_RAM_LOCKTRACK_MIN                                    0x1
#define    OFDM_SC_RA_RAM_LOCKTRACK_RESET                                  0x1
#define    OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT                              0x2
#define    OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX                               0x3
#define    OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT                               0x4
#define    OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH                        0x5
#define    OFDM_SC_RA_RAM_LOCKTRACK_LC                                     0x6
#define    OFDM_SC_RA_RAM_LOCKTRACK_TRACK                                  0x7
#define    OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR                            0x8
#define    OFDM_SC_RA_RAM_LOCKTRACK_MAX                                    0x9

#define  OFDM_SC_RA_RAM_OP_PARAM__A                                        0x3C20048
#define  OFDM_SC_RA_RAM_OP_PARAM__W                                        13
#define  OFDM_SC_RA_RAM_OP_PARAM__M                                        0x1FFF
#define  OFDM_SC_RA_RAM_OP_PARAM__PRE                                      0x0
#define    OFDM_SC_RA_RAM_OP_PARAM_MODE__B                                 0
#define    OFDM_SC_RA_RAM_OP_PARAM_MODE__W                                 2
#define    OFDM_SC_RA_RAM_OP_PARAM_MODE__M                                 0x3
#define    OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_MODE_2K                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_MODE_8K                               0x1
#define    OFDM_SC_RA_RAM_OP_PARAM_GUARD__B                                2
#define    OFDM_SC_RA_RAM_OP_PARAM_GUARD__W                                2
#define    OFDM_SC_RA_RAM_OP_PARAM_GUARD__M                                0xC
#define    OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE                              0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_32                              0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_16                              0x4
#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_8                               0x8
#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_4                               0xC
#define    OFDM_SC_RA_RAM_OP_PARAM_CONST__B                                4
#define    OFDM_SC_RA_RAM_OP_PARAM_CONST__W                                2
#define    OFDM_SC_RA_RAM_OP_PARAM_CONST__M                                0x30
#define    OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE                              0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK                            0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16                           0x10
#define      OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64                           0x20
#define    OFDM_SC_RA_RAM_OP_PARAM_HIER__B                                 6
#define    OFDM_SC_RA_RAM_OP_PARAM_HIER__W                                 3
#define    OFDM_SC_RA_RAM_OP_PARAM_HIER__M                                 0x1C0
#define    OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_NO                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_A1                               0x40
#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_A2                               0x80
#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_A4                               0xC0
#define    OFDM_SC_RA_RAM_OP_PARAM_RATE__B                                 9
#define    OFDM_SC_RA_RAM_OP_PARAM_RATE__W                                 3
#define    OFDM_SC_RA_RAM_OP_PARAM_RATE__M                                 0xE00
#define    OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2                              0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3                              0x200
#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4                              0x400
#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6                              0x600
#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8                              0x800
#define    OFDM_SC_RA_RAM_OP_PARAM_PRIO__B                                 12
#define    OFDM_SC_RA_RAM_OP_PARAM_PRIO__W                                 1
#define    OFDM_SC_RA_RAM_OP_PARAM_PRIO__M                                 0x1000
#define    OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI                               0x0
#define      OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO                               0x1000

#define  OFDM_SC_RA_RAM_OP_AUTO__A                                         0x3C20049
#define  OFDM_SC_RA_RAM_OP_AUTO__W                                         6
#define  OFDM_SC_RA_RAM_OP_AUTO__M                                         0x3F
#define  OFDM_SC_RA_RAM_OP_AUTO__PRE                                       0x1F
#define    OFDM_SC_RA_RAM_OP_AUTO_MODE__B                                  0
#define    OFDM_SC_RA_RAM_OP_AUTO_MODE__W                                  1
#define    OFDM_SC_RA_RAM_OP_AUTO_MODE__M                                  0x1
#define    OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE                                0x1
#define    OFDM_SC_RA_RAM_OP_AUTO_GUARD__B                                 1
#define    OFDM_SC_RA_RAM_OP_AUTO_GUARD__W                                 1
#define    OFDM_SC_RA_RAM_OP_AUTO_GUARD__M                                 0x2
#define    OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE                               0x2
#define    OFDM_SC_RA_RAM_OP_AUTO_CONST__B                                 2
#define    OFDM_SC_RA_RAM_OP_AUTO_CONST__W                                 1
#define    OFDM_SC_RA_RAM_OP_AUTO_CONST__M                                 0x4
#define    OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE                               0x4
#define    OFDM_SC_RA_RAM_OP_AUTO_HIER__B                                  3
#define    OFDM_SC_RA_RAM_OP_AUTO_HIER__W                                  1
#define    OFDM_SC_RA_RAM_OP_AUTO_HIER__M                                  0x8
#define    OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE                                0x8
#define    OFDM_SC_RA_RAM_OP_AUTO_RATE__B                                  4
#define    OFDM_SC_RA_RAM_OP_AUTO_RATE__W                                  1
#define    OFDM_SC_RA_RAM_OP_AUTO_RATE__M                                  0x10
#define    OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE                                0x10
#define    OFDM_SC_RA_RAM_OP_AUTO_PRIO__B                                  5
#define    OFDM_SC_RA_RAM_OP_AUTO_PRIO__W                                  1
#define    OFDM_SC_RA_RAM_OP_AUTO_PRIO__M                                  0x20
#define    OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE                                0x0

#define  OFDM_SC_RA_RAM_PILOT_STATUS__A                                    0x3C2004A
#define  OFDM_SC_RA_RAM_PILOT_STATUS__W                                    16
#define  OFDM_SC_RA_RAM_PILOT_STATUS__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_STATUS__PRE                                  0x0
#define    OFDM_SC_RA_RAM_PILOT_STATUS_OK                                  0x0
#define    OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR                           0x1
#define    OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR                           0x2
#define    OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR                           0x3

#define  OFDM_SC_RA_RAM_LOCK__A                                            0x3C2004B
#define  OFDM_SC_RA_RAM_LOCK__W                                            4
#define  OFDM_SC_RA_RAM_LOCK__M                                            0xF
#define  OFDM_SC_RA_RAM_LOCK__PRE                                          0x0
#define    OFDM_SC_RA_RAM_LOCK_DEMOD__B                                    0
#define    OFDM_SC_RA_RAM_LOCK_DEMOD__W                                    1
#define    OFDM_SC_RA_RAM_LOCK_DEMOD__M                                    0x1
#define    OFDM_SC_RA_RAM_LOCK_DEMOD__PRE                                  0x0
#define    OFDM_SC_RA_RAM_LOCK_FEC__B                                      1
#define    OFDM_SC_RA_RAM_LOCK_FEC__W                                      1
#define    OFDM_SC_RA_RAM_LOCK_FEC__M                                      0x2
#define    OFDM_SC_RA_RAM_LOCK_FEC__PRE                                    0x0
#define    OFDM_SC_RA_RAM_LOCK_MPEG__B                                     2
#define    OFDM_SC_RA_RAM_LOCK_MPEG__W                                     1
#define    OFDM_SC_RA_RAM_LOCK_MPEG__M                                     0x4
#define    OFDM_SC_RA_RAM_LOCK_MPEG__PRE                                   0x0
#define    OFDM_SC_RA_RAM_LOCK_NODVBT__B                                   3
#define    OFDM_SC_RA_RAM_LOCK_NODVBT__W                                   1
#define    OFDM_SC_RA_RAM_LOCK_NODVBT__M                                   0x8
#define    OFDM_SC_RA_RAM_LOCK_NODVBT__PRE                                 0x0

#define  OFDM_SC_RA_RAM_BE_OPT_ENA__A                                      0x3C2004C
#define  OFDM_SC_RA_RAM_BE_OPT_ENA__W                                      5
#define  OFDM_SC_RA_RAM_BE_OPT_ENA__M                                      0x1F
#define  OFDM_SC_RA_RAM_BE_OPT_ENA__PRE                                    0x1C
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B                      0
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W                      1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M                      0x1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE                    0x0
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B                             1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W                             1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M                             0x2
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE                           0x0
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B                            2
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W                            1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M                            0x4
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE                          0x4
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B                            3
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W                            1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M                            0x8
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE                          0x8
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B                           4
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W                           1
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M                           0x10
#define    OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE                         0x10

#define  OFDM_SC_RA_RAM_BE_OPT_DELAY__A                                    0x3C2004D
#define  OFDM_SC_RA_RAM_BE_OPT_DELAY__W                                    16
#define  OFDM_SC_RA_RAM_BE_OPT_DELAY__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE                                  0x80
#define  OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A                               0x3C2004E
#define  OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W                               16
#define  OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M                               0xFFFF
#define  OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE                             0x400
#define  OFDM_SC_RA_RAM_ECHO_THRES__A                                      0x3C2004F
#define  OFDM_SC_RA_RAM_ECHO_THRES__W                                      16
#define  OFDM_SC_RA_RAM_ECHO_THRES__M                                      0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_THRES__PRE                                    0x6419
#define    OFDM_SC_RA_RAM_ECHO_THRES_8K__B                                 0
#define    OFDM_SC_RA_RAM_ECHO_THRES_8K__W                                 8
#define    OFDM_SC_RA_RAM_ECHO_THRES_8K__M                                 0xFF
#define    OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE                               0x19
#define    OFDM_SC_RA_RAM_ECHO_THRES_2K__B                                 8
#define    OFDM_SC_RA_RAM_ECHO_THRES_2K__W                                 8
#define    OFDM_SC_RA_RAM_ECHO_THRES_2K__M                                 0xFF00
#define    OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE                               0x6400

#define  OFDM_SC_RA_RAM_CONFIG__A                                          0x3C20050
#define  OFDM_SC_RA_RAM_CONFIG__W                                          16
#define  OFDM_SC_RA_RAM_CONFIG__M                                          0xFFFF
#define  OFDM_SC_RA_RAM_CONFIG__PRE                                        0x14
#define    OFDM_SC_RA_RAM_CONFIG_ID__B                                     0
#define    OFDM_SC_RA_RAM_CONFIG_ID__W                                     1
#define    OFDM_SC_RA_RAM_CONFIG_ID__M                                     0x1
#define    OFDM_SC_RA_RAM_CONFIG_ID__PRE                                   0x0
#define      OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO                               0x0
#define      OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER                          0x1
#define    OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B                      1
#define    OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W                      1
#define    OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M                      0x2
#define    OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE                    0x0
#define    OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B                              2
#define    OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W                              1
#define    OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M                              0x4
#define    OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE                            0x4
#define    OFDM_SC_RA_RAM_CONFIG_MIXMODE__B                                3
#define    OFDM_SC_RA_RAM_CONFIG_MIXMODE__W                                1
#define    OFDM_SC_RA_RAM_CONFIG_MIXMODE__M                                0x8
#define    OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE                              0x0
#define    OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B                               4
#define    OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W                               1
#define    OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M                               0x10
#define    OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE                             0x10
#define    OFDM_SC_RA_RAM_CONFIG_SLAVE__B                                  5
#define    OFDM_SC_RA_RAM_CONFIG_SLAVE__W                                  1
#define    OFDM_SC_RA_RAM_CONFIG_SLAVE__M                                  0x20
#define    OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE                                0x0
#define    OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B                                6
#define    OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W                                1
#define    OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M                                0x40
#define    OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE                              0x0
#define    OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B                           7
#define    OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W                           1
#define    OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M                           0x80
#define    OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE                         0x0
#define    OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B                           8
#define    OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W                           1
#define    OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M                           0x100
#define    OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE                         0x0
#define    OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B                       9
#define    OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W                       1
#define    OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M                       0x200
#define    OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE                     0x0
#define    OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B                        10
#define    OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W                        1
#define    OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M                        0x400
#define    OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE                      0x0
#define    OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B                          11
#define    OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W                          1
#define    OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M                          0x800
#define    OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE                        0x0
#define    OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B                             15
#define    OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W                             1
#define    OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M                             0x8000
#define    OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE                           0x0

#define  OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A                                0x3C20054
#define  OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W                                16
#define  OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M                                0xFFFF
#define  OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE                              0xA0
#define  OFDM_SC_RA_RAM_FR_2K_MAN_SH__A                                    0x3C20055
#define  OFDM_SC_RA_RAM_FR_2K_MAN_SH__W                                    16
#define  OFDM_SC_RA_RAM_FR_2K_MAN_SH__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE                                  0x7
#define  OFDM_SC_RA_RAM_FR_2K_TAP_SH__A                                    0x3C20056
#define  OFDM_SC_RA_RAM_FR_2K_TAP_SH__W                                    16
#define  OFDM_SC_RA_RAM_FR_2K_TAP_SH__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE                                  0x3
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A                                  0x3C20057
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W                                  16
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE                                0x2
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A                                   0x3C20058
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W                                   16
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M                                   0xFFFF
#define  OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE                                 0x2
#define  OFDM_SC_RA_RAM_FR_8K_MAN_SH__A                                    0x3C20059
#define  OFDM_SC_RA_RAM_FR_8K_MAN_SH__W                                    16
#define  OFDM_SC_RA_RAM_FR_8K_MAN_SH__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE                                  0x7
#define  OFDM_SC_RA_RAM_FR_8K_TAP_SH__A                                    0x3C2005A
#define  OFDM_SC_RA_RAM_FR_8K_TAP_SH__W                                    16
#define  OFDM_SC_RA_RAM_FR_8K_TAP_SH__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE                                  0x1
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A                                  0x3C2005B
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W                                  16
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE                                0x2
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A                                   0x3C2005C
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W                                   16
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M                                   0xFFFF
#define  OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE                                 0x1
#define  OFDM_SC_RA_RAM_CO_TD_CAL_2K__A                                    0x3C2005D
#define  OFDM_SC_RA_RAM_CO_TD_CAL_2K__W                                    16
#define  OFDM_SC_RA_RAM_CO_TD_CAL_2K__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE                                  0xFFEB
#define  OFDM_SC_RA_RAM_CO_TD_CAL_8K__A                                    0x3C2005E
#define  OFDM_SC_RA_RAM_CO_TD_CAL_8K__W                                    16
#define  OFDM_SC_RA_RAM_CO_TD_CAL_8K__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE                                  0xFFE8
#define  OFDM_SC_RA_RAM_MOTION_OFFSET__A                                   0x3C2005F
#define  OFDM_SC_RA_RAM_MOTION_OFFSET__W                                   16
#define  OFDM_SC_RA_RAM_MOTION_OFFSET__M                                   0xFFFF
#define  OFDM_SC_RA_RAM_MOTION_OFFSET__PRE                                 0x2
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A                               0x3C20060
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE                             0xFFFE
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A                               0x3C20061
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE                             0x330
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A                               0x3C20062
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE                             0x0
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A                               0x3C20063
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE                             0x4
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A                               0x3C20064
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE                             0x0
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A                               0x3C20065
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE                             0x80
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A                               0x3C20066
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE                             0x0
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A                               0x3C20067
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W                               16
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M                               0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE                             0xFFFE
#define  OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A                                0x3C2006E
#define  OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W                                16
#define  OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M                                0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE                              0x1
#define  OFDM_SC_RA_RAM_PILOT_POW_TARGET__A                                0x3C2006F
#define  OFDM_SC_RA_RAM_PILOT_POW_TARGET__W                                16
#define  OFDM_SC_RA_RAM_PILOT_POW_TARGET__M                                0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE                              0x320
#define  OFDM_SC_RA_RAM_STATE_PROC_START_1__A                              0x3C20070
#define  OFDM_SC_RA_RAM_STATE_PROC_START_1__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_1__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE                            0x80
#define  OFDM_SC_RA_RAM_STATE_PROC_START_2__A                              0x3C20071
#define  OFDM_SC_RA_RAM_STATE_PROC_START_2__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_2__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE                            0x2
#define  OFDM_SC_RA_RAM_STATE_PROC_START_3__A                              0x3C20072
#define  OFDM_SC_RA_RAM_STATE_PROC_START_3__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_3__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE                            0x40
#define  OFDM_SC_RA_RAM_STATE_PROC_START_4__A                              0x3C20073
#define  OFDM_SC_RA_RAM_STATE_PROC_START_4__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_4__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE                            0x4
#define  OFDM_SC_RA_RAM_STATE_PROC_START_5__A                              0x3C20074
#define  OFDM_SC_RA_RAM_STATE_PROC_START_5__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_5__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE                            0x4
#define  OFDM_SC_RA_RAM_STATE_PROC_START_6__A                              0x3C20075
#define  OFDM_SC_RA_RAM_STATE_PROC_START_6__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_6__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE                            0x780
#define  OFDM_SC_RA_RAM_STATE_PROC_START_7__A                              0x3C20076
#define  OFDM_SC_RA_RAM_STATE_PROC_START_7__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_7__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE                            0x230
#define  OFDM_SC_RA_RAM_STATE_PROC_START_8__A                              0x3C20077
#define  OFDM_SC_RA_RAM_STATE_PROC_START_8__W                              16
#define  OFDM_SC_RA_RAM_STATE_PROC_START_8__M                              0xFFFF
#define  OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE                            0x0
#define  OFDM_SC_RA_RAM_FR_THRES_2K__A                                     0x3C2007C
#define  OFDM_SC_RA_RAM_FR_THRES_2K__W                                     16
#define  OFDM_SC_RA_RAM_FR_THRES_2K__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_FR_THRES_2K__PRE                                   0xEA6
#define  OFDM_SC_RA_RAM_FR_THRES_8K__A                                     0x3C2007D
#define  OFDM_SC_RA_RAM_FR_THRES_8K__W                                     16
#define  OFDM_SC_RA_RAM_FR_THRES_8K__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_FR_THRES_8K__PRE                                   0x1A2C
#define  OFDM_SC_RA_RAM_STATUS__A                                          0x3C2007E
#define  OFDM_SC_RA_RAM_STATUS__W                                          16
#define  OFDM_SC_RA_RAM_STATUS__M                                          0xFFFF
#define  OFDM_SC_RA_RAM_STATUS__PRE                                        0x0
#define  OFDM_SC_RA_RAM_NF_BORDER_INIT__A                                  0x3C2007F
#define  OFDM_SC_RA_RAM_NF_BORDER_INIT__W                                  16
#define  OFDM_SC_RA_RAM_NF_BORDER_INIT__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE                                0x708
#define  OFDM_SC_RA_RAM_TIMER__A                                           0x3C20080
#define  OFDM_SC_RA_RAM_TIMER__W                                           16
#define  OFDM_SC_RA_RAM_TIMER__M                                           0xFFFF
#define  OFDM_SC_RA_RAM_TIMER__PRE                                         0x0
#define  OFDM_SC_RA_RAM_FI_OFFSET__A                                       0x3C20081
#define  OFDM_SC_RA_RAM_FI_OFFSET__W                                       16
#define  OFDM_SC_RA_RAM_FI_OFFSET__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_FI_OFFSET__PRE                                     0x382
#define  OFDM_SC_RA_RAM_ECHO_GUARD__A                                      0x3C20082
#define  OFDM_SC_RA_RAM_ECHO_GUARD__W                                      16
#define  OFDM_SC_RA_RAM_ECHO_GUARD__M                                      0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_GUARD__PRE                                    0x18
#define  OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A                                  0x3C2008D
#define  OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W                                  16
#define  OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE                                0x640
#define  OFDM_SC_RA_RAM_IF_SAVE_0__A                                       0x3C2008E
#define  OFDM_SC_RA_RAM_IF_SAVE_0__W                                       16
#define  OFDM_SC_RA_RAM_IF_SAVE_0__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_IF_SAVE_0__PRE                                     0x0
#define  OFDM_SC_RA_RAM_IF_SAVE_1__A                                       0x3C2008F
#define  OFDM_SC_RA_RAM_IF_SAVE_1__W                                       16
#define  OFDM_SC_RA_RAM_IF_SAVE_1__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_IF_SAVE_1__PRE                                     0x0
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A                           0x3C20098
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W                           16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M                           0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE                         0x258
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A                           0x3C20099
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W                           16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M                           0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE                         0x258
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A                            0x3C2009A
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W                            16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M                            0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE                          0x258
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A                            0x3C2009B
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W                            16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M                            0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE                          0x258
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A                           0x3C2009C
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W                           16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M                           0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE                         0xDAC
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A                           0x3C2009D
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W                           16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M                           0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE                         0xDAC
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A                            0x3C2009E
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W                            16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M                            0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE                          0xDAC
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A                            0x3C2009F
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W                            16
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M                            0xFFFF
#define  OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE                          0xDAC
#define  OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A                                  0x3C200B2
#define  OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W                                  16
#define  OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE                                0xC8
#define  OFDM_SC_RA_RAM_MG_VALID_THRES__A                                  0x3C200B7
#define  OFDM_SC_RA_RAM_MG_VALID_THRES__W                                  16
#define  OFDM_SC_RA_RAM_MG_VALID_THRES__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_MG_VALID_THRES__PRE                                0x230
#define  OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A                                0x3C200B8
#define  OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W                                16
#define  OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M                                0xFFFF
#define  OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE                              0x320
#define  OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A                              0x3C200B9
#define  OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W                              16
#define  OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M                              0xFFFF
#define  OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE                            0x32
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A                          0x3C200BA
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W                          16
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M                          0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE                        0x443
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B                     0
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W                     5
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M                     0x1F
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE                   0x3
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B                     5
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W                     5
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M                     0x3E0
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE                   0x40
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B                     10
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W                     5
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M                     0x7C00
#define    OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE                   0x400

#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A                        0x3C200BB
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W                        16
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M                        0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE                      0x3
#define  OFDM_SC_RA_RAM_PILOT_SPD_THRES__A                                 0x3C200BC
#define  OFDM_SC_RA_RAM_PILOT_SPD_THRES__W                                 16
#define  OFDM_SC_RA_RAM_PILOT_SPD_THRES__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE                               0x6
#define  OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A                               0x3C200BD
#define  OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W                               16
#define  OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M                               0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE                             0x28
#define  OFDM_SC_RA_RAM_PILOT_CPD_THRES__A                                 0x3C200BE
#define  OFDM_SC_RA_RAM_PILOT_CPD_THRES__W                                 16
#define  OFDM_SC_RA_RAM_PILOT_CPD_THRES__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE                               0x6
#define  OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A                               0x3C200BF
#define  OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W                               16
#define  OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M                               0xFFFF
#define  OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE                             0x14
#define  OFDM_SC_RA_RAM_IR_FREQ__A                                         0x3C200D0
#define  OFDM_SC_RA_RAM_IR_FREQ__W                                         16
#define  OFDM_SC_RA_RAM_IR_FREQ__M                                         0xFFFF
#define  OFDM_SC_RA_RAM_IR_FREQ__PRE                                       0x0
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A                             0x3C200D1
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W                             16
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M                             0xFFFF
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE                           0x9
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A                            0x3C200D2
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W                            16
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M                            0xFFFF
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE                          0x4
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A                            0x3C200D3
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W                            16
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M                            0xFFFF
#define  OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE                          0x100
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A                             0x3C200D4
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W                             16
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M                             0xFFFF
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE                           0x9
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A                            0x3C200D5
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W                            16
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M                            0xFFFF
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE                          0x4
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A                            0x3C200D6
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W                            16
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M                            0xFFFF
#define  OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE                          0x100
#define  OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A                               0x3C200D7
#define  OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W                               16
#define  OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M                               0xFFFF
#define  OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE                             0x9
#define  OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A                              0x3C200D8
#define  OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W                              16
#define  OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M                              0xFFFF
#define  OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE                            0x4
#define  OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A                              0x3C200D9
#define  OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W                              16
#define  OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M                              0xFFFF
#define  OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE                            0x100
#define  OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A                               0x3C200DA
#define  OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W                               16
#define  OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M                               0xFFFF
#define  OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE                             0xB
#define  OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A                              0x3C200DB
#define  OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W                              16
#define  OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M                              0xFFFF
#define  OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE                            0x1
#define  OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A                              0x3C200DC
#define  OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W                              16
#define  OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M                              0xFFFF
#define  OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE                            0x40
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A                                  0x3C200DD
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W                                  16
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE                                0x18
#define  OFDM_SC_RA_RAM_ECHO_SHT_LIM__A                                    0x3C200DE
#define  OFDM_SC_RA_RAM_ECHO_SHT_LIM__W                                    16
#define  OFDM_SC_RA_RAM_ECHO_SHT_LIM__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE                                  0x1
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A                                 0x3C200DF
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W                                 16
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE                               0x14C0
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B                         0
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W                         10
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M                         0x3FF
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE                       0xC0
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B                       10
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W                       6
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M                       0xFC00
#define    OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE                     0x1400

#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A                             0x3C200E0
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W                             16
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M                             0xFFFF
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE                           0x7
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A                            0x3C200E1
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W                            16
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M                            0xFFFF
#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE                          0x1
#define  OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A                               0x3C200E2
#define  OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W                               16
#define  OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M                               0xFFFF
#define  OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE                             0xE8
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A                             0x3C200E3
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W                             16
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M                             0xFFFF
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE                           0xE
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A                            0x3C200E4
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W                            16
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M                            0xFFFF
#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE                          0x7
#define  OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A                               0x3C200E5
#define  OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W                               16
#define  OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M                               0xFFFF
#define  OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE                             0xA0
#define  OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A                                 0x3C200E7
#define  OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W                                 16
#define  OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE                               0x4E2
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A                               0x3C200E8
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W                               16
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M                               0xFFFF
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE                             0x2
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A                                0x3C200E9
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W                                16
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M                                0xFFFF
#define  OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE                              0x44C
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A                                 0x3C200EA
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W                                 16
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE                               0xC8
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT__A                                     0x3C200EB
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT__W                                     16
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE                                   0x0
#define  OFDM_SC_RA_RAM_BAND__A                                            0x3C200EC
#define  OFDM_SC_RA_RAM_BAND__W                                            16
#define  OFDM_SC_RA_RAM_BAND__M                                            0xFFFF
#define  OFDM_SC_RA_RAM_BAND__PRE                                          0x0
#define    OFDM_SC_RA_RAM_BAND_INTERVAL__B                                 0
#define    OFDM_SC_RA_RAM_BAND_INTERVAL__W                                 4
#define    OFDM_SC_RA_RAM_BAND_INTERVAL__M                                 0xF
#define    OFDM_SC_RA_RAM_BAND_INTERVAL__PRE                               0x0
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B                       8
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W                       1
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M                       0x100
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE                     0x0
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B                       9
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W                       1
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M                       0x200
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE                     0x0
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B                        10
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W                        1
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M                        0x400
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE                      0x0
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B                        11
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W                        1
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M                        0x800
#define    OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE                      0x0
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B                        12
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W                        1
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M                        0x1000
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE                      0x0
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B                        13
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W                        1
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M                        0x2000
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE                      0x0
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B                         14
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W                         1
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M                         0x4000
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE                       0x0
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B                         15
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W                         1
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M                         0x8000
#define    OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE                       0x0

#define  OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A                              0x3C200ED
#define  OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W                              16
#define  OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M                              0xFFFF
#define  OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE                            0xC0
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A                                0x3C200EE
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W                                16
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M                                0xFFFF
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE                              0x19
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A                                0x3C200EF
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W                                16
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M                                0xFFFF
#define  OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE                              0x1B
#define  OFDM_SC_RA_RAM_REG_0__A                                           0x3C200F0
#define  OFDM_SC_RA_RAM_REG_0__W                                           16
#define  OFDM_SC_RA_RAM_REG_0__M                                           0xFFFF
#define  OFDM_SC_RA_RAM_REG_0__PRE                                         0x0
#define  OFDM_SC_RA_RAM_REG_1__A                                           0x3C200F1
#define  OFDM_SC_RA_RAM_REG_1__W                                           16
#define  OFDM_SC_RA_RAM_REG_1__M                                           0xFFFF
#define  OFDM_SC_RA_RAM_REG_1__PRE                                         0x0
#define  OFDM_SC_RA_RAM_BREAK__A                                           0x3C200F2
#define  OFDM_SC_RA_RAM_BREAK__W                                           16
#define  OFDM_SC_RA_RAM_BREAK__M                                           0xFFFF
#define  OFDM_SC_RA_RAM_BREAK__PRE                                         0x0
#define  OFDM_SC_RA_RAM_BOOTCOUNT__A                                       0x3C200F3
#define  OFDM_SC_RA_RAM_BOOTCOUNT__W                                       16
#define  OFDM_SC_RA_RAM_BOOTCOUNT__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_BOOTCOUNT__PRE                                     0x0
#define  OFDM_SC_RA_RAM_LC_ABS_2K__A                                       0x3C200F4
#define  OFDM_SC_RA_RAM_LC_ABS_2K__W                                       16
#define  OFDM_SC_RA_RAM_LC_ABS_2K__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_LC_ABS_2K__PRE                                     0x1F
#define  OFDM_SC_RA_RAM_LC_ABS_8K__A                                       0x3C200F5
#define  OFDM_SC_RA_RAM_LC_ABS_8K__W                                       16
#define  OFDM_SC_RA_RAM_LC_ABS_8K__M                                       0xFFFF
#define  OFDM_SC_RA_RAM_LC_ABS_8K__PRE                                     0x1F
#define  OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A                                  0x3C200F6
#define  OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W                                  16
#define  OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE                                0x1
#define  OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A                                0x3C200F7
#define  OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W                                16
#define  OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M                                0xFFFF
#define  OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE                              0x14
#define  OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A                                0x3C200F8
#define  OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W                                16
#define  OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M                                0xFFFF
#define  OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE                              0xB6F
#define    OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B             0
#define    OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W             16
#define    OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M             0xFFFF
#define    OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE           0xB6F

#define  OFDM_SC_RA_RAM_LC_CP__A                                           0x3C200F9
#define  OFDM_SC_RA_RAM_LC_CP__W                                           16
#define  OFDM_SC_RA_RAM_LC_CP__M                                           0xFFFF
#define  OFDM_SC_RA_RAM_LC_CP__PRE                                         0x1
#define  OFDM_SC_RA_RAM_LC_DIFF__A                                         0x3C200FA
#define  OFDM_SC_RA_RAM_LC_DIFF__W                                         16
#define  OFDM_SC_RA_RAM_LC_DIFF__M                                         0xFFFF
#define  OFDM_SC_RA_RAM_LC_DIFF__PRE                                       0x7
#define  OFDM_SC_RA_RAM_ECHO_NF_THRES__A                                   0x3C200FB
#define  OFDM_SC_RA_RAM_ECHO_NF_THRES__W                                   16
#define  OFDM_SC_RA_RAM_ECHO_NF_THRES__M                                   0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE                                 0x1B58
#define  OFDM_SC_RA_RAM_ECHO_NF_FEC__A                                     0x3C200FC
#define  OFDM_SC_RA_RAM_ECHO_NF_FEC__W                                     16
#define  OFDM_SC_RA_RAM_ECHO_NF_FEC__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE                                   0x0

#define  OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A                                  0x3C200FD
#define  OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W                                  16
#define  OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE                                0xFF38
#define  OFDM_SC_RA_RAM_RELOCK__A                                          0x3C200FE
#define  OFDM_SC_RA_RAM_RELOCK__W                                          16
#define  OFDM_SC_RA_RAM_RELOCK__M                                          0xFFFF
#define  OFDM_SC_RA_RAM_RELOCK__PRE                                        0x0
#define  OFDM_SC_RA_RAM_STACKUNDERFLOW__A                                  0x3C200FF
#define  OFDM_SC_RA_RAM_STACKUNDERFLOW__W                                  16
#define  OFDM_SC_RA_RAM_STACKUNDERFLOW__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A                                 0x3C20148
#define  OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W                                 16
#define  OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE                               0x0
#define  OFDM_SC_RA_RAM_NF_PREPOST__A                                      0x3C20149
#define  OFDM_SC_RA_RAM_NF_PREPOST__W                                      16
#define  OFDM_SC_RA_RAM_NF_PREPOST__M                                      0xFFFF
#define  OFDM_SC_RA_RAM_NF_PREPOST__PRE                                    0x0
#define  OFDM_SC_RA_RAM_NF_PREBORDER__A                                    0x3C2014A
#define  OFDM_SC_RA_RAM_NF_PREBORDER__W                                    16
#define  OFDM_SC_RA_RAM_NF_PREBORDER__M                                    0xFFFF
#define  OFDM_SC_RA_RAM_NF_PREBORDER__PRE                                  0x0
#define  OFDM_SC_RA_RAM_NF_START__A                                        0x3C2014B
#define  OFDM_SC_RA_RAM_NF_START__W                                        16
#define  OFDM_SC_RA_RAM_NF_START__M                                        0xFFFF
#define  OFDM_SC_RA_RAM_NF_START__PRE                                      0x0
#define  OFDM_SC_RA_RAM_NF_MINISI_0__A                                     0x3C2014C
#define  OFDM_SC_RA_RAM_NF_MINISI_0__W                                     16
#define  OFDM_SC_RA_RAM_NF_MINISI_0__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_NF_MINISI_0__PRE                                   0x0
#define  OFDM_SC_RA_RAM_NF_MINISI_1__A                                     0x3C2014D
#define  OFDM_SC_RA_RAM_NF_MINISI_1__W                                     16
#define  OFDM_SC_RA_RAM_NF_MINISI_1__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_NF_MINISI_1__PRE                                   0x0
#define  OFDM_SC_RA_RAM_NF_NRECHOES__A                                     0x3C2014F
#define  OFDM_SC_RA_RAM_NF_NRECHOES__W                                     16
#define  OFDM_SC_RA_RAM_NF_NRECHOES__M                                     0xFFFF
#define  OFDM_SC_RA_RAM_NF_NRECHOES__PRE                                   0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A                                  0x3C20150
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A                                  0x3C20151
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A                                  0x3C20152
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A                                  0x3C20153
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A                                  0x3C20154
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A                                  0x3C20155
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A                                  0x3C20156
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A                                  0x3C20157
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A                                  0x3C20158
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A                                  0x3C20159
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W                                  16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M                                  0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE                                0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A                                 0x3C2015A
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W                                 16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE                               0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A                                 0x3C2015B
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W                                 16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE                               0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A                                 0x3C2015C
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W                                 16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE                               0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A                                 0x3C2015D
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W                                 16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE                               0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A                                 0x3C2015E
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W                                 16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE                               0x0
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A                                 0x3C2015F
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W                                 16
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M                                 0xFFFF
#define  OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE                               0x0
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A                          0x3C201A0
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W                          16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M                          0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE                        0x100
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A                          0x3C201A1
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W                          16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M                          0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE                        0x4
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A                             0x3C201A2
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W                             16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M                             0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE                           0x1E2
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A                             0x3C201A3
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W                             16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M                             0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE                           0x4
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A                            0x3C201A4
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W                            16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M                            0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE                          0x10D
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A                            0x3C201A5
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W                            16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M                            0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE                          0x5
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A                         0x3C201A6
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE                       0x17D
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A                         0x3C201A7
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE                       0x4
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A                         0x3C201A8
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE                       0x133
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A                         0x3C201A9
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE                       0x5
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A                            0x3C201AA
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W                            16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M                            0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE                          0x114
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A                            0x3C201AB
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W                            16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M                            0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE                          0x5
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A                         0x3C201AC
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE                       0x14A
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A                         0x3C201AD
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE                       0x4
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A                         0x3C201AE
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE                       0x1BB
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A                         0x3C201AF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W                         16
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M                         0xFFFF
#define  OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE                       0x4
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_0__A                                0x3C201FE
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_0__W                                16
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_0__M                                0xFFFF
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE                              0x0
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_1__A                                0x3C201FF
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_1__W                                16
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_1__M                                0xFFFF
#define  OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE                              0x0





#define  QAM_COMM_EXEC__A                                                  0x1400000
#define  QAM_COMM_EXEC__W                                                  2
#define  QAM_COMM_EXEC__M                                                  0x3
#define  QAM_COMM_EXEC__PRE                                                0x0
#define    QAM_COMM_EXEC_STOP                                              0x0
#define    QAM_COMM_EXEC_ACTIVE                                            0x1
#define    QAM_COMM_EXEC_HOLD                                              0x2

#define  QAM_COMM_MB__A                                                    0x1400002
#define  QAM_COMM_MB__W                                                    16
#define  QAM_COMM_MB__M                                                    0xFFFF
#define  QAM_COMM_MB__PRE                                                  0x0
#define  QAM_COMM_INT_REQ__A                                               0x1400003
#define  QAM_COMM_INT_REQ__W                                               16
#define  QAM_COMM_INT_REQ__M                                               0xFFFF
#define  QAM_COMM_INT_REQ__PRE                                             0x0

#define    QAM_COMM_INT_REQ_SL_REQ__B                                      0
#define    QAM_COMM_INT_REQ_SL_REQ__W                                      1
#define    QAM_COMM_INT_REQ_SL_REQ__M                                      0x1
#define    QAM_COMM_INT_REQ_SL_REQ__PRE                                    0x0

#define    QAM_COMM_INT_REQ_LC_REQ__B                                      1
#define    QAM_COMM_INT_REQ_LC_REQ__W                                      1
#define    QAM_COMM_INT_REQ_LC_REQ__M                                      0x2
#define    QAM_COMM_INT_REQ_LC_REQ__PRE                                    0x0

#define    QAM_COMM_INT_REQ_VD_REQ__B                                      2
#define    QAM_COMM_INT_REQ_VD_REQ__W                                      1
#define    QAM_COMM_INT_REQ_VD_REQ__M                                      0x4
#define    QAM_COMM_INT_REQ_VD_REQ__PRE                                    0x0

#define    QAM_COMM_INT_REQ_SY_REQ__B                                      3
#define    QAM_COMM_INT_REQ_SY_REQ__W                                      1
#define    QAM_COMM_INT_REQ_SY_REQ__M                                      0x8
#define    QAM_COMM_INT_REQ_SY_REQ__PRE                                    0x0

#define  QAM_COMM_INT_STA__A                                               0x1400005
#define  QAM_COMM_INT_STA__W                                               16
#define  QAM_COMM_INT_STA__M                                               0xFFFF
#define  QAM_COMM_INT_STA__PRE                                             0x0
#define  QAM_COMM_INT_MSK__A                                               0x1400006
#define  QAM_COMM_INT_MSK__W                                               16
#define  QAM_COMM_INT_MSK__M                                               0xFFFF
#define  QAM_COMM_INT_MSK__PRE                                             0x0
#define  QAM_COMM_INT_STM__A                                               0x1400007
#define  QAM_COMM_INT_STM__W                                               16
#define  QAM_COMM_INT_STM__M                                               0xFFFF
#define  QAM_COMM_INT_STM__PRE                                             0x0



#define  QAM_TOP_COMM_EXEC__A                                              0x1410000
#define  QAM_TOP_COMM_EXEC__W                                              2
#define  QAM_TOP_COMM_EXEC__M                                              0x3
#define  QAM_TOP_COMM_EXEC__PRE                                            0x0
#define    QAM_TOP_COMM_EXEC_STOP                                          0x0
#define    QAM_TOP_COMM_EXEC_ACTIVE                                        0x1
#define    QAM_TOP_COMM_EXEC_HOLD                                          0x2


#define  QAM_TOP_ANNEX__A                                                  0x1410010
#define  QAM_TOP_ANNEX__W                                                  2
#define  QAM_TOP_ANNEX__M                                                  0x3
#define  QAM_TOP_ANNEX__PRE                                                0x0
#define    QAM_TOP_ANNEX_A                                                 0x0
#define    QAM_TOP_ANNEX_B                                                 0x1
#define    QAM_TOP_ANNEX_C                                                 0x2
#define    QAM_TOP_ANNEX_D                                                 0x3


#define  QAM_TOP_CONSTELLATION__A                                          0x1410011
#define  QAM_TOP_CONSTELLATION__W                                          3
#define  QAM_TOP_CONSTELLATION__M                                          0x7
#define  QAM_TOP_CONSTELLATION__PRE                                        0x5
#define    QAM_TOP_CONSTELLATION_NONE                                      0x0
#define    QAM_TOP_CONSTELLATION_QPSK                                      0x1
#define    QAM_TOP_CONSTELLATION_QAM8                                      0x2
#define    QAM_TOP_CONSTELLATION_QAM16                                     0x3
#define    QAM_TOP_CONSTELLATION_QAM32                                     0x4
#define    QAM_TOP_CONSTELLATION_QAM64                                     0x5
#define    QAM_TOP_CONSTELLATION_QAM128                                    0x6
#define    QAM_TOP_CONSTELLATION_QAM256                                    0x7



#define  QAM_FQ_COMM_EXEC__A                                               0x1420000
#define  QAM_FQ_COMM_EXEC__W                                               2
#define  QAM_FQ_COMM_EXEC__M                                               0x3
#define  QAM_FQ_COMM_EXEC__PRE                                             0x0
#define    QAM_FQ_COMM_EXEC_STOP                                           0x0
#define    QAM_FQ_COMM_EXEC_ACTIVE                                         0x1
#define    QAM_FQ_COMM_EXEC_HOLD                                           0x2

#define  QAM_FQ_MODE__A                                                    0x1420010
#define  QAM_FQ_MODE__W                                                    3
#define  QAM_FQ_MODE__M                                                    0x7
#define  QAM_FQ_MODE__PRE                                                  0x0

#define    QAM_FQ_MODE_TAPRESET__B                                         0
#define    QAM_FQ_MODE_TAPRESET__W                                         1
#define    QAM_FQ_MODE_TAPRESET__M                                         0x1
#define    QAM_FQ_MODE_TAPRESET__PRE                                       0x0
#define      QAM_FQ_MODE_TAPRESET_RST                                      0x1

#define    QAM_FQ_MODE_TAPLMS__B                                           1
#define    QAM_FQ_MODE_TAPLMS__W                                           1
#define    QAM_FQ_MODE_TAPLMS__M                                           0x2
#define    QAM_FQ_MODE_TAPLMS__PRE                                         0x0
#define      QAM_FQ_MODE_TAPLMS_UPD                                        0x2

#define    QAM_FQ_MODE_TAPDRAIN__B                                         2
#define    QAM_FQ_MODE_TAPDRAIN__W                                         1
#define    QAM_FQ_MODE_TAPDRAIN__M                                         0x4
#define    QAM_FQ_MODE_TAPDRAIN__PRE                                       0x0
#define      QAM_FQ_MODE_TAPDRAIN_DRAIN                                    0x4


#define  QAM_FQ_MU_FACTOR__A                                               0x1420011
#define  QAM_FQ_MU_FACTOR__W                                               3
#define  QAM_FQ_MU_FACTOR__M                                               0x7
#define  QAM_FQ_MU_FACTOR__PRE                                             0x0

#define  QAM_FQ_LA_FACTOR__A                                               0x1420012
#define  QAM_FQ_LA_FACTOR__W                                               4
#define  QAM_FQ_LA_FACTOR__M                                               0xF
#define  QAM_FQ_LA_FACTOR__PRE                                             0xC
#define  QAM_FQ_CENTTAP_IDX__A                                             0x1420016
#define  QAM_FQ_CENTTAP_IDX__W                                             5
#define  QAM_FQ_CENTTAP_IDX__M                                             0x1F
#define  QAM_FQ_CENTTAP_IDX__PRE                                           0x13

#define    QAM_FQ_CENTTAP_IDX_IDX__B                                       0
#define    QAM_FQ_CENTTAP_IDX_IDX__W                                       5
#define    QAM_FQ_CENTTAP_IDX_IDX__M                                       0x1F
#define    QAM_FQ_CENTTAP_IDX_IDX__PRE                                     0x13

#define  QAM_FQ_CENTTAP_VALUE__A                                           0x1420017
#define  QAM_FQ_CENTTAP_VALUE__W                                           12
#define  QAM_FQ_CENTTAP_VALUE__M                                           0xFFF
#define  QAM_FQ_CENTTAP_VALUE__PRE                                         0x600

#define    QAM_FQ_CENTTAP_VALUE_TAP__B                                     0
#define    QAM_FQ_CENTTAP_VALUE_TAP__W                                     12
#define    QAM_FQ_CENTTAP_VALUE_TAP__M                                     0xFFF
#define    QAM_FQ_CENTTAP_VALUE_TAP__PRE                                   0x600

#define  QAM_FQ_TAP_RE_EL0__A                                              0x1420020
#define  QAM_FQ_TAP_RE_EL0__W                                              12
#define  QAM_FQ_TAP_RE_EL0__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL0__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL0_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL0_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL0_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL0_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL0__A                                              0x1420021
#define  QAM_FQ_TAP_IM_EL0__W                                              12
#define  QAM_FQ_TAP_IM_EL0__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL0__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL0_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL0_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL0_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL0_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL1__A                                              0x1420022
#define  QAM_FQ_TAP_RE_EL1__W                                              12
#define  QAM_FQ_TAP_RE_EL1__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL1__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL1_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL1_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL1_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL1_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL1__A                                              0x1420023
#define  QAM_FQ_TAP_IM_EL1__W                                              12
#define  QAM_FQ_TAP_IM_EL1__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL1__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL1_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL1_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL1_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL1_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL2__A                                              0x1420024
#define  QAM_FQ_TAP_RE_EL2__W                                              12
#define  QAM_FQ_TAP_RE_EL2__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL2__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL2_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL2_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL2_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL2_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL2__A                                              0x1420025
#define  QAM_FQ_TAP_IM_EL2__W                                              12
#define  QAM_FQ_TAP_IM_EL2__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL2__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL2_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL2_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL2_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL2_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL3__A                                              0x1420026
#define  QAM_FQ_TAP_RE_EL3__W                                              12
#define  QAM_FQ_TAP_RE_EL3__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL3__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL3_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL3_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL3_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL3_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL3__A                                              0x1420027
#define  QAM_FQ_TAP_IM_EL3__W                                              12
#define  QAM_FQ_TAP_IM_EL3__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL3__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL3_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL3_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL3_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL3_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL4__A                                              0x1420028
#define  QAM_FQ_TAP_RE_EL4__W                                              12
#define  QAM_FQ_TAP_RE_EL4__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL4__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL4_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL4_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL4_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL4_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL4__A                                              0x1420029
#define  QAM_FQ_TAP_IM_EL4__W                                              12
#define  QAM_FQ_TAP_IM_EL4__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL4__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL4_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL4_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL4_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL4_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL5__A                                              0x142002A
#define  QAM_FQ_TAP_RE_EL5__W                                              12
#define  QAM_FQ_TAP_RE_EL5__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL5__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL5_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL5_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL5_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL5_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL5__A                                              0x142002B
#define  QAM_FQ_TAP_IM_EL5__W                                              12
#define  QAM_FQ_TAP_IM_EL5__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL5__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL5_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL5_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL5_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL5_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL6__A                                              0x142002C
#define  QAM_FQ_TAP_RE_EL6__W                                              12
#define  QAM_FQ_TAP_RE_EL6__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL6__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL6_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL6_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL6_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL6_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL6__A                                              0x142002D
#define  QAM_FQ_TAP_IM_EL6__W                                              12
#define  QAM_FQ_TAP_IM_EL6__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL6__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL6_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL6_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL6_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL6_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL7__A                                              0x142002E
#define  QAM_FQ_TAP_RE_EL7__W                                              12
#define  QAM_FQ_TAP_RE_EL7__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL7__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL7_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL7_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL7_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL7_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL7__A                                              0x142002F
#define  QAM_FQ_TAP_IM_EL7__W                                              12
#define  QAM_FQ_TAP_IM_EL7__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL7__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL7_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL7_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL7_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL7_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL8__A                                              0x1420030
#define  QAM_FQ_TAP_RE_EL8__W                                              12
#define  QAM_FQ_TAP_RE_EL8__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL8__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL8_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL8_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL8_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL8_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL8__A                                              0x1420031
#define  QAM_FQ_TAP_IM_EL8__W                                              12
#define  QAM_FQ_TAP_IM_EL8__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL8__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL8_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL8_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL8_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL8_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL9__A                                              0x1420032
#define  QAM_FQ_TAP_RE_EL9__W                                              12
#define  QAM_FQ_TAP_RE_EL9__M                                              0xFFF
#define  QAM_FQ_TAP_RE_EL9__PRE                                            0x2

#define    QAM_FQ_TAP_RE_EL9_TAP__B                                        0
#define    QAM_FQ_TAP_RE_EL9_TAP__W                                        12
#define    QAM_FQ_TAP_RE_EL9_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_RE_EL9_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_IM_EL9__A                                              0x1420033
#define  QAM_FQ_TAP_IM_EL9__W                                              12
#define  QAM_FQ_TAP_IM_EL9__M                                              0xFFF
#define  QAM_FQ_TAP_IM_EL9__PRE                                            0x2

#define    QAM_FQ_TAP_IM_EL9_TAP__B                                        0
#define    QAM_FQ_TAP_IM_EL9_TAP__W                                        12
#define    QAM_FQ_TAP_IM_EL9_TAP__M                                        0xFFF
#define    QAM_FQ_TAP_IM_EL9_TAP__PRE                                      0x2

#define  QAM_FQ_TAP_RE_EL10__A                                             0x1420034
#define  QAM_FQ_TAP_RE_EL10__W                                             12
#define  QAM_FQ_TAP_RE_EL10__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL10__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL10_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL10_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL10_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL10_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL10__A                                             0x1420035
#define  QAM_FQ_TAP_IM_EL10__W                                             12
#define  QAM_FQ_TAP_IM_EL10__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL10__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL10_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL10_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL10_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL10_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL11__A                                             0x1420036
#define  QAM_FQ_TAP_RE_EL11__W                                             12
#define  QAM_FQ_TAP_RE_EL11__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL11__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL11_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL11_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL11_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL11_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL11__A                                             0x1420037
#define  QAM_FQ_TAP_IM_EL11__W                                             12
#define  QAM_FQ_TAP_IM_EL11__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL11__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL11_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL11_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL11_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL11_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL12__A                                             0x1420038
#define  QAM_FQ_TAP_RE_EL12__W                                             12
#define  QAM_FQ_TAP_RE_EL12__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL12__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL12_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL12_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL12_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL12_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL12__A                                             0x1420039
#define  QAM_FQ_TAP_IM_EL12__W                                             12
#define  QAM_FQ_TAP_IM_EL12__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL12__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL12_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL12_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL12_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL12_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL13__A                                             0x142003A
#define  QAM_FQ_TAP_RE_EL13__W                                             12
#define  QAM_FQ_TAP_RE_EL13__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL13__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL13_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL13_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL13_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL13_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL13__A                                             0x142003B
#define  QAM_FQ_TAP_IM_EL13__W                                             12
#define  QAM_FQ_TAP_IM_EL13__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL13__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL13_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL13_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL13_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL13_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL14__A                                             0x142003C
#define  QAM_FQ_TAP_RE_EL14__W                                             12
#define  QAM_FQ_TAP_RE_EL14__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL14__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL14_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL14_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL14_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL14_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL14__A                                             0x142003D
#define  QAM_FQ_TAP_IM_EL14__W                                             12
#define  QAM_FQ_TAP_IM_EL14__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL14__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL14_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL14_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL14_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL14_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL15__A                                             0x142003E
#define  QAM_FQ_TAP_RE_EL15__W                                             12
#define  QAM_FQ_TAP_RE_EL15__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL15__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL15_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL15_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL15_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL15_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL15__A                                             0x142003F
#define  QAM_FQ_TAP_IM_EL15__W                                             12
#define  QAM_FQ_TAP_IM_EL15__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL15__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL15_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL15_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL15_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL15_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL16__A                                             0x1420040
#define  QAM_FQ_TAP_RE_EL16__W                                             12
#define  QAM_FQ_TAP_RE_EL16__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL16__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL16_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL16_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL16_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL16_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL16__A                                             0x1420041
#define  QAM_FQ_TAP_IM_EL16__W                                             12
#define  QAM_FQ_TAP_IM_EL16__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL16__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL16_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL16_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL16_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL16_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL17__A                                             0x1420042
#define  QAM_FQ_TAP_RE_EL17__W                                             12
#define  QAM_FQ_TAP_RE_EL17__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL17__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL17_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL17_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL17_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL17_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL17__A                                             0x1420043
#define  QAM_FQ_TAP_IM_EL17__W                                             12
#define  QAM_FQ_TAP_IM_EL17__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL17__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL17_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL17_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL17_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL17_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL18__A                                             0x1420044
#define  QAM_FQ_TAP_RE_EL18__W                                             12
#define  QAM_FQ_TAP_RE_EL18__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL18__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL18_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL18_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL18_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL18_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL18__A                                             0x1420045
#define  QAM_FQ_TAP_IM_EL18__W                                             12
#define  QAM_FQ_TAP_IM_EL18__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL18__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL18_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL18_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL18_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL18_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL19__A                                             0x1420046
#define  QAM_FQ_TAP_RE_EL19__W                                             12
#define  QAM_FQ_TAP_RE_EL19__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL19__PRE                                           0x600

#define    QAM_FQ_TAP_RE_EL19_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL19_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL19_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL19_TAP__PRE                                     0x600

#define  QAM_FQ_TAP_IM_EL19__A                                             0x1420047
#define  QAM_FQ_TAP_IM_EL19__W                                             12
#define  QAM_FQ_TAP_IM_EL19__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL19__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL19_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL19_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL19_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL19_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL20__A                                             0x1420048
#define  QAM_FQ_TAP_RE_EL20__W                                             12
#define  QAM_FQ_TAP_RE_EL20__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL20__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL20_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL20_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL20_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL20_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL20__A                                             0x1420049
#define  QAM_FQ_TAP_IM_EL20__W                                             12
#define  QAM_FQ_TAP_IM_EL20__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL20__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL20_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL20_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL20_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL20_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL21__A                                             0x142004A
#define  QAM_FQ_TAP_RE_EL21__W                                             12
#define  QAM_FQ_TAP_RE_EL21__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL21__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL21_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL21_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL21_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL21_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL21__A                                             0x142004B
#define  QAM_FQ_TAP_IM_EL21__W                                             12
#define  QAM_FQ_TAP_IM_EL21__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL21__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL21_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL21_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL21_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL21_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL22__A                                             0x142004C
#define  QAM_FQ_TAP_RE_EL22__W                                             12
#define  QAM_FQ_TAP_RE_EL22__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL22__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL22_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL22_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL22_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL22_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL22__A                                             0x142004D
#define  QAM_FQ_TAP_IM_EL22__W                                             12
#define  QAM_FQ_TAP_IM_EL22__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL22__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL22_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL22_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL22_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL22_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_RE_EL23__A                                             0x142004E
#define  QAM_FQ_TAP_RE_EL23__W                                             12
#define  QAM_FQ_TAP_RE_EL23__M                                             0xFFF
#define  QAM_FQ_TAP_RE_EL23__PRE                                           0x2

#define    QAM_FQ_TAP_RE_EL23_TAP__B                                       0
#define    QAM_FQ_TAP_RE_EL23_TAP__W                                       12
#define    QAM_FQ_TAP_RE_EL23_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_RE_EL23_TAP__PRE                                     0x2

#define  QAM_FQ_TAP_IM_EL23__A                                             0x142004F
#define  QAM_FQ_TAP_IM_EL23__W                                             12
#define  QAM_FQ_TAP_IM_EL23__M                                             0xFFF
#define  QAM_FQ_TAP_IM_EL23__PRE                                           0x2

#define    QAM_FQ_TAP_IM_EL23_TAP__B                                       0
#define    QAM_FQ_TAP_IM_EL23_TAP__W                                       12
#define    QAM_FQ_TAP_IM_EL23_TAP__M                                       0xFFF
#define    QAM_FQ_TAP_IM_EL23_TAP__PRE                                     0x2



#define  QAM_SL_COMM_EXEC__A                                               0x1430000
#define  QAM_SL_COMM_EXEC__W                                               2
#define  QAM_SL_COMM_EXEC__M                                               0x3
#define  QAM_SL_COMM_EXEC__PRE                                             0x0
#define    QAM_SL_COMM_EXEC_STOP                                           0x0
#define    QAM_SL_COMM_EXEC_ACTIVE                                         0x1
#define    QAM_SL_COMM_EXEC_HOLD                                           0x2

#define  QAM_SL_COMM_MB__A                                                 0x1430002
#define  QAM_SL_COMM_MB__W                                                 4
#define  QAM_SL_COMM_MB__M                                                 0xF
#define  QAM_SL_COMM_MB__PRE                                               0x0
#define    QAM_SL_COMM_MB_CTL__B                                           0
#define    QAM_SL_COMM_MB_CTL__W                                           1
#define    QAM_SL_COMM_MB_CTL__M                                           0x1
#define    QAM_SL_COMM_MB_CTL__PRE                                         0x0
#define      QAM_SL_COMM_MB_CTL_OFF                                        0x0
#define      QAM_SL_COMM_MB_CTL_ON                                         0x1
#define    QAM_SL_COMM_MB_OBS__B                                           1
#define    QAM_SL_COMM_MB_OBS__W                                           1
#define    QAM_SL_COMM_MB_OBS__M                                           0x2
#define    QAM_SL_COMM_MB_OBS__PRE                                         0x0
#define      QAM_SL_COMM_MB_OBS_OFF                                        0x0
#define      QAM_SL_COMM_MB_OBS_ON                                         0x2
#define    QAM_SL_COMM_MB_MUX_OBS__B                                       2
#define    QAM_SL_COMM_MB_MUX_OBS__W                                       2
#define    QAM_SL_COMM_MB_MUX_OBS__M                                       0xC
#define    QAM_SL_COMM_MB_MUX_OBS__PRE                                     0x0
#define      QAM_SL_COMM_MB_MUX_OBS_CONST_CORR                             0x0
#define      QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O                             0x4
#define      QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O                             0x8
#define      QAM_SL_COMM_MB_MUX_OBS_VDEC_O                                 0xC

#define  QAM_SL_COMM_INT_REQ__A                                            0x1430003
#define  QAM_SL_COMM_INT_REQ__W                                            1
#define  QAM_SL_COMM_INT_REQ__M                                            0x1
#define  QAM_SL_COMM_INT_REQ__PRE                                          0x0
#define  QAM_SL_COMM_INT_STA__A                                            0x1430005
#define  QAM_SL_COMM_INT_STA__W                                            2
#define  QAM_SL_COMM_INT_STA__M                                            0x3
#define  QAM_SL_COMM_INT_STA__PRE                                          0x0

#define    QAM_SL_COMM_INT_STA_MED_ERR_INT__B                              0
#define    QAM_SL_COMM_INT_STA_MED_ERR_INT__W                              1
#define    QAM_SL_COMM_INT_STA_MED_ERR_INT__M                              0x1
#define    QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE                            0x0

#define    QAM_SL_COMM_INT_STA_MER_INT__B                                  1
#define    QAM_SL_COMM_INT_STA_MER_INT__W                                  1
#define    QAM_SL_COMM_INT_STA_MER_INT__M                                  0x2
#define    QAM_SL_COMM_INT_STA_MER_INT__PRE                                0x0

#define  QAM_SL_COMM_INT_MSK__A                                            0x1430006
#define  QAM_SL_COMM_INT_MSK__W                                            2
#define  QAM_SL_COMM_INT_MSK__M                                            0x3
#define  QAM_SL_COMM_INT_MSK__PRE                                          0x0
#define    QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B                              0
#define    QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W                              1
#define    QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M                              0x1
#define    QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE                            0x0
#define    QAM_SL_COMM_INT_MSK_MER_MSK__B                                  1
#define    QAM_SL_COMM_INT_MSK_MER_MSK__W                                  1
#define    QAM_SL_COMM_INT_MSK_MER_MSK__M                                  0x2
#define    QAM_SL_COMM_INT_MSK_MER_MSK__PRE                                0x0

#define  QAM_SL_COMM_INT_STM__A                                            0x1430007
#define  QAM_SL_COMM_INT_STM__W                                            2
#define  QAM_SL_COMM_INT_STM__M                                            0x3
#define  QAM_SL_COMM_INT_STM__PRE                                          0x0
#define    QAM_SL_COMM_INT_STM_MED_ERR_STM__B                              0
#define    QAM_SL_COMM_INT_STM_MED_ERR_STM__W                              1
#define    QAM_SL_COMM_INT_STM_MED_ERR_STM__M                              0x1
#define    QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE                            0x0
#define    QAM_SL_COMM_INT_STM_MER_STM__B                                  1
#define    QAM_SL_COMM_INT_STM_MER_STM__W                                  1
#define    QAM_SL_COMM_INT_STM_MER_STM__M                                  0x2
#define    QAM_SL_COMM_INT_STM_MER_STM__PRE                                0x0

#define  QAM_SL_MODE__A                                                    0x1430010
#define  QAM_SL_MODE__W                                                    11
#define  QAM_SL_MODE__M                                                    0x7FF
#define  QAM_SL_MODE__PRE                                                  0xA

#define    QAM_SL_MODE_SLICER4LC__B                                        0
#define    QAM_SL_MODE_SLICER4LC__W                                        2
#define    QAM_SL_MODE_SLICER4LC__M                                        0x3
#define    QAM_SL_MODE_SLICER4LC__PRE                                      0x2
#define      QAM_SL_MODE_SLICER4LC_RECT                                    0x0
#define      QAM_SL_MODE_SLICER4LC_ONET                                    0x1
#define      QAM_SL_MODE_SLICER4LC_RAD                                     0x2

#define    QAM_SL_MODE_SLICER4DQ__B                                        2
#define    QAM_SL_MODE_SLICER4DQ__W                                        2
#define    QAM_SL_MODE_SLICER4DQ__M                                        0xC
#define    QAM_SL_MODE_SLICER4DQ__PRE                                      0x8
#define      QAM_SL_MODE_SLICER4DQ_RECT                                    0x0
#define      QAM_SL_MODE_SLICER4DQ_ONET                                    0x4
#define      QAM_SL_MODE_SLICER4DQ_RAD                                     0x8

#define    QAM_SL_MODE_SLICER4VD__B                                        4
#define    QAM_SL_MODE_SLICER4VD__W                                        2
#define    QAM_SL_MODE_SLICER4VD__M                                        0x30
#define    QAM_SL_MODE_SLICER4VD__PRE                                      0x0
#define      QAM_SL_MODE_SLICER4VD_RECT                                    0x0
#define      QAM_SL_MODE_SLICER4VD_ONET                                    0x10
#define      QAM_SL_MODE_SLICER4VD_RAD                                     0x20

#define    QAM_SL_MODE_ROT_DIS__B                                          6
#define    QAM_SL_MODE_ROT_DIS__W                                          1
#define    QAM_SL_MODE_ROT_DIS__M                                          0x40
#define    QAM_SL_MODE_ROT_DIS__PRE                                        0x0
#define      QAM_SL_MODE_ROT_DIS_ROTATE                                    0x0
#define      QAM_SL_MODE_ROT_DIS_DISABLED                                  0x40

#define    QAM_SL_MODE_DQROT_DIS__B                                        7
#define    QAM_SL_MODE_DQROT_DIS__W                                        1
#define    QAM_SL_MODE_DQROT_DIS__M                                        0x80
#define    QAM_SL_MODE_DQROT_DIS__PRE                                      0x0
#define      QAM_SL_MODE_DQROT_DIS_ROTATE                                  0x0
#define      QAM_SL_MODE_DQROT_DIS_DISABLED                                0x80

#define    QAM_SL_MODE_DFE_DIS__B                                          8
#define    QAM_SL_MODE_DFE_DIS__W                                          1
#define    QAM_SL_MODE_DFE_DIS__M                                          0x100
#define    QAM_SL_MODE_DFE_DIS__PRE                                        0x0
#define      QAM_SL_MODE_DFE_DIS_DQ                                        0x0
#define      QAM_SL_MODE_DFE_DIS_DISABLED                                  0x100

#define    QAM_SL_MODE_RADIUS_MIX__B                                       9
#define    QAM_SL_MODE_RADIUS_MIX__W                                       1
#define    QAM_SL_MODE_RADIUS_MIX__M                                       0x200
#define    QAM_SL_MODE_RADIUS_MIX__PRE                                     0x0
#define      QAM_SL_MODE_RADIUS_MIX_OFF                                    0x0
#define      QAM_SL_MODE_RADIUS_MIX_RADMIX                                 0x200

#define    QAM_SL_MODE_TILT_COMP__B                                        10
#define    QAM_SL_MODE_TILT_COMP__W                                        1
#define    QAM_SL_MODE_TILT_COMP__M                                        0x400
#define    QAM_SL_MODE_TILT_COMP__PRE                                      0x0
#define      QAM_SL_MODE_TILT_COMP_OFF                                     0x0
#define      QAM_SL_MODE_TILT_COMP_TILTCOMP                                0x400


#define  QAM_SL_K_FACTOR__A                                                0x1430011
#define  QAM_SL_K_FACTOR__W                                                4
#define  QAM_SL_K_FACTOR__M                                                0xF
#define  QAM_SL_K_FACTOR__PRE                                              0xC
#define  QAM_SL_MEDIAN__A                                                  0x1430012
#define  QAM_SL_MEDIAN__W                                                  14
#define  QAM_SL_MEDIAN__M                                                  0x3FFF
#define  QAM_SL_MEDIAN__PRE                                                0x2C86

#define    QAM_SL_MEDIAN_LENGTH__B                                         0
#define    QAM_SL_MEDIAN_LENGTH__W                                         2
#define    QAM_SL_MEDIAN_LENGTH__M                                         0x3
#define    QAM_SL_MEDIAN_LENGTH__PRE                                       0x2
#define      QAM_SL_MEDIAN_LENGTH_MEDL1                                    0x0
#define      QAM_SL_MEDIAN_LENGTH_MEDL2                                    0x1
#define      QAM_SL_MEDIAN_LENGTH_MEDL4                                    0x2
#define      QAM_SL_MEDIAN_LENGTH_MEDL8                                    0x3

#define    QAM_SL_MEDIAN_CORRECT__B                                        2
#define    QAM_SL_MEDIAN_CORRECT__W                                        4
#define    QAM_SL_MEDIAN_CORRECT__M                                        0x3C
#define    QAM_SL_MEDIAN_CORRECT__PRE                                      0x4

#define    QAM_SL_MEDIAN_TOLERANCE__B                                      6
#define    QAM_SL_MEDIAN_TOLERANCE__W                                      7
#define    QAM_SL_MEDIAN_TOLERANCE__M                                      0x1FC0
#define    QAM_SL_MEDIAN_TOLERANCE__PRE                                    0xC80

#define    QAM_SL_MEDIAN_FAST__B                                           13
#define    QAM_SL_MEDIAN_FAST__W                                           1
#define    QAM_SL_MEDIAN_FAST__M                                           0x2000
#define    QAM_SL_MEDIAN_FAST__PRE                                         0x2000
#define      QAM_SL_MEDIAN_FAST_AVER                                       0x0
#define      QAM_SL_MEDIAN_FAST_LAST                                       0x2000


#define  QAM_SL_ALPHA__A                                                   0x1430013
#define  QAM_SL_ALPHA__W                                                   3
#define  QAM_SL_ALPHA__M                                                   0x7
#define  QAM_SL_ALPHA__PRE                                                 0x0

#define  QAM_SL_PHASELIMIT__A                                              0x1430014
#define  QAM_SL_PHASELIMIT__W                                              9
#define  QAM_SL_PHASELIMIT__M                                              0x1FF
#define  QAM_SL_PHASELIMIT__PRE                                            0x0
#define  QAM_SL_MTA_LENGTH__A                                              0x1430015
#define  QAM_SL_MTA_LENGTH__W                                              2
#define  QAM_SL_MTA_LENGTH__M                                              0x3
#define  QAM_SL_MTA_LENGTH__PRE                                            0x1

#define    QAM_SL_MTA_LENGTH_LENGTH__B                                     0
#define    QAM_SL_MTA_LENGTH_LENGTH__W                                     2
#define    QAM_SL_MTA_LENGTH_LENGTH__M                                     0x3
#define    QAM_SL_MTA_LENGTH_LENGTH__PRE                                   0x1

#define  QAM_SL_MEDIAN_ERROR__A                                            0x1430016
#define  QAM_SL_MEDIAN_ERROR__W                                            10
#define  QAM_SL_MEDIAN_ERROR__M                                            0x3FF
#define  QAM_SL_MEDIAN_ERROR__PRE                                          0x0

#define    QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B                               0
#define    QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W                               10
#define    QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M                               0x3FF
#define    QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE                             0x0


#define  QAM_SL_ERR_POWER__A                                               0x1430017
#define  QAM_SL_ERR_POWER__W                                               16
#define  QAM_SL_ERR_POWER__M                                               0xFFFF
#define  QAM_SL_ERR_POWER__PRE                                             0x0
#define  QAM_SL_QUAL_QAM_4_0__A                                            0x1430018
#define  QAM_SL_QUAL_QAM_4_0__W                                            3
#define  QAM_SL_QUAL_QAM_4_0__M                                            0x7
#define  QAM_SL_QUAL_QAM_4_0__PRE                                          0x5

#define    QAM_SL_QUAL_QAM_4_0_Q0__B                                       0
#define    QAM_SL_QUAL_QAM_4_0_Q0__W                                       3
#define    QAM_SL_QUAL_QAM_4_0_Q0__M                                       0x7
#define    QAM_SL_QUAL_QAM_4_0_Q0__PRE                                     0x5

#define  QAM_SL_QUAL_QAM_8_0__A                                            0x1430019
#define  QAM_SL_QUAL_QAM_8_0__W                                            6
#define  QAM_SL_QUAL_QAM_8_0__M                                            0x3F
#define  QAM_SL_QUAL_QAM_8_0__PRE                                          0xD

#define    QAM_SL_QUAL_QAM_8_0_Q0__B                                       0
#define    QAM_SL_QUAL_QAM_8_0_Q0__W                                       3
#define    QAM_SL_QUAL_QAM_8_0_Q0__M                                       0x7
#define    QAM_SL_QUAL_QAM_8_0_Q0__PRE                                     0x5

#define    QAM_SL_QUAL_QAM_8_0_Q1__B                                       3
#define    QAM_SL_QUAL_QAM_8_0_Q1__W                                       3
#define    QAM_SL_QUAL_QAM_8_0_Q1__M                                       0x38
#define    QAM_SL_QUAL_QAM_8_0_Q1__PRE                                     0x8

#define  QAM_SL_QUAL_QAM_16_0__A                                           0x143001A
#define  QAM_SL_QUAL_QAM_16_0__W                                           3
#define  QAM_SL_QUAL_QAM_16_0__M                                           0x7
#define  QAM_SL_QUAL_QAM_16_0__PRE                                         0x1

#define    QAM_SL_QUAL_QAM_16_0_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_16_0_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_16_0_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_16_0_Q0__PRE                                    0x1

#define  QAM_SL_QUAL_QAM_16_1__A                                           0x143001B
#define  QAM_SL_QUAL_QAM_16_1__W                                           6
#define  QAM_SL_QUAL_QAM_16_1__M                                           0x3F
#define  QAM_SL_QUAL_QAM_16_1__PRE                                         0x5

#define    QAM_SL_QUAL_QAM_16_1_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_16_1_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_16_1_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_16_1_Q0__PRE                                    0x5

#define    QAM_SL_QUAL_QAM_16_1_Q1__B                                      3
#define    QAM_SL_QUAL_QAM_16_1_Q1__W                                      3
#define    QAM_SL_QUAL_QAM_16_1_Q1__M                                      0x38
#define    QAM_SL_QUAL_QAM_16_1_Q1__PRE                                    0x0

#define  QAM_SL_QUAL_QAM_32_0__A                                           0x143001C
#define  QAM_SL_QUAL_QAM_32_0__W                                           3
#define  QAM_SL_QUAL_QAM_32_0__M                                           0x7
#define  QAM_SL_QUAL_QAM_32_0__PRE                                         0x4

#define    QAM_SL_QUAL_QAM_32_0_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_32_0_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_32_0_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_32_0_Q0__PRE                                    0x4

#define  QAM_SL_QUAL_QAM_32_1__A                                           0x143001D
#define  QAM_SL_QUAL_QAM_32_1__W                                           6
#define  QAM_SL_QUAL_QAM_32_1__M                                           0x3F
#define  QAM_SL_QUAL_QAM_32_1__PRE                                         0x3

#define    QAM_SL_QUAL_QAM_32_1_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_32_1_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_32_1_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_32_1_Q0__PRE                                    0x3

#define    QAM_SL_QUAL_QAM_32_1_Q1__B                                      3
#define    QAM_SL_QUAL_QAM_32_1_Q1__W                                      3
#define    QAM_SL_QUAL_QAM_32_1_Q1__M                                      0x38
#define    QAM_SL_QUAL_QAM_32_1_Q1__PRE                                    0x0

#define  QAM_SL_QUAL_QAM_32_2__A                                           0x143001E
#define  QAM_SL_QUAL_QAM_32_2__W                                           9
#define  QAM_SL_QUAL_QAM_32_2__M                                           0x1FF
#define  QAM_SL_QUAL_QAM_32_2__PRE                                         0x0

#define    QAM_SL_QUAL_QAM_32_2_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_32_2_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_32_2_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_32_2_Q0__PRE                                    0x0

#define    QAM_SL_QUAL_QAM_32_2_Q1__B                                      3
#define    QAM_SL_QUAL_QAM_32_2_Q1__W                                      3
#define    QAM_SL_QUAL_QAM_32_2_Q1__M                                      0x38
#define    QAM_SL_QUAL_QAM_32_2_Q1__PRE                                    0x0

#define    QAM_SL_QUAL_QAM_32_2_Q2__B                                      6
#define    QAM_SL_QUAL_QAM_32_2_Q2__W                                      3
#define    QAM_SL_QUAL_QAM_32_2_Q2__M                                      0x1C0
#define    QAM_SL_QUAL_QAM_32_2_Q2__PRE                                    0x0

#define  QAM_SL_QUAL_QAM_64_0__A                                           0x143001F
#define  QAM_SL_QUAL_QAM_64_0__W                                           3
#define  QAM_SL_QUAL_QAM_64_0__M                                           0x7
#define  QAM_SL_QUAL_QAM_64_0__PRE                                         0x1

#define    QAM_SL_QUAL_QAM_64_0_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_64_0_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_64_0_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_64_0_Q0__PRE                                    0x1

#define  QAM_SL_QUAL_QAM_64_1__A                                           0x1430020
#define  QAM_SL_QUAL_QAM_64_1__W                                           6
#define  QAM_SL_QUAL_QAM_64_1__M                                           0x3F
#define  QAM_SL_QUAL_QAM_64_1__PRE                                         0x2

#define    QAM_SL_QUAL_QAM_64_1_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_64_1_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_64_1_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_64_1_Q0__PRE                                    0x2

#define    QAM_SL_QUAL_QAM_64_1_Q1__B                                      3
#define    QAM_SL_QUAL_QAM_64_1_Q1__W                                      3
#define    QAM_SL_QUAL_QAM_64_1_Q1__M                                      0x38
#define    QAM_SL_QUAL_QAM_64_1_Q1__PRE                                    0x0

#define  QAM_SL_QUAL_QAM_64_2__A                                           0x1430021
#define  QAM_SL_QUAL_QAM_64_2__W                                           9
#define  QAM_SL_QUAL_QAM_64_2__M                                           0x1FF
#define  QAM_SL_QUAL_QAM_64_2__PRE                                         0x9

#define    QAM_SL_QUAL_QAM_64_2_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_64_2_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_64_2_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_64_2_Q0__PRE                                    0x1

#define    QAM_SL_QUAL_QAM_64_2_Q1__B                                      3
#define    QAM_SL_QUAL_QAM_64_2_Q1__W                                      3
#define    QAM_SL_QUAL_QAM_64_2_Q1__M                                      0x38
#define    QAM_SL_QUAL_QAM_64_2_Q1__PRE                                    0x8

#define    QAM_SL_QUAL_QAM_64_2_Q2__B                                      6
#define    QAM_SL_QUAL_QAM_64_2_Q2__W                                      3
#define    QAM_SL_QUAL_QAM_64_2_Q2__M                                      0x1C0
#define    QAM_SL_QUAL_QAM_64_2_Q2__PRE                                    0x0

#define  QAM_SL_QUAL_QAM_64_3__A                                           0x1430022
#define  QAM_SL_QUAL_QAM_64_3__W                                           12
#define  QAM_SL_QUAL_QAM_64_3__M                                           0xFFF
#define  QAM_SL_QUAL_QAM_64_3__PRE                                         0xD

#define    QAM_SL_QUAL_QAM_64_3_Q0__B                                      0
#define    QAM_SL_QUAL_QAM_64_3_Q0__W                                      3
#define    QAM_SL_QUAL_QAM_64_3_Q0__M                                      0x7
#define    QAM_SL_QUAL_QAM_64_3_Q0__PRE                                    0x5

#define    QAM_SL_QUAL_QAM_64_3_Q1__B                                      3
#define    QAM_SL_QUAL_QAM_64_3_Q1__W                                      3
#define    QAM_SL_QUAL_QAM_64_3_Q1__M                                      0x38
#define    QAM_SL_QUAL_QAM_64_3_Q1__PRE                                    0x8

#define    QAM_SL_QUAL_QAM_64_3_Q2__B                                      6
#define    QAM_SL_QUAL_QAM_64_3_Q2__W                                      3
#define    QAM_SL_QUAL_QAM_64_3_Q2__M                                      0x1C0
#define    QAM_SL_QUAL_QAM_64_3_Q2__PRE                                    0x0

#define    QAM_SL_QUAL_QAM_64_3_Q3__B                                      9
#define    QAM_SL_QUAL_QAM_64_3_Q3__W                                      3
#define    QAM_SL_QUAL_QAM_64_3_Q3__M                                      0xE00
#define    QAM_SL_QUAL_QAM_64_3_Q3__PRE                                    0x0

#define  QAM_SL_QUAL_QAM_128_0__A                                          0x1430023
#define  QAM_SL_QUAL_QAM_128_0__W                                          3
#define  QAM_SL_QUAL_QAM_128_0__M                                          0x7
#define  QAM_SL_QUAL_QAM_128_0__PRE                                        0x4

#define    QAM_SL_QUAL_QAM_128_0_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_128_0_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_128_0_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_128_0_Q0__PRE                                   0x4

#define  QAM_SL_QUAL_QAM_128_1__A                                          0x1430024
#define  QAM_SL_QUAL_QAM_128_1__W                                          6
#define  QAM_SL_QUAL_QAM_128_1__M                                          0x3F
#define  QAM_SL_QUAL_QAM_128_1__PRE                                        0x5

#define    QAM_SL_QUAL_QAM_128_1_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_128_1_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_128_1_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_128_1_Q0__PRE                                   0x5

#define    QAM_SL_QUAL_QAM_128_1_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_128_1_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_128_1_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_128_1_Q1__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_128_2__A                                          0x1430025
#define  QAM_SL_QUAL_QAM_128_2__W                                          9
#define  QAM_SL_QUAL_QAM_128_2__M                                          0x1FF
#define  QAM_SL_QUAL_QAM_128_2__PRE                                        0x1

#define    QAM_SL_QUAL_QAM_128_2_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_128_2_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_128_2_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_128_2_Q0__PRE                                   0x1

#define    QAM_SL_QUAL_QAM_128_2_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_128_2_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_128_2_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_128_2_Q1__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_2_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_128_2_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_128_2_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_128_2_Q2__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_128_3__A                                          0x1430026
#define  QAM_SL_QUAL_QAM_128_3__W                                          12
#define  QAM_SL_QUAL_QAM_128_3__M                                          0xFFF
#define  QAM_SL_QUAL_QAM_128_3__PRE                                        0x1

#define    QAM_SL_QUAL_QAM_128_3_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_128_3_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_128_3_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_128_3_Q0__PRE                                   0x1

#define    QAM_SL_QUAL_QAM_128_3_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_128_3_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_128_3_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_128_3_Q1__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_3_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_128_3_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_128_3_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_128_3_Q2__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_3_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_128_3_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_128_3_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_128_3_Q3__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_128_4__A                                          0x1430027
#define  QAM_SL_QUAL_QAM_128_4__W                                          15
#define  QAM_SL_QUAL_QAM_128_4__M                                          0x7FFF
#define  QAM_SL_QUAL_QAM_128_4__PRE                                        0x0

#define    QAM_SL_QUAL_QAM_128_4_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_128_4_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_128_4_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_128_4_Q0__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_4_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_128_4_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_128_4_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_128_4_Q1__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_4_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_128_4_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_128_4_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_128_4_Q2__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_4_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_128_4_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_128_4_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_128_4_Q3__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_4_Q4__B                                     12
#define    QAM_SL_QUAL_QAM_128_4_Q4__W                                     3
#define    QAM_SL_QUAL_QAM_128_4_Q4__M                                     0x7000
#define    QAM_SL_QUAL_QAM_128_4_Q4__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_128_5__A                                          0x1430028
#define  QAM_SL_QUAL_QAM_128_5__W                                          15
#define  QAM_SL_QUAL_QAM_128_5__M                                          0x7FFF
#define  QAM_SL_QUAL_QAM_128_5__PRE                                        0x90

#define    QAM_SL_QUAL_QAM_128_5_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_128_5_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_128_5_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_128_5_Q0__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_5_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_128_5_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_128_5_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_128_5_Q1__PRE                                   0x10

#define    QAM_SL_QUAL_QAM_128_5_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_128_5_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_128_5_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_128_5_Q2__PRE                                   0x80

#define    QAM_SL_QUAL_QAM_128_5_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_128_5_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_128_5_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_128_5_Q3__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_128_5_Q4__B                                     12
#define    QAM_SL_QUAL_QAM_128_5_Q4__W                                     3
#define    QAM_SL_QUAL_QAM_128_5_Q4__M                                     0x7000
#define    QAM_SL_QUAL_QAM_128_5_Q4__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_128_5H__A                                         0x1430029
#define  QAM_SL_QUAL_QAM_128_5H__W                                         3
#define  QAM_SL_QUAL_QAM_128_5H__M                                         0x7
#define  QAM_SL_QUAL_QAM_128_5H__PRE                                       0x0

#define    QAM_SL_QUAL_QAM_128_5H_Q5__B                                    0
#define    QAM_SL_QUAL_QAM_128_5H_Q5__W                                    3
#define    QAM_SL_QUAL_QAM_128_5H_Q5__M                                    0x7
#define    QAM_SL_QUAL_QAM_128_5H_Q5__PRE                                  0x0

#define  QAM_SL_QUAL_QAM_256_0__A                                          0x143002A
#define  QAM_SL_QUAL_QAM_256_0__W                                          3
#define  QAM_SL_QUAL_QAM_256_0__M                                          0x7
#define  QAM_SL_QUAL_QAM_256_0__PRE                                        0x3

#define    QAM_SL_QUAL_QAM_256_0_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_0_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_0_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_0_Q0__PRE                                   0x3

#define  QAM_SL_QUAL_QAM_256_1__A                                          0x143002B
#define  QAM_SL_QUAL_QAM_256_1__W                                          6
#define  QAM_SL_QUAL_QAM_256_1__M                                          0x3F
#define  QAM_SL_QUAL_QAM_256_1__PRE                                        0x1

#define    QAM_SL_QUAL_QAM_256_1_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_1_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_1_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_1_Q0__PRE                                   0x1

#define    QAM_SL_QUAL_QAM_256_1_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_1_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_1_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_1_Q1__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_2__A                                          0x143002C
#define  QAM_SL_QUAL_QAM_256_2__W                                          9
#define  QAM_SL_QUAL_QAM_256_2__M                                          0x1FF
#define  QAM_SL_QUAL_QAM_256_2__PRE                                        0x9

#define    QAM_SL_QUAL_QAM_256_2_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_2_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_2_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_2_Q0__PRE                                   0x1

#define    QAM_SL_QUAL_QAM_256_2_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_2_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_2_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_2_Q1__PRE                                   0x8

#define    QAM_SL_QUAL_QAM_256_2_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_256_2_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_256_2_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_256_2_Q2__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_3__A                                          0x143002D
#define  QAM_SL_QUAL_QAM_256_3__W                                          12
#define  QAM_SL_QUAL_QAM_256_3__M                                          0xFFF
#define  QAM_SL_QUAL_QAM_256_3__PRE                                        0x13

#define    QAM_SL_QUAL_QAM_256_3_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_3_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_3_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_3_Q0__PRE                                   0x3

#define    QAM_SL_QUAL_QAM_256_3_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_3_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_3_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_3_Q1__PRE                                   0x10

#define    QAM_SL_QUAL_QAM_256_3_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_256_3_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_256_3_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_256_3_Q2__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_256_3_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_256_3_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_256_3_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_256_3_Q3__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_4__A                                          0x143002E
#define  QAM_SL_QUAL_QAM_256_4__W                                          15
#define  QAM_SL_QUAL_QAM_256_4__M                                          0x7FFF
#define  QAM_SL_QUAL_QAM_256_4__PRE                                        0x49

#define    QAM_SL_QUAL_QAM_256_4_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_4_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_4_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_4_Q0__PRE                                   0x1

#define    QAM_SL_QUAL_QAM_256_4_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_4_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_4_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_4_Q1__PRE                                   0x8

#define    QAM_SL_QUAL_QAM_256_4_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_256_4_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_256_4_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_256_4_Q2__PRE                                   0x40

#define    QAM_SL_QUAL_QAM_256_4_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_256_4_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_256_4_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_256_4_Q3__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_256_4_Q4__B                                     12
#define    QAM_SL_QUAL_QAM_256_4_Q4__W                                     3
#define    QAM_SL_QUAL_QAM_256_4_Q4__M                                     0x7000
#define    QAM_SL_QUAL_QAM_256_4_Q4__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_5__A                                          0x143002F
#define  QAM_SL_QUAL_QAM_256_5__W                                          15
#define  QAM_SL_QUAL_QAM_256_5__M                                          0x7FFF
#define  QAM_SL_QUAL_QAM_256_5__PRE                                        0x59

#define    QAM_SL_QUAL_QAM_256_5_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_5_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_5_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_5_Q0__PRE                                   0x1

#define    QAM_SL_QUAL_QAM_256_5_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_5_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_5_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_5_Q1__PRE                                   0x18

#define    QAM_SL_QUAL_QAM_256_5_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_256_5_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_256_5_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_256_5_Q2__PRE                                   0x40

#define    QAM_SL_QUAL_QAM_256_5_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_256_5_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_256_5_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_256_5_Q3__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_256_5_Q4__B                                     12
#define    QAM_SL_QUAL_QAM_256_5_Q4__W                                     3
#define    QAM_SL_QUAL_QAM_256_5_Q4__M                                     0x7000
#define    QAM_SL_QUAL_QAM_256_5_Q4__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_5H__A                                         0x1430030
#define  QAM_SL_QUAL_QAM_256_5H__W                                         3
#define  QAM_SL_QUAL_QAM_256_5H__M                                         0x7
#define  QAM_SL_QUAL_QAM_256_5H__PRE                                       0x0

#define    QAM_SL_QUAL_QAM_256_5H_Q5__B                                    0
#define    QAM_SL_QUAL_QAM_256_5H_Q5__W                                    3
#define    QAM_SL_QUAL_QAM_256_5H_Q5__M                                    0x7
#define    QAM_SL_QUAL_QAM_256_5H_Q5__PRE                                  0x0

#define  QAM_SL_QUAL_QAM_256_6__A                                          0x1430031
#define  QAM_SL_QUAL_QAM_256_6__W                                          15
#define  QAM_SL_QUAL_QAM_256_6__M                                          0x7FFF
#define  QAM_SL_QUAL_QAM_256_6__PRE                                        0x21A

#define    QAM_SL_QUAL_QAM_256_6_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_6_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_6_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_6_Q0__PRE                                   0x2

#define    QAM_SL_QUAL_QAM_256_6_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_6_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_6_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_6_Q1__PRE                                   0x18

#define    QAM_SL_QUAL_QAM_256_6_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_256_6_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_256_6_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_256_6_Q2__PRE                                   0x0

#define    QAM_SL_QUAL_QAM_256_6_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_256_6_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_256_6_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_256_6_Q3__PRE                                   0x200

#define    QAM_SL_QUAL_QAM_256_6_Q4__B                                     12
#define    QAM_SL_QUAL_QAM_256_6_Q4__W                                     3
#define    QAM_SL_QUAL_QAM_256_6_Q4__M                                     0x7000
#define    QAM_SL_QUAL_QAM_256_6_Q4__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_6H__A                                         0x1430032
#define  QAM_SL_QUAL_QAM_256_6H__W                                         6
#define  QAM_SL_QUAL_QAM_256_6H__M                                         0x3F
#define  QAM_SL_QUAL_QAM_256_6H__PRE                                       0x0

#define    QAM_SL_QUAL_QAM_256_6H_Q5__B                                    0
#define    QAM_SL_QUAL_QAM_256_6H_Q5__W                                    3
#define    QAM_SL_QUAL_QAM_256_6H_Q5__M                                    0x7
#define    QAM_SL_QUAL_QAM_256_6H_Q5__PRE                                  0x0

#define    QAM_SL_QUAL_QAM_256_6H_Q6__B                                    3
#define    QAM_SL_QUAL_QAM_256_6H_Q6__W                                    3
#define    QAM_SL_QUAL_QAM_256_6H_Q6__M                                    0x38
#define    QAM_SL_QUAL_QAM_256_6H_Q6__PRE                                  0x0

#define  QAM_SL_QUAL_QAM_256_7__A                                          0x1430033
#define  QAM_SL_QUAL_QAM_256_7__W                                          15
#define  QAM_SL_QUAL_QAM_256_7__M                                          0x7FFF
#define  QAM_SL_QUAL_QAM_256_7__PRE                                        0x29D

#define    QAM_SL_QUAL_QAM_256_7_Q0__B                                     0
#define    QAM_SL_QUAL_QAM_256_7_Q0__W                                     3
#define    QAM_SL_QUAL_QAM_256_7_Q0__M                                     0x7
#define    QAM_SL_QUAL_QAM_256_7_Q0__PRE                                   0x5

#define    QAM_SL_QUAL_QAM_256_7_Q1__B                                     3
#define    QAM_SL_QUAL_QAM_256_7_Q1__W                                     3
#define    QAM_SL_QUAL_QAM_256_7_Q1__M                                     0x38
#define    QAM_SL_QUAL_QAM_256_7_Q1__PRE                                   0x18

#define    QAM_SL_QUAL_QAM_256_7_Q2__B                                     6
#define    QAM_SL_QUAL_QAM_256_7_Q2__W                                     3
#define    QAM_SL_QUAL_QAM_256_7_Q2__M                                     0x1C0
#define    QAM_SL_QUAL_QAM_256_7_Q2__PRE                                   0x80

#define    QAM_SL_QUAL_QAM_256_7_Q3__B                                     9
#define    QAM_SL_QUAL_QAM_256_7_Q3__W                                     3
#define    QAM_SL_QUAL_QAM_256_7_Q3__M                                     0xE00
#define    QAM_SL_QUAL_QAM_256_7_Q3__PRE                                   0x200

#define    QAM_SL_QUAL_QAM_256_7_Q4__B                                     12
#define    QAM_SL_QUAL_QAM_256_7_Q4__W                                     3
#define    QAM_SL_QUAL_QAM_256_7_Q4__M                                     0x7000
#define    QAM_SL_QUAL_QAM_256_7_Q4__PRE                                   0x0

#define  QAM_SL_QUAL_QAM_256_7H__A                                         0x1430034
#define  QAM_SL_QUAL_QAM_256_7H__W                                         9
#define  QAM_SL_QUAL_QAM_256_7H__M                                         0x1FF
#define  QAM_SL_QUAL_QAM_256_7H__PRE                                       0x0

#define    QAM_SL_QUAL_QAM_256_7H_Q5__B                                    0
#define    QAM_SL_QUAL_QAM_256_7H_Q5__W                                    3
#define    QAM_SL_QUAL_QAM_256_7H_Q5__M                                    0x7
#define    QAM_SL_QUAL_QAM_256_7H_Q5__PRE                                  0x0

#define    QAM_SL_QUAL_QAM_256_7H_Q6__B                                    3
#define    QAM_SL_QUAL_QAM_256_7H_Q6__W                                    3
#define    QAM_SL_QUAL_QAM_256_7H_Q6__M                                    0x38
#define    QAM_SL_QUAL_QAM_256_7H_Q6__PRE                                  0x0

#define    QAM_SL_QUAL_QAM_256_7H_Q7__B                                    6
#define    QAM_SL_QUAL_QAM_256_7H_Q7__W                                    3
#define    QAM_SL_QUAL_QAM_256_7H_Q7__M                                    0x1C0
#define    QAM_SL_QUAL_QAM_256_7H_Q7__PRE                                  0x0



#define  QAM_DQ_COMM_EXEC__A                                               0x1440000
#define  QAM_DQ_COMM_EXEC__W                                               2
#define  QAM_DQ_COMM_EXEC__M                                               0x3
#define  QAM_DQ_COMM_EXEC__PRE                                             0x0
#define    QAM_DQ_COMM_EXEC_STOP                                           0x0
#define    QAM_DQ_COMM_EXEC_ACTIVE                                         0x1
#define    QAM_DQ_COMM_EXEC_HOLD                                           0x2

#define  QAM_DQ_MODE__A                                                    0x1440010
#define  QAM_DQ_MODE__W                                                    5
#define  QAM_DQ_MODE__M                                                    0x1F
#define  QAM_DQ_MODE__PRE                                                  0x0

#define    QAM_DQ_MODE_TAPRESET__B                                         0
#define    QAM_DQ_MODE_TAPRESET__W                                         1
#define    QAM_DQ_MODE_TAPRESET__M                                         0x1
#define    QAM_DQ_MODE_TAPRESET__PRE                                       0x0
#define      QAM_DQ_MODE_TAPRESET_RST                                      0x1

#define    QAM_DQ_MODE_TAPLMS__B                                           1
#define    QAM_DQ_MODE_TAPLMS__W                                           1
#define    QAM_DQ_MODE_TAPLMS__M                                           0x2
#define    QAM_DQ_MODE_TAPLMS__PRE                                         0x0
#define      QAM_DQ_MODE_TAPLMS_UPD                                        0x2

#define    QAM_DQ_MODE_TAPDRAIN__B                                         2
#define    QAM_DQ_MODE_TAPDRAIN__W                                         1
#define    QAM_DQ_MODE_TAPDRAIN__M                                         0x4
#define    QAM_DQ_MODE_TAPDRAIN__PRE                                       0x0
#define      QAM_DQ_MODE_TAPDRAIN_DRAIN                                    0x4

#define    QAM_DQ_MODE_FB__B                                               3
#define    QAM_DQ_MODE_FB__W                                               2
#define    QAM_DQ_MODE_FB__M                                               0x18
#define    QAM_DQ_MODE_FB__PRE                                             0x0
#define      QAM_DQ_MODE_FB_CMA                                            0x0
#define      QAM_DQ_MODE_FB_RADIUS                                         0x8
#define      QAM_DQ_MODE_FB_DFB                                            0x10
#define      QAM_DQ_MODE_FB_TRELLIS                                        0x18


#define  QAM_DQ_MU_FACTOR__A                                               0x1440011
#define  QAM_DQ_MU_FACTOR__W                                               3
#define  QAM_DQ_MU_FACTOR__M                                               0x7
#define  QAM_DQ_MU_FACTOR__PRE                                             0x0

#define  QAM_DQ_LA_FACTOR__A                                               0x1440012
#define  QAM_DQ_LA_FACTOR__W                                               4
#define  QAM_DQ_LA_FACTOR__M                                               0xF
#define  QAM_DQ_LA_FACTOR__PRE                                             0xC

#define  QAM_DQ_CMA_RATIO__A                                               0x1440013
#define  QAM_DQ_CMA_RATIO__W                                               14
#define  QAM_DQ_CMA_RATIO__M                                               0x3FFF
#define  QAM_DQ_CMA_RATIO__PRE                                             0x3CF9
#define    QAM_DQ_CMA_RATIO_QPSK                                           0x2000
#define    QAM_DQ_CMA_RATIO_QAM16                                          0x34CD
#define    QAM_DQ_CMA_RATIO_QAM64                                          0x3A00
#define    QAM_DQ_CMA_RATIO_QAM256                                         0x3B4D
#define    QAM_DQ_CMA_RATIO_QAM1024                                        0x3BA0

#define  QAM_DQ_QUAL_RADSEL__A                                             0x1440014
#define  QAM_DQ_QUAL_RADSEL__W                                             3
#define  QAM_DQ_QUAL_RADSEL__M                                             0x7
#define  QAM_DQ_QUAL_RADSEL__PRE                                           0x0

#define    QAM_DQ_QUAL_RADSEL_BIT__B                                       0
#define    QAM_DQ_QUAL_RADSEL_BIT__W                                       3
#define    QAM_DQ_QUAL_RADSEL_BIT__M                                       0x7
#define    QAM_DQ_QUAL_RADSEL_BIT__PRE                                     0x0
#define      QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS                            0x0
#define      QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA                               0x6

#define  QAM_DQ_QUAL_ENA__A                                                0x1440015
#define  QAM_DQ_QUAL_ENA__W                                                1
#define  QAM_DQ_QUAL_ENA__M                                                0x1
#define  QAM_DQ_QUAL_ENA__PRE                                              0x0

#define    QAM_DQ_QUAL_ENA_ENA__B                                          0
#define    QAM_DQ_QUAL_ENA_ENA__W                                          1
#define    QAM_DQ_QUAL_ENA_ENA__M                                          0x1
#define    QAM_DQ_QUAL_ENA_ENA__PRE                                        0x0
#define      QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING                            0x1

#define  QAM_DQ_QUAL_FUN0__A                                               0x1440018
#define  QAM_DQ_QUAL_FUN0__W                                               6
#define  QAM_DQ_QUAL_FUN0__M                                               0x3F
#define  QAM_DQ_QUAL_FUN0__PRE                                             0x4

#define    QAM_DQ_QUAL_FUN0_BIT__B                                         0
#define    QAM_DQ_QUAL_FUN0_BIT__W                                         6
#define    QAM_DQ_QUAL_FUN0_BIT__M                                         0x3F
#define    QAM_DQ_QUAL_FUN0_BIT__PRE                                       0x4

#define  QAM_DQ_QUAL_FUN1__A                                               0x1440019
#define  QAM_DQ_QUAL_FUN1__W                                               6
#define  QAM_DQ_QUAL_FUN1__M                                               0x3F
#define  QAM_DQ_QUAL_FUN1__PRE                                             0x4

#define    QAM_DQ_QUAL_FUN1_BIT__B                                         0
#define    QAM_DQ_QUAL_FUN1_BIT__W                                         6
#define    QAM_DQ_QUAL_FUN1_BIT__M                                         0x3F
#define    QAM_DQ_QUAL_FUN1_BIT__PRE                                       0x4

#define  QAM_DQ_QUAL_FUN2__A                                               0x144001A
#define  QAM_DQ_QUAL_FUN2__W                                               6
#define  QAM_DQ_QUAL_FUN2__M                                               0x3F
#define  QAM_DQ_QUAL_FUN2__PRE                                             0x4

#define    QAM_DQ_QUAL_FUN2_BIT__B                                         0
#define    QAM_DQ_QUAL_FUN2_BIT__W                                         6
#define    QAM_DQ_QUAL_FUN2_BIT__M                                         0x3F
#define    QAM_DQ_QUAL_FUN2_BIT__PRE                                       0x4

#define  QAM_DQ_QUAL_FUN3__A                                               0x144001B
#define  QAM_DQ_QUAL_FUN3__W                                               6
#define  QAM_DQ_QUAL_FUN3__M                                               0x3F
#define  QAM_DQ_QUAL_FUN3__PRE                                             0x4

#define    QAM_DQ_QUAL_FUN3_BIT__B                                         0
#define    QAM_DQ_QUAL_FUN3_BIT__W                                         6
#define    QAM_DQ_QUAL_FUN3_BIT__M                                         0x3F
#define    QAM_DQ_QUAL_FUN3_BIT__PRE                                       0x4

#define  QAM_DQ_QUAL_FUN4__A                                               0x144001C
#define  QAM_DQ_QUAL_FUN4__W                                               6
#define  QAM_DQ_QUAL_FUN4__M                                               0x3F
#define  QAM_DQ_QUAL_FUN4__PRE                                             0x6

#define    QAM_DQ_QUAL_FUN4_BIT__B                                         0
#define    QAM_DQ_QUAL_FUN4_BIT__W                                         6
#define    QAM_DQ_QUAL_FUN4_BIT__M                                         0x3F
#define    QAM_DQ_QUAL_FUN4_BIT__PRE                                       0x6

#define  QAM_DQ_QUAL_FUN5__A                                               0x144001D
#define  QAM_DQ_QUAL_FUN5__W                                               6
#define  QAM_DQ_QUAL_FUN5__M                                               0x3F
#define  QAM_DQ_QUAL_FUN5__PRE                                             0x6

#define    QAM_DQ_QUAL_FUN5_BIT__B                                         0
#define    QAM_DQ_QUAL_FUN5_BIT__W                                         6
#define    QAM_DQ_QUAL_FUN5_BIT__M                                         0x3F
#define    QAM_DQ_QUAL_FUN5_BIT__PRE                                       0x6

#define  QAM_DQ_RAW_LIM__A                                                 0x144001E
#define  QAM_DQ_RAW_LIM__W                                                 5
#define  QAM_DQ_RAW_LIM__M                                                 0x1F
#define  QAM_DQ_RAW_LIM__PRE                                               0x1F

#define    QAM_DQ_RAW_LIM_BIT__B                                           0
#define    QAM_DQ_RAW_LIM_BIT__W                                           5
#define    QAM_DQ_RAW_LIM_BIT__M                                           0x1F
#define    QAM_DQ_RAW_LIM_BIT__PRE                                         0x1F

#define  QAM_DQ_TAP_RE_EL0__A                                              0x1440020
#define  QAM_DQ_TAP_RE_EL0__W                                              12
#define  QAM_DQ_TAP_RE_EL0__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL0__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL0_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL0_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL0_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL0_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL0__A                                              0x1440021
#define  QAM_DQ_TAP_IM_EL0__W                                              12
#define  QAM_DQ_TAP_IM_EL0__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL0__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL0_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL0_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL0_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL0_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL1__A                                              0x1440022
#define  QAM_DQ_TAP_RE_EL1__W                                              12
#define  QAM_DQ_TAP_RE_EL1__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL1__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL1_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL1_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL1_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL1_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL1__A                                              0x1440023
#define  QAM_DQ_TAP_IM_EL1__W                                              12
#define  QAM_DQ_TAP_IM_EL1__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL1__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL1_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL1_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL1_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL1_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL2__A                                              0x1440024
#define  QAM_DQ_TAP_RE_EL2__W                                              12
#define  QAM_DQ_TAP_RE_EL2__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL2__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL2_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL2_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL2_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL2_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL2__A                                              0x1440025
#define  QAM_DQ_TAP_IM_EL2__W                                              12
#define  QAM_DQ_TAP_IM_EL2__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL2__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL2_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL2_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL2_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL2_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL3__A                                              0x1440026
#define  QAM_DQ_TAP_RE_EL3__W                                              12
#define  QAM_DQ_TAP_RE_EL3__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL3__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL3_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL3_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL3_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL3_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL3__A                                              0x1440027
#define  QAM_DQ_TAP_IM_EL3__W                                              12
#define  QAM_DQ_TAP_IM_EL3__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL3__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL3_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL3_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL3_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL3_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL4__A                                              0x1440028
#define  QAM_DQ_TAP_RE_EL4__W                                              12
#define  QAM_DQ_TAP_RE_EL4__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL4__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL4_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL4_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL4_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL4_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL4__A                                              0x1440029
#define  QAM_DQ_TAP_IM_EL4__W                                              12
#define  QAM_DQ_TAP_IM_EL4__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL4__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL4_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL4_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL4_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL4_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL5__A                                              0x144002A
#define  QAM_DQ_TAP_RE_EL5__W                                              12
#define  QAM_DQ_TAP_RE_EL5__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL5__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL5_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL5_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL5_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL5_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL5__A                                              0x144002B
#define  QAM_DQ_TAP_IM_EL5__W                                              12
#define  QAM_DQ_TAP_IM_EL5__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL5__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL5_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL5_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL5_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL5_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL6__A                                              0x144002C
#define  QAM_DQ_TAP_RE_EL6__W                                              12
#define  QAM_DQ_TAP_RE_EL6__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL6__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL6_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL6_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL6_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL6_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL6__A                                              0x144002D
#define  QAM_DQ_TAP_IM_EL6__W                                              12
#define  QAM_DQ_TAP_IM_EL6__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL6__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL6_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL6_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL6_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL6_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL7__A                                              0x144002E
#define  QAM_DQ_TAP_RE_EL7__W                                              12
#define  QAM_DQ_TAP_RE_EL7__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL7__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL7_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL7_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL7_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL7_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL7__A                                              0x144002F
#define  QAM_DQ_TAP_IM_EL7__W                                              12
#define  QAM_DQ_TAP_IM_EL7__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL7__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL7_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL7_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL7_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL7_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL8__A                                              0x1440030
#define  QAM_DQ_TAP_RE_EL8__W                                              12
#define  QAM_DQ_TAP_RE_EL8__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL8__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL8_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL8_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL8_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL8_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL8__A                                              0x1440031
#define  QAM_DQ_TAP_IM_EL8__W                                              12
#define  QAM_DQ_TAP_IM_EL8__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL8__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL8_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL8_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL8_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL8_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL9__A                                              0x1440032
#define  QAM_DQ_TAP_RE_EL9__W                                              12
#define  QAM_DQ_TAP_RE_EL9__M                                              0xFFF
#define  QAM_DQ_TAP_RE_EL9__PRE                                            0x2

#define    QAM_DQ_TAP_RE_EL9_TAP__B                                        0
#define    QAM_DQ_TAP_RE_EL9_TAP__W                                        12
#define    QAM_DQ_TAP_RE_EL9_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_RE_EL9_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_IM_EL9__A                                              0x1440033
#define  QAM_DQ_TAP_IM_EL9__W                                              12
#define  QAM_DQ_TAP_IM_EL9__M                                              0xFFF
#define  QAM_DQ_TAP_IM_EL9__PRE                                            0x2

#define    QAM_DQ_TAP_IM_EL9_TAP__B                                        0
#define    QAM_DQ_TAP_IM_EL9_TAP__W                                        12
#define    QAM_DQ_TAP_IM_EL9_TAP__M                                        0xFFF
#define    QAM_DQ_TAP_IM_EL9_TAP__PRE                                      0x2

#define  QAM_DQ_TAP_RE_EL10__A                                             0x1440034
#define  QAM_DQ_TAP_RE_EL10__W                                             12
#define  QAM_DQ_TAP_RE_EL10__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL10__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL10_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL10_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL10_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL10_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL10__A                                             0x1440035
#define  QAM_DQ_TAP_IM_EL10__W                                             12
#define  QAM_DQ_TAP_IM_EL10__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL10__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL10_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL10_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL10_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL10_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL11__A                                             0x1440036
#define  QAM_DQ_TAP_RE_EL11__W                                             12
#define  QAM_DQ_TAP_RE_EL11__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL11__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL11_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL11_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL11_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL11_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL11__A                                             0x1440037
#define  QAM_DQ_TAP_IM_EL11__W                                             12
#define  QAM_DQ_TAP_IM_EL11__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL11__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL11_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL11_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL11_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL11_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL12__A                                             0x1440038
#define  QAM_DQ_TAP_RE_EL12__W                                             12
#define  QAM_DQ_TAP_RE_EL12__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL12__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL12_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL12_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL12_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL12_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL12__A                                             0x1440039
#define  QAM_DQ_TAP_IM_EL12__W                                             12
#define  QAM_DQ_TAP_IM_EL12__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL12__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL12_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL12_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL12_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL12_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL13__A                                             0x144003A
#define  QAM_DQ_TAP_RE_EL13__W                                             12
#define  QAM_DQ_TAP_RE_EL13__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL13__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL13_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL13_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL13_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL13_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL13__A                                             0x144003B
#define  QAM_DQ_TAP_IM_EL13__W                                             12
#define  QAM_DQ_TAP_IM_EL13__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL13__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL13_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL13_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL13_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL13_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL14__A                                             0x144003C
#define  QAM_DQ_TAP_RE_EL14__W                                             12
#define  QAM_DQ_TAP_RE_EL14__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL14__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL14_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL14_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL14_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL14_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL14__A                                             0x144003D
#define  QAM_DQ_TAP_IM_EL14__W                                             12
#define  QAM_DQ_TAP_IM_EL14__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL14__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL14_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL14_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL14_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL14_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL15__A                                             0x144003E
#define  QAM_DQ_TAP_RE_EL15__W                                             12
#define  QAM_DQ_TAP_RE_EL15__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL15__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL15_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL15_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL15_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL15_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL15__A                                             0x144003F
#define  QAM_DQ_TAP_IM_EL15__W                                             12
#define  QAM_DQ_TAP_IM_EL15__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL15__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL15_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL15_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL15_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL15_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL16__A                                             0x1440040
#define  QAM_DQ_TAP_RE_EL16__W                                             12
#define  QAM_DQ_TAP_RE_EL16__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL16__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL16_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL16_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL16_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL16_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL16__A                                             0x1440041
#define  QAM_DQ_TAP_IM_EL16__W                                             12
#define  QAM_DQ_TAP_IM_EL16__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL16__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL16_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL16_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL16_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL16_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL17__A                                             0x1440042
#define  QAM_DQ_TAP_RE_EL17__W                                             12
#define  QAM_DQ_TAP_RE_EL17__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL17__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL17_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL17_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL17_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL17_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL17__A                                             0x1440043
#define  QAM_DQ_TAP_IM_EL17__W                                             12
#define  QAM_DQ_TAP_IM_EL17__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL17__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL17_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL17_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL17_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL17_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL18__A                                             0x1440044
#define  QAM_DQ_TAP_RE_EL18__W                                             12
#define  QAM_DQ_TAP_RE_EL18__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL18__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL18_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL18_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL18_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL18_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL18__A                                             0x1440045
#define  QAM_DQ_TAP_IM_EL18__W                                             12
#define  QAM_DQ_TAP_IM_EL18__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL18__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL18_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL18_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL18_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL18_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL19__A                                             0x1440046
#define  QAM_DQ_TAP_RE_EL19__W                                             12
#define  QAM_DQ_TAP_RE_EL19__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL19__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL19_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL19_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL19_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL19_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL19__A                                             0x1440047
#define  QAM_DQ_TAP_IM_EL19__W                                             12
#define  QAM_DQ_TAP_IM_EL19__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL19__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL19_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL19_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL19_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL19_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL20__A                                             0x1440048
#define  QAM_DQ_TAP_RE_EL20__W                                             12
#define  QAM_DQ_TAP_RE_EL20__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL20__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL20_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL20_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL20_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL20_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL20__A                                             0x1440049
#define  QAM_DQ_TAP_IM_EL20__W                                             12
#define  QAM_DQ_TAP_IM_EL20__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL20__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL20_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL20_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL20_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL20_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL21__A                                             0x144004A
#define  QAM_DQ_TAP_RE_EL21__W                                             12
#define  QAM_DQ_TAP_RE_EL21__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL21__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL21_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL21_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL21_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL21_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL21__A                                             0x144004B
#define  QAM_DQ_TAP_IM_EL21__W                                             12
#define  QAM_DQ_TAP_IM_EL21__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL21__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL21_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL21_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL21_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL21_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL22__A                                             0x144004C
#define  QAM_DQ_TAP_RE_EL22__W                                             12
#define  QAM_DQ_TAP_RE_EL22__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL22__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL22_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL22_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL22_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL22_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL22__A                                             0x144004D
#define  QAM_DQ_TAP_IM_EL22__W                                             12
#define  QAM_DQ_TAP_IM_EL22__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL22__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL22_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL22_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL22_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL22_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL23__A                                             0x144004E
#define  QAM_DQ_TAP_RE_EL23__W                                             12
#define  QAM_DQ_TAP_RE_EL23__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL23__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL23_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL23_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL23_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL23_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL23__A                                             0x144004F
#define  QAM_DQ_TAP_IM_EL23__W                                             12
#define  QAM_DQ_TAP_IM_EL23__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL23__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL23_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL23_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL23_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL23_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL24__A                                             0x1440050
#define  QAM_DQ_TAP_RE_EL24__W                                             12
#define  QAM_DQ_TAP_RE_EL24__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL24__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL24_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL24_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL24_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL24_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL24__A                                             0x1440051
#define  QAM_DQ_TAP_IM_EL24__W                                             12
#define  QAM_DQ_TAP_IM_EL24__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL24__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL24_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL24_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL24_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL24_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL25__A                                             0x1440052
#define  QAM_DQ_TAP_RE_EL25__W                                             12
#define  QAM_DQ_TAP_RE_EL25__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL25__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL25_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL25_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL25_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL25_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL25__A                                             0x1440053
#define  QAM_DQ_TAP_IM_EL25__W                                             12
#define  QAM_DQ_TAP_IM_EL25__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL25__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL25_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL25_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL25_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL25_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL26__A                                             0x1440054
#define  QAM_DQ_TAP_RE_EL26__W                                             12
#define  QAM_DQ_TAP_RE_EL26__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL26__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL26_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL26_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL26_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL26_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL26__A                                             0x1440055
#define  QAM_DQ_TAP_IM_EL26__W                                             12
#define  QAM_DQ_TAP_IM_EL26__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL26__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL26_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL26_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL26_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL26_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_RE_EL27__A                                             0x1440056
#define  QAM_DQ_TAP_RE_EL27__W                                             12
#define  QAM_DQ_TAP_RE_EL27__M                                             0xFFF
#define  QAM_DQ_TAP_RE_EL27__PRE                                           0x2

#define    QAM_DQ_TAP_RE_EL27_TAP__B                                       0
#define    QAM_DQ_TAP_RE_EL27_TAP__W                                       12
#define    QAM_DQ_TAP_RE_EL27_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_RE_EL27_TAP__PRE                                     0x2

#define  QAM_DQ_TAP_IM_EL27__A                                             0x1440057
#define  QAM_DQ_TAP_IM_EL27__W                                             12
#define  QAM_DQ_TAP_IM_EL27__M                                             0xFFF
#define  QAM_DQ_TAP_IM_EL27__PRE                                           0x2

#define    QAM_DQ_TAP_IM_EL27_TAP__B                                       0
#define    QAM_DQ_TAP_IM_EL27_TAP__W                                       12
#define    QAM_DQ_TAP_IM_EL27_TAP__M                                       0xFFF
#define    QAM_DQ_TAP_IM_EL27_TAP__PRE                                     0x2



#define  QAM_LC_COMM_EXEC__A                                               0x1450000
#define  QAM_LC_COMM_EXEC__W                                               2
#define  QAM_LC_COMM_EXEC__M                                               0x3
#define  QAM_LC_COMM_EXEC__PRE                                             0x0
#define    QAM_LC_COMM_EXEC_STOP                                           0x0
#define    QAM_LC_COMM_EXEC_ACTIVE                                         0x1
#define    QAM_LC_COMM_EXEC_HOLD                                           0x2

#define  QAM_LC_COMM_MB__A                                                 0x1450002
#define  QAM_LC_COMM_MB__W                                                 2
#define  QAM_LC_COMM_MB__M                                                 0x3
#define  QAM_LC_COMM_MB__PRE                                               0x0
#define    QAM_LC_COMM_MB_CTL__B                                           0
#define    QAM_LC_COMM_MB_CTL__W                                           1
#define    QAM_LC_COMM_MB_CTL__M                                           0x1
#define    QAM_LC_COMM_MB_CTL__PRE                                         0x0
#define      QAM_LC_COMM_MB_CTL_OFF                                        0x0
#define      QAM_LC_COMM_MB_CTL_ON                                         0x1
#define    QAM_LC_COMM_MB_OBS__B                                           1
#define    QAM_LC_COMM_MB_OBS__W                                           1
#define    QAM_LC_COMM_MB_OBS__M                                           0x2
#define    QAM_LC_COMM_MB_OBS__PRE                                         0x0
#define      QAM_LC_COMM_MB_OBS_OFF                                        0x0
#define      QAM_LC_COMM_MB_OBS_ON                                         0x2

#define  QAM_LC_COMM_INT_REQ__A                                            0x1450003
#define  QAM_LC_COMM_INT_REQ__W                                            1
#define  QAM_LC_COMM_INT_REQ__M                                            0x1
#define  QAM_LC_COMM_INT_REQ__PRE                                          0x0
#define  QAM_LC_COMM_INT_STA__A                                            0x1450005
#define  QAM_LC_COMM_INT_STA__W                                            3
#define  QAM_LC_COMM_INT_STA__M                                            0x7
#define  QAM_LC_COMM_INT_STA__PRE                                          0x0

#define    QAM_LC_COMM_INT_STA_READY__B                                    0
#define    QAM_LC_COMM_INT_STA_READY__W                                    1
#define    QAM_LC_COMM_INT_STA_READY__M                                    0x1
#define    QAM_LC_COMM_INT_STA_READY__PRE                                  0x0

#define    QAM_LC_COMM_INT_STA_OVERFLOW__B                                 1
#define    QAM_LC_COMM_INT_STA_OVERFLOW__W                                 1
#define    QAM_LC_COMM_INT_STA_OVERFLOW__M                                 0x2
#define    QAM_LC_COMM_INT_STA_OVERFLOW__PRE                               0x0

#define    QAM_LC_COMM_INT_STA_FREQ_WRAP__B                                2
#define    QAM_LC_COMM_INT_STA_FREQ_WRAP__W                                1
#define    QAM_LC_COMM_INT_STA_FREQ_WRAP__M                                0x4
#define    QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE                              0x0

#define  QAM_LC_COMM_INT_MSK__A                                            0x1450006
#define  QAM_LC_COMM_INT_MSK__W                                            3
#define  QAM_LC_COMM_INT_MSK__M                                            0x7
#define  QAM_LC_COMM_INT_MSK__PRE                                          0x0
#define    QAM_LC_COMM_INT_MSK_READY__B                                    0
#define    QAM_LC_COMM_INT_MSK_READY__W                                    1
#define    QAM_LC_COMM_INT_MSK_READY__M                                    0x1
#define    QAM_LC_COMM_INT_MSK_READY__PRE                                  0x0
#define    QAM_LC_COMM_INT_MSK_OVERFLOW__B                                 1
#define    QAM_LC_COMM_INT_MSK_OVERFLOW__W                                 1
#define    QAM_LC_COMM_INT_MSK_OVERFLOW__M                                 0x2
#define    QAM_LC_COMM_INT_MSK_OVERFLOW__PRE                               0x0
#define    QAM_LC_COMM_INT_MSK_FREQ_WRAP__B                                2
#define    QAM_LC_COMM_INT_MSK_FREQ_WRAP__W                                1
#define    QAM_LC_COMM_INT_MSK_FREQ_WRAP__M                                0x4
#define    QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE                              0x0

#define  QAM_LC_COMM_INT_STM__A                                            0x1450007
#define  QAM_LC_COMM_INT_STM__W                                            3
#define  QAM_LC_COMM_INT_STM__M                                            0x7
#define  QAM_LC_COMM_INT_STM__PRE                                          0x0
#define    QAM_LC_COMM_INT_STM_READY__B                                    0
#define    QAM_LC_COMM_INT_STM_READY__W                                    1
#define    QAM_LC_COMM_INT_STM_READY__M                                    0x1
#define    QAM_LC_COMM_INT_STM_READY__PRE                                  0x0
#define    QAM_LC_COMM_INT_STM_OVERFLOW__B                                 1
#define    QAM_LC_COMM_INT_STM_OVERFLOW__W                                 1
#define    QAM_LC_COMM_INT_STM_OVERFLOW__M                                 0x2
#define    QAM_LC_COMM_INT_STM_OVERFLOW__PRE                               0x0
#define    QAM_LC_COMM_INT_STM_FREQ_WRAP__B                                2
#define    QAM_LC_COMM_INT_STM_FREQ_WRAP__W                                1
#define    QAM_LC_COMM_INT_STM_FREQ_WRAP__M                                0x4
#define    QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE                              0x0

#define  QAM_LC_MODE__A                                                    0x1450010
#define  QAM_LC_MODE__W                                                    4
#define  QAM_LC_MODE__M                                                    0xF
#define  QAM_LC_MODE__PRE                                                  0xE

#define    QAM_LC_MODE_ENABLE_A__B                                         0
#define    QAM_LC_MODE_ENABLE_A__W                                         1
#define    QAM_LC_MODE_ENABLE_A__M                                         0x1
#define    QAM_LC_MODE_ENABLE_A__PRE                                       0x0

#define    QAM_LC_MODE_ENABLE_F__B                                         1
#define    QAM_LC_MODE_ENABLE_F__W                                         1
#define    QAM_LC_MODE_ENABLE_F__M                                         0x2
#define    QAM_LC_MODE_ENABLE_F__PRE                                       0x2

#define    QAM_LC_MODE_ENABLE_R__B                                         2
#define    QAM_LC_MODE_ENABLE_R__W                                         1
#define    QAM_LC_MODE_ENABLE_R__M                                         0x4
#define    QAM_LC_MODE_ENABLE_R__PRE                                       0x4

#define    QAM_LC_MODE_ENABLE_PQUAL__B                                     3
#define    QAM_LC_MODE_ENABLE_PQUAL__W                                     1
#define    QAM_LC_MODE_ENABLE_PQUAL__M                                     0x8
#define    QAM_LC_MODE_ENABLE_PQUAL__PRE                                   0x8

#define  QAM_LC_CA__A                                                      0x1450011
#define  QAM_LC_CA__W                                                      6
#define  QAM_LC_CA__M                                                      0x3F
#define  QAM_LC_CA__PRE                                                    0x28

#define    QAM_LC_CA_COEF__B                                               0
#define    QAM_LC_CA_COEF__W                                               6
#define    QAM_LC_CA_COEF__M                                               0x3F
#define    QAM_LC_CA_COEF__PRE                                             0x28

#define  QAM_LC_CF__A                                                      0x1450012
#define  QAM_LC_CF__W                                                      8
#define  QAM_LC_CF__M                                                      0xFF
#define  QAM_LC_CF__PRE                                                    0x30

#define    QAM_LC_CF_COEF__B                                               0
#define    QAM_LC_CF_COEF__W                                               8
#define    QAM_LC_CF_COEF__M                                               0xFF
#define    QAM_LC_CF_COEF__PRE                                             0x30

#define  QAM_LC_CF1__A                                                     0x1450013
#define  QAM_LC_CF1__W                                                     8
#define  QAM_LC_CF1__M                                                     0xFF
#define  QAM_LC_CF1__PRE                                                   0x14

#define    QAM_LC_CF1_COEF__B                                              0
#define    QAM_LC_CF1_COEF__W                                              8
#define    QAM_LC_CF1_COEF__M                                              0xFF
#define    QAM_LC_CF1_COEF__PRE                                            0x14

#define  QAM_LC_CP__A                                                      0x1450014
#define  QAM_LC_CP__W                                                      8
#define  QAM_LC_CP__M                                                      0xFF
#define  QAM_LC_CP__PRE                                                    0x64

#define    QAM_LC_CP_COEF__B                                               0
#define    QAM_LC_CP_COEF__W                                               8
#define    QAM_LC_CP_COEF__M                                               0xFF
#define    QAM_LC_CP_COEF__PRE                                             0x64

#define  QAM_LC_CI__A                                                      0x1450015
#define  QAM_LC_CI__W                                                      8
#define  QAM_LC_CI__M                                                      0xFF
#define  QAM_LC_CI__PRE                                                    0x32

#define    QAM_LC_CI_COEF__B                                               0
#define    QAM_LC_CI_COEF__W                                               8
#define    QAM_LC_CI_COEF__M                                               0xFF
#define    QAM_LC_CI_COEF__PRE                                             0x32

#define  QAM_LC_EP__A                                                      0x1450016
#define  QAM_LC_EP__W                                                      6
#define  QAM_LC_EP__M                                                      0x3F
#define  QAM_LC_EP__PRE                                                    0x0

#define    QAM_LC_EP_COEF__B                                               0
#define    QAM_LC_EP_COEF__W                                               6
#define    QAM_LC_EP_COEF__M                                               0x3F
#define    QAM_LC_EP_COEF__PRE                                             0x0

#define  QAM_LC_EI__A                                                      0x1450017
#define  QAM_LC_EI__W                                                      6
#define  QAM_LC_EI__M                                                      0x3F
#define  QAM_LC_EI__PRE                                                    0x0

#define    QAM_LC_EI_COEF__B                                               0
#define    QAM_LC_EI_COEF__W                                               6
#define    QAM_LC_EI_COEF__M                                               0x3F
#define    QAM_LC_EI_COEF__PRE                                             0x0

#define  QAM_LC_QUAL_TAB0__A                                               0x1450018
#define  QAM_LC_QUAL_TAB0__W                                               5
#define  QAM_LC_QUAL_TAB0__M                                               0x1F
#define  QAM_LC_QUAL_TAB0__PRE                                             0x0

#define    QAM_LC_QUAL_TAB0_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB0_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB0_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB0_VALUE__PRE                                     0x0

#define  QAM_LC_QUAL_TAB1__A                                               0x1450019
#define  QAM_LC_QUAL_TAB1__W                                               5
#define  QAM_LC_QUAL_TAB1__M                                               0x1F
#define  QAM_LC_QUAL_TAB1__PRE                                             0x1

#define    QAM_LC_QUAL_TAB1_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB1_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB1_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB1_VALUE__PRE                                     0x1

#define  QAM_LC_QUAL_TAB2__A                                               0x145001A
#define  QAM_LC_QUAL_TAB2__W                                               5
#define  QAM_LC_QUAL_TAB2__M                                               0x1F
#define  QAM_LC_QUAL_TAB2__PRE                                             0x2

#define    QAM_LC_QUAL_TAB2_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB2_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB2_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB2_VALUE__PRE                                     0x2

#define  QAM_LC_QUAL_TAB3__A                                               0x145001B
#define  QAM_LC_QUAL_TAB3__W                                               5
#define  QAM_LC_QUAL_TAB3__M                                               0x1F
#define  QAM_LC_QUAL_TAB3__PRE                                             0x3

#define    QAM_LC_QUAL_TAB3_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB3_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB3_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB3_VALUE__PRE                                     0x3

#define  QAM_LC_QUAL_TAB4__A                                               0x145001C
#define  QAM_LC_QUAL_TAB4__W                                               5
#define  QAM_LC_QUAL_TAB4__M                                               0x1F
#define  QAM_LC_QUAL_TAB4__PRE                                             0x4

#define    QAM_LC_QUAL_TAB4_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB4_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB4_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB4_VALUE__PRE                                     0x4

#define  QAM_LC_QUAL_TAB5__A                                               0x145001D
#define  QAM_LC_QUAL_TAB5__W                                               5
#define  QAM_LC_QUAL_TAB5__M                                               0x1F
#define  QAM_LC_QUAL_TAB5__PRE                                             0x5

#define    QAM_LC_QUAL_TAB5_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB5_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB5_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB5_VALUE__PRE                                     0x5

#define  QAM_LC_QUAL_TAB6__A                                               0x145001E
#define  QAM_LC_QUAL_TAB6__W                                               5
#define  QAM_LC_QUAL_TAB6__M                                               0x1F
#define  QAM_LC_QUAL_TAB6__PRE                                             0x6

#define    QAM_LC_QUAL_TAB6_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB6_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB6_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB6_VALUE__PRE                                     0x6

#define  QAM_LC_QUAL_TAB8__A                                               0x145001F
#define  QAM_LC_QUAL_TAB8__W                                               5
#define  QAM_LC_QUAL_TAB8__M                                               0x1F
#define  QAM_LC_QUAL_TAB8__PRE                                             0x8

#define    QAM_LC_QUAL_TAB8_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB8_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB8_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB8_VALUE__PRE                                     0x8

#define  QAM_LC_QUAL_TAB9__A                                               0x1450020
#define  QAM_LC_QUAL_TAB9__W                                               5
#define  QAM_LC_QUAL_TAB9__M                                               0x1F
#define  QAM_LC_QUAL_TAB9__PRE                                             0x9

#define    QAM_LC_QUAL_TAB9_VALUE__B                                       0
#define    QAM_LC_QUAL_TAB9_VALUE__W                                       5
#define    QAM_LC_QUAL_TAB9_VALUE__M                                       0x1F
#define    QAM_LC_QUAL_TAB9_VALUE__PRE                                     0x9

#define  QAM_LC_QUAL_TAB10__A                                              0x1450021
#define  QAM_LC_QUAL_TAB10__W                                              5
#define  QAM_LC_QUAL_TAB10__M                                              0x1F
#define  QAM_LC_QUAL_TAB10__PRE                                            0xA

#define    QAM_LC_QUAL_TAB10_VALUE__B                                      0
#define    QAM_LC_QUAL_TAB10_VALUE__W                                      5
#define    QAM_LC_QUAL_TAB10_VALUE__M                                      0x1F
#define    QAM_LC_QUAL_TAB10_VALUE__PRE                                    0xA

#define  QAM_LC_QUAL_TAB12__A                                              0x1450022
#define  QAM_LC_QUAL_TAB12__W                                              5
#define  QAM_LC_QUAL_TAB12__M                                              0x1F
#define  QAM_LC_QUAL_TAB12__PRE                                            0xC

#define    QAM_LC_QUAL_TAB12_VALUE__B                                      0
#define    QAM_LC_QUAL_TAB12_VALUE__W                                      5
#define    QAM_LC_QUAL_TAB12_VALUE__M                                      0x1F
#define    QAM_LC_QUAL_TAB12_VALUE__PRE                                    0xC

#define  QAM_LC_QUAL_TAB15__A                                              0x1450023
#define  QAM_LC_QUAL_TAB15__W                                              5
#define  QAM_LC_QUAL_TAB15__M                                              0x1F
#define  QAM_LC_QUAL_TAB15__PRE                                            0xF

#define    QAM_LC_QUAL_TAB15_VALUE__B                                      0
#define    QAM_LC_QUAL_TAB15_VALUE__W                                      5
#define    QAM_LC_QUAL_TAB15_VALUE__M                                      0x1F
#define    QAM_LC_QUAL_TAB15_VALUE__PRE                                    0xF

#define  QAM_LC_QUAL_TAB16__A                                              0x1450024
#define  QAM_LC_QUAL_TAB16__W                                              5
#define  QAM_LC_QUAL_TAB16__M                                              0x1F
#define  QAM_LC_QUAL_TAB16__PRE                                            0x10

#define    QAM_LC_QUAL_TAB16_VALUE__B                                      0
#define    QAM_LC_QUAL_TAB16_VALUE__W                                      5
#define    QAM_LC_QUAL_TAB16_VALUE__M                                      0x1F
#define    QAM_LC_QUAL_TAB16_VALUE__PRE                                    0x10

#define  QAM_LC_QUAL_TAB20__A                                              0x1450025
#define  QAM_LC_QUAL_TAB20__W                                              5
#define  QAM_LC_QUAL_TAB20__M                                              0x1F
#define  QAM_LC_QUAL_TAB20__PRE                                            0x14

#define    QAM_LC_QUAL_TAB20_VALUE__B                                      0
#define    QAM_LC_QUAL_TAB20_VALUE__W                                      5
#define    QAM_LC_QUAL_TAB20_VALUE__M                                      0x1F
#define    QAM_LC_QUAL_TAB20_VALUE__PRE                                    0x14

#define  QAM_LC_QUAL_TAB25__A                                              0x1450026
#define  QAM_LC_QUAL_TAB25__W                                              5
#define  QAM_LC_QUAL_TAB25__M                                              0x1F
#define  QAM_LC_QUAL_TAB25__PRE                                            0x19

#define    QAM_LC_QUAL_TAB25_VALUE__B                                      0
#define    QAM_LC_QUAL_TAB25_VALUE__W                                      5
#define    QAM_LC_QUAL_TAB25_VALUE__M                                      0x1F
#define    QAM_LC_QUAL_TAB25_VALUE__PRE                                    0x19

#define  QAM_LC_EQ_TIMING__A                                               0x1450027
#define  QAM_LC_EQ_TIMING__W                                               10
#define  QAM_LC_EQ_TIMING__M                                               0x3FF
#define  QAM_LC_EQ_TIMING__PRE                                             0x0

#define    QAM_LC_EQ_TIMING_OFFS__B                                        0
#define    QAM_LC_EQ_TIMING_OFFS__W                                        10
#define    QAM_LC_EQ_TIMING_OFFS__M                                        0x3FF
#define    QAM_LC_EQ_TIMING_OFFS__PRE                                      0x0

#define  QAM_LC_LPF_FACTORP__A                                             0x1450028
#define  QAM_LC_LPF_FACTORP__W                                             3
#define  QAM_LC_LPF_FACTORP__M                                             0x7
#define  QAM_LC_LPF_FACTORP__PRE                                           0x3

#define    QAM_LC_LPF_FACTORP_FACTOR__B                                    0
#define    QAM_LC_LPF_FACTORP_FACTOR__W                                    3
#define    QAM_LC_LPF_FACTORP_FACTOR__M                                    0x7
#define    QAM_LC_LPF_FACTORP_FACTOR__PRE                                  0x3

#define  QAM_LC_LPF_FACTORI__A                                             0x1450029
#define  QAM_LC_LPF_FACTORI__W                                             3
#define  QAM_LC_LPF_FACTORI__M                                             0x7
#define  QAM_LC_LPF_FACTORI__PRE                                           0x3

#define    QAM_LC_LPF_FACTORI_FACTOR__B                                    0
#define    QAM_LC_LPF_FACTORI_FACTOR__W                                    3
#define    QAM_LC_LPF_FACTORI_FACTOR__M                                    0x7
#define    QAM_LC_LPF_FACTORI_FACTOR__PRE                                  0x3

#define  QAM_LC_RATE_LIMIT__A                                              0x145002A
#define  QAM_LC_RATE_LIMIT__W                                              2
#define  QAM_LC_RATE_LIMIT__M                                              0x3
#define  QAM_LC_RATE_LIMIT__PRE                                            0x3

#define    QAM_LC_RATE_LIMIT_LIMIT__B                                      0
#define    QAM_LC_RATE_LIMIT_LIMIT__W                                      2
#define    QAM_LC_RATE_LIMIT_LIMIT__M                                      0x3
#define    QAM_LC_RATE_LIMIT_LIMIT__PRE                                    0x3

#define  QAM_LC_SYMBOL_FREQ__A                                             0x145002B
#define  QAM_LC_SYMBOL_FREQ__W                                             10
#define  QAM_LC_SYMBOL_FREQ__M                                             0x3FF
#define  QAM_LC_SYMBOL_FREQ__PRE                                           0x1FF

#define    QAM_LC_SYMBOL_FREQ_FREQ__B                                      0
#define    QAM_LC_SYMBOL_FREQ_FREQ__W                                      10
#define    QAM_LC_SYMBOL_FREQ_FREQ__M                                      0x3FF
#define    QAM_LC_SYMBOL_FREQ_FREQ__PRE                                    0x1FF

#define  QAM_LC_MTA_LENGTH__A                                              0x145002C
#define  QAM_LC_MTA_LENGTH__W                                              2
#define  QAM_LC_MTA_LENGTH__M                                              0x3
#define  QAM_LC_MTA_LENGTH__PRE                                            0x2

#define    QAM_LC_MTA_LENGTH_LENGTH__B                                     0
#define    QAM_LC_MTA_LENGTH_LENGTH__W                                     2
#define    QAM_LC_MTA_LENGTH_LENGTH__M                                     0x3
#define    QAM_LC_MTA_LENGTH_LENGTH__PRE                                   0x2

#define  QAM_LC_AMP_ACCU__A                                                0x145002D
#define  QAM_LC_AMP_ACCU__W                                                14
#define  QAM_LC_AMP_ACCU__M                                                0x3FFF
#define  QAM_LC_AMP_ACCU__PRE                                              0x600

#define    QAM_LC_AMP_ACCU_ACCU__B                                         0
#define    QAM_LC_AMP_ACCU_ACCU__W                                         14
#define    QAM_LC_AMP_ACCU_ACCU__M                                         0x3FFF
#define    QAM_LC_AMP_ACCU_ACCU__PRE                                       0x600

#define  QAM_LC_FREQ_ACCU__A                                               0x145002E
#define  QAM_LC_FREQ_ACCU__W                                               10
#define  QAM_LC_FREQ_ACCU__M                                               0x3FF
#define  QAM_LC_FREQ_ACCU__PRE                                             0x0

#define    QAM_LC_FREQ_ACCU_ACCU__B                                        0
#define    QAM_LC_FREQ_ACCU_ACCU__W                                        10
#define    QAM_LC_FREQ_ACCU_ACCU__M                                        0x3FF
#define    QAM_LC_FREQ_ACCU_ACCU__PRE                                      0x0

#define  QAM_LC_RATE_ACCU__A                                               0x145002F
#define  QAM_LC_RATE_ACCU__W                                               10
#define  QAM_LC_RATE_ACCU__M                                               0x3FF
#define  QAM_LC_RATE_ACCU__PRE                                             0x0

#define    QAM_LC_RATE_ACCU_ACCU__B                                        0
#define    QAM_LC_RATE_ACCU_ACCU__W                                        10
#define    QAM_LC_RATE_ACCU_ACCU__M                                        0x3FF
#define    QAM_LC_RATE_ACCU_ACCU__PRE                                      0x0

#define  QAM_LC_AMPLITUDE__A                                               0x1450030
#define  QAM_LC_AMPLITUDE__W                                               10
#define  QAM_LC_AMPLITUDE__M                                               0x3FF
#define  QAM_LC_AMPLITUDE__PRE                                             0x0

#define    QAM_LC_AMPLITUDE_SIZE__B                                        0
#define    QAM_LC_AMPLITUDE_SIZE__W                                        10
#define    QAM_LC_AMPLITUDE_SIZE__M                                        0x3FF
#define    QAM_LC_AMPLITUDE_SIZE__PRE                                      0x0

#define  QAM_LC_RAD_ERROR__A                                               0x1450031
#define  QAM_LC_RAD_ERROR__W                                               10
#define  QAM_LC_RAD_ERROR__M                                               0x3FF
#define  QAM_LC_RAD_ERROR__PRE                                             0x0

#define    QAM_LC_RAD_ERROR_SIZE__B                                        0
#define    QAM_LC_RAD_ERROR_SIZE__W                                        10
#define    QAM_LC_RAD_ERROR_SIZE__M                                        0x3FF
#define    QAM_LC_RAD_ERROR_SIZE__PRE                                      0x0

#define  QAM_LC_FREQ_OFFS__A                                               0x1450032
#define  QAM_LC_FREQ_OFFS__W                                               10
#define  QAM_LC_FREQ_OFFS__M                                               0x3FF
#define  QAM_LC_FREQ_OFFS__PRE                                             0x0

#define    QAM_LC_FREQ_OFFS_OFFS__B                                        0
#define    QAM_LC_FREQ_OFFS_OFFS__W                                        10
#define    QAM_LC_FREQ_OFFS_OFFS__M                                        0x3FF
#define    QAM_LC_FREQ_OFFS_OFFS__PRE                                      0x0

#define  QAM_LC_PHASE_ERROR__A                                             0x1450033
#define  QAM_LC_PHASE_ERROR__W                                             10
#define  QAM_LC_PHASE_ERROR__M                                             0x3FF
#define  QAM_LC_PHASE_ERROR__PRE                                           0x0

#define    QAM_LC_PHASE_ERROR_SIZE__B                                      0
#define    QAM_LC_PHASE_ERROR_SIZE__W                                      10
#define    QAM_LC_PHASE_ERROR_SIZE__M                                      0x3FF
#define    QAM_LC_PHASE_ERROR_SIZE__PRE                                    0x0



#define  QAM_SY_COMM_EXEC__A                                               0x1470000
#define  QAM_SY_COMM_EXEC__W                                               2
#define  QAM_SY_COMM_EXEC__M                                               0x3
#define  QAM_SY_COMM_EXEC__PRE                                             0x0
#define    QAM_SY_COMM_EXEC_STOP                                           0x0
#define    QAM_SY_COMM_EXEC_ACTIVE                                         0x1
#define    QAM_SY_COMM_EXEC_HOLD                                           0x2

#define  QAM_SY_COMM_MB__A                                                 0x1470002
#define  QAM_SY_COMM_MB__W                                                 4
#define  QAM_SY_COMM_MB__M                                                 0xF
#define  QAM_SY_COMM_MB__PRE                                               0x0
#define    QAM_SY_COMM_MB_CTL__B                                           0
#define    QAM_SY_COMM_MB_CTL__W                                           1
#define    QAM_SY_COMM_MB_CTL__M                                           0x1
#define    QAM_SY_COMM_MB_CTL__PRE                                         0x0
#define      QAM_SY_COMM_MB_CTL_OFF                                        0x0
#define      QAM_SY_COMM_MB_CTL_ON                                         0x1
#define    QAM_SY_COMM_MB_OBS__B                                           1
#define    QAM_SY_COMM_MB_OBS__W                                           1
#define    QAM_SY_COMM_MB_OBS__M                                           0x2
#define    QAM_SY_COMM_MB_OBS__PRE                                         0x0
#define      QAM_SY_COMM_MB_OBS_OFF                                        0x0
#define      QAM_SY_COMM_MB_OBS_ON                                         0x2
#define    QAM_SY_COMM_MB_MUX_CTL__B                                       2
#define    QAM_SY_COMM_MB_MUX_CTL__W                                       1
#define    QAM_SY_COMM_MB_MUX_CTL__M                                       0x4
#define    QAM_SY_COMM_MB_MUX_CTL__PRE                                     0x0
#define      QAM_SY_COMM_MB_MUX_CTL_MB0                                    0x0
#define      QAM_SY_COMM_MB_MUX_CTL_MB1                                    0x4
#define    QAM_SY_COMM_MB_MUX_OBS__B                                       3
#define    QAM_SY_COMM_MB_MUX_OBS__W                                       1
#define    QAM_SY_COMM_MB_MUX_OBS__M                                       0x8
#define    QAM_SY_COMM_MB_MUX_OBS__PRE                                     0x0
#define      QAM_SY_COMM_MB_MUX_OBS_MB0                                    0x0
#define      QAM_SY_COMM_MB_MUX_OBS_MB1                                    0x8

#define  QAM_SY_COMM_INT_REQ__A                                            0x1470003
#define  QAM_SY_COMM_INT_REQ__W                                            1
#define  QAM_SY_COMM_INT_REQ__M                                            0x1
#define  QAM_SY_COMM_INT_REQ__PRE                                          0x0
#define  QAM_SY_COMM_INT_STA__A                                            0x1470005
#define  QAM_SY_COMM_INT_STA__W                                            4
#define  QAM_SY_COMM_INT_STA__M                                            0xF
#define  QAM_SY_COMM_INT_STA__PRE                                          0x0

#define    QAM_SY_COMM_INT_STA_LOCK_INT__B                                 0
#define    QAM_SY_COMM_INT_STA_LOCK_INT__W                                 1
#define    QAM_SY_COMM_INT_STA_LOCK_INT__M                                 0x1
#define    QAM_SY_COMM_INT_STA_LOCK_INT__PRE                               0x0

#define    QAM_SY_COMM_INT_STA_UNLOCK_INT__B                               1
#define    QAM_SY_COMM_INT_STA_UNLOCK_INT__W                               1
#define    QAM_SY_COMM_INT_STA_UNLOCK_INT__M                               0x2
#define    QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE                             0x0

#define    QAM_SY_COMM_INT_STA_TIMEOUT_INT__B                              2
#define    QAM_SY_COMM_INT_STA_TIMEOUT_INT__W                              1
#define    QAM_SY_COMM_INT_STA_TIMEOUT_INT__M                              0x4
#define    QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE                            0x0

#define    QAM_SY_COMM_INT_STA_CTL_WORD_INT__B                             3
#define    QAM_SY_COMM_INT_STA_CTL_WORD_INT__W                             1
#define    QAM_SY_COMM_INT_STA_CTL_WORD_INT__M                             0x8
#define    QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE                           0x0

#define  QAM_SY_COMM_INT_MSK__A                                            0x1470006
#define  QAM_SY_COMM_INT_MSK__W                                            4
#define  QAM_SY_COMM_INT_MSK__M                                            0xF
#define  QAM_SY_COMM_INT_MSK__PRE                                          0x0
#define    QAM_SY_COMM_INT_MSK_LOCK_MSK__B                                 0
#define    QAM_SY_COMM_INT_MSK_LOCK_MSK__W                                 1
#define    QAM_SY_COMM_INT_MSK_LOCK_MSK__M                                 0x1
#define    QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE                               0x0
#define    QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B                               1
#define    QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W                               1
#define    QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M                               0x2
#define    QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE                             0x0
#define    QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B                              2
#define    QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W                              1
#define    QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M                              0x4
#define    QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE                            0x0
#define    QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B                             3
#define    QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W                             1
#define    QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M                             0x8
#define    QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE                           0x0

#define  QAM_SY_COMM_INT_STM__A                                            0x1470007
#define  QAM_SY_COMM_INT_STM__W                                            4
#define  QAM_SY_COMM_INT_STM__M                                            0xF
#define  QAM_SY_COMM_INT_STM__PRE                                          0x0
#define    QAM_SY_COMM_INT_STM_LOCK_MSK__B                                 0
#define    QAM_SY_COMM_INT_STM_LOCK_MSK__W                                 1
#define    QAM_SY_COMM_INT_STM_LOCK_MSK__M                                 0x1
#define    QAM_SY_COMM_INT_STM_LOCK_MSK__PRE                               0x0
#define    QAM_SY_COMM_INT_STM_UNLOCK_MSK__B                               1
#define    QAM_SY_COMM_INT_STM_UNLOCK_MSK__W                               1
#define    QAM_SY_COMM_INT_STM_UNLOCK_MSK__M                               0x2
#define    QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE                             0x0
#define    QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B                              2
#define    QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W                              1
#define    QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M                              0x4
#define    QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE                            0x0
#define    QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B                             3
#define    QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W                             1
#define    QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M                             0x8
#define    QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE                           0x0

#define  QAM_SY_STATUS__A                                                  0x1470010
#define  QAM_SY_STATUS__W                                                  2
#define  QAM_SY_STATUS__M                                                  0x3
#define  QAM_SY_STATUS__PRE                                                0x0

#define    QAM_SY_STATUS_SYNC_STATE__B                                     0
#define    QAM_SY_STATUS_SYNC_STATE__W                                     2
#define    QAM_SY_STATUS_SYNC_STATE__M                                     0x3
#define    QAM_SY_STATUS_SYNC_STATE__PRE                                   0x0


#define  QAM_SY_TIMEOUT__A                                                 0x1470011
#define  QAM_SY_TIMEOUT__W                                                 16
#define  QAM_SY_TIMEOUT__M                                                 0xFFFF
#define  QAM_SY_TIMEOUT__PRE                                               0x3A98

#define  QAM_SY_SYNC_LWM__A                                                0x1470012
#define  QAM_SY_SYNC_LWM__W                                                4
#define  QAM_SY_SYNC_LWM__M                                                0xF
#define  QAM_SY_SYNC_LWM__PRE                                              0x2

#define  QAM_SY_SYNC_AWM__A                                                0x1470013
#define  QAM_SY_SYNC_AWM__W                                                4
#define  QAM_SY_SYNC_AWM__M                                                0xF
#define  QAM_SY_SYNC_AWM__PRE                                              0x3

#define  QAM_SY_SYNC_HWM__A                                                0x1470014
#define  QAM_SY_SYNC_HWM__W                                                4
#define  QAM_SY_SYNC_HWM__M                                                0xF
#define  QAM_SY_SYNC_HWM__PRE                                              0x5

#define  QAM_SY_UNLOCK__A                                                  0x1470015
#define  QAM_SY_UNLOCK__W                                                  1
#define  QAM_SY_UNLOCK__M                                                  0x1
#define  QAM_SY_UNLOCK__PRE                                                0x0
#define  QAM_SY_CONTROL_WORD__A                                            0x1470016
#define  QAM_SY_CONTROL_WORD__W                                            4
#define  QAM_SY_CONTROL_WORD__M                                            0xF
#define  QAM_SY_CONTROL_WORD__PRE                                          0x0

#define    QAM_SY_CONTROL_WORD_CTRL_WORD__B                                0
#define    QAM_SY_CONTROL_WORD_CTRL_WORD__W                                4
#define    QAM_SY_CONTROL_WORD_CTRL_WORD__M                                0xF
#define    QAM_SY_CONTROL_WORD_CTRL_WORD__PRE                              0x0


#define  QAM_SY_SP_INV__A                                                  0x1470017
#define  QAM_SY_SP_INV__W                                                  1
#define  QAM_SY_SP_INV__M                                                  0x1
#define  QAM_SY_SP_INV__PRE                                                0x0
#define    QAM_SY_SP_INV_SPECTRUM_INV_DIS                                  0x0
#define    QAM_SY_SP_INV_SPECTRUM_INV_ENA                                  0x1



#define  QAM_VD_ISS_RAM__A                                                 0x1480000



#define  QAM_VD_QSS_RAM__A                                                 0x1490000



#define  QAM_VD_SYM_RAM__A                                                 0x14A0000





#define  SCU_COMM_EXEC__A                                                  0x800000
#define  SCU_COMM_EXEC__W                                                  2
#define  SCU_COMM_EXEC__M                                                  0x3
#define  SCU_COMM_EXEC__PRE                                                0x0
#define    SCU_COMM_EXEC_STOP                                              0x0
#define    SCU_COMM_EXEC_ACTIVE                                            0x1
#define    SCU_COMM_EXEC_HOLD                                              0x2

#define  SCU_COMM_STATE__A                                                 0x800001
#define  SCU_COMM_STATE__W                                                 16
#define  SCU_COMM_STATE__M                                                 0xFFFF
#define  SCU_COMM_STATE__PRE                                               0x0

#define    SCU_COMM_STATE_COMM_STATE__B                                    0
#define    SCU_COMM_STATE_COMM_STATE__W                                    16
#define    SCU_COMM_STATE_COMM_STATE__M                                    0xFFFF
#define    SCU_COMM_STATE_COMM_STATE__PRE                                  0x0



#define  SCU_TOP_COMM_EXEC__A                                              0x810000
#define  SCU_TOP_COMM_EXEC__W                                              2
#define  SCU_TOP_COMM_EXEC__M                                              0x3
#define  SCU_TOP_COMM_EXEC__PRE                                            0x0
#define    SCU_TOP_COMM_EXEC_STOP                                          0x0
#define    SCU_TOP_COMM_EXEC_ACTIVE                                        0x1
#define    SCU_TOP_COMM_EXEC_HOLD                                          0x2


#define  SCU_TOP_COMM_STATE__A                                             0x810001
#define  SCU_TOP_COMM_STATE__W                                             16
#define  SCU_TOP_COMM_STATE__M                                             0xFFFF
#define  SCU_TOP_COMM_STATE__PRE                                           0x0
#define  SCU_TOP_MWAIT_CTR__A                                              0x810010
#define  SCU_TOP_MWAIT_CTR__W                                              2
#define  SCU_TOP_MWAIT_CTR__M                                              0x3
#define  SCU_TOP_MWAIT_CTR__PRE                                            0x0

#define    SCU_TOP_MWAIT_CTR_MWAIT_SEL__B                                  0
#define    SCU_TOP_MWAIT_CTR_MWAIT_SEL__W                                  1
#define    SCU_TOP_MWAIT_CTR_MWAIT_SEL__M                                  0x1
#define    SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE                                0x0
#define      SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF                         0x0
#define      SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON                          0x1

#define    SCU_TOP_MWAIT_CTR_READY_DIS__B                                  1
#define    SCU_TOP_MWAIT_CTR_READY_DIS__W                                  1
#define    SCU_TOP_MWAIT_CTR_READY_DIS__M                                  0x2
#define    SCU_TOP_MWAIT_CTR_READY_DIS__PRE                                0x0
#define      SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON                            0x0
#define      SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF                           0x2



#define  SCU_LOW_RAM__A                                                    0x820000

#define    SCU_LOW_RAM_LOW__B                                              0
#define    SCU_LOW_RAM_LOW__W                                              16
#define    SCU_LOW_RAM_LOW__M                                              0xFFFF
#define    SCU_LOW_RAM_LOW__PRE                                            0x0



#define  SCU_HIGH_RAM__A                                                   0x830000

#define    SCU_HIGH_RAM_HIGH__B                                            0
#define    SCU_HIGH_RAM_HIGH__W                                            16
#define    SCU_HIGH_RAM_HIGH__M                                            0xFFFF
#define    SCU_HIGH_RAM_HIGH__PRE                                          0x0






#define  SCU_RAM_DRIVER_DEBUG__A                                           0x831EBF
#define  SCU_RAM_DRIVER_DEBUG__W                                           16
#define  SCU_RAM_DRIVER_DEBUG__M                                           0xFFFF
#define  SCU_RAM_DRIVER_DEBUG__PRE                                         0x0

#define  SCU_RAM_SP__A                                                     0x831EC0
#define  SCU_RAM_SP__W                                                     16
#define  SCU_RAM_SP__M                                                     0xFFFF
#define  SCU_RAM_SP__PRE                                                   0x0

#define  SCU_RAM_QAM_NEVERLOCK_CNT__A                                      0x831EC1
#define  SCU_RAM_QAM_NEVERLOCK_CNT__W                                      16
#define  SCU_RAM_QAM_NEVERLOCK_CNT__M                                      0xFFFF
#define  SCU_RAM_QAM_NEVERLOCK_CNT__PRE                                    0x0

#define  SCU_RAM_QAM_WRONG_RATE_CNT__A                                     0x831EC2
#define  SCU_RAM_QAM_WRONG_RATE_CNT__W                                     16
#define  SCU_RAM_QAM_WRONG_RATE_CNT__M                                     0xFFFF
#define  SCU_RAM_QAM_WRONG_RATE_CNT__PRE                                   0x0

#define  SCU_RAM_QAM_NO_ACQ_CNT__A                                         0x831EC3
#define  SCU_RAM_QAM_NO_ACQ_CNT__W                                         16
#define  SCU_RAM_QAM_NO_ACQ_CNT__M                                         0xFFFF
#define  SCU_RAM_QAM_NO_ACQ_CNT__PRE                                       0x0

#define  SCU_RAM_QAM_FSM_STEP_PERIOD__A                                    0x831EC4
#define  SCU_RAM_QAM_FSM_STEP_PERIOD__W                                    16
#define  SCU_RAM_QAM_FSM_STEP_PERIOD__M                                    0xFFFF
#define  SCU_RAM_QAM_FSM_STEP_PERIOD__PRE                                  0x4B0

#define  SCU_RAM_AGC_KI_MIN_IFGAIN__A                                      0x831EC5
#define  SCU_RAM_AGC_KI_MIN_IFGAIN__W                                      16
#define  SCU_RAM_AGC_KI_MIN_IFGAIN__M                                      0xFFFF
#define  SCU_RAM_AGC_KI_MIN_IFGAIN__PRE                                    0x8000

#define  SCU_RAM_AGC_KI_MAX_IFGAIN__A                                      0x831EC6
#define  SCU_RAM_AGC_KI_MAX_IFGAIN__W                                      16
#define  SCU_RAM_AGC_KI_MAX_IFGAIN__M                                      0xFFFF
#define  SCU_RAM_AGC_KI_MAX_IFGAIN__PRE                                    0x0
#define  SCU_RAM_GPIO__A                                                   0x831EC7
#define  SCU_RAM_GPIO__W                                                   2
#define  SCU_RAM_GPIO__M                                                   0x3
#define  SCU_RAM_GPIO__PRE                                                 0x0

#define    SCU_RAM_GPIO_HW_LOCK_IND__B                                     0
#define    SCU_RAM_GPIO_HW_LOCK_IND__W                                     1
#define    SCU_RAM_GPIO_HW_LOCK_IND__M                                     0x1
#define    SCU_RAM_GPIO_HW_LOCK_IND__PRE                                   0x0
#define      SCU_RAM_GPIO_HW_LOCK_IND_DISABLE                              0x0
#define      SCU_RAM_GPIO_HW_LOCK_IND_ENABLE                               0x1

#define    SCU_RAM_GPIO_VSYNC_IND__B                                       1
#define    SCU_RAM_GPIO_VSYNC_IND__W                                       1
#define    SCU_RAM_GPIO_VSYNC_IND__M                                       0x2
#define    SCU_RAM_GPIO_VSYNC_IND__PRE                                     0x0
#define      SCU_RAM_GPIO_VSYNC_IND_DISABLE                                0x0
#define      SCU_RAM_GPIO_VSYNC_IND_ENABLE                                 0x2

#define  SCU_RAM_AGC_CLP_CTRL_MODE__A                                      0x831EC8
#define  SCU_RAM_AGC_CLP_CTRL_MODE__W                                      8
#define  SCU_RAM_AGC_CLP_CTRL_MODE__M                                      0xFF
#define  SCU_RAM_AGC_CLP_CTRL_MODE__PRE                                    0x0

#define    SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B                         0
#define    SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W                         1
#define    SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M                         0x1
#define    SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE                       0x0
#define      SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE                    0x0
#define      SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE                     0x1

#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B                        1
#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W                        1
#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M                        0x2
#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE                      0x0
#define      SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE              0x0
#define      SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE             0x2

#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B                       2
#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W                       1
#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M                       0x4
#define    SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE                     0x0
#define      SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE            0x0
#define      SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE             0x4


#define  SCU_RAM_AGC_KI_MIN_RFGAIN__A                                      0x831EC9
#define  SCU_RAM_AGC_KI_MIN_RFGAIN__W                                      16
#define  SCU_RAM_AGC_KI_MIN_RFGAIN__M                                      0xFFFF
#define  SCU_RAM_AGC_KI_MIN_RFGAIN__PRE                                    0x8000

#define  SCU_RAM_AGC_KI_MAX_RFGAIN__A                                      0x831ECA
#define  SCU_RAM_AGC_KI_MAX_RFGAIN__W                                      16
#define  SCU_RAM_AGC_KI_MAX_RFGAIN__M                                      0xFFFF
#define  SCU_RAM_AGC_KI_MAX_RFGAIN__PRE                                    0x0

#define  SCU_RAM_FEC_ACCUM_PKT_FAILURES__A                                 0x831ECB
#define  SCU_RAM_FEC_ACCUM_PKT_FAILURES__W                                 16
#define  SCU_RAM_FEC_ACCUM_PKT_FAILURES__M                                 0xFFFF
#define  SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE                               0x0

#define  SCU_RAM_INHIBIT_1__A                                              0x831ECC
#define  SCU_RAM_INHIBIT_1__W                                              16
#define  SCU_RAM_INHIBIT_1__M                                              0xFFFF
#define  SCU_RAM_INHIBIT_1__PRE                                            0x0

#define  SCU_RAM_HTOL_BUF_0__A                                             0x831ECD
#define  SCU_RAM_HTOL_BUF_0__W                                             16
#define  SCU_RAM_HTOL_BUF_0__M                                             0xFFFF
#define  SCU_RAM_HTOL_BUF_0__PRE                                           0x0

#define  SCU_RAM_HTOL_BUF_1__A                                             0x831ECE
#define  SCU_RAM_HTOL_BUF_1__W                                             16
#define  SCU_RAM_HTOL_BUF_1__M                                             0xFFFF
#define  SCU_RAM_HTOL_BUF_1__PRE                                           0x0

#define  SCU_RAM_INHIBIT_2__A                                              0x831ECF
#define  SCU_RAM_INHIBIT_2__W                                              16
#define  SCU_RAM_INHIBIT_2__M                                              0xFFFF
#define  SCU_RAM_INHIBIT_2__PRE                                            0x0

#define  SCU_RAM_TR_SHORT_BUF_0__A                                         0x831ED0
#define  SCU_RAM_TR_SHORT_BUF_0__W                                         16
#define  SCU_RAM_TR_SHORT_BUF_0__M                                         0xFFFF
#define  SCU_RAM_TR_SHORT_BUF_0__PRE                                       0x0

#define  SCU_RAM_TR_SHORT_BUF_1__A                                         0x831ED1
#define  SCU_RAM_TR_SHORT_BUF_1__W                                         16
#define  SCU_RAM_TR_SHORT_BUF_1__M                                         0xFFFF
#define  SCU_RAM_TR_SHORT_BUF_1__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_0__A                                          0x831ED2
#define  SCU_RAM_TR_LONG_BUF_0__W                                          16
#define  SCU_RAM_TR_LONG_BUF_0__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_0__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_1__A                                          0x831ED3
#define  SCU_RAM_TR_LONG_BUF_1__W                                          16
#define  SCU_RAM_TR_LONG_BUF_1__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_1__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_2__A                                          0x831ED4
#define  SCU_RAM_TR_LONG_BUF_2__W                                          16
#define  SCU_RAM_TR_LONG_BUF_2__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_2__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_3__A                                          0x831ED5
#define  SCU_RAM_TR_LONG_BUF_3__W                                          16
#define  SCU_RAM_TR_LONG_BUF_3__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_3__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_4__A                                          0x831ED6
#define  SCU_RAM_TR_LONG_BUF_4__W                                          16
#define  SCU_RAM_TR_LONG_BUF_4__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_4__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_5__A                                          0x831ED7
#define  SCU_RAM_TR_LONG_BUF_5__W                                          16
#define  SCU_RAM_TR_LONG_BUF_5__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_5__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_6__A                                          0x831ED8
#define  SCU_RAM_TR_LONG_BUF_6__W                                          16
#define  SCU_RAM_TR_LONG_BUF_6__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_6__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_7__A                                          0x831ED9
#define  SCU_RAM_TR_LONG_BUF_7__W                                          16
#define  SCU_RAM_TR_LONG_BUF_7__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_7__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_8__A                                          0x831EDA
#define  SCU_RAM_TR_LONG_BUF_8__W                                          16
#define  SCU_RAM_TR_LONG_BUF_8__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_8__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_9__A                                          0x831EDB
#define  SCU_RAM_TR_LONG_BUF_9__W                                          16
#define  SCU_RAM_TR_LONG_BUF_9__M                                          0xFFFF
#define  SCU_RAM_TR_LONG_BUF_9__PRE                                        0x0

#define  SCU_RAM_TR_LONG_BUF_10__A                                         0x831EDC
#define  SCU_RAM_TR_LONG_BUF_10__W                                         16
#define  SCU_RAM_TR_LONG_BUF_10__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_10__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_11__A                                         0x831EDD
#define  SCU_RAM_TR_LONG_BUF_11__W                                         16
#define  SCU_RAM_TR_LONG_BUF_11__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_11__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_12__A                                         0x831EDE
#define  SCU_RAM_TR_LONG_BUF_12__W                                         16
#define  SCU_RAM_TR_LONG_BUF_12__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_12__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_13__A                                         0x831EDF
#define  SCU_RAM_TR_LONG_BUF_13__W                                         16
#define  SCU_RAM_TR_LONG_BUF_13__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_13__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_14__A                                         0x831EE0
#define  SCU_RAM_TR_LONG_BUF_14__W                                         16
#define  SCU_RAM_TR_LONG_BUF_14__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_14__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_15__A                                         0x831EE1
#define  SCU_RAM_TR_LONG_BUF_15__W                                         16
#define  SCU_RAM_TR_LONG_BUF_15__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_15__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_16__A                                         0x831EE2
#define  SCU_RAM_TR_LONG_BUF_16__W                                         16
#define  SCU_RAM_TR_LONG_BUF_16__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_16__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_17__A                                         0x831EE3
#define  SCU_RAM_TR_LONG_BUF_17__W                                         16
#define  SCU_RAM_TR_LONG_BUF_17__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_17__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_18__A                                         0x831EE4
#define  SCU_RAM_TR_LONG_BUF_18__W                                         16
#define  SCU_RAM_TR_LONG_BUF_18__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_18__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_19__A                                         0x831EE5
#define  SCU_RAM_TR_LONG_BUF_19__W                                         16
#define  SCU_RAM_TR_LONG_BUF_19__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_19__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_20__A                                         0x831EE6
#define  SCU_RAM_TR_LONG_BUF_20__W                                         16
#define  SCU_RAM_TR_LONG_BUF_20__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_20__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_21__A                                         0x831EE7
#define  SCU_RAM_TR_LONG_BUF_21__W                                         16
#define  SCU_RAM_TR_LONG_BUF_21__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_21__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_22__A                                         0x831EE8
#define  SCU_RAM_TR_LONG_BUF_22__W                                         16
#define  SCU_RAM_TR_LONG_BUF_22__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_22__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_23__A                                         0x831EE9
#define  SCU_RAM_TR_LONG_BUF_23__W                                         16
#define  SCU_RAM_TR_LONG_BUF_23__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_23__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_24__A                                         0x831EEA
#define  SCU_RAM_TR_LONG_BUF_24__W                                         16
#define  SCU_RAM_TR_LONG_BUF_24__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_24__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_25__A                                         0x831EEB
#define  SCU_RAM_TR_LONG_BUF_25__W                                         16
#define  SCU_RAM_TR_LONG_BUF_25__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_25__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_26__A                                         0x831EEC
#define  SCU_RAM_TR_LONG_BUF_26__W                                         16
#define  SCU_RAM_TR_LONG_BUF_26__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_26__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_27__A                                         0x831EED
#define  SCU_RAM_TR_LONG_BUF_27__W                                         16
#define  SCU_RAM_TR_LONG_BUF_27__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_27__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_28__A                                         0x831EEE
#define  SCU_RAM_TR_LONG_BUF_28__W                                         16
#define  SCU_RAM_TR_LONG_BUF_28__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_28__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_29__A                                         0x831EEF
#define  SCU_RAM_TR_LONG_BUF_29__W                                         16
#define  SCU_RAM_TR_LONG_BUF_29__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_29__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_30__A                                         0x831EF0
#define  SCU_RAM_TR_LONG_BUF_30__W                                         16
#define  SCU_RAM_TR_LONG_BUF_30__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_30__PRE                                       0x0

#define  SCU_RAM_TR_LONG_BUF_31__A                                         0x831EF1
#define  SCU_RAM_TR_LONG_BUF_31__W                                         16
#define  SCU_RAM_TR_LONG_BUF_31__M                                         0xFFFF
#define  SCU_RAM_TR_LONG_BUF_31__PRE                                       0x0
#define  SCU_RAM_ATV_AMS_MAX__A                                            0x831EF2
#define  SCU_RAM_ATV_AMS_MAX__W                                            11
#define  SCU_RAM_ATV_AMS_MAX__M                                            0x7FF
#define  SCU_RAM_ATV_AMS_MAX__PRE                                          0x0

#define    SCU_RAM_ATV_AMS_MAX_AMS_MAX__B                                  0
#define    SCU_RAM_ATV_AMS_MAX_AMS_MAX__W                                  11
#define    SCU_RAM_ATV_AMS_MAX_AMS_MAX__M                                  0x7FF
#define    SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE                                0x0

#define  SCU_RAM_ATV_AMS_MIN__A                                            0x831EF3
#define  SCU_RAM_ATV_AMS_MIN__W                                            11
#define  SCU_RAM_ATV_AMS_MIN__M                                            0x7FF
#define  SCU_RAM_ATV_AMS_MIN__PRE                                          0x7FF

#define    SCU_RAM_ATV_AMS_MIN_AMS_MIN__B                                  0
#define    SCU_RAM_ATV_AMS_MIN_AMS_MIN__W                                  11
#define    SCU_RAM_ATV_AMS_MIN_AMS_MIN__M                                  0x7FF
#define    SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE                                0x7FF

#define  SCU_RAM_ATV_FIELD_CNT__A                                          0x831EF4
#define  SCU_RAM_ATV_FIELD_CNT__W                                          9
#define  SCU_RAM_ATV_FIELD_CNT__M                                          0x1FF
#define  SCU_RAM_ATV_FIELD_CNT__PRE                                        0x0

#define    SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B                              0
#define    SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W                              9
#define    SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M                              0x1FF
#define    SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE                            0x0

#define  SCU_RAM_ATV_AAGC_FAST__A                                          0x831EF5
#define  SCU_RAM_ATV_AAGC_FAST__W                                          1
#define  SCU_RAM_ATV_AAGC_FAST__M                                          0x1
#define  SCU_RAM_ATV_AAGC_FAST__PRE                                        0x0

#define    SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B                              0
#define    SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W                              1
#define    SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M                              0x1
#define    SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE                            0x0
#define      SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF                           0x0
#define      SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON                            0x1

#define  SCU_RAM_ATV_AAGC_LP2__A                                           0x831EF6
#define  SCU_RAM_ATV_AAGC_LP2__W                                           16
#define  SCU_RAM_ATV_AAGC_LP2__M                                           0xFFFF
#define  SCU_RAM_ATV_AAGC_LP2__PRE                                         0x0

#define    SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B                                0
#define    SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W                                16
#define    SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M                                0xFFFF
#define    SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE                              0x0

#define  SCU_RAM_ATV_BP_LVL__A                                             0x831EF7
#define  SCU_RAM_ATV_BP_LVL__W                                             11
#define  SCU_RAM_ATV_BP_LVL__M                                             0x7FF
#define  SCU_RAM_ATV_BP_LVL__PRE                                           0x0

#define    SCU_RAM_ATV_BP_LVL_BP_LVL__B                                    0
#define    SCU_RAM_ATV_BP_LVL_BP_LVL__W                                    11
#define    SCU_RAM_ATV_BP_LVL_BP_LVL__M                                    0x7FF
#define    SCU_RAM_ATV_BP_LVL_BP_LVL__PRE                                  0x0

#define  SCU_RAM_ATV_BP_RELY__A                                            0x831EF8
#define  SCU_RAM_ATV_BP_RELY__W                                            8
#define  SCU_RAM_ATV_BP_RELY__M                                            0xFF
#define  SCU_RAM_ATV_BP_RELY__PRE                                          0x0

#define    SCU_RAM_ATV_BP_RELY_BP_RELY__B                                  0
#define    SCU_RAM_ATV_BP_RELY_BP_RELY__W                                  8
#define    SCU_RAM_ATV_BP_RELY_BP_RELY__M                                  0xFF
#define    SCU_RAM_ATV_BP_RELY_BP_RELY__PRE                                0x0

#define  SCU_RAM_ATV_BP_MTA__A                                             0x831EF9
#define  SCU_RAM_ATV_BP_MTA__W                                             14
#define  SCU_RAM_ATV_BP_MTA__M                                             0x3FFF
#define  SCU_RAM_ATV_BP_MTA__PRE                                           0x0

#define    SCU_RAM_ATV_BP_MTA_BP_MTA__B                                    0
#define    SCU_RAM_ATV_BP_MTA_BP_MTA__W                                    14
#define    SCU_RAM_ATV_BP_MTA_BP_MTA__M                                    0x3FFF
#define    SCU_RAM_ATV_BP_MTA_BP_MTA__PRE                                  0x0

#define  SCU_RAM_ATV_BP_REF__A                                             0x831EFA
#define  SCU_RAM_ATV_BP_REF__W                                             11
#define  SCU_RAM_ATV_BP_REF__M                                             0x7FF
#define  SCU_RAM_ATV_BP_REF__PRE                                           0x0

#define    SCU_RAM_ATV_BP_REF_BP_REF__B                                    0
#define    SCU_RAM_ATV_BP_REF_BP_REF__W                                    11
#define    SCU_RAM_ATV_BP_REF_BP_REF__M                                    0x7FF
#define    SCU_RAM_ATV_BP_REF_BP_REF__PRE                                  0x0

#define  SCU_RAM_ATV_BP_REF_MIN__A                                         0x831EFB
#define  SCU_RAM_ATV_BP_REF_MIN__W                                         11
#define  SCU_RAM_ATV_BP_REF_MIN__M                                         0x7FF
#define  SCU_RAM_ATV_BP_REF_MIN__PRE                                       0x64

#define    SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B                            0
#define    SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W                            11
#define    SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M                            0x7FF
#define    SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE                          0x64

#define  SCU_RAM_ATV_BP_REF_MAX__A                                         0x831EFC
#define  SCU_RAM_ATV_BP_REF_MAX__W                                         11
#define  SCU_RAM_ATV_BP_REF_MAX__M                                         0x7FF
#define  SCU_RAM_ATV_BP_REF_MAX__PRE                                       0x104

#define    SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B                            0
#define    SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W                            11
#define    SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M                            0x7FF
#define    SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE                          0x104

#define  SCU_RAM_ATV_BP_CNT__A                                             0x831EFD
#define  SCU_RAM_ATV_BP_CNT__W                                             8
#define  SCU_RAM_ATV_BP_CNT__M                                             0xFF
#define  SCU_RAM_ATV_BP_CNT__PRE                                           0x0

#define    SCU_RAM_ATV_BP_CNT_BP_CNT__B                                    0
#define    SCU_RAM_ATV_BP_CNT_BP_CNT__W                                    8
#define    SCU_RAM_ATV_BP_CNT_BP_CNT__M                                    0xFF
#define    SCU_RAM_ATV_BP_CNT_BP_CNT__PRE                                  0x0

#define  SCU_RAM_ATV_BP_XD_CNT__A                                          0x831EFE
#define  SCU_RAM_ATV_BP_XD_CNT__W                                          12
#define  SCU_RAM_ATV_BP_XD_CNT__M                                          0xFFF
#define  SCU_RAM_ATV_BP_XD_CNT__PRE                                        0x0

#define    SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B                              0
#define    SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W                              12
#define    SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M                              0xFFF
#define    SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE                            0x0

#define  SCU_RAM_ATV_PAGC_KI_MIN__A                                        0x831EFF
#define  SCU_RAM_ATV_PAGC_KI_MIN__W                                        12
#define  SCU_RAM_ATV_PAGC_KI_MIN__M                                        0xFFF
#define  SCU_RAM_ATV_PAGC_KI_MIN__PRE                                      0x445

#define    SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B                          0
#define    SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W                          12
#define    SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M                          0xFFF
#define    SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE                        0x445

#define  SCU_RAM_ATV_BPC_KI_MIN__A                                         0x831F00
#define  SCU_RAM_ATV_BPC_KI_MIN__W                                         12
#define  SCU_RAM_ATV_BPC_KI_MIN__M                                         0xFFF
#define  SCU_RAM_ATV_BPC_KI_MIN__PRE                                       0x223

#define    SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B                            0
#define    SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W                            12
#define    SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M                            0xFFF
#define    SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE                          0x223


#define  SCU_RAM_OFDM_AGC_POW_TGT__A                                       0x831F01
#define  SCU_RAM_OFDM_AGC_POW_TGT__W                                       15
#define  SCU_RAM_OFDM_AGC_POW_TGT__M                                       0x7FFF
#define  SCU_RAM_OFDM_AGC_POW_TGT__PRE                                     0x5848

#define  SCU_RAM_OFDM_RSV_01__A                                            0x831F02
#define  SCU_RAM_OFDM_RSV_01__W                                            16
#define  SCU_RAM_OFDM_RSV_01__M                                            0xFFFF
#define  SCU_RAM_OFDM_RSV_01__PRE                                          0x0

#define  SCU_RAM_OFDM_RSV_02__A                                            0x831F03
#define  SCU_RAM_OFDM_RSV_02__W                                            16
#define  SCU_RAM_OFDM_RSV_02__M                                            0xFFFF
#define  SCU_RAM_OFDM_RSV_02__PRE                                          0x0
#define  SCU_RAM_FEC_PRE_RS_BER__A                                         0x831F04
#define  SCU_RAM_FEC_PRE_RS_BER__W                                         16
#define  SCU_RAM_FEC_PRE_RS_BER__M                                         0xFFFF
#define  SCU_RAM_FEC_PRE_RS_BER__PRE                                       0x0

#define    SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B                       0
#define    SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W                       16
#define    SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M                       0xFFFF
#define    SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE                     0x0

#define  SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A                               0x831F05
#define  SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W                               16
#define  SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M                               0xFFFF
#define  SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE                             0x0

#define    SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B             0
#define    SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W             16
#define    SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M             0xFFFF
#define    SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE           0x0

#define  SCU_RAM_ATV_VSYNC_LINE_CNT__A                                     0x831F06
#define  SCU_RAM_ATV_VSYNC_LINE_CNT__W                                     16
#define  SCU_RAM_ATV_VSYNC_LINE_CNT__M                                     0xFFFF
#define  SCU_RAM_ATV_VSYNC_LINE_CNT__PRE                                   0x0

#define    SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B                       0
#define    SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W                       16
#define    SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M                       0xFFFF
#define    SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE                     0x0

#define  SCU_RAM_ATV_VSYNC_PERIOD__A                                       0x831F07
#define  SCU_RAM_ATV_VSYNC_PERIOD__W                                       16
#define  SCU_RAM_ATV_VSYNC_PERIOD__M                                       0xFFFF
#define  SCU_RAM_ATV_VSYNC_PERIOD__PRE                                     0x0

#define    SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B                         0
#define    SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W                         16
#define    SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M                         0xFFFF
#define    SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE                       0x0

#define  SCU_RAM_FREE_7944__A                                              0x831F08
#define  SCU_RAM_FREE_7944__W                                              16
#define  SCU_RAM_FREE_7944__M                                              0xFFFF
#define  SCU_RAM_FREE_7944__PRE                                            0x0

#define    SCU_RAM_FREE_7944_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7944_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7944_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7945__A                                              0x831F09
#define  SCU_RAM_FREE_7945__W                                              16
#define  SCU_RAM_FREE_7945__M                                              0xFFFF
#define  SCU_RAM_FREE_7945__PRE                                            0x0

#define    SCU_RAM_FREE_7945_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7945_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7945_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7946__A                                              0x831F0A
#define  SCU_RAM_FREE_7946__W                                              16
#define  SCU_RAM_FREE_7946__M                                              0xFFFF
#define  SCU_RAM_FREE_7946__PRE                                            0x0

#define    SCU_RAM_FREE_7946_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7946_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7946_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7947__A                                              0x831F0B
#define  SCU_RAM_FREE_7947__W                                              16
#define  SCU_RAM_FREE_7947__M                                              0xFFFF
#define  SCU_RAM_FREE_7947__PRE                                            0x0

#define    SCU_RAM_FREE_7947_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7947_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7947_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7948__A                                              0x831F0C
#define  SCU_RAM_FREE_7948__W                                              16
#define  SCU_RAM_FREE_7948__M                                              0xFFFF
#define  SCU_RAM_FREE_7948__PRE                                            0x0

#define    SCU_RAM_FREE_7948_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7948_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7948_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7949__A                                              0x831F0D
#define  SCU_RAM_FREE_7949__W                                              16
#define  SCU_RAM_FREE_7949__M                                              0xFFFF
#define  SCU_RAM_FREE_7949__PRE                                            0x0

#define    SCU_RAM_FREE_7949_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7949_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7949_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7950__A                                              0x831F0E
#define  SCU_RAM_FREE_7950__W                                              16
#define  SCU_RAM_FREE_7950__M                                              0xFFFF
#define  SCU_RAM_FREE_7950__PRE                                            0x0

#define    SCU_RAM_FREE_7950_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7950_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7950_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7951__A                                              0x831F0F
#define  SCU_RAM_FREE_7951__W                                              16
#define  SCU_RAM_FREE_7951__M                                              0xFFFF
#define  SCU_RAM_FREE_7951__PRE                                            0x0

#define    SCU_RAM_FREE_7951_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7951_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7951_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7952__A                                              0x831F10
#define  SCU_RAM_FREE_7952__W                                              16
#define  SCU_RAM_FREE_7952__M                                              0xFFFF
#define  SCU_RAM_FREE_7952__PRE                                            0x0

#define    SCU_RAM_FREE_7952_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7952_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7952_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7953__A                                              0x831F11
#define  SCU_RAM_FREE_7953__W                                              16
#define  SCU_RAM_FREE_7953__M                                              0xFFFF
#define  SCU_RAM_FREE_7953__PRE                                            0x0

#define    SCU_RAM_FREE_7953_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7953_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7953_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7954__A                                              0x831F12
#define  SCU_RAM_FREE_7954__W                                              16
#define  SCU_RAM_FREE_7954__M                                              0xFFFF
#define  SCU_RAM_FREE_7954__PRE                                            0x0

#define    SCU_RAM_FREE_7954_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7954_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7954_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7955__A                                              0x831F13
#define  SCU_RAM_FREE_7955__W                                              16
#define  SCU_RAM_FREE_7955__M                                              0xFFFF
#define  SCU_RAM_FREE_7955__PRE                                            0x0

#define    SCU_RAM_FREE_7955_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7955_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7955_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE                             0x0


#define  SCU_RAM_ADC_COMP_CONTROL__A                                       0x831F14
#define  SCU_RAM_ADC_COMP_CONTROL__W                                       3
#define  SCU_RAM_ADC_COMP_CONTROL__M                                       0x7
#define  SCU_RAM_ADC_COMP_CONTROL__PRE                                     0x0
#define    SCU_RAM_ADC_COMP_CONTROL_CONFIG                                 0x0
#define    SCU_RAM_ADC_COMP_CONTROL_DO_AGC                                 0x1
#define    SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST                             0x2
#define    SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE                             0x3


#define  SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A                                0x831F15
#define  SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W                                16
#define  SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M                                0xFFFF
#define  SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE                              0x32

#define  SCU_RAM_AGC_KI_CYCCNT__A                                          0x831F16
#define  SCU_RAM_AGC_KI_CYCCNT__W                                          16
#define  SCU_RAM_AGC_KI_CYCCNT__M                                          0xFFFF
#define  SCU_RAM_AGC_KI_CYCCNT__PRE                                        0x0

#define  SCU_RAM_AGC_KI_CYCLEN__A                                          0x831F17
#define  SCU_RAM_AGC_KI_CYCLEN__W                                          16
#define  SCU_RAM_AGC_KI_CYCLEN__M                                          0xFFFF
#define  SCU_RAM_AGC_KI_CYCLEN__PRE                                        0x1F4

#define  SCU_RAM_AGC_SNS_CYCLEN__A                                         0x831F18
#define  SCU_RAM_AGC_SNS_CYCLEN__W                                         16
#define  SCU_RAM_AGC_SNS_CYCLEN__M                                         0xFFFF
#define  SCU_RAM_AGC_SNS_CYCLEN__PRE                                       0x1F4

#define  SCU_RAM_AGC_RF_SNS_DEV_MAX__A                                     0x831F19
#define  SCU_RAM_AGC_RF_SNS_DEV_MAX__W                                     16
#define  SCU_RAM_AGC_RF_SNS_DEV_MAX__M                                     0xFFFF
#define  SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE                                   0x3FF

#define  SCU_RAM_AGC_RF_SNS_DEV_MIN__A                                     0x831F1A
#define  SCU_RAM_AGC_RF_SNS_DEV_MIN__W                                     16
#define  SCU_RAM_AGC_RF_SNS_DEV_MIN__M                                     0xFFFF
#define  SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE                                   0xFC01

#define  SCU_RAM_AGC_RF_MAX__A                                             0x831F1B
#define  SCU_RAM_AGC_RF_MAX__W                                             15
#define  SCU_RAM_AGC_RF_MAX__M                                             0x7FFF
#define  SCU_RAM_AGC_RF_MAX__PRE                                           0x7FFF
#define  SCU_RAM_FREE_7964__A                                              0x831F1C
#define  SCU_RAM_FREE_7964__W                                              16
#define  SCU_RAM_FREE_7964__M                                              0xFFFF
#define  SCU_RAM_FREE_7964__PRE                                            0x0

#define    SCU_RAM_FREE_7964_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7964_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7964_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7965__A                                              0x831F1D
#define  SCU_RAM_FREE_7965__W                                              16
#define  SCU_RAM_FREE_7965__M                                              0xFFFF
#define  SCU_RAM_FREE_7965__PRE                                            0x0

#define    SCU_RAM_FREE_7965_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7965_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7965_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7966__A                                              0x831F1E
#define  SCU_RAM_FREE_7966__W                                              16
#define  SCU_RAM_FREE_7966__M                                              0xFFFF
#define  SCU_RAM_FREE_7966__PRE                                            0x0

#define    SCU_RAM_FREE_7966_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7966_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7966_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7967__A                                              0x831F1F
#define  SCU_RAM_FREE_7967__W                                              16
#define  SCU_RAM_FREE_7967__M                                              0xFFFF
#define  SCU_RAM_FREE_7967__PRE                                            0x0

#define    SCU_RAM_FREE_7967_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7967_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7967_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_QAM_PARAM_MIRRORING__A                                    0x831F20
#define  SCU_RAM_QAM_PARAM_MIRRORING__W                                    8
#define  SCU_RAM_QAM_PARAM_MIRRORING__M                                    0xFF
#define  SCU_RAM_QAM_PARAM_MIRRORING__PRE                                  0x0

#define    SCU_RAM_QAM_PARAM_MIRRORING_SET__B                              0
#define    SCU_RAM_QAM_PARAM_MIRRORING_SET__W                              1
#define    SCU_RAM_QAM_PARAM_MIRRORING_SET__M                              0x1
#define    SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE                            0x0
#define      SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL                        0x0
#define      SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED                      0x1

#define    SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B                             1
#define    SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W                             1
#define    SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M                             0x2
#define    SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE                           0x0
#define      SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF                          0x0
#define      SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON                           0x2

#define    SCU_RAM_QAM_PARAM_MIRRORING_DET__B                              2
#define    SCU_RAM_QAM_PARAM_MIRRORING_DET__W                              1
#define    SCU_RAM_QAM_PARAM_MIRRORING_DET__M                              0x4
#define    SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE                            0x0
#define      SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL                        0x0
#define      SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED                      0x4

#define  SCU_RAM_QAM_PARAM_OPTIONS__A                                      0x831F21
#define  SCU_RAM_QAM_PARAM_OPTIONS__W                                      8
#define  SCU_RAM_QAM_PARAM_OPTIONS__M                                      0xFF
#define  SCU_RAM_QAM_PARAM_OPTIONS__PRE                                    0x0

#define    SCU_RAM_QAM_PARAM_OPTIONS_SET__B                                0
#define    SCU_RAM_QAM_PARAM_OPTIONS_SET__W                                1
#define    SCU_RAM_QAM_PARAM_OPTIONS_SET__M                                0x1
#define    SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE                              0x0
#define      SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL                          0x0
#define      SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED                        0x1

#define    SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B                               1
#define    SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W                               1
#define    SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M                               0x2
#define    SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE                             0x0
#define      SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF                            0x0
#define      SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON                             0x2

#define    SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B                              4
#define    SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W                              1
#define    SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M                              0x10
#define    SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE                            0x0
#define      SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED                      0x0
#define      SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL                        0x10

#define  SCU_RAM_FREE_7970__A                                              0x831F22
#define  SCU_RAM_FREE_7970__W                                              16
#define  SCU_RAM_FREE_7970__M                                              0xFFFF
#define  SCU_RAM_FREE_7970__PRE                                            0x0

#define    SCU_RAM_FREE_7970_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7970_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7970_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_FREE_7971__A                                              0x831F23
#define  SCU_RAM_FREE_7971__W                                              16
#define  SCU_RAM_FREE_7971__M                                              0xFFFF
#define  SCU_RAM_FREE_7971__PRE                                            0x0

#define    SCU_RAM_FREE_7971_SCU_RAM_FREE__B                               0
#define    SCU_RAM_FREE_7971_SCU_RAM_FREE__W                               16
#define    SCU_RAM_FREE_7971_SCU_RAM_FREE__M                               0xFFFF
#define    SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE                             0x0

#define  SCU_RAM_AGC_CONFIG__A                                             0x831F24
#define  SCU_RAM_AGC_CONFIG__W                                             16
#define  SCU_RAM_AGC_CONFIG__M                                             0xFFFF
#define  SCU_RAM_AGC_CONFIG__PRE                                           0x0

#define    SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B                            0
#define    SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W                            1
#define    SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M                            0x1
#define    SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE                          0x0

#define    SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B                            1
#define    SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W                            1
#define    SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M                            0x2
#define    SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE                          0x0

#define    SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B                         2
#define    SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W                         1
#define    SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M                         0x4
#define    SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE                       0x0

#define    SCU_RAM_AGC_CONFIG_INV_IF_POL__B                                8
#define    SCU_RAM_AGC_CONFIG_INV_IF_POL__W                                1
#define    SCU_RAM_AGC_CONFIG_INV_IF_POL__M                                0x100
#define    SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE                              0x0

#define    SCU_RAM_AGC_CONFIG_INV_RF_POL__B                                9
#define    SCU_RAM_AGC_CONFIG_INV_RF_POL__W                                1
#define    SCU_RAM_AGC_CONFIG_INV_RF_POL__M                                0x200
#define    SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE                              0x0

#define  SCU_RAM_AGC_KI__A                                                 0x831F25
#define  SCU_RAM_AGC_KI__W                                                 15
#define  SCU_RAM_AGC_KI__M                                                 0x7FFF
#define  SCU_RAM_AGC_KI__PRE                                               0x22A

#define    SCU_RAM_AGC_KI_DGAIN__B                                         0
#define    SCU_RAM_AGC_KI_DGAIN__W                                         4
#define    SCU_RAM_AGC_KI_DGAIN__M                                         0xF
#define    SCU_RAM_AGC_KI_DGAIN__PRE                                       0xA

#define    SCU_RAM_AGC_KI_RF__B                                            4
#define    SCU_RAM_AGC_KI_RF__W                                            4
#define    SCU_RAM_AGC_KI_RF__M                                            0xF0
#define    SCU_RAM_AGC_KI_RF__PRE                                          0x20

#define    SCU_RAM_AGC_KI_IF__B                                            8
#define    SCU_RAM_AGC_KI_IF__W                                            4
#define    SCU_RAM_AGC_KI_IF__M                                            0xF00
#define    SCU_RAM_AGC_KI_IF__PRE                                          0x200

#define  SCU_RAM_AGC_KI_RED__A                                             0x831F26
#define  SCU_RAM_AGC_KI_RED__W                                             6
#define  SCU_RAM_AGC_KI_RED__M                                             0x3F
#define  SCU_RAM_AGC_KI_RED__PRE                                           0x0

#define    SCU_RAM_AGC_KI_RED_INNER_RED__B                                 0
#define    SCU_RAM_AGC_KI_RED_INNER_RED__W                                 2
#define    SCU_RAM_AGC_KI_RED_INNER_RED__M                                 0x3
#define    SCU_RAM_AGC_KI_RED_INNER_RED__PRE                               0x0

#define    SCU_RAM_AGC_KI_RED_RAGC_RED__B                                  2
#define    SCU_RAM_AGC_KI_RED_RAGC_RED__W                                  2
#define    SCU_RAM_AGC_KI_RED_RAGC_RED__M                                  0xC
#define    SCU_RAM_AGC_KI_RED_RAGC_RED__PRE                                0x0

#define    SCU_RAM_AGC_KI_RED_IAGC_RED__B                                  4
#define    SCU_RAM_AGC_KI_RED_IAGC_RED__W                                  2
#define    SCU_RAM_AGC_KI_RED_IAGC_RED__M                                  0x30
#define    SCU_RAM_AGC_KI_RED_IAGC_RED__PRE                                0x0


#define  SCU_RAM_AGC_KI_INNERGAIN_MIN__A                                   0x831F27
#define  SCU_RAM_AGC_KI_INNERGAIN_MIN__W                                   16
#define  SCU_RAM_AGC_KI_INNERGAIN_MIN__M                                   0xFFFF
#define  SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE                                 0x0

#define  SCU_RAM_AGC_KI_MINGAIN__A                                         0x831F28
#define  SCU_RAM_AGC_KI_MINGAIN__W                                         16
#define  SCU_RAM_AGC_KI_MINGAIN__M                                         0xFFFF
#define  SCU_RAM_AGC_KI_MINGAIN__PRE                                       0x8000

#define  SCU_RAM_AGC_KI_MAXGAIN__A                                         0x831F29
#define  SCU_RAM_AGC_KI_MAXGAIN__W                                         16
#define  SCU_RAM_AGC_KI_MAXGAIN__M                                         0xFFFF
#define  SCU_RAM_AGC_KI_MAXGAIN__PRE                                       0x0

#define  SCU_RAM_AGC_KI_MAXMINGAIN_TH__A                                   0x831F2A
#define  SCU_RAM_AGC_KI_MAXMINGAIN_TH__W                                   16
#define  SCU_RAM_AGC_KI_MAXMINGAIN_TH__M                                   0xFFFF
#define  SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE                                 0x0
#define  SCU_RAM_AGC_KI_MIN__A                                             0x831F2B
#define  SCU_RAM_AGC_KI_MIN__W                                             12
#define  SCU_RAM_AGC_KI_MIN__M                                             0xFFF
#define  SCU_RAM_AGC_KI_MIN__PRE                                           0x111

#define    SCU_RAM_AGC_KI_MIN_DGAIN__B                                     0
#define    SCU_RAM_AGC_KI_MIN_DGAIN__W                                     4
#define    SCU_RAM_AGC_KI_MIN_DGAIN__M                                     0xF
#define    SCU_RAM_AGC_KI_MIN_DGAIN__PRE                                   0x1

#define    SCU_RAM_AGC_KI_MIN_RF__B                                        4
#define    SCU_RAM_AGC_KI_MIN_RF__W                                        4
#define    SCU_RAM_AGC_KI_MIN_RF__M                                        0xF0
#define    SCU_RAM_AGC_KI_MIN_RF__PRE                                      0x10

#define    SCU_RAM_AGC_KI_MIN_IF__B                                        8
#define    SCU_RAM_AGC_KI_MIN_IF__W                                        4
#define    SCU_RAM_AGC_KI_MIN_IF__M                                        0xF00
#define    SCU_RAM_AGC_KI_MIN_IF__PRE                                      0x100

#define  SCU_RAM_AGC_KI_MAX__A                                             0x831F2C
#define  SCU_RAM_AGC_KI_MAX__W                                             12
#define  SCU_RAM_AGC_KI_MAX__M                                             0xFFF
#define  SCU_RAM_AGC_KI_MAX__PRE                                           0xFFF

#define    SCU_RAM_AGC_KI_MAX_DGAIN__B                                     0
#define    SCU_RAM_AGC_KI_MAX_DGAIN__W                                     4
#define    SCU_RAM_AGC_KI_MAX_DGAIN__M                                     0xF
#define    SCU_RAM_AGC_KI_MAX_DGAIN__PRE                                   0xF

#define    SCU_RAM_AGC_KI_MAX_RF__B                                        4
#define    SCU_RAM_AGC_KI_MAX_RF__W                                        4
#define    SCU_RAM_AGC_KI_MAX_RF__M                                        0xF0
#define    SCU_RAM_AGC_KI_MAX_RF__PRE                                      0xF0

#define    SCU_RAM_AGC_KI_MAX_IF__B                                        8
#define    SCU_RAM_AGC_KI_MAX_IF__W                                        4
#define    SCU_RAM_AGC_KI_MAX_IF__M                                        0xF00
#define    SCU_RAM_AGC_KI_MAX_IF__PRE                                      0xF00


#define  SCU_RAM_AGC_CLP_SUM__A                                            0x831F2D
#define  SCU_RAM_AGC_CLP_SUM__W                                            16
#define  SCU_RAM_AGC_CLP_SUM__M                                            0xFFFF
#define  SCU_RAM_AGC_CLP_SUM__PRE                                          0x0

#define  SCU_RAM_AGC_CLP_SUM_MIN__A                                        0x831F2E
#define  SCU_RAM_AGC_CLP_SUM_MIN__W                                        16
#define  SCU_RAM_AGC_CLP_SUM_MIN__M                                        0xFFFF
#define  SCU_RAM_AGC_CLP_SUM_MIN__PRE                                      0x8

#define  SCU_RAM_AGC_CLP_SUM_MAX__A                                        0x831F2F
#define  SCU_RAM_AGC_CLP_SUM_MAX__W                                        16
#define  SCU_RAM_AGC_CLP_SUM_MAX__M                                        0xFFFF
#define  SCU_RAM_AGC_CLP_SUM_MAX__PRE                                      0x400

#define  SCU_RAM_AGC_CLP_CYCLEN__A                                         0x831F30
#define  SCU_RAM_AGC_CLP_CYCLEN__W                                         16
#define  SCU_RAM_AGC_CLP_CYCLEN__M                                         0xFFFF
#define  SCU_RAM_AGC_CLP_CYCLEN__PRE                                       0x1F4

#define  SCU_RAM_AGC_CLP_CYCCNT__A                                         0x831F31
#define  SCU_RAM_AGC_CLP_CYCCNT__W                                         16
#define  SCU_RAM_AGC_CLP_CYCCNT__M                                         0xFFFF
#define  SCU_RAM_AGC_CLP_CYCCNT__PRE                                       0x0

#define  SCU_RAM_AGC_CLP_DIR_TO__A                                         0x831F32
#define  SCU_RAM_AGC_CLP_DIR_TO__W                                         8
#define  SCU_RAM_AGC_CLP_DIR_TO__M                                         0xFF
#define  SCU_RAM_AGC_CLP_DIR_TO__PRE                                       0xFC

#define  SCU_RAM_AGC_CLP_DIR_WD__A                                         0x831F33
#define  SCU_RAM_AGC_CLP_DIR_WD__W                                         8
#define  SCU_RAM_AGC_CLP_DIR_WD__M                                         0xFF
#define  SCU_RAM_AGC_CLP_DIR_WD__PRE                                       0x0

#define  SCU_RAM_AGC_CLP_DIR_STP__A                                        0x831F34
#define  SCU_RAM_AGC_CLP_DIR_STP__W                                        16
#define  SCU_RAM_AGC_CLP_DIR_STP__M                                        0xFFFF
#define  SCU_RAM_AGC_CLP_DIR_STP__PRE                                      0x1

#define  SCU_RAM_AGC_SNS_SUM__A                                            0x831F35
#define  SCU_RAM_AGC_SNS_SUM__W                                            16
#define  SCU_RAM_AGC_SNS_SUM__M                                            0xFFFF
#define  SCU_RAM_AGC_SNS_SUM__PRE                                          0x0

#define  SCU_RAM_AGC_SNS_SUM_MIN__A                                        0x831F36
#define  SCU_RAM_AGC_SNS_SUM_MIN__W                                        16
#define  SCU_RAM_AGC_SNS_SUM_MIN__M                                        0xFFFF
#define  SCU_RAM_AGC_SNS_SUM_MIN__PRE                                      0x8

#define  SCU_RAM_AGC_SNS_SUM_MAX__A                                        0x831F37
#define  SCU_RAM_AGC_SNS_SUM_MAX__W                                        16
#define  SCU_RAM_AGC_SNS_SUM_MAX__M                                        0xFFFF
#define  SCU_RAM_AGC_SNS_SUM_MAX__PRE                                      0x400

#define  SCU_RAM_AGC_SNS_CYCCNT__A                                         0x831F38
#define  SCU_RAM_AGC_SNS_CYCCNT__W                                         16
#define  SCU_RAM_AGC_SNS_CYCCNT__M                                         0xFFFF
#define  SCU_RAM_AGC_SNS_CYCCNT__PRE                                       0x0

#define  SCU_RAM_AGC_SNS_DIR_TO__A                                         0x831F39
#define  SCU_RAM_AGC_SNS_DIR_TO__W                                         8
#define  SCU_RAM_AGC_SNS_DIR_TO__M                                         0xFF
#define  SCU_RAM_AGC_SNS_DIR_TO__PRE                                       0xFC

#define  SCU_RAM_AGC_SNS_DIR_WD__A                                         0x831F3A
#define  SCU_RAM_AGC_SNS_DIR_WD__W                                         8
#define  SCU_RAM_AGC_SNS_DIR_WD__M                                         0xFF
#define  SCU_RAM_AGC_SNS_DIR_WD__PRE                                       0x0

#define  SCU_RAM_AGC_SNS_DIR_STP__A                                        0x831F3B
#define  SCU_RAM_AGC_SNS_DIR_STP__W                                        16
#define  SCU_RAM_AGC_SNS_DIR_STP__M                                        0xFFFF
#define  SCU_RAM_AGC_SNS_DIR_STP__PRE                                      0x1

#define  SCU_RAM_AGC_INGAIN__A                                             0x831F3C
#define  SCU_RAM_AGC_INGAIN__W                                             16
#define  SCU_RAM_AGC_INGAIN__M                                             0xFFFF
#define  SCU_RAM_AGC_INGAIN__PRE                                           0x708

#define  SCU_RAM_AGC_INGAIN_TGT__A                                         0x831F3D
#define  SCU_RAM_AGC_INGAIN_TGT__W                                         15
#define  SCU_RAM_AGC_INGAIN_TGT__M                                         0x7FFF
#define  SCU_RAM_AGC_INGAIN_TGT__PRE                                       0x708

#define  SCU_RAM_AGC_INGAIN_TGT_MIN__A                                     0x831F3E
#define  SCU_RAM_AGC_INGAIN_TGT_MIN__W                                     15
#define  SCU_RAM_AGC_INGAIN_TGT_MIN__M                                     0x7FFF
#define  SCU_RAM_AGC_INGAIN_TGT_MIN__PRE                                   0x708

#define  SCU_RAM_AGC_INGAIN_TGT_MAX__A                                     0x831F3F
#define  SCU_RAM_AGC_INGAIN_TGT_MAX__W                                     15
#define  SCU_RAM_AGC_INGAIN_TGT_MAX__M                                     0x7FFF
#define  SCU_RAM_AGC_INGAIN_TGT_MAX__PRE                                   0x3FFF

#define  SCU_RAM_AGC_IF_IACCU_HI__A                                        0x831F40
#define  SCU_RAM_AGC_IF_IACCU_HI__W                                        16
#define  SCU_RAM_AGC_IF_IACCU_HI__M                                        0xFFFF
#define  SCU_RAM_AGC_IF_IACCU_HI__PRE                                      0x0

#define  SCU_RAM_AGC_IF_IACCU_LO__A                                        0x831F41
#define  SCU_RAM_AGC_IF_IACCU_LO__W                                        8
#define  SCU_RAM_AGC_IF_IACCU_LO__M                                        0xFF
#define  SCU_RAM_AGC_IF_IACCU_LO__PRE                                      0x0

#define  SCU_RAM_AGC_IF_IACCU_HI_TGT__A                                    0x831F42
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT__W                                    15
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT__M                                    0x7FFF
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE                                  0x2008

#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A                                0x831F43
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W                                15
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M                                0x7FFF
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE                              0x0

#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A                                0x831F44
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W                                15
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M                                0x7FFF
#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE                              0x251C

#define  SCU_RAM_AGC_RF_IACCU_HI__A                                        0x831F45
#define  SCU_RAM_AGC_RF_IACCU_HI__W                                        16
#define  SCU_RAM_AGC_RF_IACCU_HI__M                                        0xFFFF
#define  SCU_RAM_AGC_RF_IACCU_HI__PRE                                      0x0

#define  SCU_RAM_AGC_RF_IACCU_LO__A                                        0x831F46
#define  SCU_RAM_AGC_RF_IACCU_LO__W                                        8
#define  SCU_RAM_AGC_RF_IACCU_LO__M                                        0xFF
#define  SCU_RAM_AGC_RF_IACCU_LO__PRE                                      0x0

#define  SCU_RAM_AGC_RF_IACCU_HI_CO__A                                     0x831F47
#define  SCU_RAM_AGC_RF_IACCU_HI_CO__W                                     16
#define  SCU_RAM_AGC_RF_IACCU_HI_CO__M                                     0xFFFF
#define  SCU_RAM_AGC_RF_IACCU_HI_CO__PRE                                   0x0
#define  SCU_RAM_ATV_STANDARD__A                                           0x831F48
#define  SCU_RAM_ATV_STANDARD__W                                           12
#define  SCU_RAM_ATV_STANDARD__M                                           0xFFF
#define  SCU_RAM_ATV_STANDARD__PRE                                         0x2

#define    SCU_RAM_ATV_STANDARD_STANDARD__B                                0
#define    SCU_RAM_ATV_STANDARD_STANDARD__W                                12
#define    SCU_RAM_ATV_STANDARD_STANDARD__M                                0xFFF
#define    SCU_RAM_ATV_STANDARD_STANDARD__PRE                              0x2
#define      SCU_RAM_ATV_STANDARD_STANDARD_MN                              0x2
#define      SCU_RAM_ATV_STANDARD_STANDARD_B                               0x103
#define      SCU_RAM_ATV_STANDARD_STANDARD_G                               0x3
#define      SCU_RAM_ATV_STANDARD_STANDARD_DK                              0x4
#define      SCU_RAM_ATV_STANDARD_STANDARD_L                               0x9
#define      SCU_RAM_ATV_STANDARD_STANDARD_LP                              0x109
#define      SCU_RAM_ATV_STANDARD_STANDARD_I                               0xA
#define      SCU_RAM_ATV_STANDARD_STANDARD_FM                              0x40

#define  SCU_RAM_ATV_DETECT__A                                             0x831F49
#define  SCU_RAM_ATV_DETECT__W                                             1
#define  SCU_RAM_ATV_DETECT__M                                             0x1
#define  SCU_RAM_ATV_DETECT__PRE                                           0x0

#define    SCU_RAM_ATV_DETECT_DETECT__B                                    0
#define    SCU_RAM_ATV_DETECT_DETECT__W                                    1
#define    SCU_RAM_ATV_DETECT_DETECT__M                                    0x1
#define    SCU_RAM_ATV_DETECT_DETECT__PRE                                  0x0
#define      SCU_RAM_ATV_DETECT_DETECT_FALSE                               0x0
#define      SCU_RAM_ATV_DETECT_DETECT_TRUE                                0x1

#define  SCU_RAM_ATV_DETECT_TH__A                                          0x831F4A
#define  SCU_RAM_ATV_DETECT_TH__W                                          8
#define  SCU_RAM_ATV_DETECT_TH__M                                          0xFF
#define  SCU_RAM_ATV_DETECT_TH__PRE                                        0x7F

#define    SCU_RAM_ATV_DETECT_TH_DETECT_TH__B                              0
#define    SCU_RAM_ATV_DETECT_TH_DETECT_TH__W                              8
#define    SCU_RAM_ATV_DETECT_TH_DETECT_TH__M                              0xFF
#define    SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE                            0x7F

#define  SCU_RAM_ATV_LOCK__A                                               0x831F4B
#define  SCU_RAM_ATV_LOCK__W                                               2
#define  SCU_RAM_ATV_LOCK__M                                               0x3
#define  SCU_RAM_ATV_LOCK__PRE                                             0x0

#define    SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B                                 0
#define    SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W                                 1
#define    SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M                                 0x1
#define    SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE                               0x0
#define      SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK                          0x0
#define      SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK                             0x1

#define    SCU_RAM_ATV_LOCK_SYNC_FLAG__B                                   1
#define    SCU_RAM_ATV_LOCK_SYNC_FLAG__W                                   1
#define    SCU_RAM_ATV_LOCK_SYNC_FLAG__M                                   0x2
#define    SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE                                 0x0
#define      SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC                            0x0
#define      SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC                               0x2

#define  SCU_RAM_ATV_CR_LOCK__A                                            0x831F4C
#define  SCU_RAM_ATV_CR_LOCK__W                                            11
#define  SCU_RAM_ATV_CR_LOCK__M                                            0x7FF
#define  SCU_RAM_ATV_CR_LOCK__PRE                                          0x0

#define    SCU_RAM_ATV_CR_LOCK_CR_LOCK__B                                  0
#define    SCU_RAM_ATV_CR_LOCK_CR_LOCK__W                                  11
#define    SCU_RAM_ATV_CR_LOCK_CR_LOCK__M                                  0x7FF
#define    SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE                                0x0

#define  SCU_RAM_ATV_AGC_MODE__A                                           0x831F4D
#define  SCU_RAM_ATV_AGC_MODE__W                                           8
#define  SCU_RAM_ATV_AGC_MODE__M                                           0xFF
#define  SCU_RAM_ATV_AGC_MODE__PRE                                         0x50

#define    SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B                                2
#define    SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W                                1
#define    SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M                                0x4
#define    SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE                              0x0
#define      SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST                        0x0
#define      SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW                        0x4

#define    SCU_RAM_ATV_AGC_MODE_BP_EN__B                                   3
#define    SCU_RAM_ATV_AGC_MODE_BP_EN__W                                   1
#define    SCU_RAM_ATV_AGC_MODE_BP_EN__M                                   0x8
#define    SCU_RAM_ATV_AGC_MODE_BP_EN__PRE                                 0x0
#define      SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE                        0x0
#define      SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE                         0x8

#define    SCU_RAM_ATV_AGC_MODE_SIF_STD__B                                 4
#define    SCU_RAM_ATV_AGC_MODE_SIF_STD__W                                 2
#define    SCU_RAM_ATV_AGC_MODE_SIF_STD__M                                 0x30
#define    SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE                               0x10
#define      SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF                      0x0
#define      SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM                       0x10
#define      SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM                       0x20

#define    SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B                            6
#define    SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W                            1
#define    SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M                            0x40
#define    SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE                          0x40
#define      SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE                0x0
#define      SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE                 0x40

#define    SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B                               7
#define    SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W                               1
#define    SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M                               0x80
#define    SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE                             0x0
#define      SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE                     0x0
#define      SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE                    0x80


#define  SCU_RAM_ATV_RSV_01__A                                             0x831F4E
#define  SCU_RAM_ATV_RSV_01__W                                             16
#define  SCU_RAM_ATV_RSV_01__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_01__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_02__A                                             0x831F4F
#define  SCU_RAM_ATV_RSV_02__W                                             16
#define  SCU_RAM_ATV_RSV_02__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_02__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_03__A                                             0x831F50
#define  SCU_RAM_ATV_RSV_03__W                                             16
#define  SCU_RAM_ATV_RSV_03__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_03__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_04__A                                             0x831F51
#define  SCU_RAM_ATV_RSV_04__W                                             16
#define  SCU_RAM_ATV_RSV_04__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_04__PRE                                           0x0
#define  SCU_RAM_ATV_FAGC_TH_RED__A                                        0x831F52
#define  SCU_RAM_ATV_FAGC_TH_RED__W                                        8
#define  SCU_RAM_ATV_FAGC_TH_RED__M                                        0xFF
#define  SCU_RAM_ATV_FAGC_TH_RED__PRE                                      0xA

#define    SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B                          0
#define    SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W                          8
#define    SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M                          0xFF
#define    SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE                        0xA

#define  SCU_RAM_ATV_AMS_MAX_REF__A                                        0x831F53
#define  SCU_RAM_ATV_AMS_MAX_REF__W                                        11
#define  SCU_RAM_ATV_AMS_MAX_REF__M                                        0x7FF
#define  SCU_RAM_ATV_AMS_MAX_REF__PRE                                      0x2BC

#define    SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B                          0
#define    SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W                          11
#define    SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M                          0x7FF
#define    SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE                        0x2BC
#define      SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN                     0x2BC
#define      SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK                        0x2D0
#define      SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I                         0x314
#define      SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP                       0x28A

#define  SCU_RAM_ATV_ACT_AMX__A                                            0x831F54
#define  SCU_RAM_ATV_ACT_AMX__W                                            11
#define  SCU_RAM_ATV_ACT_AMX__M                                            0x7FF
#define  SCU_RAM_ATV_ACT_AMX__PRE                                          0x0

#define    SCU_RAM_ATV_ACT_AMX_ACT_AMX__B                                  0
#define    SCU_RAM_ATV_ACT_AMX_ACT_AMX__W                                  11
#define    SCU_RAM_ATV_ACT_AMX_ACT_AMX__M                                  0x7FF
#define    SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE                                0x0

#define  SCU_RAM_ATV_ACT_AMI__A                                            0x831F55
#define  SCU_RAM_ATV_ACT_AMI__W                                            11
#define  SCU_RAM_ATV_ACT_AMI__M                                            0x7FF
#define  SCU_RAM_ATV_ACT_AMI__PRE                                          0x0

#define    SCU_RAM_ATV_ACT_AMI_ACT_AMI__B                                  0
#define    SCU_RAM_ATV_ACT_AMI_ACT_AMI__W                                  11
#define    SCU_RAM_ATV_ACT_AMI_ACT_AMI__M                                  0x7FF
#define    SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE                                0x0

#define  SCU_RAM_ATV_BPC_REF_PERIOD__A                                     0x831F56
#define  SCU_RAM_ATV_BPC_REF_PERIOD__W                                     16
#define  SCU_RAM_ATV_BPC_REF_PERIOD__M                                     0xFFFF
#define  SCU_RAM_ATV_BPC_REF_PERIOD__PRE                                   0x0

#define    SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B                    0
#define    SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W                    16
#define    SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M                    0xFFFF
#define    SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE                  0x0

#define  SCU_RAM_ATV_BPC_REF_CNT__A                                        0x831F57
#define  SCU_RAM_ATV_BPC_REF_CNT__W                                        16
#define  SCU_RAM_ATV_BPC_REF_CNT__M                                        0xFFFF
#define  SCU_RAM_ATV_BPC_REF_CNT__PRE                                      0x0

#define    SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B                          0
#define    SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W                          16
#define    SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M                          0xFFFF
#define    SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE                        0x0


#define  SCU_RAM_ATV_RSV_07__A                                             0x831F58
#define  SCU_RAM_ATV_RSV_07__W                                             16
#define  SCU_RAM_ATV_RSV_07__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_07__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_08__A                                             0x831F59
#define  SCU_RAM_ATV_RSV_08__W                                             16
#define  SCU_RAM_ATV_RSV_08__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_08__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_09__A                                             0x831F5A
#define  SCU_RAM_ATV_RSV_09__W                                             16
#define  SCU_RAM_ATV_RSV_09__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_09__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_10__A                                             0x831F5B
#define  SCU_RAM_ATV_RSV_10__W                                             16
#define  SCU_RAM_ATV_RSV_10__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_10__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_11__A                                             0x831F5C
#define  SCU_RAM_ATV_RSV_11__W                                             16
#define  SCU_RAM_ATV_RSV_11__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_11__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_12__A                                             0x831F5D
#define  SCU_RAM_ATV_RSV_12__W                                             16
#define  SCU_RAM_ATV_RSV_12__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_12__PRE                                           0x0
#define  SCU_RAM_ATV_VID_GAIN_HI__A                                        0x831F5E
#define  SCU_RAM_ATV_VID_GAIN_HI__W                                        16
#define  SCU_RAM_ATV_VID_GAIN_HI__M                                        0xFFFF
#define  SCU_RAM_ATV_VID_GAIN_HI__PRE                                      0x1000

#define    SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B                          0
#define    SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W                          16
#define    SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M                          0xFFFF
#define    SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE                        0x1000

#define  SCU_RAM_ATV_VID_GAIN_LO__A                                        0x831F5F
#define  SCU_RAM_ATV_VID_GAIN_LO__W                                        8
#define  SCU_RAM_ATV_VID_GAIN_LO__M                                        0xFF
#define  SCU_RAM_ATV_VID_GAIN_LO__PRE                                      0x0

#define    SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B                          0
#define    SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W                          8
#define    SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M                          0xFF
#define    SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE                        0x0


#define  SCU_RAM_ATV_RSV_13__A                                             0x831F60
#define  SCU_RAM_ATV_RSV_13__W                                             16
#define  SCU_RAM_ATV_RSV_13__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_13__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_14__A                                             0x831F61
#define  SCU_RAM_ATV_RSV_14__W                                             16
#define  SCU_RAM_ATV_RSV_14__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_14__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_15__A                                             0x831F62
#define  SCU_RAM_ATV_RSV_15__W                                             16
#define  SCU_RAM_ATV_RSV_15__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_15__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_16__A                                             0x831F63
#define  SCU_RAM_ATV_RSV_16__W                                             16
#define  SCU_RAM_ATV_RSV_16__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_16__PRE                                           0x0
#define  SCU_RAM_ATV_AAGC_CNT__A                                           0x831F64
#define  SCU_RAM_ATV_AAGC_CNT__W                                           8
#define  SCU_RAM_ATV_AAGC_CNT__M                                           0xFF
#define  SCU_RAM_ATV_AAGC_CNT__PRE                                         0x7

#define    SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B                                0
#define    SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W                                8
#define    SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M                                0xFF
#define    SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE                              0x7

#define  SCU_RAM_ATV_SIF_GAIN__A                                           0x831F65
#define  SCU_RAM_ATV_SIF_GAIN__W                                           11
#define  SCU_RAM_ATV_SIF_GAIN__M                                           0x7FF
#define  SCU_RAM_ATV_SIF_GAIN__PRE                                         0x80

#define    SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B                                0
#define    SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W                                11
#define    SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M                                0x7FF
#define    SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE                              0x80


#define  SCU_RAM_ATV_RSV_17__A                                             0x831F66
#define  SCU_RAM_ATV_RSV_17__W                                             16
#define  SCU_RAM_ATV_RSV_17__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_17__PRE                                           0x0

#define  SCU_RAM_ATV_RSV_18__A                                             0x831F67
#define  SCU_RAM_ATV_RSV_18__W                                             16
#define  SCU_RAM_ATV_RSV_18__M                                             0xFFFF
#define  SCU_RAM_ATV_RSV_18__PRE                                           0x0

#define  SCU_RAM_ATV_RATE_OFS__A                                           0x831F68
#define  SCU_RAM_ATV_RATE_OFS__W                                           12
#define  SCU_RAM_ATV_RATE_OFS__M                                           0xFFF
#define  SCU_RAM_ATV_RATE_OFS__PRE                                         0x0

#define  SCU_RAM_ATV_LO_INCR__A                                            0x831F69
#define  SCU_RAM_ATV_LO_INCR__W                                            12
#define  SCU_RAM_ATV_LO_INCR__M                                            0xFFF
#define  SCU_RAM_ATV_LO_INCR__PRE                                          0x0

#define  SCU_RAM_ATV_IIR_CRIT__A                                           0x831F6A
#define  SCU_RAM_ATV_IIR_CRIT__W                                           12
#define  SCU_RAM_ATV_IIR_CRIT__M                                           0xFFF
#define  SCU_RAM_ATV_IIR_CRIT__PRE                                         0x0

#define  SCU_RAM_ATV_DEF_RATE_OFS__A                                       0x831F6B
#define  SCU_RAM_ATV_DEF_RATE_OFS__W                                       12
#define  SCU_RAM_ATV_DEF_RATE_OFS__M                                       0xFFF
#define  SCU_RAM_ATV_DEF_RATE_OFS__PRE                                     0x0

#define  SCU_RAM_ATV_DEF_LO_INCR__A                                        0x831F6C
#define  SCU_RAM_ATV_DEF_LO_INCR__W                                        12
#define  SCU_RAM_ATV_DEF_LO_INCR__M                                        0xFFF
#define  SCU_RAM_ATV_DEF_LO_INCR__PRE                                      0x0

#define  SCU_RAM_ATV_ENABLE_IIR_WA__A                                      0x831F6D
#define  SCU_RAM_ATV_ENABLE_IIR_WA__W                                      1
#define  SCU_RAM_ATV_ENABLE_IIR_WA__M                                      0x1
#define  SCU_RAM_ATV_ENABLE_IIR_WA__PRE                                    0x0
#define  SCU_RAM_ATV_MOD_CONTROL__A                                        0x831F6E
#define  SCU_RAM_ATV_MOD_CONTROL__W                                        12
#define  SCU_RAM_ATV_MOD_CONTROL__M                                        0xFFF
#define  SCU_RAM_ATV_MOD_CONTROL__PRE                                      0x0

#define    SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B                          0
#define    SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W                          12
#define    SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M                          0xFFF
#define    SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE                        0x0

#define  SCU_RAM_ATV_PAGC_KI_MAX__A                                        0x831F6F
#define  SCU_RAM_ATV_PAGC_KI_MAX__W                                        12
#define  SCU_RAM_ATV_PAGC_KI_MAX__M                                        0xFFF
#define  SCU_RAM_ATV_PAGC_KI_MAX__PRE                                      0x667

#define    SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B                          0
#define    SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W                          12
#define    SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M                          0xFFF
#define    SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE                        0x667

#define  SCU_RAM_ATV_BPC_KI_MAX__A                                         0x831F70
#define  SCU_RAM_ATV_BPC_KI_MAX__W                                         12
#define  SCU_RAM_ATV_BPC_KI_MAX__M                                         0xFFF
#define  SCU_RAM_ATV_BPC_KI_MAX__PRE                                       0x337

#define    SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B                           0
#define    SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W                           12
#define    SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M                           0xFFF
#define    SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE                         0x337

#define  SCU_RAM_ATV_NAGC_KI_MAX__A                                        0x831F71
#define  SCU_RAM_ATV_NAGC_KI_MAX__W                                        12
#define  SCU_RAM_ATV_NAGC_KI_MAX__M                                        0xFFF
#define  SCU_RAM_ATV_NAGC_KI_MAX__PRE                                      0x447

#define    SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B                          0
#define    SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W                          12
#define    SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M                          0xFFF
#define    SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE                        0x447

#define  SCU_RAM_ATV_NAGC_KI_MIN__A                                        0x831F72
#define  SCU_RAM_ATV_NAGC_KI_MIN__W                                        12
#define  SCU_RAM_ATV_NAGC_KI_MIN__M                                        0xFFF
#define  SCU_RAM_ATV_NAGC_KI_MIN__PRE                                      0x225

#define    SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B                          0
#define    SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W                          12
#define    SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M                          0xFFF
#define    SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE                        0x225

#define  SCU_RAM_ATV_KI_CHANGE_TH__A                                       0x831F73
#define  SCU_RAM_ATV_KI_CHANGE_TH__W                                       8
#define  SCU_RAM_ATV_KI_CHANGE_TH__M                                       0xFF
#define  SCU_RAM_ATV_KI_CHANGE_TH__PRE                                     0x14

#define    SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B                        0
#define    SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W                        8
#define    SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M                        0xFF
#define    SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE                      0x14
#define      SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD                 0x14
#define      SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD                 0x28

#define  SCU_RAM_QAM_PARAM_ANNEX__A                                        0x831F74
#define  SCU_RAM_QAM_PARAM_ANNEX__W                                        2
#define  SCU_RAM_QAM_PARAM_ANNEX__M                                        0x3
#define  SCU_RAM_QAM_PARAM_ANNEX__PRE                                      0x1

#define    SCU_RAM_QAM_PARAM_ANNEX_BIT__B                                  0
#define    SCU_RAM_QAM_PARAM_ANNEX_BIT__W                                  2
#define    SCU_RAM_QAM_PARAM_ANNEX_BIT__M                                  0x3
#define    SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE                                0x1
#define      SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A                           0x0
#define      SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B                           0x1
#define      SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C                           0x2
#define      SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D                           0x3

#define  SCU_RAM_QAM_PARAM_CONSTELLATION__A                                0x831F75
#define  SCU_RAM_QAM_PARAM_CONSTELLATION__W                                3
#define  SCU_RAM_QAM_PARAM_CONSTELLATION__M                                0x7
#define  SCU_RAM_QAM_PARAM_CONSTELLATION__PRE                              0x5

#define    SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B                          0
#define    SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W                          3
#define    SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M                          0x7
#define    SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE                        0x5
#define      SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN                   0x0
#define      SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16                    0x3
#define      SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32                    0x4
#define      SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64                    0x5
#define      SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128                   0x6
#define      SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256                   0x7

#define  SCU_RAM_QAM_PARAM_INTERLEAVE__A                                   0x831F76
#define  SCU_RAM_QAM_PARAM_INTERLEAVE__W                                   8
#define  SCU_RAM_QAM_PARAM_INTERLEAVE__M                                   0xFF
#define  SCU_RAM_QAM_PARAM_INTERLEAVE__PRE                                 0x1

#define    SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B                             0
#define    SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W                             8
#define    SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M                             0xFF
#define    SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE                           0x1
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1                      0x0
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2                   0x1
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2                      0x2
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2                       0x3
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3                      0x4
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4                       0x5
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4                      0x6
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8                       0x7
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5                      0x8
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16                       0x9
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6                      0xA
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7                      0xC
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8                      0xE
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17                      0x10
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4                        0x11
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN                      0xFE
#define      SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO                         0xFF

#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A                                0x831F77
#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W                                16
#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M                                0xFFFF
#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE                              0x0

#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B                          0
#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W                          16
#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M                          0xFFFF
#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE                        0x0

#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A                                0x831F78
#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W                                16
#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M                                0xFFFF
#define  SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE                              0x0

#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B                          0
#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W                          16
#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M                          0xFFFF
#define    SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE                        0x0

#define  SCU_RAM_QAM_EQ_CENTERTAP__A                                       0x831F79
#define  SCU_RAM_QAM_EQ_CENTERTAP__W                                       16
#define  SCU_RAM_QAM_EQ_CENTERTAP__M                                       0xFFFF
#define  SCU_RAM_QAM_EQ_CENTERTAP__PRE                                     0x13

#define    SCU_RAM_QAM_EQ_CENTERTAP_BIT__B                                 0
#define    SCU_RAM_QAM_EQ_CENTERTAP_BIT__W                                 8
#define    SCU_RAM_QAM_EQ_CENTERTAP_BIT__M                                 0xFF
#define    SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE                               0x13

#define  SCU_RAM_QAM_WR_RSV_0__A                                           0x831F7A
#define  SCU_RAM_QAM_WR_RSV_0__W                                           16
#define  SCU_RAM_QAM_WR_RSV_0__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_0__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_0_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_0_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_0_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_0_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A                                0x831F7B
#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W                                16
#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M                                0xFFFF
#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE                              0x0

#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B                          0
#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W                          16
#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M                          0xFFFF
#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE                        0x0

#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A                                0x831F7C
#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W                                16
#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M                                0xFFFF
#define  SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE                              0x0

#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B                          0
#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W                          16
#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M                          0xFFFF
#define    SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE                        0x0

#define  SCU_RAM_QAM_WR_RSV_5__A                                           0x831F7D
#define  SCU_RAM_QAM_WR_RSV_5__W                                           16
#define  SCU_RAM_QAM_WR_RSV_5__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_5__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_5_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_5_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_5_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_5_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_6__A                                           0x831F7E
#define  SCU_RAM_QAM_WR_RSV_6__W                                           16
#define  SCU_RAM_QAM_WR_RSV_6__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_6__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_6_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_6_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_6_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_6_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_7__A                                           0x831F7F
#define  SCU_RAM_QAM_WR_RSV_7__W                                           16
#define  SCU_RAM_QAM_WR_RSV_7__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_7__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_7_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_7_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_7_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_7_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_8__A                                           0x831F80
#define  SCU_RAM_QAM_WR_RSV_8__W                                           16
#define  SCU_RAM_QAM_WR_RSV_8__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_8__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_8_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_8_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_8_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_8_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_9__A                                           0x831F81
#define  SCU_RAM_QAM_WR_RSV_9__W                                           16
#define  SCU_RAM_QAM_WR_RSV_9__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_9__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_9_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_9_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_9_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_9_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_10__A                                          0x831F82
#define  SCU_RAM_QAM_WR_RSV_10__W                                          16
#define  SCU_RAM_QAM_WR_RSV_10__M                                          0xFFFF
#define  SCU_RAM_QAM_WR_RSV_10__PRE                                        0x0

#define    SCU_RAM_QAM_WR_RSV_10_BIT__B                                    0
#define    SCU_RAM_QAM_WR_RSV_10_BIT__W                                    16
#define    SCU_RAM_QAM_WR_RSV_10_BIT__M                                    0xFFFF
#define    SCU_RAM_QAM_WR_RSV_10_BIT__PRE                                  0x0

#define  SCU_RAM_QAM_FSM_FMHUM_TO__A                                       0x831F83
#define  SCU_RAM_QAM_FSM_FMHUM_TO__W                                       16
#define  SCU_RAM_QAM_FSM_FMHUM_TO__M                                       0xFFFF
#define  SCU_RAM_QAM_FSM_FMHUM_TO__PRE                                     0x258

#define    SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B                                 0
#define    SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W                                 16
#define    SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M                                 0xFFFF
#define    SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE                               0x258
#define      SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO                      0x0

#define  SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A                                 0x831F84
#define  SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W                                 16
#define  SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M                                 0xFFFF
#define  SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE                               0x0

#define    SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B                           0
#define    SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W                           16
#define    SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M                           0xFFFF
#define    SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE                         0x0

#define  SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A                                0x831F85
#define  SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W                                16
#define  SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M                                0xFFFF
#define  SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE                              0x0

#define    SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B                          0
#define    SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W                          16
#define    SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M                          0xFFFF
#define    SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE                        0x0

#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A                                  0x831F86
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W                                  16
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M                                  0xFFFF
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE                                0x0

#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B                            0
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W                            16
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M                            0xFFFF
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE                          0x0

#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A                                  0x831F87
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W                                  16
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M                                  0xFFFF
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE                                0x0

#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B                            0
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W                            16
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M                            0xFFFF
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE                          0x0

#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A                                  0x831F88
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W                                  16
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M                                  0xFFFF
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE                                0x0

#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B                            0
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W                            16
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M                            0xFFFF
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE                          0x0

#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A                                  0x831F89
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W                                  16
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M                                  0xFFFF
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE                                0x0

#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B                            0
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W                            16
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M                            0xFFFF
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE                          0x0

#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A                                  0x831F8A
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W                                  16
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M                                  0xFFFF
#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE                                0x0

#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B                            0
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W                            16
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M                            0xFFFF
#define    SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE                          0x0

#define  SCU_RAM_QAM_FSM_STATE_TGT__A                                      0x831F8B
#define  SCU_RAM_QAM_FSM_STATE_TGT__W                                      4
#define  SCU_RAM_QAM_FSM_STATE_TGT__M                                      0xF
#define  SCU_RAM_QAM_FSM_STATE_TGT__PRE                                    0x0

#define    SCU_RAM_QAM_FSM_STATE_TGT_BIT__B                                0
#define    SCU_RAM_QAM_FSM_STATE_TGT_BIT__W                                4
#define    SCU_RAM_QAM_FSM_STATE_TGT_BIT__M                                0xF
#define    SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE                              0x0
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP                     0x0
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE                    0x1
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ                    0x2
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT                 0x3
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE                   0x4
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE                0x5
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING                        0x6
#define      SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST                  0x7

#define  SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A                                  0x831F8C
#define  SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W                                  9
#define  SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M                                  0x1FF
#define  SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE                                0x0

#define    SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B                        0
#define    SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W                        1
#define    SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M                        0x1
#define    SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE                      0x0

#define  SCU_RAM_QAM_FSM_ATH__A                                            0x831F8D
#define  SCU_RAM_QAM_FSM_ATH__W                                            16
#define  SCU_RAM_QAM_FSM_ATH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_ATH__PRE                                          0x0

#define    SCU_RAM_QAM_FSM_ATH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_ATH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_ATH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_ATH_BIT__PRE                                    0x0

#define  SCU_RAM_QAM_FSM_RTH__A                                            0x831F8E
#define  SCU_RAM_QAM_FSM_RTH__W                                            16
#define  SCU_RAM_QAM_FSM_RTH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_RTH__PRE                                          0x4B

#define    SCU_RAM_QAM_FSM_RTH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_RTH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_RTH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_RTH_BIT__PRE                                    0x4B
#define      SCU_RAM_QAM_FSM_RTH_BIT_QAM_16                                0x8C
#define      SCU_RAM_QAM_FSM_RTH_BIT_QAM_32                                0x50
#define      SCU_RAM_QAM_FSM_RTH_BIT_QAM_64                                0x4E
#define      SCU_RAM_QAM_FSM_RTH_BIT_QAM_128                               0x32
#define      SCU_RAM_QAM_FSM_RTH_BIT_QAM_256                               0x2D

#define  SCU_RAM_QAM_FSM_FTH__A                                            0x831F8F
#define  SCU_RAM_QAM_FSM_FTH__W                                            16
#define  SCU_RAM_QAM_FSM_FTH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_FTH__PRE                                          0x3C

#define    SCU_RAM_QAM_FSM_FTH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_FTH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_FTH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_FTH_BIT__PRE                                    0x3C
#define      SCU_RAM_QAM_FSM_FTH_BIT_QAM_16                                0x32
#define      SCU_RAM_QAM_FSM_FTH_BIT_QAM_32                                0x1E
#define      SCU_RAM_QAM_FSM_FTH_BIT_QAM_64                                0x1E
#define      SCU_RAM_QAM_FSM_FTH_BIT_QAM_128                               0x14
#define      SCU_RAM_QAM_FSM_FTH_BIT_QAM_256                               0x14

#define  SCU_RAM_QAM_FSM_PTH__A                                            0x831F90
#define  SCU_RAM_QAM_FSM_PTH__W                                            16
#define  SCU_RAM_QAM_FSM_PTH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_PTH__PRE                                          0x64

#define    SCU_RAM_QAM_FSM_PTH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_PTH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_PTH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_PTH_BIT__PRE                                    0x64
#define      SCU_RAM_QAM_FSM_PTH_BIT_QAM_16                                0xC8
#define      SCU_RAM_QAM_FSM_PTH_BIT_QAM_32                                0x96
#define      SCU_RAM_QAM_FSM_PTH_BIT_QAM_64                                0x8C
#define      SCU_RAM_QAM_FSM_PTH_BIT_QAM_128                               0x64
#define      SCU_RAM_QAM_FSM_PTH_BIT_QAM_256                               0x64

#define  SCU_RAM_QAM_FSM_MTH__A                                            0x831F91
#define  SCU_RAM_QAM_FSM_MTH__W                                            16
#define  SCU_RAM_QAM_FSM_MTH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_MTH__PRE                                          0x6E

#define    SCU_RAM_QAM_FSM_MTH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_MTH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_MTH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_MTH_BIT__PRE                                    0x6E
#define      SCU_RAM_QAM_FSM_MTH_BIT_QAM_16                                0x5A
#define      SCU_RAM_QAM_FSM_MTH_BIT_QAM_32                                0x50
#define      SCU_RAM_QAM_FSM_MTH_BIT_QAM_64                                0x46
#define      SCU_RAM_QAM_FSM_MTH_BIT_QAM_128                               0x3C
#define      SCU_RAM_QAM_FSM_MTH_BIT_QAM_256                               0x50

#define  SCU_RAM_QAM_FSM_CTH__A                                            0x831F92
#define  SCU_RAM_QAM_FSM_CTH__W                                            16
#define  SCU_RAM_QAM_FSM_CTH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_CTH__PRE                                          0x50

#define    SCU_RAM_QAM_FSM_CTH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_CTH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_CTH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_CTH_BIT__PRE                                    0x50
#define      SCU_RAM_QAM_FSM_CTH_BIT_QAM_16                                0xA0
#define      SCU_RAM_QAM_FSM_CTH_BIT_QAM_32                                0x8C
#define      SCU_RAM_QAM_FSM_CTH_BIT_QAM_64                                0x8C
#define      SCU_RAM_QAM_FSM_CTH_BIT_QAM_128                               0x8C
#define      SCU_RAM_QAM_FSM_CTH_BIT_QAM_256                               0x8C

#define  SCU_RAM_QAM_FSM_QTH__A                                            0x831F93
#define  SCU_RAM_QAM_FSM_QTH__W                                            16
#define  SCU_RAM_QAM_FSM_QTH__M                                            0xFFFF
#define  SCU_RAM_QAM_FSM_QTH__PRE                                          0x96

#define    SCU_RAM_QAM_FSM_QTH_BIT__B                                      0
#define    SCU_RAM_QAM_FSM_QTH_BIT__W                                      16
#define    SCU_RAM_QAM_FSM_QTH_BIT__M                                      0xFFFF
#define    SCU_RAM_QAM_FSM_QTH_BIT__PRE                                    0x96
#define      SCU_RAM_QAM_FSM_QTH_BIT_QAM_16                                0xE6
#define      SCU_RAM_QAM_FSM_QTH_BIT_QAM_32                                0xAA
#define      SCU_RAM_QAM_FSM_QTH_BIT_QAM_64                                0xC3
#define      SCU_RAM_QAM_FSM_QTH_BIT_QAM_128                               0x8C
#define      SCU_RAM_QAM_FSM_QTH_BIT_QAM_256                               0x96

#define  SCU_RAM_QAM_FSM_RATE_LIM__A                                       0x831F94
#define  SCU_RAM_QAM_FSM_RATE_LIM__W                                       16
#define  SCU_RAM_QAM_FSM_RATE_LIM__M                                       0xFFFF
#define  SCU_RAM_QAM_FSM_RATE_LIM__PRE                                     0x28

#define    SCU_RAM_QAM_FSM_RATE_LIM_BIT__B                                 0
#define    SCU_RAM_QAM_FSM_RATE_LIM_BIT__W                                 16
#define    SCU_RAM_QAM_FSM_RATE_LIM_BIT__M                                 0xFFFF
#define    SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE                               0x28
#define      SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16                           0x46
#define      SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32                           0x46
#define      SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64                           0x46
#define      SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128                          0x46
#define      SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256                          0x46

#define  SCU_RAM_QAM_FSM_FREQ_LIM__A                                       0x831F95
#define  SCU_RAM_QAM_FSM_FREQ_LIM__W                                       16
#define  SCU_RAM_QAM_FSM_FREQ_LIM__M                                       0xFFFF
#define  SCU_RAM_QAM_FSM_FREQ_LIM__PRE                                     0xF

#define    SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B                                 0
#define    SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W                                 16
#define    SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M                                 0xFFFF
#define    SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE                               0xF
#define      SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16                           0x1E
#define      SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32                           0x14
#define      SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64                           0x28
#define      SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128                          0x8
#define      SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256                          0x28

#define  SCU_RAM_QAM_FSM_COUNT_LIM__A                                      0x831F96
#define  SCU_RAM_QAM_FSM_COUNT_LIM__W                                      16
#define  SCU_RAM_QAM_FSM_COUNT_LIM__M                                      0xFFFF
#define  SCU_RAM_QAM_FSM_COUNT_LIM__PRE                                    0x4

#define    SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B                                0
#define    SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W                                16
#define    SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M                                0xFFFF
#define    SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE                              0x4
#define      SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16                          0x4
#define      SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32                          0x6
#define      SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64                          0x6
#define      SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128                         0x7
#define      SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256                         0x6

#define  SCU_RAM_QAM_LC_CA_COARSE__A                                       0x831F97
#define  SCU_RAM_QAM_LC_CA_COARSE__W                                       16
#define  SCU_RAM_QAM_LC_CA_COARSE__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CA_COARSE__PRE                                     0x28

#define    SCU_RAM_QAM_LC_CA_COARSE_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CA_COARSE_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CA_COARSE_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE                               0x28

#define  SCU_RAM_QAM_LC_CA_MEDIUM__A                                       0x831F98
#define  SCU_RAM_QAM_LC_CA_MEDIUM__W                                       16
#define  SCU_RAM_QAM_LC_CA_MEDIUM__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CA_MEDIUM__PRE                                     0x28

#define    SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE                               0x28

#define  SCU_RAM_QAM_LC_CA_FINE__A                                         0x831F99
#define  SCU_RAM_QAM_LC_CA_FINE__W                                         16
#define  SCU_RAM_QAM_LC_CA_FINE__M                                         0xFFFF
#define  SCU_RAM_QAM_LC_CA_FINE__PRE                                       0xF

#define    SCU_RAM_QAM_LC_CA_FINE_BIT__B                                   0
#define    SCU_RAM_QAM_LC_CA_FINE_BIT__W                                   8
#define    SCU_RAM_QAM_LC_CA_FINE_BIT__M                                   0xFF
#define    SCU_RAM_QAM_LC_CA_FINE_BIT__PRE                                 0xF

#define  SCU_RAM_QAM_LC_CP_COARSE__A                                       0x831F9A
#define  SCU_RAM_QAM_LC_CP_COARSE__W                                       16
#define  SCU_RAM_QAM_LC_CP_COARSE__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CP_COARSE__PRE                                     0x64

#define    SCU_RAM_QAM_LC_CP_COARSE_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CP_COARSE_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CP_COARSE_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE                               0x64

#define  SCU_RAM_QAM_LC_CP_MEDIUM__A                                       0x831F9B
#define  SCU_RAM_QAM_LC_CP_MEDIUM__W                                       16
#define  SCU_RAM_QAM_LC_CP_MEDIUM__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CP_MEDIUM__PRE                                     0x1E

#define    SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE                               0x1E

#define  SCU_RAM_QAM_LC_CP_FINE__A                                         0x831F9C
#define  SCU_RAM_QAM_LC_CP_FINE__W                                         16
#define  SCU_RAM_QAM_LC_CP_FINE__M                                         0xFFFF
#define  SCU_RAM_QAM_LC_CP_FINE__PRE                                       0x5

#define    SCU_RAM_QAM_LC_CP_FINE_BIT__B                                   0
#define    SCU_RAM_QAM_LC_CP_FINE_BIT__W                                   8
#define    SCU_RAM_QAM_LC_CP_FINE_BIT__M                                   0xFF
#define    SCU_RAM_QAM_LC_CP_FINE_BIT__PRE                                 0x5

#define  SCU_RAM_QAM_LC_CI_COARSE__A                                       0x831F9D
#define  SCU_RAM_QAM_LC_CI_COARSE__W                                       16
#define  SCU_RAM_QAM_LC_CI_COARSE__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CI_COARSE__PRE                                     0x32

#define    SCU_RAM_QAM_LC_CI_COARSE_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CI_COARSE_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CI_COARSE_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE                               0x32

#define  SCU_RAM_QAM_LC_CI_MEDIUM__A                                       0x831F9E
#define  SCU_RAM_QAM_LC_CI_MEDIUM__W                                       16
#define  SCU_RAM_QAM_LC_CI_MEDIUM__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CI_MEDIUM__PRE                                     0x1E

#define    SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE                               0x1E

#define  SCU_RAM_QAM_LC_CI_FINE__A                                         0x831F9F
#define  SCU_RAM_QAM_LC_CI_FINE__W                                         16
#define  SCU_RAM_QAM_LC_CI_FINE__M                                         0xFFFF
#define  SCU_RAM_QAM_LC_CI_FINE__PRE                                       0x5

#define    SCU_RAM_QAM_LC_CI_FINE_BIT__B                                   0
#define    SCU_RAM_QAM_LC_CI_FINE_BIT__W                                   8
#define    SCU_RAM_QAM_LC_CI_FINE_BIT__M                                   0xFF
#define    SCU_RAM_QAM_LC_CI_FINE_BIT__PRE                                 0x5

#define  SCU_RAM_QAM_LC_EP_COARSE__A                                       0x831FA0
#define  SCU_RAM_QAM_LC_EP_COARSE__W                                       16
#define  SCU_RAM_QAM_LC_EP_COARSE__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_EP_COARSE__PRE                                     0x18

#define    SCU_RAM_QAM_LC_EP_COARSE_BIT__B                                 0
#define    SCU_RAM_QAM_LC_EP_COARSE_BIT__W                                 8
#define    SCU_RAM_QAM_LC_EP_COARSE_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE                               0x18

#define  SCU_RAM_QAM_LC_EP_MEDIUM__A                                       0x831FA1
#define  SCU_RAM_QAM_LC_EP_MEDIUM__W                                       16
#define  SCU_RAM_QAM_LC_EP_MEDIUM__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_EP_MEDIUM__PRE                                     0x18

#define    SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B                                 0
#define    SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W                                 8
#define    SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE                               0x18

#define  SCU_RAM_QAM_LC_EP_FINE__A                                         0x831FA2
#define  SCU_RAM_QAM_LC_EP_FINE__W                                         16
#define  SCU_RAM_QAM_LC_EP_FINE__M                                         0xFFFF
#define  SCU_RAM_QAM_LC_EP_FINE__PRE                                       0xC

#define    SCU_RAM_QAM_LC_EP_FINE_BIT__B                                   0
#define    SCU_RAM_QAM_LC_EP_FINE_BIT__W                                   8
#define    SCU_RAM_QAM_LC_EP_FINE_BIT__M                                   0xFF
#define    SCU_RAM_QAM_LC_EP_FINE_BIT__PRE                                 0xC

#define  SCU_RAM_QAM_LC_EI_COARSE__A                                       0x831FA3
#define  SCU_RAM_QAM_LC_EI_COARSE__W                                       16
#define  SCU_RAM_QAM_LC_EI_COARSE__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_EI_COARSE__PRE                                     0x10

#define    SCU_RAM_QAM_LC_EI_COARSE_BIT__B                                 0
#define    SCU_RAM_QAM_LC_EI_COARSE_BIT__W                                 8
#define    SCU_RAM_QAM_LC_EI_COARSE_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE                               0x10

#define  SCU_RAM_QAM_LC_EI_MEDIUM__A                                       0x831FA4
#define  SCU_RAM_QAM_LC_EI_MEDIUM__W                                       16
#define  SCU_RAM_QAM_LC_EI_MEDIUM__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_EI_MEDIUM__PRE                                     0x10

#define    SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B                                 0
#define    SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W                                 8
#define    SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE                               0x10

#define  SCU_RAM_QAM_LC_EI_FINE__A                                         0x831FA5
#define  SCU_RAM_QAM_LC_EI_FINE__W                                         16
#define  SCU_RAM_QAM_LC_EI_FINE__M                                         0xFFFF
#define  SCU_RAM_QAM_LC_EI_FINE__PRE                                       0xC

#define    SCU_RAM_QAM_LC_EI_FINE_BIT__B                                   0
#define    SCU_RAM_QAM_LC_EI_FINE_BIT__W                                   8
#define    SCU_RAM_QAM_LC_EI_FINE_BIT__M                                   0xFF
#define    SCU_RAM_QAM_LC_EI_FINE_BIT__PRE                                 0xC

#define  SCU_RAM_QAM_LC_CF_COARSE__A                                       0x831FA6
#define  SCU_RAM_QAM_LC_CF_COARSE__W                                       16
#define  SCU_RAM_QAM_LC_CF_COARSE__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CF_COARSE__PRE                                     0x30

#define    SCU_RAM_QAM_LC_CF_COARSE_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CF_COARSE_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CF_COARSE_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE                               0x30

#define  SCU_RAM_QAM_LC_CF_MEDIUM__A                                       0x831FA7
#define  SCU_RAM_QAM_LC_CF_MEDIUM__W                                       16
#define  SCU_RAM_QAM_LC_CF_MEDIUM__M                                       0xFFFF
#define  SCU_RAM_QAM_LC_CF_MEDIUM__PRE                                     0x19

#define    SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B                                 0
#define    SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W                                 8
#define    SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M                                 0xFF
#define    SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE                               0x19

#define  SCU_RAM_QAM_LC_CF_FINE__A                                         0x831FA8
#define  SCU_RAM_QAM_LC_CF_FINE__W                                         16
#define  SCU_RAM_QAM_LC_CF_FINE__M                                         0xFFFF
#define  SCU_RAM_QAM_LC_CF_FINE__PRE                                       0x10

#define    SCU_RAM_QAM_LC_CF_FINE_BIT__B                                   0
#define    SCU_RAM_QAM_LC_CF_FINE_BIT__W                                   8
#define    SCU_RAM_QAM_LC_CF_FINE_BIT__M                                   0xFF
#define    SCU_RAM_QAM_LC_CF_FINE_BIT__PRE                                 0x10

#define  SCU_RAM_QAM_LC_CF1_COARSE__A                                      0x831FA9
#define  SCU_RAM_QAM_LC_CF1_COARSE__W                                      16
#define  SCU_RAM_QAM_LC_CF1_COARSE__M                                      0xFFFF
#define  SCU_RAM_QAM_LC_CF1_COARSE__PRE                                    0xA

#define    SCU_RAM_QAM_LC_CF1_COARSE_BIT__B                                0
#define    SCU_RAM_QAM_LC_CF1_COARSE_BIT__W                                8
#define    SCU_RAM_QAM_LC_CF1_COARSE_BIT__M                                0xFF
#define    SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE                              0xA

#define  SCU_RAM_QAM_LC_CF1_MEDIUM__A                                      0x831FAA
#define  SCU_RAM_QAM_LC_CF1_MEDIUM__W                                      16
#define  SCU_RAM_QAM_LC_CF1_MEDIUM__M                                      0xFFFF
#define  SCU_RAM_QAM_LC_CF1_MEDIUM__PRE                                    0xA

#define    SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B                                0
#define    SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W                                8
#define    SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M                                0xFF
#define    SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE                              0xA

#define  SCU_RAM_QAM_LC_CF1_FINE__A                                        0x831FAB
#define  SCU_RAM_QAM_LC_CF1_FINE__W                                        16
#define  SCU_RAM_QAM_LC_CF1_FINE__M                                        0xFFFF
#define  SCU_RAM_QAM_LC_CF1_FINE__PRE                                      0x5

#define    SCU_RAM_QAM_LC_CF1_FINE_BIT__B                                  0
#define    SCU_RAM_QAM_LC_CF1_FINE_BIT__W                                  8
#define    SCU_RAM_QAM_LC_CF1_FINE_BIT__M                                  0xFF
#define    SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE                                0x5

#define  SCU_RAM_QAM_SL_SIG_POWER__A                                       0x831FAC
#define  SCU_RAM_QAM_SL_SIG_POWER__W                                       16
#define  SCU_RAM_QAM_SL_SIG_POWER__M                                       0xFFFF
#define  SCU_RAM_QAM_SL_SIG_POWER__PRE                                     0xAA00

#define    SCU_RAM_QAM_SL_SIG_POWER_BIT__B                                 0
#define    SCU_RAM_QAM_SL_SIG_POWER_BIT__W                                 16
#define    SCU_RAM_QAM_SL_SIG_POWER_BIT__M                                 0xFFFF
#define    SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE                               0xAA00

#define  SCU_RAM_QAM_EQ_CMA_RAD0__A                                        0x831FAD
#define  SCU_RAM_QAM_EQ_CMA_RAD0__W                                        14
#define  SCU_RAM_QAM_EQ_CMA_RAD0__M                                        0x3FFF
#define  SCU_RAM_QAM_EQ_CMA_RAD0__PRE                                      0x3418

#define    SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B                                  0
#define    SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W                                  14
#define    SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M                                  0x3FFF
#define    SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE                                0x3418
#define      SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16                            0x34CD
#define      SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32                            0x1A33
#define      SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64                            0x3418
#define      SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128                           0x1814
#define      SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256                           0x2CEE

#define  SCU_RAM_QAM_EQ_CMA_RAD1__A                                        0x831FAE
#define  SCU_RAM_QAM_EQ_CMA_RAD1__W                                        14
#define  SCU_RAM_QAM_EQ_CMA_RAD1__M                                        0x3FFF
#define  SCU_RAM_QAM_EQ_CMA_RAD1__PRE                                      0x314A

#define    SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B                                  0
#define    SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W                                  14
#define    SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M                                  0x3FFF
#define    SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE                                0x314A
#define      SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16                            0x34CD
#define      SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32                            0x1A33
#define      SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64                            0x314A
#define      SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128                           0x19C6
#define      SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256                           0x2F34

#define  SCU_RAM_QAM_EQ_CMA_RAD2__A                                        0x831FAF
#define  SCU_RAM_QAM_EQ_CMA_RAD2__W                                        14
#define  SCU_RAM_QAM_EQ_CMA_RAD2__M                                        0x3FFF
#define  SCU_RAM_QAM_EQ_CMA_RAD2__PRE                                      0x2ED4

#define    SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B                                  0
#define    SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W                                  14
#define    SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M                                  0x3FFF
#define    SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE                                0x2ED4
#define      SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16                            0x34CD
#define      SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32                            0x1A33
#define      SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64                            0x2ED4
#define      SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128                           0x18FA
#define      SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256                           0x30FF

#define  SCU_RAM_QAM_EQ_CMA_RAD3__A                                        0x831FB0
#define  SCU_RAM_QAM_EQ_CMA_RAD3__W                                        14
#define  SCU_RAM_QAM_EQ_CMA_RAD3__M                                        0x3FFF
#define  SCU_RAM_QAM_EQ_CMA_RAD3__PRE                                      0x35F1

#define    SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B                                  0
#define    SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W                                  14
#define    SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M                                  0x3FFF
#define    SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE                                0x35F1
#define      SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16                            0x34CD
#define      SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32                            0x1A33
#define      SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64                            0x35F1
#define      SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128                           0x1909
#define      SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256                           0x3283

#define  SCU_RAM_QAM_EQ_CMA_RAD4__A                                        0x831FB1
#define  SCU_RAM_QAM_EQ_CMA_RAD4__W                                        14
#define  SCU_RAM_QAM_EQ_CMA_RAD4__M                                        0x3FFF
#define  SCU_RAM_QAM_EQ_CMA_RAD4__PRE                                      0x35F1

#define    SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B                                  0
#define    SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W                                  14
#define    SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M                                  0x3FFF
#define    SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE                                0x35F1
#define      SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16                            0x34CD
#define      SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32                            0x1A33
#define      SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64                            0x35F1
#define      SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128                           0x1A00
#define      SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256                           0x353D

#define  SCU_RAM_QAM_EQ_CMA_RAD5__A                                        0x831FB2
#define  SCU_RAM_QAM_EQ_CMA_RAD5__W                                        14
#define  SCU_RAM_QAM_EQ_CMA_RAD5__M                                        0x3FFF
#define  SCU_RAM_QAM_EQ_CMA_RAD5__PRE                                      0x3CF9

#define    SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B                                  0
#define    SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W                                  14
#define    SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M                                  0x3FFF
#define    SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE                                0x3CF9
#define      SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16                            0x34CD
#define      SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32                            0x1A33
#define      SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64                            0x3CF9
#define      SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128                           0x1C46
#define      SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256                           0x3C19

#define  SCU_RAM_QAM_CTL_ENA__A                                            0x831FB3
#define  SCU_RAM_QAM_CTL_ENA__W                                            16
#define  SCU_RAM_QAM_CTL_ENA__M                                            0xFFFF
#define  SCU_RAM_QAM_CTL_ENA__PRE                                          0x7FF

#define    SCU_RAM_QAM_CTL_ENA_AMP__B                                      0
#define    SCU_RAM_QAM_CTL_ENA_AMP__W                                      1
#define    SCU_RAM_QAM_CTL_ENA_AMP__M                                      0x1
#define    SCU_RAM_QAM_CTL_ENA_AMP__PRE                                    0x1

#define    SCU_RAM_QAM_CTL_ENA_ACQ__B                                      1
#define    SCU_RAM_QAM_CTL_ENA_ACQ__W                                      1
#define    SCU_RAM_QAM_CTL_ENA_ACQ__M                                      0x2
#define    SCU_RAM_QAM_CTL_ENA_ACQ__PRE                                    0x2

#define    SCU_RAM_QAM_CTL_ENA_EQU__B                                      2
#define    SCU_RAM_QAM_CTL_ENA_EQU__W                                      1
#define    SCU_RAM_QAM_CTL_ENA_EQU__M                                      0x4
#define    SCU_RAM_QAM_CTL_ENA_EQU__PRE                                    0x4

#define    SCU_RAM_QAM_CTL_ENA_SLC__B                                      3
#define    SCU_RAM_QAM_CTL_ENA_SLC__W                                      1
#define    SCU_RAM_QAM_CTL_ENA_SLC__M                                      0x8
#define    SCU_RAM_QAM_CTL_ENA_SLC__PRE                                    0x8

#define    SCU_RAM_QAM_CTL_ENA_LC__B                                       4
#define    SCU_RAM_QAM_CTL_ENA_LC__W                                       1
#define    SCU_RAM_QAM_CTL_ENA_LC__M                                       0x10
#define    SCU_RAM_QAM_CTL_ENA_LC__PRE                                     0x10

#define    SCU_RAM_QAM_CTL_ENA_AGC__B                                      5
#define    SCU_RAM_QAM_CTL_ENA_AGC__W                                      1
#define    SCU_RAM_QAM_CTL_ENA_AGC__M                                      0x20
#define    SCU_RAM_QAM_CTL_ENA_AGC__PRE                                    0x20

#define    SCU_RAM_QAM_CTL_ENA_FEC__B                                      6
#define    SCU_RAM_QAM_CTL_ENA_FEC__W                                      1
#define    SCU_RAM_QAM_CTL_ENA_FEC__M                                      0x40
#define    SCU_RAM_QAM_CTL_ENA_FEC__PRE                                    0x40

#define    SCU_RAM_QAM_CTL_ENA_AXIS__B                                     7
#define    SCU_RAM_QAM_CTL_ENA_AXIS__W                                     1
#define    SCU_RAM_QAM_CTL_ENA_AXIS__M                                     0x80
#define    SCU_RAM_QAM_CTL_ENA_AXIS__PRE                                   0x80

#define    SCU_RAM_QAM_CTL_ENA_FMHUM__B                                    8
#define    SCU_RAM_QAM_CTL_ENA_FMHUM__W                                    1
#define    SCU_RAM_QAM_CTL_ENA_FMHUM__M                                    0x100
#define    SCU_RAM_QAM_CTL_ENA_FMHUM__PRE                                  0x100

#define    SCU_RAM_QAM_CTL_ENA_EQTIME__B                                   9
#define    SCU_RAM_QAM_CTL_ENA_EQTIME__W                                   1
#define    SCU_RAM_QAM_CTL_ENA_EQTIME__M                                   0x200
#define    SCU_RAM_QAM_CTL_ENA_EQTIME__PRE                                 0x200

#define    SCU_RAM_QAM_CTL_ENA_EXTLCK__B                                   10
#define    SCU_RAM_QAM_CTL_ENA_EXTLCK__W                                   1
#define    SCU_RAM_QAM_CTL_ENA_EXTLCK__M                                   0x400
#define    SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE                                 0x400

#define  SCU_RAM_QAM_WR_RSV_1__A                                           0x831FB4
#define  SCU_RAM_QAM_WR_RSV_1__W                                           16
#define  SCU_RAM_QAM_WR_RSV_1__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_1__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_1_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_1_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_1_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_1_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_2__A                                           0x831FB5
#define  SCU_RAM_QAM_WR_RSV_2__W                                           16
#define  SCU_RAM_QAM_WR_RSV_2__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_2__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_2_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_2_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_2_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_2_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_WR_RSV_3__A                                           0x831FB6
#define  SCU_RAM_QAM_WR_RSV_3__W                                           16
#define  SCU_RAM_QAM_WR_RSV_3__M                                           0xFFFF
#define  SCU_RAM_QAM_WR_RSV_3__PRE                                         0x0

#define    SCU_RAM_QAM_WR_RSV_3_BIT__B                                     0
#define    SCU_RAM_QAM_WR_RSV_3_BIT__W                                     16
#define    SCU_RAM_QAM_WR_RSV_3_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_WR_RSV_3_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_ACTIVE_CONSTELLATION__A                               0x831FB7
#define  SCU_RAM_QAM_ACTIVE_CONSTELLATION__W                               3
#define  SCU_RAM_QAM_ACTIVE_CONSTELLATION__M                               0x7
#define  SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE                             0x0

#define    SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B                         0
#define    SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W                         3
#define    SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M                         0x7
#define    SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE                       0x0
#define      SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN                  0x0
#define      SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16                   0x3
#define      SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32                   0x4
#define      SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64                   0x5
#define      SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128                  0x6
#define      SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256                  0x7

#define  SCU_RAM_QAM_ACTIVE_INTERLEAVE__A                                  0x831FB8
#define  SCU_RAM_QAM_ACTIVE_INTERLEAVE__W                                  8
#define  SCU_RAM_QAM_ACTIVE_INTERLEAVE__M                                  0xFF
#define  SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE                                0x1

#define    SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B                            0
#define    SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W                            8
#define    SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M                            0xFF
#define    SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE                          0x1
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1                     0x0
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2                  0x1
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2                     0x2
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2                      0x3
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3                     0x4
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4                      0x5
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4                     0x6
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8                      0x7
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5                     0x8
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16                      0x9
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6                     0xA
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7                     0xC
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8                     0xE
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17                     0x10
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4                       0x11
#define      SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN                     0xFE

#define  SCU_RAM_QAM_RD_RSV_4__A                                           0x831FB9
#define  SCU_RAM_QAM_RD_RSV_4__W                                           16
#define  SCU_RAM_QAM_RD_RSV_4__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_4__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_4_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_4_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_4_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_4_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_LOCKED__A                                             0x831FBA
#define  SCU_RAM_QAM_LOCKED__W                                             16
#define  SCU_RAM_QAM_LOCKED__M                                             0xFFFF
#define  SCU_RAM_QAM_LOCKED__PRE                                           0x0

#define    SCU_RAM_QAM_LOCKED_INTLEVEL__B                                  0
#define    SCU_RAM_QAM_LOCKED_INTLEVEL__W                                  8
#define    SCU_RAM_QAM_LOCKED_INTLEVEL__M                                  0xFF
#define    SCU_RAM_QAM_LOCKED_INTLEVEL__PRE                                0x0
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED                        0x0
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK                            0x1
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK                           0x2
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK                           0x3
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK                        0x4
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK                        0x5
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK                          0x6
#define      SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK                       0x7

#define    SCU_RAM_QAM_LOCKED_LOCKED__B                                    8
#define    SCU_RAM_QAM_LOCKED_LOCKED__W                                    8
#define    SCU_RAM_QAM_LOCKED_LOCKED__M                                    0xFF00
#define    SCU_RAM_QAM_LOCKED_LOCKED__PRE                                  0x0
#define      SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED                          0x0
#define      SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED                        0x4000
#define      SCU_RAM_QAM_LOCKED_LOCKED_LOCKED                              0x8000
#define      SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK                          0xC000

#define  SCU_RAM_QAM_EVENTS_OCC_HI__A                                      0x831FBB
#define  SCU_RAM_QAM_EVENTS_OCC_HI__W                                      16
#define  SCU_RAM_QAM_EVENTS_OCC_HI__M                                      0xFFFF
#define  SCU_RAM_QAM_EVENTS_OCC_HI__PRE                                    0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B                             0
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W                             1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M                             0x1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE                           0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B                        1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W                        1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M                        0x2
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE                      0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B                               2
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W                               1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M                               0x4
#define    SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE                             0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B                         3
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W                         1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M                         0x8
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE                       0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B                        4
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W                        1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M                        0x10
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE                      0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B                            5
#define    SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W                            1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M                            0x20
#define    SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE                          0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B                          6
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W                          1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M                          0x40
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE                        0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B                         7
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W                         1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M                         0x80
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE                       0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B                            8
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W                            1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M                            0x100
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE                          0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B                          9
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W                          1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M                          0x200
#define    SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE                        0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B                            10
#define    SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W                            1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M                            0x400
#define    SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE                          0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B                            11
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W                            1
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M                            0x800
#define    SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE                          0x0

#define    SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B                                12
#define    SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W                                4
#define    SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M                                0xF000
#define    SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE                              0x0

#define  SCU_RAM_QAM_EVENTS_OCC_LO__A                                      0x831FBC
#define  SCU_RAM_QAM_EVENTS_OCC_LO__W                                      16
#define  SCU_RAM_QAM_EVENTS_OCC_LO__M                                      0xFFFF
#define  SCU_RAM_QAM_EVENTS_OCC_LO__PRE                                    0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B                              0
#define    SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W                              1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M                              0x1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE                            0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B                               1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W                               1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M                               0x2
#define    SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE                             0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B                              2
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W                              1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M                              0x4
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE                            0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B                              3
#define    SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W                              1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M                              0x8
#define    SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE                            0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B                             4
#define    SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W                             1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M                             0x10
#define    SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE                           0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_MER__B                                5
#define    SCU_RAM_QAM_EVENTS_OCC_LO_MER__W                                1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_MER__M                                0x20
#define    SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE                              0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B                               6
#define    SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W                               1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M                               0x40
#define    SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE                             0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B                           7
#define    SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W                           1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M                           0x80
#define    SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE                         0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_SER__B                                8
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SER__W                                1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SER__M                                0x100
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE                              0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B                         9
#define    SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W                         1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M                         0x200
#define    SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE                       0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B                         10
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W                         1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M                         0x400
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE                       0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B                        11
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W                        1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M                        0x800
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE                      0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B                        12
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W                        1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M                        0x1000
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE                      0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B                           13
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W                           1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M                           0x2000
#define    SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE                         0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B                         14
#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W                         1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M                         0x4000
#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE                       0x0

#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B                        15
#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W                        1
#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M                        0x8000
#define    SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE                      0x0

#define  SCU_RAM_QAM_EVENTS_SCHED_HI__A                                    0x831FBD
#define  SCU_RAM_QAM_EVENTS_SCHED_HI__W                                    16
#define  SCU_RAM_QAM_EVENTS_SCHED_HI__M                                    0xFFFF
#define  SCU_RAM_QAM_EVENTS_SCHED_HI__PRE                                  0x0

#define    SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B                              0
#define    SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W                              16
#define    SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M                              0xFFFF
#define    SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE                            0x0

#define  SCU_RAM_QAM_EVENTS_SCHED_LO__A                                    0x831FBE
#define  SCU_RAM_QAM_EVENTS_SCHED_LO__W                                    16
#define  SCU_RAM_QAM_EVENTS_SCHED_LO__M                                    0xFFFF
#define  SCU_RAM_QAM_EVENTS_SCHED_LO__PRE                                  0x0

#define    SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B                              0
#define    SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W                              16
#define    SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M                              0xFFFF
#define    SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE                            0x0

#define  SCU_RAM_QAM_TASKLETS_SCHED__A                                     0x831FBF
#define  SCU_RAM_QAM_TASKLETS_SCHED__W                                     16
#define  SCU_RAM_QAM_TASKLETS_SCHED__M                                     0xFFFF
#define  SCU_RAM_QAM_TASKLETS_SCHED__PRE                                   0x0

#define    SCU_RAM_QAM_TASKLETS_SCHED_BIT__B                               0
#define    SCU_RAM_QAM_TASKLETS_SCHED_BIT__W                               16
#define    SCU_RAM_QAM_TASKLETS_SCHED_BIT__M                               0xFFFF
#define    SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE                             0x0

#define  SCU_RAM_QAM_TASKLETS_RUN__A                                       0x831FC0
#define  SCU_RAM_QAM_TASKLETS_RUN__W                                       16
#define  SCU_RAM_QAM_TASKLETS_RUN__M                                       0xFFFF
#define  SCU_RAM_QAM_TASKLETS_RUN__PRE                                     0x0

#define    SCU_RAM_QAM_TASKLETS_RUN_BIT__B                                 0
#define    SCU_RAM_QAM_TASKLETS_RUN_BIT__W                                 16
#define    SCU_RAM_QAM_TASKLETS_RUN_BIT__M                                 0xFFFF
#define    SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE                               0x0

#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A                               0x831FC1
#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W                               16
#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M                               0xFFFF
#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE                             0x0

#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B                         0
#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W                         16
#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M                         0xFFFF
#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE                       0x0

#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A                               0x831FC2
#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W                               16
#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M                               0xFFFF
#define  SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE                             0x0

#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B                         0
#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W                         16
#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M                         0xFFFF
#define    SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE                       0x0

#define  SCU_RAM_QAM_RD_RSV_5__A                                           0x831FC3
#define  SCU_RAM_QAM_RD_RSV_5__W                                           16
#define  SCU_RAM_QAM_RD_RSV_5__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_5__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_5_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_5_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_5_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_5_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_6__A                                           0x831FC4
#define  SCU_RAM_QAM_RD_RSV_6__W                                           16
#define  SCU_RAM_QAM_RD_RSV_6__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_6__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_6_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_6_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_6_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_6_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_7__A                                           0x831FC5
#define  SCU_RAM_QAM_RD_RSV_7__W                                           16
#define  SCU_RAM_QAM_RD_RSV_7__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_7__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_7_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_7_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_7_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_7_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_8__A                                           0x831FC6
#define  SCU_RAM_QAM_RD_RSV_8__W                                           16
#define  SCU_RAM_QAM_RD_RSV_8__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_8__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_8_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_8_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_8_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_8_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_9__A                                           0x831FC7
#define  SCU_RAM_QAM_RD_RSV_9__W                                           16
#define  SCU_RAM_QAM_RD_RSV_9__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_9__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_9_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_9_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_9_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_9_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_10__A                                          0x831FC8
#define  SCU_RAM_QAM_RD_RSV_10__W                                          16
#define  SCU_RAM_QAM_RD_RSV_10__M                                          0xFFFF
#define  SCU_RAM_QAM_RD_RSV_10__PRE                                        0x0

#define    SCU_RAM_QAM_RD_RSV_10_BIT__B                                    0
#define    SCU_RAM_QAM_RD_RSV_10_BIT__W                                    16
#define    SCU_RAM_QAM_RD_RSV_10_BIT__M                                    0xFFFF
#define    SCU_RAM_QAM_RD_RSV_10_BIT__PRE                                  0x0

#define  SCU_RAM_QAM_AGC_TPOW_OFFS__A                                      0x831FC9
#define  SCU_RAM_QAM_AGC_TPOW_OFFS__W                                      16
#define  SCU_RAM_QAM_AGC_TPOW_OFFS__M                                      0xFFFF
#define  SCU_RAM_QAM_AGC_TPOW_OFFS__PRE                                    0x0

#define    SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B                                0
#define    SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W                                16
#define    SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M                                0xFFFF
#define    SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE                              0x0

#define  SCU_RAM_QAM_FSM_STATE__A                                          0x831FCA
#define  SCU_RAM_QAM_FSM_STATE__W                                          4
#define  SCU_RAM_QAM_FSM_STATE__M                                          0xF
#define  SCU_RAM_QAM_FSM_STATE__PRE                                        0x0

#define    SCU_RAM_QAM_FSM_STATE_BIT__B                                    0
#define    SCU_RAM_QAM_FSM_STATE_BIT__W                                    4
#define    SCU_RAM_QAM_FSM_STATE_BIT__M                                    0xF
#define    SCU_RAM_QAM_FSM_STATE_BIT__PRE                                  0x0
#define      SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP                         0x0
#define      SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE                        0x1
#define      SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ                        0x2
#define      SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT                     0x3
#define      SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE                       0x4
#define      SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE                    0x5
#define      SCU_RAM_QAM_FSM_STATE_BIT_TRACKING                            0x6
#define      SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST                      0x7

#define  SCU_RAM_QAM_FSM_STATE_NEW__A                                      0x831FCB
#define  SCU_RAM_QAM_FSM_STATE_NEW__W                                      4
#define  SCU_RAM_QAM_FSM_STATE_NEW__M                                      0xF
#define  SCU_RAM_QAM_FSM_STATE_NEW__PRE                                    0x0

#define    SCU_RAM_QAM_FSM_STATE_NEW_BIT__B                                0
#define    SCU_RAM_QAM_FSM_STATE_NEW_BIT__W                                4
#define    SCU_RAM_QAM_FSM_STATE_NEW_BIT__M                                0xF
#define    SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE                              0x0
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP                     0x0
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE                    0x1
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ                    0x2
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT                 0x3
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE                   0x4
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE                0x5
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING                        0x6
#define      SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST                  0x7

#define  SCU_RAM_QAM_FSM_LOCK_FLAGS__A                                     0x831FCC
#define  SCU_RAM_QAM_FSM_LOCK_FLAGS__W                                     13
#define  SCU_RAM_QAM_FSM_LOCK_FLAGS__M                                     0x1FFF
#define  SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE                                   0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B                           0
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W                           1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M                           0x1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE                         0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B                       1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W                       1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M                       0x2
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE                     0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B                        2
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W                        1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M                        0x4
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE                      0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B                          3
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W                          1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M                          0x8
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE                        0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B                       4
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W                       1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M                       0x10
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE                     0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B                        5
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W                        1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M                        0x20
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE                      0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B                       6
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W                       1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M                       0x40
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE                     0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B                         7
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W                         1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M                         0x80
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE                       0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B                        8
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W                        1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M                        0x100
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE                      0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B                           9
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W                           1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M                           0x200
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE                         0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B                         10
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W                         1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M                         0x400
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE                       0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B                           11
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W                           1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M                           0x800
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE                         0x0

#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B                       12
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W                       1
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M                       0x1000
#define    SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE                     0x0

#define  SCU_RAM_QAM_FSM_RATE_VARIATION__A                                 0x831FCD
#define  SCU_RAM_QAM_FSM_RATE_VARIATION__W                                 16
#define  SCU_RAM_QAM_FSM_RATE_VARIATION__M                                 0xFFFF
#define  SCU_RAM_QAM_FSM_RATE_VARIATION__PRE                               0x46

#define    SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B                           0
#define    SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W                           16
#define    SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M                           0xFFFF
#define    SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE                         0x46

#define  SCU_RAM_QAM_FSM_FREQ_VARIATION__A                                 0x831FCE
#define  SCU_RAM_QAM_FSM_FREQ_VARIATION__W                                 16
#define  SCU_RAM_QAM_FSM_FREQ_VARIATION__M                                 0xFFFF
#define  SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE                               0x1E

#define    SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B                           0
#define    SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W                           16
#define    SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M                           0xFFFF
#define    SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE                         0x1E

#define  SCU_RAM_QAM_ERR_STATE__A                                          0x831FCF
#define  SCU_RAM_QAM_ERR_STATE__W                                          4
#define  SCU_RAM_QAM_ERR_STATE__M                                          0xF
#define  SCU_RAM_QAM_ERR_STATE__PRE                                        0x0

#define    SCU_RAM_QAM_ERR_STATE_BIT__B                                    0
#define    SCU_RAM_QAM_ERR_STATE_BIT__W                                    4
#define    SCU_RAM_QAM_ERR_STATE_BIT__M                                    0xF
#define    SCU_RAM_QAM_ERR_STATE_BIT__PRE                                  0x0
#define      SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP                         0x0
#define      SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE                        0x1
#define      SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ                        0x2
#define      SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT                     0x3
#define      SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE                       0x4
#define      SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE                    0x5
#define      SCU_RAM_QAM_ERR_STATE_BIT_TRACKING                            0x6
#define      SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST                      0x7

#define  SCU_RAM_QAM_ERR_LOCK_FLAGS__A                                     0x831FD0
#define  SCU_RAM_QAM_ERR_LOCK_FLAGS__W                                     9
#define  SCU_RAM_QAM_ERR_LOCK_FLAGS__M                                     0x1FF
#define  SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE                                   0x0

#define    SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B                           0
#define    SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W                           1
#define    SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M                           0x1
#define    SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE                         0x0

#define  SCU_RAM_QAM_EQ_LOCK__A                                            0x831FD1
#define  SCU_RAM_QAM_EQ_LOCK__W                                            1
#define  SCU_RAM_QAM_EQ_LOCK__M                                            0x1
#define  SCU_RAM_QAM_EQ_LOCK__PRE                                          0x0

#define    SCU_RAM_QAM_EQ_LOCK_BIT__B                                      0
#define    SCU_RAM_QAM_EQ_LOCK_BIT__W                                      1
#define    SCU_RAM_QAM_EQ_LOCK_BIT__M                                      0x1
#define    SCU_RAM_QAM_EQ_LOCK_BIT__PRE                                    0x0

#define  SCU_RAM_QAM_EQ_STATE__A                                           0x831FD2
#define  SCU_RAM_QAM_EQ_STATE__W                                           16
#define  SCU_RAM_QAM_EQ_STATE__M                                           0xFFFF
#define  SCU_RAM_QAM_EQ_STATE__PRE                                         0x0

#define    SCU_RAM_QAM_EQ_STATE_BIT__B                                     0
#define    SCU_RAM_QAM_EQ_STATE_BIT__W                                     16
#define    SCU_RAM_QAM_EQ_STATE_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_EQ_STATE_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_0__A                                           0x831FD3
#define  SCU_RAM_QAM_RD_RSV_0__W                                           16
#define  SCU_RAM_QAM_RD_RSV_0__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_0__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_0_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_0_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_0_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_0_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_1__A                                           0x831FD4
#define  SCU_RAM_QAM_RD_RSV_1__W                                           16
#define  SCU_RAM_QAM_RD_RSV_1__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_1__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_1_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_1_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_1_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_1_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_2__A                                           0x831FD5
#define  SCU_RAM_QAM_RD_RSV_2__W                                           16
#define  SCU_RAM_QAM_RD_RSV_2__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_2__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_2_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_2_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_2_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_2_BIT__PRE                                   0x0

#define  SCU_RAM_QAM_RD_RSV_3__A                                           0x831FD6
#define  SCU_RAM_QAM_RD_RSV_3__W                                           16
#define  SCU_RAM_QAM_RD_RSV_3__M                                           0xFFFF
#define  SCU_RAM_QAM_RD_RSV_3__PRE                                         0x0

#define    SCU_RAM_QAM_RD_RSV_3_BIT__B                                     0
#define    SCU_RAM_QAM_RD_RSV_3_BIT__W                                     16
#define    SCU_RAM_QAM_RD_RSV_3_BIT__M                                     0xFFFF
#define    SCU_RAM_QAM_RD_RSV_3_BIT__PRE                                   0x0


#define  SCU_RAM_FREE_8151__A                                              0x831FD7
#define  SCU_RAM_FREE_8151__W                                              16
#define  SCU_RAM_FREE_8151__M                                              0xFFFF
#define  SCU_RAM_FREE_8151__PRE                                            0x0

#define  SCU_RAM_FREE_8152__A                                              0x831FD8
#define  SCU_RAM_FREE_8152__W                                              16
#define  SCU_RAM_FREE_8152__M                                              0xFFFF
#define  SCU_RAM_FREE_8152__PRE                                            0x0

#define  SCU_RAM_FREE_8153__A                                              0x831FD9
#define  SCU_RAM_FREE_8153__W                                              16
#define  SCU_RAM_FREE_8153__M                                              0xFFFF
#define  SCU_RAM_FREE_8153__PRE                                            0x0

#define  SCU_RAM_FREE_8154__A                                              0x831FDA
#define  SCU_RAM_FREE_8154__W                                              16
#define  SCU_RAM_FREE_8154__M                                              0xFFFF
#define  SCU_RAM_FREE_8154__PRE                                            0x0

#define  SCU_RAM_FREE_8155__A                                              0x831FDB
#define  SCU_RAM_FREE_8155__W                                              16
#define  SCU_RAM_FREE_8155__M                                              0xFFFF
#define  SCU_RAM_FREE_8155__PRE                                            0x0

#define  SCU_RAM_FREE_8156__A                                              0x831FDC
#define  SCU_RAM_FREE_8156__W                                              16
#define  SCU_RAM_FREE_8156__M                                              0xFFFF
#define  SCU_RAM_FREE_8156__PRE                                            0x0

#define  SCU_RAM_FREE_8157__A                                              0x831FDD
#define  SCU_RAM_FREE_8157__W                                              16
#define  SCU_RAM_FREE_8157__M                                              0xFFFF
#define  SCU_RAM_FREE_8157__PRE                                            0x0

#define  SCU_RAM_FREE_8158__A                                              0x831FDE
#define  SCU_RAM_FREE_8158__W                                              16
#define  SCU_RAM_FREE_8158__M                                              0xFFFF
#define  SCU_RAM_FREE_8158__PRE                                            0x0

#define  SCU_RAM_FREE_8159__A                                              0x831FDF
#define  SCU_RAM_FREE_8159__W                                              16
#define  SCU_RAM_FREE_8159__M                                              0xFFFF
#define  SCU_RAM_FREE_8159__PRE                                            0x0

#define  SCU_RAM_FREE_8160__A                                              0x831FE0
#define  SCU_RAM_FREE_8160__W                                              16
#define  SCU_RAM_FREE_8160__M                                              0xFFFF
#define  SCU_RAM_FREE_8160__PRE                                            0x0

#define  SCU_RAM_FREE_8161__A                                              0x831FE1
#define  SCU_RAM_FREE_8161__W                                              16
#define  SCU_RAM_FREE_8161__M                                              0xFFFF
#define  SCU_RAM_FREE_8161__PRE                                            0x0

#define  SCU_RAM_FREE_8162__A                                              0x831FE2
#define  SCU_RAM_FREE_8162__W                                              16
#define  SCU_RAM_FREE_8162__M                                              0xFFFF
#define  SCU_RAM_FREE_8162__PRE                                            0x0

#define  SCU_RAM_FREE_8163__A                                              0x831FE3
#define  SCU_RAM_FREE_8163__W                                              16
#define  SCU_RAM_FREE_8163__M                                              0xFFFF
#define  SCU_RAM_FREE_8163__PRE                                            0x0

#define  SCU_RAM_FREE_8164__A                                              0x831FE4
#define  SCU_RAM_FREE_8164__W                                              16
#define  SCU_RAM_FREE_8164__M                                              0xFFFF
#define  SCU_RAM_FREE_8164__PRE                                            0x0

#define  SCU_RAM_FREE_8165__A                                              0x831FE5
#define  SCU_RAM_FREE_8165__W                                              16
#define  SCU_RAM_FREE_8165__M                                              0xFFFF
#define  SCU_RAM_FREE_8165__PRE                                            0x0

#define  SCU_RAM_FREE_8166__A                                              0x831FE6
#define  SCU_RAM_FREE_8166__W                                              16
#define  SCU_RAM_FREE_8166__M                                              0xFFFF
#define  SCU_RAM_FREE_8166__PRE                                            0x0

#define  SCU_RAM_FREE_8167__A                                              0x831FE7
#define  SCU_RAM_FREE_8167__W                                              16
#define  SCU_RAM_FREE_8167__M                                              0xFFFF
#define  SCU_RAM_FREE_8167__PRE                                            0x0

#define  SCU_RAM_FREE_8168__A                                              0x831FE8
#define  SCU_RAM_FREE_8168__W                                              16
#define  SCU_RAM_FREE_8168__M                                              0xFFFF
#define  SCU_RAM_FREE_8168__PRE                                            0x0

#define  SCU_RAM_FREE_8169__A                                              0x831FE9
#define  SCU_RAM_FREE_8169__W                                              16
#define  SCU_RAM_FREE_8169__M                                              0xFFFF
#define  SCU_RAM_FREE_8169__PRE                                            0x0

#define  SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A                                0x831FEA
#define  SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W                                16
#define  SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M                                0xFFFF
#define  SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE                              0x1E

#define  SCU_RAM_DRIVER_VER_HI__A                                          0x831FEB
#define  SCU_RAM_DRIVER_VER_HI__W                                          16
#define  SCU_RAM_DRIVER_VER_HI__M                                          0xFFFF
#define  SCU_RAM_DRIVER_VER_HI__PRE                                        0x0

#define  SCU_RAM_DRIVER_VER_LO__A                                          0x831FEC
#define  SCU_RAM_DRIVER_VER_LO__W                                          16
#define  SCU_RAM_DRIVER_VER_LO__M                                          0xFFFF
#define  SCU_RAM_DRIVER_VER_LO__PRE                                        0x0

#define  SCU_RAM_PARAM_15__A                                               0x831FED
#define  SCU_RAM_PARAM_15__W                                               16
#define  SCU_RAM_PARAM_15__M                                               0xFFFF
#define  SCU_RAM_PARAM_15__PRE                                             0x0

#define  SCU_RAM_PARAM_14__A                                               0x831FEE
#define  SCU_RAM_PARAM_14__W                                               16
#define  SCU_RAM_PARAM_14__M                                               0xFFFF
#define  SCU_RAM_PARAM_14__PRE                                             0x0

#define  SCU_RAM_PARAM_13__A                                               0x831FEF
#define  SCU_RAM_PARAM_13__W                                               16
#define  SCU_RAM_PARAM_13__M                                               0xFFFF
#define  SCU_RAM_PARAM_13__PRE                                             0x0

#define  SCU_RAM_PARAM_12__A                                               0x831FF0
#define  SCU_RAM_PARAM_12__W                                               16
#define  SCU_RAM_PARAM_12__M                                               0xFFFF
#define  SCU_RAM_PARAM_12__PRE                                             0x0

#define  SCU_RAM_PARAM_11__A                                               0x831FF1
#define  SCU_RAM_PARAM_11__W                                               16
#define  SCU_RAM_PARAM_11__M                                               0xFFFF
#define  SCU_RAM_PARAM_11__PRE                                             0x0

#define  SCU_RAM_PARAM_10__A                                               0x831FF2
#define  SCU_RAM_PARAM_10__W                                               16
#define  SCU_RAM_PARAM_10__M                                               0xFFFF
#define  SCU_RAM_PARAM_10__PRE                                             0x0

#define  SCU_RAM_PARAM_9__A                                                0x831FF3
#define  SCU_RAM_PARAM_9__W                                                16
#define  SCU_RAM_PARAM_9__M                                                0xFFFF
#define  SCU_RAM_PARAM_9__PRE                                              0x0

#define  SCU_RAM_PARAM_8__A                                                0x831FF4
#define  SCU_RAM_PARAM_8__W                                                16
#define  SCU_RAM_PARAM_8__M                                                0xFFFF
#define  SCU_RAM_PARAM_8__PRE                                              0x0

#define  SCU_RAM_PARAM_7__A                                                0x831FF5
#define  SCU_RAM_PARAM_7__W                                                16
#define  SCU_RAM_PARAM_7__M                                                0xFFFF
#define  SCU_RAM_PARAM_7__PRE                                              0x0

#define  SCU_RAM_PARAM_6__A                                                0x831FF6
#define  SCU_RAM_PARAM_6__W                                                16
#define  SCU_RAM_PARAM_6__M                                                0xFFFF
#define  SCU_RAM_PARAM_6__PRE                                              0x0

#define  SCU_RAM_PARAM_5__A                                                0x831FF7
#define  SCU_RAM_PARAM_5__W                                                16
#define  SCU_RAM_PARAM_5__M                                                0xFFFF
#define  SCU_RAM_PARAM_5__PRE                                              0x0

#define  SCU_RAM_PARAM_4__A                                                0x831FF8
#define  SCU_RAM_PARAM_4__W                                                16
#define  SCU_RAM_PARAM_4__M                                                0xFFFF
#define  SCU_RAM_PARAM_4__PRE                                              0x0

#define  SCU_RAM_PARAM_3__A                                                0x831FF9
#define  SCU_RAM_PARAM_3__W                                                16
#define  SCU_RAM_PARAM_3__M                                                0xFFFF
#define  SCU_RAM_PARAM_3__PRE                                              0x0

#define  SCU_RAM_PARAM_2__A                                                0x831FFA
#define  SCU_RAM_PARAM_2__W                                                16
#define  SCU_RAM_PARAM_2__M                                                0xFFFF
#define  SCU_RAM_PARAM_2__PRE                                              0x0

#define  SCU_RAM_PARAM_1__A                                                0x831FFB
#define  SCU_RAM_PARAM_1__W                                                16
#define  SCU_RAM_PARAM_1__M                                                0xFFFF
#define  SCU_RAM_PARAM_1__PRE                                              0x0
#define    SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED                   0x0
#define    SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED                 0x4000
#define    SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED                       0x8000
#define    SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK                   0xC000


#define  SCU_RAM_PARAM_0__A                                                0x831FFC
#define  SCU_RAM_PARAM_0__W                                                16
#define  SCU_RAM_PARAM_0__M                                                0xFFFF
#define  SCU_RAM_PARAM_0__PRE                                              0x0
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD                    0x2
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD                     0x103
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD                     0x3
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD                    0x4
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD                     0x9
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD                    0x109
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD                     0xA
#define    SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD                    0x40
#define    SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A                        0x0
#define    SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B                        0x1
#define    SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C                        0x2
#define    SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D                        0x3
#define    SCU_RAM_PARAM_0_RESULT_OK                                       0x0
#define    SCU_RAM_PARAM_0_RESULT_UNKCMD                                   0xFFFF
#define    SCU_RAM_PARAM_0_RESULT_UNKSTD                                   0xFFFE
#define    SCU_RAM_PARAM_0_RESULT_INVPAR                                   0xFFFD
#define    SCU_RAM_PARAM_0_RESULT_SIZE                                     0xFFFC


#define  SCU_RAM_COMMAND__A                                                0x831FFD
#define  SCU_RAM_COMMAND__W                                                16
#define  SCU_RAM_COMMAND__M                                                0xFFFF
#define  SCU_RAM_COMMAND__PRE                                              0x0
#define    SCU_RAM_COMMAND_CMD_DEMOD_RESET                                 0x1
#define    SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV                               0x2
#define    SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM                             0x3
#define    SCU_RAM_COMMAND_CMD_DEMOD_START                                 0x4
#define    SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK                              0x5
#define    SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM                             0x6
#define    SCU_RAM_COMMAND_CMD_DEMOD_HOLD                                  0x7
#define    SCU_RAM_COMMAND_CMD_DEMOD_RESUME                                0x8
#define    SCU_RAM_COMMAND_CMD_DEMOD_STOP                                  0x9
#define    SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE                        0x80
#define    SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE                      0x81
#define    SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL                          0x82
#define    SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR                         0x83
#define    SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE                          0x84
#define    SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE                       0x85
#define    SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS                          0x80
#define    SCU_RAM_COMMAND_CMD_DEBUG_HTOL                                  0x81
#define    SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER                     0x82
#define    SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK                     0x83
#define    SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK                      0x84
#define    SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS                           0x85
#define    SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI                           0x86
#define    SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW                               0x87
#define    SCU_RAM_COMMAND_CMD_ADMIN_NOP                                   0xFF
#define    SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION                           0xFE
#define    SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION                      0xFD
#define    SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS                       0xC0
#define    SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART                        0xC1

#define    SCU_RAM_COMMAND_STANDARD__B                                     8
#define    SCU_RAM_COMMAND_STANDARD__W                                     8
#define    SCU_RAM_COMMAND_STANDARD__M                                     0xFF00
#define    SCU_RAM_COMMAND_STANDARD__PRE                                   0x0
#define      SCU_RAM_COMMAND_STANDARD_ATV                                  0x100
#define      SCU_RAM_COMMAND_STANDARD_QAM                                  0x200
#define      SCU_RAM_COMMAND_STANDARD_VSB                                  0x300
#define      SCU_RAM_COMMAND_STANDARD_OFDM                                 0x400
#define      SCU_RAM_COMMAND_STANDARD_OOB                                  0x8000
#define      SCU_RAM_COMMAND_STANDARD_TOP                                  0xFF00

#define  SCU_RAM_VERSION_HI__A                                             0x831FFE
#define  SCU_RAM_VERSION_HI__W                                             16
#define  SCU_RAM_VERSION_HI__M                                             0xFFFF
#define  SCU_RAM_VERSION_HI__PRE                                           0x0

#define    SCU_RAM_VERSION_HI_VER_MAJOR_N3__B                              12
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N3__W                              4
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N3__M                              0xF000
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE                            0x0

#define    SCU_RAM_VERSION_HI_VER_MAJOR_N2__B                              8
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N2__W                              4
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N2__M                              0xF00
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE                            0x0

#define    SCU_RAM_VERSION_HI_VER_MAJOR_N1__B                              4
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N1__W                              4
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N1__M                              0xF0
#define    SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE                            0x0

#define    SCU_RAM_VERSION_HI_VER_MINOR_N1__B                              0
#define    SCU_RAM_VERSION_HI_VER_MINOR_N1__W                              4
#define    SCU_RAM_VERSION_HI_VER_MINOR_N1__M                              0xF
#define    SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE                            0x0

#define  SCU_RAM_VERSION_LO__A                                             0x831FFF
#define  SCU_RAM_VERSION_LO__W                                             16
#define  SCU_RAM_VERSION_LO__M                                             0xFFFF
#define  SCU_RAM_VERSION_LO__PRE                                           0x0

#define    SCU_RAM_VERSION_LO_VER_PATCH_N4__B                              12
#define    SCU_RAM_VERSION_LO_VER_PATCH_N4__W                              4
#define    SCU_RAM_VERSION_LO_VER_PATCH_N4__M                              0xF000
#define    SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE                            0x0

#define    SCU_RAM_VERSION_LO_VER_PATCH_N3__B                              8
#define    SCU_RAM_VERSION_LO_VER_PATCH_N3__W                              4
#define    SCU_RAM_VERSION_LO_VER_PATCH_N3__M                              0xF00
#define    SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE                            0x0

#define    SCU_RAM_VERSION_LO_VER_PATCH_N2__B                              4
#define    SCU_RAM_VERSION_LO_VER_PATCH_N2__W                              4
#define    SCU_RAM_VERSION_LO_VER_PATCH_N2__M                              0xF0
#define    SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE                            0x0

#define    SCU_RAM_VERSION_LO_VER_PATCH_N1__B                              0
#define    SCU_RAM_VERSION_LO_VER_PATCH_N1__W                              4
#define    SCU_RAM_VERSION_LO_VER_PATCH_N1__M                              0xF
#define    SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE                            0x0





#define  SIO_COMM_EXEC__A                                                  0x400000
#define  SIO_COMM_EXEC__W                                                  2
#define  SIO_COMM_EXEC__M                                                  0x3
#define  SIO_COMM_EXEC__PRE                                                0x0
#define    SIO_COMM_EXEC_STOP                                              0x0
#define    SIO_COMM_EXEC_ACTIVE                                            0x1
#define    SIO_COMM_EXEC_HOLD                                              0x2

#define  SIO_COMM_STATE__A                                                 0x400001
#define  SIO_COMM_STATE__W                                                 16
#define  SIO_COMM_STATE__M                                                 0xFFFF
#define  SIO_COMM_STATE__PRE                                               0x0
#define  SIO_COMM_MB__A                                                    0x400002
#define  SIO_COMM_MB__W                                                    16
#define  SIO_COMM_MB__M                                                    0xFFFF
#define  SIO_COMM_MB__PRE                                                  0x0
#define  SIO_COMM_INT_REQ__A                                               0x400003
#define  SIO_COMM_INT_REQ__W                                               16
#define  SIO_COMM_INT_REQ__M                                               0xFFFF
#define  SIO_COMM_INT_REQ__PRE                                             0x0

#define    SIO_COMM_INT_REQ_HI_REQ__B                                      0
#define    SIO_COMM_INT_REQ_HI_REQ__W                                      1
#define    SIO_COMM_INT_REQ_HI_REQ__M                                      0x1
#define    SIO_COMM_INT_REQ_HI_REQ__PRE                                    0x0

#define    SIO_COMM_INT_REQ_SA_REQ__B                                      1
#define    SIO_COMM_INT_REQ_SA_REQ__W                                      1
#define    SIO_COMM_INT_REQ_SA_REQ__M                                      0x2
#define    SIO_COMM_INT_REQ_SA_REQ__PRE                                    0x0

#define    SIO_COMM_INT_REQ_BL_REQ__B                                      2
#define    SIO_COMM_INT_REQ_BL_REQ__W                                      1
#define    SIO_COMM_INT_REQ_BL_REQ__M                                      0x4
#define    SIO_COMM_INT_REQ_BL_REQ__PRE                                    0x0

#define  SIO_COMM_INT_STA__A                                               0x400005
#define  SIO_COMM_INT_STA__W                                               16
#define  SIO_COMM_INT_STA__M                                               0xFFFF
#define  SIO_COMM_INT_STA__PRE                                             0x0
#define  SIO_COMM_INT_MSK__A                                               0x400006
#define  SIO_COMM_INT_MSK__W                                               16
#define  SIO_COMM_INT_MSK__M                                               0xFFFF
#define  SIO_COMM_INT_MSK__PRE                                             0x0
#define  SIO_COMM_INT_STM__A                                               0x400007
#define  SIO_COMM_INT_STM__W                                               16
#define  SIO_COMM_INT_STM__M                                               0xFFFF
#define  SIO_COMM_INT_STM__PRE                                             0x0



#define  SIO_TOP_COMM_EXEC__A                                              0x410000
#define  SIO_TOP_COMM_EXEC__W                                              2
#define  SIO_TOP_COMM_EXEC__M                                              0x3
#define  SIO_TOP_COMM_EXEC__PRE                                            0x0
#define    SIO_TOP_COMM_EXEC_STOP                                          0x0
#define    SIO_TOP_COMM_EXEC_ACTIVE                                        0x1
#define    SIO_TOP_COMM_EXEC_HOLD                                          0x2


#define  SIO_TOP_COMM_KEY__A                                               0x41000F
#define  SIO_TOP_COMM_KEY__W                                               16
#define  SIO_TOP_COMM_KEY__M                                               0xFFFF
#define  SIO_TOP_COMM_KEY__PRE                                             0x0
#define    SIO_TOP_COMM_KEY_KEY                                            0xFABA


#define  SIO_TOP_JTAGID_LO__A                                              0x410012
#define  SIO_TOP_JTAGID_LO__W                                              16
#define  SIO_TOP_JTAGID_LO__M                                              0xFFFF
#define  SIO_TOP_JTAGID_LO__PRE                                            0x0

#define  SIO_TOP_JTAGID_HI__A                                              0x410013
#define  SIO_TOP_JTAGID_HI__W                                              16
#define  SIO_TOP_JTAGID_HI__M                                              0xFFFF
#define  SIO_TOP_JTAGID_HI__PRE                                            0x0




#define  SIO_HI_RA_RAM_S0_FLG_SMM__A                                       0x420010
#define  SIO_HI_RA_RAM_S0_FLG_SMM__W                                       1
#define  SIO_HI_RA_RAM_S0_FLG_SMM__M                                       0x1
#define  SIO_HI_RA_RAM_S0_FLG_SMM__PRE                                     0x0

#define  SIO_HI_RA_RAM_S0_DEV_ID__A                                        0x420011
#define  SIO_HI_RA_RAM_S0_DEV_ID__W                                        7
#define  SIO_HI_RA_RAM_S0_DEV_ID__M                                        0x7F
#define  SIO_HI_RA_RAM_S0_DEV_ID__PRE                                      0x52

#define  SIO_HI_RA_RAM_S0_FLG_CRC__A                                       0x420012
#define  SIO_HI_RA_RAM_S0_FLG_CRC__W                                       1
#define  SIO_HI_RA_RAM_S0_FLG_CRC__M                                       0x1
#define  SIO_HI_RA_RAM_S0_FLG_CRC__PRE                                     0x0
#define  SIO_HI_RA_RAM_S0_FLG_ACC__A                                       0x420013
#define  SIO_HI_RA_RAM_S0_FLG_ACC__W                                       4
#define  SIO_HI_RA_RAM_S0_FLG_ACC__M                                       0xF
#define  SIO_HI_RA_RAM_S0_FLG_ACC__PRE                                     0x0

#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B                              0
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W                              2
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M                              0x3
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE                            0x0

#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B                          2
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W                          1
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M                          0x4
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE                        0x0

#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B                          3
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W                          1
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M                          0x8
#define    SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE                        0x0

#define  SIO_HI_RA_RAM_S0_STATE__A                                         0x420014
#define  SIO_HI_RA_RAM_S0_STATE__W                                         1
#define  SIO_HI_RA_RAM_S0_STATE__M                                         0x1
#define  SIO_HI_RA_RAM_S0_STATE__PRE                                       0x0

#define    SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B                            0
#define    SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W                            1
#define    SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M                            0x1
#define    SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE                          0x0

#define  SIO_HI_RA_RAM_S0_BLK_BNK__A                                       0x420015
#define  SIO_HI_RA_RAM_S0_BLK_BNK__W                                       12
#define  SIO_HI_RA_RAM_S0_BLK_BNK__M                                       0xFFF
#define  SIO_HI_RA_RAM_S0_BLK_BNK__PRE                                     0x82

#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B                          0
#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W                          6
#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M                          0x3F
#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE                        0x2

#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B                          6
#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W                          6
#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M                          0xFC0
#define    SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE                        0x80

#define  SIO_HI_RA_RAM_S0_ADDR__A                                          0x420016
#define  SIO_HI_RA_RAM_S0_ADDR__W                                          16
#define  SIO_HI_RA_RAM_S0_ADDR__M                                          0xFFFF
#define  SIO_HI_RA_RAM_S0_ADDR__PRE                                        0x0

#define    SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B                            0
#define    SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W                            16
#define    SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M                            0xFFFF
#define    SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE                          0x0


#define  SIO_HI_RA_RAM_S0_CRC__A                                           0x420017
#define  SIO_HI_RA_RAM_S0_CRC__W                                           16
#define  SIO_HI_RA_RAM_S0_CRC__M                                           0xFFFF
#define  SIO_HI_RA_RAM_S0_CRC__PRE                                         0x0

#define  SIO_HI_RA_RAM_S0_BUFFER__A                                        0x420018
#define  SIO_HI_RA_RAM_S0_BUFFER__W                                        16
#define  SIO_HI_RA_RAM_S0_BUFFER__M                                        0xFFFF
#define  SIO_HI_RA_RAM_S0_BUFFER__PRE                                      0x0

#define  SIO_HI_RA_RAM_S0_RMWBUF__A                                        0x420019
#define  SIO_HI_RA_RAM_S0_RMWBUF__W                                        16
#define  SIO_HI_RA_RAM_S0_RMWBUF__M                                        0xFFFF
#define  SIO_HI_RA_RAM_S0_RMWBUF__PRE                                      0x0

#define  SIO_HI_RA_RAM_S0_FLG_VB__A                                        0x42001A
#define  SIO_HI_RA_RAM_S0_FLG_VB__W                                        1
#define  SIO_HI_RA_RAM_S0_FLG_VB__M                                        0x1
#define  SIO_HI_RA_RAM_S0_FLG_VB__PRE                                      0x0

#define  SIO_HI_RA_RAM_S0_TEMP0__A                                         0x42001B
#define  SIO_HI_RA_RAM_S0_TEMP0__W                                         16
#define  SIO_HI_RA_RAM_S0_TEMP0__M                                         0xFFFF
#define  SIO_HI_RA_RAM_S0_TEMP0__PRE                                       0x0

#define  SIO_HI_RA_RAM_S0_TEMP1__A                                         0x42001C
#define  SIO_HI_RA_RAM_S0_TEMP1__W                                         16
#define  SIO_HI_RA_RAM_S0_TEMP1__M                                         0xFFFF
#define  SIO_HI_RA_RAM_S0_TEMP1__PRE                                       0x0

#define  SIO_HI_RA_RAM_S0_OFFSET__A                                        0x42001D
#define  SIO_HI_RA_RAM_S0_OFFSET__W                                        16
#define  SIO_HI_RA_RAM_S0_OFFSET__M                                        0xFFFF
#define  SIO_HI_RA_RAM_S0_OFFSET__PRE                                      0x0

#define  SIO_HI_RA_RAM_S1_FLG_SMM__A                                       0x420020
#define  SIO_HI_RA_RAM_S1_FLG_SMM__W                                       1
#define  SIO_HI_RA_RAM_S1_FLG_SMM__M                                       0x1
#define  SIO_HI_RA_RAM_S1_FLG_SMM__PRE                                     0x0

#define  SIO_HI_RA_RAM_S1_DEV_ID__A                                        0x420021
#define  SIO_HI_RA_RAM_S1_DEV_ID__W                                        7
#define  SIO_HI_RA_RAM_S1_DEV_ID__M                                        0x7F
#define  SIO_HI_RA_RAM_S1_DEV_ID__PRE                                      0x52

#define  SIO_HI_RA_RAM_S1_FLG_CRC__A                                       0x420022
#define  SIO_HI_RA_RAM_S1_FLG_CRC__W                                       1
#define  SIO_HI_RA_RAM_S1_FLG_CRC__M                                       0x1
#define  SIO_HI_RA_RAM_S1_FLG_CRC__PRE                                     0x0
#define  SIO_HI_RA_RAM_S1_FLG_ACC__A                                       0x420023
#define  SIO_HI_RA_RAM_S1_FLG_ACC__W                                       4
#define  SIO_HI_RA_RAM_S1_FLG_ACC__M                                       0xF
#define  SIO_HI_RA_RAM_S1_FLG_ACC__PRE                                     0x0

#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B                              0
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W                              2
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M                              0x3
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE                            0x0

#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B                          2
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W                          1
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M                          0x4
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE                        0x0

#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B                          3
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W                          1
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M                          0x8
#define    SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE                        0x0

#define  SIO_HI_RA_RAM_S1_STATE__A                                         0x420024
#define  SIO_HI_RA_RAM_S1_STATE__W                                         1
#define  SIO_HI_RA_RAM_S1_STATE__M                                         0x1
#define  SIO_HI_RA_RAM_S1_STATE__PRE                                       0x0

#define    SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B                            0
#define    SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W                            1
#define    SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M                            0x1
#define    SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE                          0x0

#define  SIO_HI_RA_RAM_S1_BLK_BNK__A                                       0x420025
#define  SIO_HI_RA_RAM_S1_BLK_BNK__W                                       12
#define  SIO_HI_RA_RAM_S1_BLK_BNK__M                                       0xFFF
#define  SIO_HI_RA_RAM_S1_BLK_BNK__PRE                                     0x82

#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B                          0
#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W                          6
#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M                          0x3F
#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE                        0x2

#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B                          6
#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W                          6
#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M                          0xFC0
#define    SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE                        0x80

#define  SIO_HI_RA_RAM_S1_ADDR__A                                          0x420026
#define  SIO_HI_RA_RAM_S1_ADDR__W                                          16
#define  SIO_HI_RA_RAM_S1_ADDR__M                                          0xFFFF
#define  SIO_HI_RA_RAM_S1_ADDR__PRE                                        0x0

#define    SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B                            0
#define    SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W                            16
#define    SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M                            0xFFFF
#define    SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE                          0x0


#define  SIO_HI_RA_RAM_S1_CRC__A                                           0x420027
#define  SIO_HI_RA_RAM_S1_CRC__W                                           16
#define  SIO_HI_RA_RAM_S1_CRC__M                                           0xFFFF
#define  SIO_HI_RA_RAM_S1_CRC__PRE                                         0x0

#define  SIO_HI_RA_RAM_S1_BUFFER__A                                        0x420028
#define  SIO_HI_RA_RAM_S1_BUFFER__W                                        16
#define  SIO_HI_RA_RAM_S1_BUFFER__M                                        0xFFFF
#define  SIO_HI_RA_RAM_S1_BUFFER__PRE                                      0x0

#define  SIO_HI_RA_RAM_S1_RMWBUF__A                                        0x420029
#define  SIO_HI_RA_RAM_S1_RMWBUF__W                                        16
#define  SIO_HI_RA_RAM_S1_RMWBUF__M                                        0xFFFF
#define  SIO_HI_RA_RAM_S1_RMWBUF__PRE                                      0x0

#define  SIO_HI_RA_RAM_S1_FLG_VB__A                                        0x42002A
#define  SIO_HI_RA_RAM_S1_FLG_VB__W                                        1
#define  SIO_HI_RA_RAM_S1_FLG_VB__M                                        0x1
#define  SIO_HI_RA_RAM_S1_FLG_VB__PRE                                      0x0

#define  SIO_HI_RA_RAM_S1_TEMP0__A                                         0x42002B
#define  SIO_HI_RA_RAM_S1_TEMP0__W                                         16
#define  SIO_HI_RA_RAM_S1_TEMP0__M                                         0xFFFF
#define  SIO_HI_RA_RAM_S1_TEMP0__PRE                                       0x0

#define  SIO_HI_RA_RAM_S1_TEMP1__A                                         0x42002C
#define  SIO_HI_RA_RAM_S1_TEMP1__W                                         16
#define  SIO_HI_RA_RAM_S1_TEMP1__M                                         0xFFFF
#define  SIO_HI_RA_RAM_S1_TEMP1__PRE                                       0x0

#define  SIO_HI_RA_RAM_S1_OFFSET__A                                        0x42002D
#define  SIO_HI_RA_RAM_S1_OFFSET__W                                        16
#define  SIO_HI_RA_RAM_S1_OFFSET__M                                        0xFFFF
#define  SIO_HI_RA_RAM_S1_OFFSET__PRE                                      0x0
#define  SIO_HI_RA_RAM_SEMA__A                                             0x420030
#define  SIO_HI_RA_RAM_SEMA__W                                             1
#define  SIO_HI_RA_RAM_SEMA__M                                             0x1
#define  SIO_HI_RA_RAM_SEMA__PRE                                           0x0
#define    SIO_HI_RA_RAM_SEMA_FREE                                         0x0
#define    SIO_HI_RA_RAM_SEMA_BUSY                                         0x1

#define  SIO_HI_RA_RAM_RES__A                                              0x420031
#define  SIO_HI_RA_RAM_RES__W                                              3
#define  SIO_HI_RA_RAM_RES__M                                              0x7
#define  SIO_HI_RA_RAM_RES__PRE                                            0x0
#define    SIO_HI_RA_RAM_RES_OK                                            0x0
#define    SIO_HI_RA_RAM_RES_ERROR                                         0x1
#define    SIO_HI_RA_RAM_RES_I2C_START_FOUND                               0x1
#define    SIO_HI_RA_RAM_RES_I2C_STOP_FOUND                                0x2
#define    SIO_HI_RA_RAM_RES_I2C_ARB_LOST                                  0x3
#define    SIO_HI_RA_RAM_RES_I2C_ERROR                                     0x4

#define  SIO_HI_RA_RAM_CMD__A                                              0x420032
#define  SIO_HI_RA_RAM_CMD__W                                              4
#define  SIO_HI_RA_RAM_CMD__M                                              0xF
#define  SIO_HI_RA_RAM_CMD__PRE                                            0x0
#define    SIO_HI_RA_RAM_CMD_NULL                                          0x0
#define    SIO_HI_RA_RAM_CMD_UIO                                           0x1
#define    SIO_HI_RA_RAM_CMD_RESET                                         0x2
#define    SIO_HI_RA_RAM_CMD_CONFIG                                        0x3
#define    SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER                             0x4
#define    SIO_HI_RA_RAM_CMD_I2C_TRANSMIT                                  0x5
#define    SIO_HI_RA_RAM_CMD_EXEC                                          0x6
#define    SIO_HI_RA_RAM_CMD_BRDCTRL                                       0x7
#define    SIO_HI_RA_RAM_CMD_ATOMIC_COPY                                   0x8

#define  SIO_HI_RA_RAM_PAR_1__A                                            0x420033
#define  SIO_HI_RA_RAM_PAR_1__W                                            16
#define  SIO_HI_RA_RAM_PAR_1__M                                            0xFFFF
#define  SIO_HI_RA_RAM_PAR_1__PRE                                          0x0
#define    SIO_HI_RA_RAM_PAR_1_PAR1__B                                     0
#define    SIO_HI_RA_RAM_PAR_1_PAR1__W                                     16
#define    SIO_HI_RA_RAM_PAR_1_PAR1__M                                     0xFFFF
#define    SIO_HI_RA_RAM_PAR_1_PAR1__PRE                                   0x0
#define      SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY                              0x3945

#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B                              0
#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W                              6
#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M                              0x3F
#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B                              6
#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W                              6
#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M                              0xFC0
#define    SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B                               0
#define    SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W                               1
#define    SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M                               0x1
#define    SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE                             0x0

#define    SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B                                1
#define    SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W                                1
#define    SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M                                0x2
#define    SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE                              0x0
#define      SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE                         0x0
#define      SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE                          0x2

#define    SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B                                0
#define    SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W                                10
#define    SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M                                0x3FF
#define    SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE                              0x0

#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B                              0
#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W                              6
#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M                              0x3F
#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B                              6
#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W                              6
#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M                              0xFC0
#define    SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE                            0x0

#define  SIO_HI_RA_RAM_PAR_2__A                                            0x420034
#define  SIO_HI_RA_RAM_PAR_2__W                                            16
#define  SIO_HI_RA_RAM_PAR_2__M                                            0xFFFF
#define  SIO_HI_RA_RAM_PAR_2__PRE                                          0x0
#define    SIO_HI_RA_RAM_PAR_2_PAR2__B                                     0
#define    SIO_HI_RA_RAM_PAR_2_PAR2__W                                     16
#define    SIO_HI_RA_RAM_PAR_2_PAR2__M                                     0xFFFF
#define    SIO_HI_RA_RAM_PAR_2_PAR2__PRE                                   0x0

#define    SIO_HI_RA_RAM_PAR_2_CFG_DIV__B                                  0
#define    SIO_HI_RA_RAM_PAR_2_CFG_DIV__W                                  7
#define    SIO_HI_RA_RAM_PAR_2_CFG_DIV__M                                  0x7F
#define    SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE                                0x25

#define    SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B                              0
#define    SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W                              16
#define    SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M                              0xFFFF
#define    SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B                                0
#define    SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W                                16
#define    SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M                                0xFFFF
#define    SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE                              0x0

#define    SIO_HI_RA_RAM_PAR_2_BRD_CFG__B                                  2
#define    SIO_HI_RA_RAM_PAR_2_BRD_CFG__W                                  1
#define    SIO_HI_RA_RAM_PAR_2_BRD_CFG__M                                  0x4
#define    SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE                                0x0
#define      SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN                              0x0
#define      SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED                            0x4

#define    SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B                              0
#define    SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W                              16
#define    SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M                              0xFFFF
#define    SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE                            0x0

#define  SIO_HI_RA_RAM_PAR_3__A                                            0x420035
#define  SIO_HI_RA_RAM_PAR_3__W                                            16
#define  SIO_HI_RA_RAM_PAR_3__M                                            0xFFFF
#define  SIO_HI_RA_RAM_PAR_3__PRE                                          0x0
#define    SIO_HI_RA_RAM_PAR_3_PAR3__B                                     0
#define    SIO_HI_RA_RAM_PAR_3_PAR3__W                                     16
#define    SIO_HI_RA_RAM_PAR_3_PAR3__M                                     0xFFFF
#define    SIO_HI_RA_RAM_PAR_3_PAR3__PRE                                   0x0

#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B                              0
#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W                              7
#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M                              0x7F
#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE                            0x3F

#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B                              7
#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W                              7
#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M                              0x3F80
#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE                            0x1F80

#define    SIO_HI_RA_RAM_PAR_3_ITX_LEN__B                                  0
#define    SIO_HI_RA_RAM_PAR_3_ITX_LEN__W                                  16
#define    SIO_HI_RA_RAM_PAR_3_ITX_LEN__M                                  0xFFFF
#define    SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE                                0x0

#define    SIO_HI_RA_RAM_PAR_3_ACP_LEN__B                                  0
#define    SIO_HI_RA_RAM_PAR_3_ACP_LEN__W                                  3
#define    SIO_HI_RA_RAM_PAR_3_ACP_LEN__M                                  0x7
#define    SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE                                0x0

#define    SIO_HI_RA_RAM_PAR_3_ACP_RW__B                                   3
#define    SIO_HI_RA_RAM_PAR_3_ACP_RW__W                                   1
#define    SIO_HI_RA_RAM_PAR_3_ACP_RW__M                                   0x8
#define    SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE                                 0x0
#define      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ                               0x0
#define      SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE                              0x8

#define  SIO_HI_RA_RAM_PAR_4__A                                            0x420036
#define  SIO_HI_RA_RAM_PAR_4__W                                            16
#define  SIO_HI_RA_RAM_PAR_4__M                                            0xFFFF
#define  SIO_HI_RA_RAM_PAR_4__PRE                                          0x0
#define    SIO_HI_RA_RAM_PAR_4_PAR4__B                                     0
#define    SIO_HI_RA_RAM_PAR_4_PAR4__W                                     16
#define    SIO_HI_RA_RAM_PAR_4_PAR4__M                                     0xFFFF
#define    SIO_HI_RA_RAM_PAR_4_PAR4__PRE                                   0x0

#define    SIO_HI_RA_RAM_PAR_4_CFG_WUP__B                                  0
#define    SIO_HI_RA_RAM_PAR_4_CFG_WUP__W                                  8
#define    SIO_HI_RA_RAM_PAR_4_CFG_WUP__M                                  0xFF
#define    SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE                                0xC1

#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B                              0
#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W                              6
#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M                              0x3F
#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B                              6
#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W                              6
#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M                              0xFC0
#define    SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B                              0
#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W                              6
#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M                              0x3F
#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B                              6
#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W                              6
#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M                              0xFC0
#define    SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE                            0x0

#define  SIO_HI_RA_RAM_PAR_5__A                                            0x420037
#define  SIO_HI_RA_RAM_PAR_5__W                                            16
#define  SIO_HI_RA_RAM_PAR_5__M                                            0xFFFF
#define  SIO_HI_RA_RAM_PAR_5__PRE                                          0x0
#define    SIO_HI_RA_RAM_PAR_5_PAR5__B                                     0
#define    SIO_HI_RA_RAM_PAR_5_PAR5__W                                     16
#define    SIO_HI_RA_RAM_PAR_5_PAR5__M                                     0xFFFF
#define    SIO_HI_RA_RAM_PAR_5_PAR5__PRE                                   0x0

#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B                                 0
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W                                 1
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M                                 0x1
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE                               0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE                         0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE                            0x1

#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B                                 1
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W                                 1
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M                                 0x2
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE                               0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE                         0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE                            0x2

#define    SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B                                3
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W                                1
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M                                0x8
#define    SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE                              0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE                           0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ                             0x8

#define    SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B                                5
#define    SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W                                1
#define    SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M                                0x20
#define    SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE                              0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE                         0x0
#define      SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE                          0x20

#define    SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B                              0
#define    SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W                              16
#define    SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M                              0xFFFF
#define    SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE                            0x0

#define    SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B                              0
#define    SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W                              16
#define    SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M                              0xFFFF
#define    SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE                            0x0

#define  SIO_HI_RA_RAM_PAR_6__A                                            0x420038
#define  SIO_HI_RA_RAM_PAR_6__W                                            16
#define  SIO_HI_RA_RAM_PAR_6__M                                            0xFFFF
#define  SIO_HI_RA_RAM_PAR_6__PRE                                          0x95FF
#define    SIO_HI_RA_RAM_PAR_6_PAR6__B                                     0
#define    SIO_HI_RA_RAM_PAR_6_PAR6__W                                     16
#define    SIO_HI_RA_RAM_PAR_6_PAR6__M                                     0xFFFF
#define    SIO_HI_RA_RAM_PAR_6_PAR6__PRE                                   0x0

#define    SIO_HI_RA_RAM_PAR_6_CFG_TOD__B                                  0
#define    SIO_HI_RA_RAM_PAR_6_CFG_TOD__W                                  8
#define    SIO_HI_RA_RAM_PAR_6_CFG_TOD__M                                  0xFF
#define    SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE                                0xFF

#define    SIO_HI_RA_RAM_PAR_6_CFG_WDD__B                                  8
#define    SIO_HI_RA_RAM_PAR_6_CFG_WDD__W                                  8
#define    SIO_HI_RA_RAM_PAR_6_CFG_WDD__M                                  0xFF00
#define    SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE                                0x9500


#define  SIO_HI_RA_RAM_AB_TEMP__A                                          0x42006E
#define  SIO_HI_RA_RAM_AB_TEMP__W                                          16
#define  SIO_HI_RA_RAM_AB_TEMP__M                                          0xFFFF
#define  SIO_HI_RA_RAM_AB_TEMP__PRE                                        0x0

#define  SIO_HI_RA_RAM_I2C_CTL__A                                          0x42006F
#define  SIO_HI_RA_RAM_I2C_CTL__W                                          16
#define  SIO_HI_RA_RAM_I2C_CTL__M                                          0xFFFF
#define  SIO_HI_RA_RAM_I2C_CTL__PRE                                        0x0

#define  SIO_HI_RA_RAM_VB_ENTRY0__A                                        0x420070
#define  SIO_HI_RA_RAM_VB_ENTRY0__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY0__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY0__PRE                                      0x0

#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B                           0
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W                           4
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M                           0xF
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE                         0x0

#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B                           4
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W                           4
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M                           0xF0
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE                         0x0

#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B                          8
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W                          4
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M                          0xF00
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE                        0x0

#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B                          12
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W                          4
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M                          0xF000
#define    SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE                        0x0

#define  SIO_HI_RA_RAM_VB_OFFSET0__A                                       0x420071
#define  SIO_HI_RA_RAM_VB_OFFSET0__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET0__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET0__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B                         0
#define    SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W                         16
#define    SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M                         0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE                       0x0


#define  SIO_HI_RA_RAM_VB_ENTRY1__A                                        0x420072
#define  SIO_HI_RA_RAM_VB_ENTRY1__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY1__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY1__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET1__A                                       0x420073
#define  SIO_HI_RA_RAM_VB_OFFSET1__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET1__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET1__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE                        0x0


#define  SIO_HI_RA_RAM_VB_ENTRY2__A                                        0x420074
#define  SIO_HI_RA_RAM_VB_ENTRY2__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY2__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY2__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET2__A                                       0x420075
#define  SIO_HI_RA_RAM_VB_OFFSET2__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET2__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET2__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE                        0x0


#define  SIO_HI_RA_RAM_VB_ENTRY3__A                                        0x420076
#define  SIO_HI_RA_RAM_VB_ENTRY3__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY3__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY3__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET3__A                                       0x420077
#define  SIO_HI_RA_RAM_VB_OFFSET3__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET3__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET3__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE                        0x0


#define  SIO_HI_RA_RAM_VB_ENTRY4__A                                        0x420078
#define  SIO_HI_RA_RAM_VB_ENTRY4__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY4__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY4__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET4__A                                       0x420079
#define  SIO_HI_RA_RAM_VB_OFFSET4__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET4__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET4__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE                        0x0


#define  SIO_HI_RA_RAM_VB_ENTRY5__A                                        0x42007A
#define  SIO_HI_RA_RAM_VB_ENTRY5__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY5__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY5__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET5__A                                       0x42007B
#define  SIO_HI_RA_RAM_VB_OFFSET5__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET5__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET5__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE                        0x0


#define  SIO_HI_RA_RAM_VB_ENTRY6__A                                        0x42007C
#define  SIO_HI_RA_RAM_VB_ENTRY6__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY6__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY6__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET6__A                                       0x42007D
#define  SIO_HI_RA_RAM_VB_OFFSET6__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET6__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET6__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE                        0x0


#define  SIO_HI_RA_RAM_VB_ENTRY7__A                                        0x42007E
#define  SIO_HI_RA_RAM_VB_ENTRY7__W                                        16
#define  SIO_HI_RA_RAM_VB_ENTRY7__M                                        0xFFFF
#define  SIO_HI_RA_RAM_VB_ENTRY7__PRE                                      0x0
#define  SIO_HI_RA_RAM_VB_OFFSET7__A                                       0x42007F
#define  SIO_HI_RA_RAM_VB_OFFSET7__W                                       16
#define  SIO_HI_RA_RAM_VB_OFFSET7__M                                       0xFFFF
#define  SIO_HI_RA_RAM_VB_OFFSET7__PRE                                     0x0

#define    SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B                          0
#define    SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W                          16
#define    SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M                          0xFFFF
#define    SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE                        0x0



#define  SIO_HI_IF_RAM_TRP_BPT_0__A                                        0x430000
#define  SIO_HI_IF_RAM_TRP_BPT_0__W                                        12
#define  SIO_HI_IF_RAM_TRP_BPT_0__M                                        0xFFF
#define  SIO_HI_IF_RAM_TRP_BPT_0__PRE                                      0x0
#define  SIO_HI_IF_RAM_TRP_BPT_1__A                                        0x430001
#define  SIO_HI_IF_RAM_TRP_BPT_1__W                                        12
#define  SIO_HI_IF_RAM_TRP_BPT_1__M                                        0xFFF
#define  SIO_HI_IF_RAM_TRP_BPT_1__PRE                                      0x0
#define  SIO_HI_IF_RAM_TRP_STK_0__A                                        0x430002
#define  SIO_HI_IF_RAM_TRP_STK_0__W                                        12
#define  SIO_HI_IF_RAM_TRP_STK_0__M                                        0xFFF
#define  SIO_HI_IF_RAM_TRP_STK_0__PRE                                      0x0
#define  SIO_HI_IF_RAM_TRP_STK_1__A                                        0x430003
#define  SIO_HI_IF_RAM_TRP_STK_1__W                                        12
#define  SIO_HI_IF_RAM_TRP_STK_1__M                                        0xFFF
#define  SIO_HI_IF_RAM_TRP_STK_1__PRE                                      0x0
#define  SIO_HI_IF_RAM_FUN_BASE__A                                         0x430300
#define  SIO_HI_IF_RAM_FUN_BASE__W                                         12
#define  SIO_HI_IF_RAM_FUN_BASE__M                                         0xFFF
#define  SIO_HI_IF_RAM_FUN_BASE__PRE                                       0x0



#define  SIO_HI_IF_COMM_EXEC__A                                            0x440000
#define  SIO_HI_IF_COMM_EXEC__W                                            2
#define  SIO_HI_IF_COMM_EXEC__M                                            0x3
#define  SIO_HI_IF_COMM_EXEC__PRE                                          0x0
#define    SIO_HI_IF_COMM_EXEC_STOP                                        0x0
#define    SIO_HI_IF_COMM_EXEC_ACTIVE                                      0x1
#define    SIO_HI_IF_COMM_EXEC_HOLD                                        0x2
#define    SIO_HI_IF_COMM_EXEC_STEP                                        0x3


#define  SIO_HI_IF_COMM_STATE__A                                           0x440001
#define  SIO_HI_IF_COMM_STATE__W                                           10
#define  SIO_HI_IF_COMM_STATE__M                                           0x3FF
#define  SIO_HI_IF_COMM_STATE__PRE                                         0x0
#define  SIO_HI_IF_COMM_INT_REQ__A                                         0x440003
#define  SIO_HI_IF_COMM_INT_REQ__W                                         1
#define  SIO_HI_IF_COMM_INT_REQ__M                                         0x1
#define  SIO_HI_IF_COMM_INT_REQ__PRE                                       0x0
#define  SIO_HI_IF_COMM_INT_STA__A                                         0x440005
#define  SIO_HI_IF_COMM_INT_STA__W                                         1
#define  SIO_HI_IF_COMM_INT_STA__M                                         0x1
#define  SIO_HI_IF_COMM_INT_STA__PRE                                       0x0
#define    SIO_HI_IF_COMM_INT_STA_STAT__B                                  0
#define    SIO_HI_IF_COMM_INT_STA_STAT__W                                  1
#define    SIO_HI_IF_COMM_INT_STA_STAT__M                                  0x1
#define    SIO_HI_IF_COMM_INT_STA_STAT__PRE                                0x0

#define  SIO_HI_IF_COMM_INT_MSK__A                                         0x440006
#define  SIO_HI_IF_COMM_INT_MSK__W                                         1
#define  SIO_HI_IF_COMM_INT_MSK__M                                         0x1
#define  SIO_HI_IF_COMM_INT_MSK__PRE                                       0x0
#define    SIO_HI_IF_COMM_INT_MSK_STAT__B                                  0
#define    SIO_HI_IF_COMM_INT_MSK_STAT__W                                  1
#define    SIO_HI_IF_COMM_INT_MSK_STAT__M                                  0x1
#define    SIO_HI_IF_COMM_INT_MSK_STAT__PRE                                0x0

#define  SIO_HI_IF_COMM_INT_STM__A                                         0x440007
#define  SIO_HI_IF_COMM_INT_STM__W                                         1
#define  SIO_HI_IF_COMM_INT_STM__M                                         0x1
#define  SIO_HI_IF_COMM_INT_STM__PRE                                       0x0
#define    SIO_HI_IF_COMM_INT_STM_STAT__B                                  0
#define    SIO_HI_IF_COMM_INT_STM_STAT__W                                  1
#define    SIO_HI_IF_COMM_INT_STM_STAT__M                                  0x1
#define    SIO_HI_IF_COMM_INT_STM_STAT__PRE                                0x0

#define  SIO_HI_IF_STK_0__A                                                0x440010
#define  SIO_HI_IF_STK_0__W                                                10
#define  SIO_HI_IF_STK_0__M                                                0x3FF
#define  SIO_HI_IF_STK_0__PRE                                              0x2

#define    SIO_HI_IF_STK_0_ADDR__B                                         0
#define    SIO_HI_IF_STK_0_ADDR__W                                         10
#define    SIO_HI_IF_STK_0_ADDR__M                                         0x3FF
#define    SIO_HI_IF_STK_0_ADDR__PRE                                       0x2

#define  SIO_HI_IF_STK_1__A                                                0x440011
#define  SIO_HI_IF_STK_1__W                                                10
#define  SIO_HI_IF_STK_1__M                                                0x3FF
#define  SIO_HI_IF_STK_1__PRE                                              0x2
#define    SIO_HI_IF_STK_1_ADDR__B                                         0
#define    SIO_HI_IF_STK_1_ADDR__W                                         10
#define    SIO_HI_IF_STK_1_ADDR__M                                         0x3FF
#define    SIO_HI_IF_STK_1_ADDR__PRE                                       0x2

#define  SIO_HI_IF_STK_2__A                                                0x440012
#define  SIO_HI_IF_STK_2__W                                                10
#define  SIO_HI_IF_STK_2__M                                                0x3FF
#define  SIO_HI_IF_STK_2__PRE                                              0x2
#define    SIO_HI_IF_STK_2_ADDR__B                                         0
#define    SIO_HI_IF_STK_2_ADDR__W                                         10
#define    SIO_HI_IF_STK_2_ADDR__M                                         0x3FF
#define    SIO_HI_IF_STK_2_ADDR__PRE                                       0x2

#define  SIO_HI_IF_STK_3__A                                                0x440013
#define  SIO_HI_IF_STK_3__W                                                10
#define  SIO_HI_IF_STK_3__M                                                0x3FF
#define  SIO_HI_IF_STK_3__PRE                                              0x2

#define    SIO_HI_IF_STK_3_ADDR__B                                         0
#define    SIO_HI_IF_STK_3_ADDR__W                                         10
#define    SIO_HI_IF_STK_3_ADDR__M                                         0x3FF
#define    SIO_HI_IF_STK_3_ADDR__PRE                                       0x2

#define  SIO_HI_IF_BPT_IDX__A                                              0x44001F
#define  SIO_HI_IF_BPT_IDX__W                                              1
#define  SIO_HI_IF_BPT_IDX__M                                              0x1
#define  SIO_HI_IF_BPT_IDX__PRE                                            0x0

#define    SIO_HI_IF_BPT_IDX_ADDR__B                                       0
#define    SIO_HI_IF_BPT_IDX_ADDR__W                                       1
#define    SIO_HI_IF_BPT_IDX_ADDR__M                                       0x1
#define    SIO_HI_IF_BPT_IDX_ADDR__PRE                                     0x0

#define  SIO_HI_IF_BPT__A                                                  0x440020
#define  SIO_HI_IF_BPT__W                                                  10
#define  SIO_HI_IF_BPT__M                                                  0x3FF
#define  SIO_HI_IF_BPT__PRE                                                0x2

#define    SIO_HI_IF_BPT_ADDR__B                                           0
#define    SIO_HI_IF_BPT_ADDR__W                                           10
#define    SIO_HI_IF_BPT_ADDR__M                                           0x3FF
#define    SIO_HI_IF_BPT_ADDR__PRE                                         0x2



#define  SIO_CC_COMM_EXEC__A                                               0x450000
#define  SIO_CC_COMM_EXEC__W                                               2
#define  SIO_CC_COMM_EXEC__M                                               0x3
#define  SIO_CC_COMM_EXEC__PRE                                             0x0
#define    SIO_CC_COMM_EXEC_STOP                                           0x0
#define    SIO_CC_COMM_EXEC_ACTIVE                                         0x1
#define    SIO_CC_COMM_EXEC_HOLD                                           0x2

#define  SIO_CC_PLL_MODE__A                                                0x450010
#define  SIO_CC_PLL_MODE__W                                                6
#define  SIO_CC_PLL_MODE__M                                                0x3F
#define  SIO_CC_PLL_MODE__PRE                                              0x0

#define    SIO_CC_PLL_MODE_FREF_SEL__B                                     0
#define    SIO_CC_PLL_MODE_FREF_SEL__W                                     2
#define    SIO_CC_PLL_MODE_FREF_SEL__M                                     0x3
#define    SIO_CC_PLL_MODE_FREF_SEL__PRE                                   0x0
#define      SIO_CC_PLL_MODE_FREF_SEL_OHW                                  0x0
#define      SIO_CC_PLL_MODE_FREF_SEL_27_00                                0x1
#define      SIO_CC_PLL_MODE_FREF_SEL_20_25                                0x2
#define      SIO_CC_PLL_MODE_FREF_SEL_4_00                                 0x3

#define    SIO_CC_PLL_MODE_LOCKSEL__B                                      2
#define    SIO_CC_PLL_MODE_LOCKSEL__W                                      2
#define    SIO_CC_PLL_MODE_LOCKSEL__M                                      0xC
#define    SIO_CC_PLL_MODE_LOCKSEL__PRE                                    0x0

#define    SIO_CC_PLL_MODE_BYPASS__B                                       4
#define    SIO_CC_PLL_MODE_BYPASS__W                                       2
#define    SIO_CC_PLL_MODE_BYPASS__M                                       0x30
#define    SIO_CC_PLL_MODE_BYPASS__PRE                                     0x0
#define      SIO_CC_PLL_MODE_BYPASS_OHW                                    0x0
#define      SIO_CC_PLL_MODE_BYPASS_OFF                                    0x10
#define      SIO_CC_PLL_MODE_BYPASS_ON                                     0x20


#define  SIO_CC_PLL_TEST__A                                                0x450011
#define  SIO_CC_PLL_TEST__W                                                8
#define  SIO_CC_PLL_TEST__M                                                0xFF
#define  SIO_CC_PLL_TEST__PRE                                              0x0

#define  SIO_CC_PLL_LOCK__A                                                0x450012
#define  SIO_CC_PLL_LOCK__W                                                1
#define  SIO_CC_PLL_LOCK__M                                                0x1
#define  SIO_CC_PLL_LOCK__PRE                                              0x0
#define  SIO_CC_CLK_TEST__A                                                0x450013
#define  SIO_CC_CLK_TEST__W                                                8
#define  SIO_CC_CLK_TEST__M                                                0xFF
#define  SIO_CC_CLK_TEST__PRE                                              0x0

#define    SIO_CC_CLK_TEST_SEL1__B                                         0
#define    SIO_CC_CLK_TEST_SEL1__W                                         3
#define    SIO_CC_CLK_TEST_SEL1__M                                         0x7
#define    SIO_CC_CLK_TEST_SEL1__PRE                                       0x0

#define    SIO_CC_CLK_TEST_ENAB1__B                                        3
#define    SIO_CC_CLK_TEST_ENAB1__W                                        1
#define    SIO_CC_CLK_TEST_ENAB1__M                                        0x8
#define    SIO_CC_CLK_TEST_ENAB1__PRE                                      0x0

#define    SIO_CC_CLK_TEST_SEL2__B                                         4
#define    SIO_CC_CLK_TEST_SEL2__W                                         3
#define    SIO_CC_CLK_TEST_SEL2__M                                         0x70
#define    SIO_CC_CLK_TEST_SEL2__PRE                                       0x0

#define    SIO_CC_CLK_TEST_ENAB2__B                                        7
#define    SIO_CC_CLK_TEST_ENAB2__W                                        1
#define    SIO_CC_CLK_TEST_ENAB2__M                                        0x80
#define    SIO_CC_CLK_TEST_ENAB2__PRE                                      0x0

#define  SIO_CC_CLK_MODE__A                                                0x450014
#define  SIO_CC_CLK_MODE__W                                                7
#define  SIO_CC_CLK_MODE__M                                                0x7F
#define  SIO_CC_CLK_MODE__PRE                                              0x0

#define    SIO_CC_CLK_MODE_DELAY__B                                        0
#define    SIO_CC_CLK_MODE_DELAY__W                                        4
#define    SIO_CC_CLK_MODE_DELAY__M                                        0xF
#define    SIO_CC_CLK_MODE_DELAY__PRE                                      0x0

#define    SIO_CC_CLK_MODE_INVERT__B                                       4
#define    SIO_CC_CLK_MODE_INVERT__W                                       1
#define    SIO_CC_CLK_MODE_INVERT__M                                       0x10
#define    SIO_CC_CLK_MODE_INVERT__PRE                                     0x0

#define    SIO_CC_CLK_MODE_OFDM_ALIGN__B                                   5
#define    SIO_CC_CLK_MODE_OFDM_ALIGN__W                                   1
#define    SIO_CC_CLK_MODE_OFDM_ALIGN__M                                   0x20
#define    SIO_CC_CLK_MODE_OFDM_ALIGN__PRE                                 0x0

#define    SIO_CC_CLK_MODE_OFDM_DUTYC__B                                   6
#define    SIO_CC_CLK_MODE_OFDM_DUTYC__W                                   1
#define    SIO_CC_CLK_MODE_OFDM_DUTYC__M                                   0x40
#define    SIO_CC_CLK_MODE_OFDM_DUTYC__PRE                                 0x0

#define  SIO_CC_PWD_MODE__A                                                0x450015
#define  SIO_CC_PWD_MODE__W                                                4
#define  SIO_CC_PWD_MODE__M                                                0xF
#define  SIO_CC_PWD_MODE__PRE                                              0x0

#define    SIO_CC_PWD_MODE_LEVEL__B                                        0
#define    SIO_CC_PWD_MODE_LEVEL__W                                        3
#define    SIO_CC_PWD_MODE_LEVEL__M                                        0x7
#define    SIO_CC_PWD_MODE_LEVEL__PRE                                      0x0
#define      SIO_CC_PWD_MODE_LEVEL_NONE                                    0x0
#define      SIO_CC_PWD_MODE_LEVEL_OFDM                                    0x1
#define      SIO_CC_PWD_MODE_LEVEL_CLOCK                                   0x2
#define      SIO_CC_PWD_MODE_LEVEL_PLL                                     0x3
#define      SIO_CC_PWD_MODE_LEVEL_OSC                                     0x4

#define    SIO_CC_PWD_MODE_USE_LOCK__B                                     3
#define    SIO_CC_PWD_MODE_USE_LOCK__W                                     1
#define    SIO_CC_PWD_MODE_USE_LOCK__M                                     0x8
#define    SIO_CC_PWD_MODE_USE_LOCK__PRE                                   0x0

#define  SIO_CC_SOFT_RST__A                                                0x450016
#define  SIO_CC_SOFT_RST__W                                                3
#define  SIO_CC_SOFT_RST__M                                                0x7
#define  SIO_CC_SOFT_RST__PRE                                              0x0

#define    SIO_CC_SOFT_RST_OFDM__B                                         0
#define    SIO_CC_SOFT_RST_OFDM__W                                         1
#define    SIO_CC_SOFT_RST_OFDM__M                                         0x1
#define    SIO_CC_SOFT_RST_OFDM__PRE                                       0x0

#define    SIO_CC_SOFT_RST_SYS__B                                          1
#define    SIO_CC_SOFT_RST_SYS__W                                          1
#define    SIO_CC_SOFT_RST_SYS__M                                          0x2
#define    SIO_CC_SOFT_RST_SYS__PRE                                        0x0

#define    SIO_CC_SOFT_RST_OSC__B                                          2
#define    SIO_CC_SOFT_RST_OSC__W                                          1
#define    SIO_CC_SOFT_RST_OSC__M                                          0x4
#define    SIO_CC_SOFT_RST_OSC__PRE                                        0x0


#define  SIO_CC_UPDATE__A                                                  0x450017
#define  SIO_CC_UPDATE__W                                                  16
#define  SIO_CC_UPDATE__M                                                  0xFFFF
#define  SIO_CC_UPDATE__PRE                                                0x0
#define    SIO_CC_UPDATE_KEY                                               0xFABA



#define  SIO_SA_COMM_EXEC__A                                               0x460000
#define  SIO_SA_COMM_EXEC__W                                               2
#define  SIO_SA_COMM_EXEC__M                                               0x3
#define  SIO_SA_COMM_EXEC__PRE                                             0x0
#define    SIO_SA_COMM_EXEC_STOP                                           0x0
#define    SIO_SA_COMM_EXEC_ACTIVE                                         0x1
#define    SIO_SA_COMM_EXEC_HOLD                                           0x2

#define  SIO_SA_COMM_INT_REQ__A                                            0x460003
#define  SIO_SA_COMM_INT_REQ__W                                            1
#define  SIO_SA_COMM_INT_REQ__M                                            0x1
#define  SIO_SA_COMM_INT_REQ__PRE                                          0x0
#define  SIO_SA_COMM_INT_STA__A                                            0x460005
#define  SIO_SA_COMM_INT_STA__W                                            4
#define  SIO_SA_COMM_INT_STA__M                                            0xF
#define  SIO_SA_COMM_INT_STA__PRE                                          0x0

#define    SIO_SA_COMM_INT_STA_TR_END_INT_STA__B                           0
#define    SIO_SA_COMM_INT_STA_TR_END_INT_STA__W                           1
#define    SIO_SA_COMM_INT_STA_TR_END_INT_STA__M                           0x1
#define    SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE                         0x0

#define    SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B                        1
#define    SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W                        1
#define    SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M                        0x2
#define    SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE                      0x0

#define    SIO_SA_COMM_INT_STA_RX_END_INT_STA__B                           2
#define    SIO_SA_COMM_INT_STA_RX_END_INT_STA__W                           1
#define    SIO_SA_COMM_INT_STA_RX_END_INT_STA__M                           0x4
#define    SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE                         0x0

#define    SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B                         3
#define    SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W                         1
#define    SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M                         0x8
#define    SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE                       0x0

#define  SIO_SA_COMM_INT_MSK__A                                            0x460006
#define  SIO_SA_COMM_INT_MSK__W                                            4
#define  SIO_SA_COMM_INT_MSK__M                                            0xF
#define  SIO_SA_COMM_INT_MSK__PRE                                          0x0

#define    SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B                          0
#define    SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W                          1
#define    SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M                          0x1
#define    SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE                        0x0

#define    SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B                       1
#define    SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W                       1
#define    SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M                       0x2
#define    SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE                     0x0

#define    SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B                          2
#define    SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W                          1
#define    SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M                          0x4
#define    SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE                        0x0

#define    SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B                        3
#define    SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W                        1
#define    SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M                        0x8
#define    SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE                      0x0

#define  SIO_SA_COMM_INT_STM__A                                            0x460007
#define  SIO_SA_COMM_INT_STM__W                                            4
#define  SIO_SA_COMM_INT_STM__M                                            0xF
#define  SIO_SA_COMM_INT_STM__PRE                                          0x0

#define    SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B                          0
#define    SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W                          1
#define    SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M                          0x1
#define    SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE                        0x0

#define    SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B                       1
#define    SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W                       1
#define    SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M                       0x2
#define    SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE                     0x0

#define    SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B                          2
#define    SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W                          1
#define    SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M                          0x4
#define    SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE                        0x0

#define    SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B                        3
#define    SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W                        1
#define    SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M                        0x8
#define    SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE                      0x0

#define  SIO_SA_PRESCALER__A                                               0x460010
#define  SIO_SA_PRESCALER__W                                               13
#define  SIO_SA_PRESCALER__M                                               0x1FFF
#define  SIO_SA_PRESCALER__PRE                                             0x18B7
#define  SIO_SA_TX_DATA0__A                                                0x460011
#define  SIO_SA_TX_DATA0__W                                                16
#define  SIO_SA_TX_DATA0__M                                                0xFFFF
#define  SIO_SA_TX_DATA0__PRE                                              0x0
#define  SIO_SA_TX_DATA1__A                                                0x460012
#define  SIO_SA_TX_DATA1__W                                                16
#define  SIO_SA_TX_DATA1__M                                                0xFFFF
#define  SIO_SA_TX_DATA1__PRE                                              0x0
#define  SIO_SA_TX_DATA2__A                                                0x460013
#define  SIO_SA_TX_DATA2__W                                                16
#define  SIO_SA_TX_DATA2__M                                                0xFFFF
#define  SIO_SA_TX_DATA2__PRE                                              0x0
#define  SIO_SA_TX_DATA3__A                                                0x460014
#define  SIO_SA_TX_DATA3__W                                                16
#define  SIO_SA_TX_DATA3__M                                                0xFFFF
#define  SIO_SA_TX_DATA3__PRE                                              0x0
#define  SIO_SA_TX_LENGTH__A                                               0x460015
#define  SIO_SA_TX_LENGTH__W                                               6
#define  SIO_SA_TX_LENGTH__M                                               0x3F
#define  SIO_SA_TX_LENGTH__PRE                                             0x0
#define  SIO_SA_TX_COMMAND__A                                              0x460016
#define  SIO_SA_TX_COMMAND__W                                              2
#define  SIO_SA_TX_COMMAND__M                                              0x3
#define  SIO_SA_TX_COMMAND__PRE                                            0x3

#define    SIO_SA_TX_COMMAND_TX_INVERT__B                                  0
#define    SIO_SA_TX_COMMAND_TX_INVERT__W                                  1
#define    SIO_SA_TX_COMMAND_TX_INVERT__M                                  0x1
#define    SIO_SA_TX_COMMAND_TX_INVERT__PRE                                0x1

#define    SIO_SA_TX_COMMAND_TX_ENABLE__B                                  1
#define    SIO_SA_TX_COMMAND_TX_ENABLE__W                                  1
#define    SIO_SA_TX_COMMAND_TX_ENABLE__M                                  0x2
#define    SIO_SA_TX_COMMAND_TX_ENABLE__PRE                                0x2

#define  SIO_SA_TX_STATUS__A                                               0x460017
#define  SIO_SA_TX_STATUS__W                                               2
#define  SIO_SA_TX_STATUS__M                                               0x3
#define  SIO_SA_TX_STATUS__PRE                                             0x0

#define    SIO_SA_TX_STATUS_BUSY__B                                        0
#define    SIO_SA_TX_STATUS_BUSY__W                                        1
#define    SIO_SA_TX_STATUS_BUSY__M                                        0x1
#define    SIO_SA_TX_STATUS_BUSY__PRE                                      0x0

#define    SIO_SA_TX_STATUS_BUFF_FULL__B                                   1
#define    SIO_SA_TX_STATUS_BUFF_FULL__W                                   1
#define    SIO_SA_TX_STATUS_BUFF_FULL__M                                   0x2
#define    SIO_SA_TX_STATUS_BUFF_FULL__PRE                                 0x0

#define  SIO_SA_RX_DATA0__A                                                0x460018
#define  SIO_SA_RX_DATA0__W                                                16
#define  SIO_SA_RX_DATA0__M                                                0xFFFF
#define  SIO_SA_RX_DATA0__PRE                                              0x0
#define  SIO_SA_RX_DATA1__A                                                0x460019
#define  SIO_SA_RX_DATA1__W                                                16
#define  SIO_SA_RX_DATA1__M                                                0xFFFF
#define  SIO_SA_RX_DATA1__PRE                                              0x0
#define  SIO_SA_RX_LENGTH__A                                               0x46001A
#define  SIO_SA_RX_LENGTH__W                                               6
#define  SIO_SA_RX_LENGTH__M                                               0x3F
#define  SIO_SA_RX_LENGTH__PRE                                             0x0
#define  SIO_SA_RX_COMMAND__A                                              0x46001B
#define  SIO_SA_RX_COMMAND__W                                              1
#define  SIO_SA_RX_COMMAND__M                                              0x1
#define  SIO_SA_RX_COMMAND__PRE                                            0x1

#define    SIO_SA_RX_COMMAND_RX_INVERT__B                                  0
#define    SIO_SA_RX_COMMAND_RX_INVERT__W                                  1
#define    SIO_SA_RX_COMMAND_RX_INVERT__M                                  0x1
#define    SIO_SA_RX_COMMAND_RX_INVERT__PRE                                0x1

#define  SIO_SA_RX_STATUS__A                                               0x46001C
#define  SIO_SA_RX_STATUS__W                                               2
#define  SIO_SA_RX_STATUS__M                                               0x3
#define  SIO_SA_RX_STATUS__PRE                                             0x0

#define    SIO_SA_RX_STATUS_BUSY__B                                        0
#define    SIO_SA_RX_STATUS_BUSY__W                                        1
#define    SIO_SA_RX_STATUS_BUSY__M                                        0x1
#define    SIO_SA_RX_STATUS_BUSY__PRE                                      0x0

#define    SIO_SA_RX_STATUS_BUFF_FULL__B                                   1
#define    SIO_SA_RX_STATUS_BUFF_FULL__W                                   1
#define    SIO_SA_RX_STATUS_BUFF_FULL__M                                   0x2
#define    SIO_SA_RX_STATUS_BUFF_FULL__PRE                                 0x0



#define  SIO_OFDM_SH_COMM_EXEC__A                                          0x470000
#define  SIO_OFDM_SH_COMM_EXEC__W                                          2
#define  SIO_OFDM_SH_COMM_EXEC__M                                          0x3
#define  SIO_OFDM_SH_COMM_EXEC__PRE                                        0x0
#define    SIO_OFDM_SH_COMM_EXEC_STOP                                      0x0
#define    SIO_OFDM_SH_COMM_EXEC_ACTIVE                                    0x1
#define    SIO_OFDM_SH_COMM_EXEC_HOLD                                      0x2

#define  SIO_OFDM_SH_COMM_MB__A                                            0x470002
#define  SIO_OFDM_SH_COMM_MB__W                                            2
#define  SIO_OFDM_SH_COMM_MB__M                                            0x3
#define  SIO_OFDM_SH_COMM_MB__PRE                                          0x0
#define    SIO_OFDM_SH_COMM_MB_CTL__B                                      0
#define    SIO_OFDM_SH_COMM_MB_CTL__W                                      1
#define    SIO_OFDM_SH_COMM_MB_CTL__M                                      0x1
#define    SIO_OFDM_SH_COMM_MB_CTL__PRE                                    0x0
#define      SIO_OFDM_SH_COMM_MB_CTL_OFF                                   0x0
#define      SIO_OFDM_SH_COMM_MB_CTL_ON                                    0x1
#define    SIO_OFDM_SH_COMM_MB_OBS__B                                      1
#define    SIO_OFDM_SH_COMM_MB_OBS__W                                      1
#define    SIO_OFDM_SH_COMM_MB_OBS__M                                      0x2
#define    SIO_OFDM_SH_COMM_MB_OBS__PRE                                    0x0
#define      SIO_OFDM_SH_COMM_MB_OBS_OFF                                   0x0
#define      SIO_OFDM_SH_COMM_MB_OBS_ON                                    0x2

#define  SIO_OFDM_SH_OFDM_RING_ENABLE__A                                   0x470010
#define  SIO_OFDM_SH_OFDM_RING_ENABLE__W                                   1
#define  SIO_OFDM_SH_OFDM_RING_ENABLE__M                                   0x1
#define  SIO_OFDM_SH_OFDM_RING_ENABLE__PRE                                 0x0
#define    SIO_OFDM_SH_OFDM_RING_ENABLE_OFF                                0x0
#define    SIO_OFDM_SH_OFDM_RING_ENABLE_ON                                 0x1

#define  SIO_OFDM_SH_OFDM_MB_CONTROL__A                                    0x470011
#define  SIO_OFDM_SH_OFDM_MB_CONTROL__W                                    2
#define  SIO_OFDM_SH_OFDM_MB_CONTROL__M                                    0x3
#define  SIO_OFDM_SH_OFDM_MB_CONTROL__PRE                                  0x0

#define    SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B                              0
#define    SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W                              1
#define    SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M                              0x1
#define    SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE                            0x0
#define      SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN                          0x0
#define      SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM                          0x1

#define    SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B                              1
#define    SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W                              1
#define    SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M                              0x2
#define    SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE                            0x0
#define      SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS                        0x0
#define      SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM                          0x2

#define  SIO_OFDM_SH_OFDM_RING_STATUS__A                                   0x470012
#define  SIO_OFDM_SH_OFDM_RING_STATUS__W                                   1
#define  SIO_OFDM_SH_OFDM_RING_STATUS__M                                   0x1
#define  SIO_OFDM_SH_OFDM_RING_STATUS__PRE                                 0x0
#define    SIO_OFDM_SH_OFDM_RING_STATUS_DOWN                               0x0
#define    SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED                            0x1

#define  SIO_OFDM_SH_OFDM_MB_FLEN__A                                       0x470013
#define  SIO_OFDM_SH_OFDM_MB_FLEN__W                                       3
#define  SIO_OFDM_SH_OFDM_MB_FLEN__M                                       0x7
#define  SIO_OFDM_SH_OFDM_MB_FLEN__PRE                                     0x6
#define    SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B                                 0
#define    SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W                                 3
#define    SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M                                 0x7
#define    SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE                               0x6



#define  SIO_BL_COMM_EXEC__A                                               0x480000
#define  SIO_BL_COMM_EXEC__W                                               2
#define  SIO_BL_COMM_EXEC__M                                               0x3
#define  SIO_BL_COMM_EXEC__PRE                                             0x0
#define    SIO_BL_COMM_EXEC_STOP                                           0x0
#define    SIO_BL_COMM_EXEC_ACTIVE                                         0x1
#define    SIO_BL_COMM_EXEC_HOLD                                           0x2

#define  SIO_BL_COMM_INT_REQ__A                                            0x480003
#define  SIO_BL_COMM_INT_REQ__W                                            1
#define  SIO_BL_COMM_INT_REQ__M                                            0x1
#define  SIO_BL_COMM_INT_REQ__PRE                                          0x0
#define  SIO_BL_COMM_INT_STA__A                                            0x480005
#define  SIO_BL_COMM_INT_STA__W                                            1
#define  SIO_BL_COMM_INT_STA__M                                            0x1
#define  SIO_BL_COMM_INT_STA__PRE                                          0x0

#define    SIO_BL_COMM_INT_STA_DONE_INT_STA__B                             0
#define    SIO_BL_COMM_INT_STA_DONE_INT_STA__W                             1
#define    SIO_BL_COMM_INT_STA_DONE_INT_STA__M                             0x1
#define    SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE                           0x0

#define  SIO_BL_COMM_INT_MSK__A                                            0x480006
#define  SIO_BL_COMM_INT_MSK__W                                            1
#define  SIO_BL_COMM_INT_MSK__M                                            0x1
#define  SIO_BL_COMM_INT_MSK__PRE                                          0x0

#define    SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B                             0
#define    SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W                             1
#define    SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M                             0x1
#define    SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE                           0x0

#define  SIO_BL_COMM_INT_STM__A                                            0x480007
#define  SIO_BL_COMM_INT_STM__W                                            1
#define  SIO_BL_COMM_INT_STM__M                                            0x1
#define  SIO_BL_COMM_INT_STM__PRE                                          0x0

#define    SIO_BL_COMM_INT_STM_DONE_INT_MSK__B                             0
#define    SIO_BL_COMM_INT_STM_DONE_INT_MSK__W                             1
#define    SIO_BL_COMM_INT_STM_DONE_INT_MSK__M                             0x1
#define    SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE                           0x0

#define  SIO_BL_STATUS__A                                                  0x480010
#define  SIO_BL_STATUS__W                                                  1
#define  SIO_BL_STATUS__M                                                  0x1
#define  SIO_BL_STATUS__PRE                                                0x0
#define  SIO_BL_MODE__A                                                    0x480011
#define  SIO_BL_MODE__W                                                    1
#define  SIO_BL_MODE__M                                                    0x1
#define  SIO_BL_MODE__PRE                                                  0x1
#define    SIO_BL_MODE_DIRECT                                              0x0
#define    SIO_BL_MODE_CHAIN                                               0x1

#define  SIO_BL_ENABLE__A                                                  0x480012
#define  SIO_BL_ENABLE__W                                                  1
#define  SIO_BL_ENABLE__M                                                  0x1
#define  SIO_BL_ENABLE__PRE                                                0x0
#define    SIO_BL_ENABLE_OFF                                               0x0
#define    SIO_BL_ENABLE_ON                                                0x1

#define  SIO_BL_TGT_HDR__A                                                 0x480014
#define  SIO_BL_TGT_HDR__W                                                 12
#define  SIO_BL_TGT_HDR__M                                                 0xFFF
#define  SIO_BL_TGT_HDR__PRE                                               0x0
#define    SIO_BL_TGT_HDR_BANK__B                                          0
#define    SIO_BL_TGT_HDR_BANK__W                                          6
#define    SIO_BL_TGT_HDR_BANK__M                                          0x3F
#define    SIO_BL_TGT_HDR_BANK__PRE                                        0x0
#define    SIO_BL_TGT_HDR_BLOCK__B                                         6
#define    SIO_BL_TGT_HDR_BLOCK__W                                         6
#define    SIO_BL_TGT_HDR_BLOCK__M                                         0xFC0
#define    SIO_BL_TGT_HDR_BLOCK__PRE                                       0x0

#define  SIO_BL_TGT_ADDR__A                                                0x480015
#define  SIO_BL_TGT_ADDR__W                                                16
#define  SIO_BL_TGT_ADDR__M                                                0xFFFF
#define  SIO_BL_TGT_ADDR__PRE                                              0x0
#define  SIO_BL_SRC_ADDR__A                                                0x480016
#define  SIO_BL_SRC_ADDR__W                                                16
#define  SIO_BL_SRC_ADDR__M                                                0xFFFF
#define  SIO_BL_SRC_ADDR__PRE                                              0x0
#define  SIO_BL_SRC_LEN__A                                                 0x480017
#define  SIO_BL_SRC_LEN__W                                                 16
#define  SIO_BL_SRC_LEN__M                                                 0xFFFF
#define  SIO_BL_SRC_LEN__PRE                                               0x0

#define  SIO_BL_CHAIN_ADDR__A                                              0x480018
#define  SIO_BL_CHAIN_ADDR__W                                              16
#define  SIO_BL_CHAIN_ADDR__M                                              0xFFFF
#define  SIO_BL_CHAIN_ADDR__PRE                                            0x0

#define  SIO_BL_CHAIN_LEN__A                                               0x480019
#define  SIO_BL_CHAIN_LEN__W                                               4
#define  SIO_BL_CHAIN_LEN__M                                               0xF
#define  SIO_BL_CHAIN_LEN__PRE                                             0x2



#define  SIO_OFDM_SH_TRB_R0_RAM__A                                         0x4C0000



#define  SIO_OFDM_SH_TRB_R1_RAM__A                                         0x4D0000



#define  SIO_BL_ROM__A                                                     0x4E0000



#define  SIO_PDR_COMM_EXEC__A                                              0x7F0000
#define  SIO_PDR_COMM_EXEC__W                                              2
#define  SIO_PDR_COMM_EXEC__M                                              0x3
#define  SIO_PDR_COMM_EXEC__PRE                                            0x0
#define    SIO_PDR_COMM_EXEC_STOP                                          0x0
#define    SIO_PDR_COMM_EXEC_ACTIVE                                        0x1
#define    SIO_PDR_COMM_EXEC_HOLD                                          0x2

#define  SIO_PDR_MON_CFG__A                                                0x7F0010
#define  SIO_PDR_MON_CFG__W                                                4
#define  SIO_PDR_MON_CFG__M                                                0xF
#define  SIO_PDR_MON_CFG__PRE                                              0x0

#define    SIO_PDR_MON_CFG_OSEL__B                                         0
#define    SIO_PDR_MON_CFG_OSEL__W                                         1
#define    SIO_PDR_MON_CFG_OSEL__M                                         0x1
#define    SIO_PDR_MON_CFG_OSEL__PRE                                       0x0

#define    SIO_PDR_MON_CFG_IACT__B                                         1
#define    SIO_PDR_MON_CFG_IACT__W                                         1
#define    SIO_PDR_MON_CFG_IACT__M                                         0x2
#define    SIO_PDR_MON_CFG_IACT__PRE                                       0x0

#define    SIO_PDR_MON_CFG_ISEL__B                                         2
#define    SIO_PDR_MON_CFG_ISEL__W                                         1
#define    SIO_PDR_MON_CFG_ISEL__M                                         0x4
#define    SIO_PDR_MON_CFG_ISEL__PRE                                       0x0

#define    SIO_PDR_MON_CFG_INV_CLK__B                                      3
#define    SIO_PDR_MON_CFG_INV_CLK__W                                      1
#define    SIO_PDR_MON_CFG_INV_CLK__M                                      0x8
#define    SIO_PDR_MON_CFG_INV_CLK__PRE                                    0x0

#define  SIO_PDR_SMA_RX_SEL__A                                             0x7F0012
#define  SIO_PDR_SMA_RX_SEL__W                                             4
#define  SIO_PDR_SMA_RX_SEL__M                                             0xF
#define  SIO_PDR_SMA_RX_SEL__PRE                                           0x0

#define    SIO_PDR_SMA_RX_SEL_SEL__B                                       0
#define    SIO_PDR_SMA_RX_SEL_SEL__W                                       4
#define    SIO_PDR_SMA_RX_SEL_SEL__M                                       0xF
#define    SIO_PDR_SMA_RX_SEL_SEL__PRE                                     0x0

#define  SIO_PDR_SILENT__A                                                 0x7F0013
#define  SIO_PDR_SILENT__W                                                 13
#define  SIO_PDR_SILENT__M                                                 0x1FFF
#define  SIO_PDR_SILENT__PRE                                               0x0

#define    SIO_PDR_SILENT_I2S_WS__B                                        0
#define    SIO_PDR_SILENT_I2S_WS__W                                        1
#define    SIO_PDR_SILENT_I2S_WS__M                                        0x1
#define    SIO_PDR_SILENT_I2S_WS__PRE                                      0x0

#define    SIO_PDR_SILENT_I2S_DA__B                                        1
#define    SIO_PDR_SILENT_I2S_DA__W                                        1
#define    SIO_PDR_SILENT_I2S_DA__M                                        0x2
#define    SIO_PDR_SILENT_I2S_DA__PRE                                      0x0

#define    SIO_PDR_SILENT_I2S_CL__B                                        2
#define    SIO_PDR_SILENT_I2S_CL__W                                        1
#define    SIO_PDR_SILENT_I2S_CL__M                                        0x4
#define    SIO_PDR_SILENT_I2S_CL__PRE                                      0x0

#define    SIO_PDR_SILENT_I2C_SCL2__B                                      3
#define    SIO_PDR_SILENT_I2C_SCL2__W                                      1
#define    SIO_PDR_SILENT_I2C_SCL2__M                                      0x8
#define    SIO_PDR_SILENT_I2C_SCL2__PRE                                    0x0

#define    SIO_PDR_SILENT_I2C_SDA2__B                                      4
#define    SIO_PDR_SILENT_I2C_SDA2__W                                      1
#define    SIO_PDR_SILENT_I2C_SDA2__M                                      0x10
#define    SIO_PDR_SILENT_I2C_SDA2__PRE                                    0x0

#define    SIO_PDR_SILENT_SMA_TX__B                                        8
#define    SIO_PDR_SILENT_SMA_TX__W                                        1
#define    SIO_PDR_SILENT_SMA_TX__M                                        0x100
#define    SIO_PDR_SILENT_SMA_TX__PRE                                      0x0

#define    SIO_PDR_SILENT_SMA_RX__B                                        9
#define    SIO_PDR_SILENT_SMA_RX__W                                        1
#define    SIO_PDR_SILENT_SMA_RX__M                                        0x200
#define    SIO_PDR_SILENT_SMA_RX__PRE                                      0x0

#define    SIO_PDR_SILENT_GPIO__B                                          10
#define    SIO_PDR_SILENT_GPIO__W                                          1
#define    SIO_PDR_SILENT_GPIO__M                                          0x400
#define    SIO_PDR_SILENT_GPIO__PRE                                        0x0

#define    SIO_PDR_SILENT_VSYNC__B                                         11
#define    SIO_PDR_SILENT_VSYNC__W                                         1
#define    SIO_PDR_SILENT_VSYNC__M                                         0x800
#define    SIO_PDR_SILENT_VSYNC__PRE                                       0x0

#define    SIO_PDR_SILENT_IRQN__B                                          12
#define    SIO_PDR_SILENT_IRQN__W                                          1
#define    SIO_PDR_SILENT_IRQN__M                                          0x1000
#define    SIO_PDR_SILENT_IRQN__PRE                                        0x0

#define  SIO_PDR_UIO_IN_LO__A                                              0x7F0014
#define  SIO_PDR_UIO_IN_LO__W                                              16
#define  SIO_PDR_UIO_IN_LO__M                                              0xFFFF
#define  SIO_PDR_UIO_IN_LO__PRE                                            0x0
#define    SIO_PDR_UIO_IN_LO_DATA__B                                       0
#define    SIO_PDR_UIO_IN_LO_DATA__W                                       16
#define    SIO_PDR_UIO_IN_LO_DATA__M                                       0xFFFF
#define    SIO_PDR_UIO_IN_LO_DATA__PRE                                     0x0

#define  SIO_PDR_UIO_IN_HI__A                                              0x7F0015
#define  SIO_PDR_UIO_IN_HI__W                                              14
#define  SIO_PDR_UIO_IN_HI__M                                              0x3FFF
#define  SIO_PDR_UIO_IN_HI__PRE                                            0x0
#define    SIO_PDR_UIO_IN_HI_DATA__B                                       0
#define    SIO_PDR_UIO_IN_HI_DATA__W                                       14
#define    SIO_PDR_UIO_IN_HI_DATA__M                                       0x3FFF
#define    SIO_PDR_UIO_IN_HI_DATA__PRE                                     0x0

#define  SIO_PDR_UIO_OUT_LO__A                                             0x7F0016
#define  SIO_PDR_UIO_OUT_LO__W                                             16
#define  SIO_PDR_UIO_OUT_LO__M                                             0xFFFF
#define  SIO_PDR_UIO_OUT_LO__PRE                                           0x0
#define    SIO_PDR_UIO_OUT_LO_DATA__B                                      0
#define    SIO_PDR_UIO_OUT_LO_DATA__W                                      16
#define    SIO_PDR_UIO_OUT_LO_DATA__M                                      0xFFFF
#define    SIO_PDR_UIO_OUT_LO_DATA__PRE                                    0x0

#define  SIO_PDR_UIO_OUT_HI__A                                             0x7F0017
#define  SIO_PDR_UIO_OUT_HI__W                                             14
#define  SIO_PDR_UIO_OUT_HI__M                                             0x3FFF
#define  SIO_PDR_UIO_OUT_HI__PRE                                           0x0
#define    SIO_PDR_UIO_OUT_HI_DATA__B                                      0
#define    SIO_PDR_UIO_OUT_HI_DATA__W                                      14
#define    SIO_PDR_UIO_OUT_HI_DATA__M                                      0x3FFF
#define    SIO_PDR_UIO_OUT_HI_DATA__PRE                                    0x0

#define  SIO_PDR_PWM1_MODE__A                                              0x7F0018
#define  SIO_PDR_PWM1_MODE__W                                              2
#define  SIO_PDR_PWM1_MODE__M                                              0x3
#define  SIO_PDR_PWM1_MODE__PRE                                            0x0
#define  SIO_PDR_PWM1_PRESCALE__A                                          0x7F0019
#define  SIO_PDR_PWM1_PRESCALE__W                                          6
#define  SIO_PDR_PWM1_PRESCALE__M                                          0x3F
#define  SIO_PDR_PWM1_PRESCALE__PRE                                        0x0
#define  SIO_PDR_PWM1_VALUE__A                                             0x7F001A
#define  SIO_PDR_PWM1_VALUE__W                                             11
#define  SIO_PDR_PWM1_VALUE__M                                             0x7FF
#define  SIO_PDR_PWM1_VALUE__PRE                                           0x0

#define  SIO_PDR_IRQN_SEL__A                                               0x7F001B
#define  SIO_PDR_IRQN_SEL__W                                               4
#define  SIO_PDR_IRQN_SEL__M                                               0xF
#define  SIO_PDR_IRQN_SEL__PRE                                             0x3
#define  SIO_PDR_PWM2_MODE__A                                              0x7F001C
#define  SIO_PDR_PWM2_MODE__W                                              2
#define  SIO_PDR_PWM2_MODE__M                                              0x3
#define  SIO_PDR_PWM2_MODE__PRE                                            0x0
#define  SIO_PDR_PWM2_PRESCALE__A                                          0x7F001D
#define  SIO_PDR_PWM2_PRESCALE__W                                          6
#define  SIO_PDR_PWM2_PRESCALE__M                                          0x3F
#define  SIO_PDR_PWM2_PRESCALE__PRE                                        0x0
#define  SIO_PDR_PWM2_VALUE__A                                             0x7F001E
#define  SIO_PDR_PWM2_VALUE__W                                             11
#define  SIO_PDR_PWM2_VALUE__M                                             0x7FF
#define  SIO_PDR_PWM2_VALUE__PRE                                           0x0
#define  SIO_PDR_OHW_CFG__A                                                0x7F001F
#define  SIO_PDR_OHW_CFG__W                                                7
#define  SIO_PDR_OHW_CFG__M                                                0x7F
#define  SIO_PDR_OHW_CFG__PRE                                              0x0

#define    SIO_PDR_OHW_CFG_FREF_SEL__B                                     0
#define    SIO_PDR_OHW_CFG_FREF_SEL__W                                     2
#define    SIO_PDR_OHW_CFG_FREF_SEL__M                                     0x3
#define    SIO_PDR_OHW_CFG_FREF_SEL__PRE                                   0x0

#define    SIO_PDR_OHW_CFG_BYPASS__B                                       2
#define    SIO_PDR_OHW_CFG_BYPASS__W                                       1
#define    SIO_PDR_OHW_CFG_BYPASS__M                                       0x4
#define    SIO_PDR_OHW_CFG_BYPASS__PRE                                     0x0

#define    SIO_PDR_OHW_CFG_ASEL__B                                         3
#define    SIO_PDR_OHW_CFG_ASEL__W                                         3
#define    SIO_PDR_OHW_CFG_ASEL__M                                         0x38
#define    SIO_PDR_OHW_CFG_ASEL__PRE                                       0x0

#define    SIO_PDR_OHW_CFG_SPEED__B                                        6
#define    SIO_PDR_OHW_CFG_SPEED__W                                        1
#define    SIO_PDR_OHW_CFG_SPEED__M                                        0x40
#define    SIO_PDR_OHW_CFG_SPEED__PRE                                      0x0

#define  SIO_PDR_I2S_WS_CFG__A                                             0x7F0020
#define  SIO_PDR_I2S_WS_CFG__W                                             9
#define  SIO_PDR_I2S_WS_CFG__M                                             0x1FF
#define  SIO_PDR_I2S_WS_CFG__PRE                                           0x10
#define    SIO_PDR_I2S_WS_CFG_MODE__B                                      0
#define    SIO_PDR_I2S_WS_CFG_MODE__W                                      3
#define    SIO_PDR_I2S_WS_CFG_MODE__M                                      0x7
#define    SIO_PDR_I2S_WS_CFG_MODE__PRE                                    0x0
#define    SIO_PDR_I2S_WS_CFG_DRIVE__B                                     3
#define    SIO_PDR_I2S_WS_CFG_DRIVE__W                                     3
#define    SIO_PDR_I2S_WS_CFG_DRIVE__M                                     0x38
#define    SIO_PDR_I2S_WS_CFG_DRIVE__PRE                                   0x10
#define    SIO_PDR_I2S_WS_CFG_KEEP__B                                      6
#define    SIO_PDR_I2S_WS_CFG_KEEP__W                                      2
#define    SIO_PDR_I2S_WS_CFG_KEEP__M                                      0xC0
#define    SIO_PDR_I2S_WS_CFG_KEEP__PRE                                    0x0
#define    SIO_PDR_I2S_WS_CFG_UIO__B                                       8
#define    SIO_PDR_I2S_WS_CFG_UIO__W                                       1
#define    SIO_PDR_I2S_WS_CFG_UIO__M                                       0x100
#define    SIO_PDR_I2S_WS_CFG_UIO__PRE                                     0x0

#define  SIO_PDR_GPIO_CFG__A                                               0x7F0021
#define  SIO_PDR_GPIO_CFG__W                                               9
#define  SIO_PDR_GPIO_CFG__M                                               0x1FF
#define  SIO_PDR_GPIO_CFG__PRE                                             0x10
#define    SIO_PDR_GPIO_CFG_MODE__B                                        0
#define    SIO_PDR_GPIO_CFG_MODE__W                                        3
#define    SIO_PDR_GPIO_CFG_MODE__M                                        0x7
#define    SIO_PDR_GPIO_CFG_MODE__PRE                                      0x0
#define    SIO_PDR_GPIO_CFG_DRIVE__B                                       3
#define    SIO_PDR_GPIO_CFG_DRIVE__W                                       3
#define    SIO_PDR_GPIO_CFG_DRIVE__M                                       0x38
#define    SIO_PDR_GPIO_CFG_DRIVE__PRE                                     0x10
#define    SIO_PDR_GPIO_CFG_KEEP__B                                        6
#define    SIO_PDR_GPIO_CFG_KEEP__W                                        2
#define    SIO_PDR_GPIO_CFG_KEEP__M                                        0xC0
#define    SIO_PDR_GPIO_CFG_KEEP__PRE                                      0x0
#define    SIO_PDR_GPIO_CFG_UIO__B                                         8
#define    SIO_PDR_GPIO_CFG_UIO__W                                         1
#define    SIO_PDR_GPIO_CFG_UIO__M                                         0x100
#define    SIO_PDR_GPIO_CFG_UIO__PRE                                       0x0

#define  SIO_PDR_MSTRT_CFG__A                                              0x7F0025
#define  SIO_PDR_MSTRT_CFG__W                                              9
#define  SIO_PDR_MSTRT_CFG__M                                              0x1FF
#define  SIO_PDR_MSTRT_CFG__PRE                                            0x50
#define    SIO_PDR_MSTRT_CFG_MODE__B                                       0
#define    SIO_PDR_MSTRT_CFG_MODE__W                                       3
#define    SIO_PDR_MSTRT_CFG_MODE__M                                       0x7
#define    SIO_PDR_MSTRT_CFG_MODE__PRE                                     0x0
#define    SIO_PDR_MSTRT_CFG_DRIVE__B                                      3
#define    SIO_PDR_MSTRT_CFG_DRIVE__W                                      3
#define    SIO_PDR_MSTRT_CFG_DRIVE__M                                      0x38
#define    SIO_PDR_MSTRT_CFG_DRIVE__PRE                                    0x10
#define    SIO_PDR_MSTRT_CFG_KEEP__B                                       6
#define    SIO_PDR_MSTRT_CFG_KEEP__W                                       2
#define    SIO_PDR_MSTRT_CFG_KEEP__M                                       0xC0
#define    SIO_PDR_MSTRT_CFG_KEEP__PRE                                     0x40
#define    SIO_PDR_MSTRT_CFG_UIO__B                                        8
#define    SIO_PDR_MSTRT_CFG_UIO__W                                        1
#define    SIO_PDR_MSTRT_CFG_UIO__M                                        0x100
#define    SIO_PDR_MSTRT_CFG_UIO__PRE                                      0x0

#define  SIO_PDR_MERR_CFG__A                                               0x7F0026
#define  SIO_PDR_MERR_CFG__W                                               9
#define  SIO_PDR_MERR_CFG__M                                               0x1FF
#define  SIO_PDR_MERR_CFG__PRE                                             0x50
#define    SIO_PDR_MERR_CFG_MODE__B                                        0
#define    SIO_PDR_MERR_CFG_MODE__W                                        3
#define    SIO_PDR_MERR_CFG_MODE__M                                        0x7
#define    SIO_PDR_MERR_CFG_MODE__PRE                                      0x0
#define    SIO_PDR_MERR_CFG_DRIVE__B                                       3
#define    SIO_PDR_MERR_CFG_DRIVE__W                                       3
#define    SIO_PDR_MERR_CFG_DRIVE__M                                       0x38
#define    SIO_PDR_MERR_CFG_DRIVE__PRE                                     0x10
#define    SIO_PDR_MERR_CFG_KEEP__B                                        6
#define    SIO_PDR_MERR_CFG_KEEP__W                                        2
#define    SIO_PDR_MERR_CFG_KEEP__M                                        0xC0
#define    SIO_PDR_MERR_CFG_KEEP__PRE                                      0x40
#define    SIO_PDR_MERR_CFG_UIO__B                                         8
#define    SIO_PDR_MERR_CFG_UIO__W                                         1
#define    SIO_PDR_MERR_CFG_UIO__M                                         0x100
#define    SIO_PDR_MERR_CFG_UIO__PRE                                       0x0

#define  SIO_PDR_MCLK_CFG__A                                               0x7F0028
#define  SIO_PDR_MCLK_CFG__W                                               9
#define  SIO_PDR_MCLK_CFG__M                                               0x1FF
#define  SIO_PDR_MCLK_CFG__PRE                                             0x50
#define    SIO_PDR_MCLK_CFG_MODE__B                                        0
#define    SIO_PDR_MCLK_CFG_MODE__W                                        3
#define    SIO_PDR_MCLK_CFG_MODE__M                                        0x7
#define    SIO_PDR_MCLK_CFG_MODE__PRE                                      0x0
#define    SIO_PDR_MCLK_CFG_DRIVE__B                                       3
#define    SIO_PDR_MCLK_CFG_DRIVE__W                                       3
#define    SIO_PDR_MCLK_CFG_DRIVE__M                                       0x38
#define    SIO_PDR_MCLK_CFG_DRIVE__PRE                                     0x10
#define    SIO_PDR_MCLK_CFG_KEEP__B                                        6
#define    SIO_PDR_MCLK_CFG_KEEP__W                                        2
#define    SIO_PDR_MCLK_CFG_KEEP__M                                        0xC0
#define    SIO_PDR_MCLK_CFG_KEEP__PRE                                      0x40
#define    SIO_PDR_MCLK_CFG_UIO__B                                         8
#define    SIO_PDR_MCLK_CFG_UIO__W                                         1
#define    SIO_PDR_MCLK_CFG_UIO__M                                         0x100
#define    SIO_PDR_MCLK_CFG_UIO__PRE                                       0x0

#define  SIO_PDR_MVAL_CFG__A                                               0x7F0029
#define  SIO_PDR_MVAL_CFG__W                                               9
#define  SIO_PDR_MVAL_CFG__M                                               0x1FF
#define  SIO_PDR_MVAL_CFG__PRE                                             0x50
#define    SIO_PDR_MVAL_CFG_MODE__B                                        0
#define    SIO_PDR_MVAL_CFG_MODE__W                                        3
#define    SIO_PDR_MVAL_CFG_MODE__M                                        0x7
#define    SIO_PDR_MVAL_CFG_MODE__PRE                                      0x0
#define    SIO_PDR_MVAL_CFG_DRIVE__B                                       3
#define    SIO_PDR_MVAL_CFG_DRIVE__W                                       3
#define    SIO_PDR_MVAL_CFG_DRIVE__M                                       0x38
#define    SIO_PDR_MVAL_CFG_DRIVE__PRE                                     0x10
#define    SIO_PDR_MVAL_CFG_KEEP__B                                        6
#define    SIO_PDR_MVAL_CFG_KEEP__W                                        2
#define    SIO_PDR_MVAL_CFG_KEEP__M                                        0xC0
#define    SIO_PDR_MVAL_CFG_KEEP__PRE                                      0x40
#define    SIO_PDR_MVAL_CFG_UIO__B                                         8
#define    SIO_PDR_MVAL_CFG_UIO__W                                         1
#define    SIO_PDR_MVAL_CFG_UIO__M                                         0x100
#define    SIO_PDR_MVAL_CFG_UIO__PRE                                       0x0

#define  SIO_PDR_MD0_CFG__A                                                0x7F002A
#define  SIO_PDR_MD0_CFG__W                                                9
#define  SIO_PDR_MD0_CFG__M                                                0x1FF
#define  SIO_PDR_MD0_CFG__PRE                                              0x50
#define    SIO_PDR_MD0_CFG_MODE__B                                         0
#define    SIO_PDR_MD0_CFG_MODE__W                                         3
#define    SIO_PDR_MD0_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD0_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD0_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD0_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD0_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD0_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD0_CFG_KEEP__B                                         6
#define    SIO_PDR_MD0_CFG_KEEP__W                                         2
#define    SIO_PDR_MD0_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD0_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD0_CFG_UIO__B                                          8
#define    SIO_PDR_MD0_CFG_UIO__W                                          1
#define    SIO_PDR_MD0_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD0_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD1_CFG__A                                                0x7F002B
#define  SIO_PDR_MD1_CFG__W                                                9
#define  SIO_PDR_MD1_CFG__M                                                0x1FF
#define  SIO_PDR_MD1_CFG__PRE                                              0x50
#define    SIO_PDR_MD1_CFG_MODE__B                                         0
#define    SIO_PDR_MD1_CFG_MODE__W                                         3
#define    SIO_PDR_MD1_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD1_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD1_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD1_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD1_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD1_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD1_CFG_KEEP__B                                         6
#define    SIO_PDR_MD1_CFG_KEEP__W                                         2
#define    SIO_PDR_MD1_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD1_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD1_CFG_UIO__B                                          8
#define    SIO_PDR_MD1_CFG_UIO__W                                          1
#define    SIO_PDR_MD1_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD1_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD2_CFG__A                                                0x7F002C
#define  SIO_PDR_MD2_CFG__W                                                9
#define  SIO_PDR_MD2_CFG__M                                                0x1FF
#define  SIO_PDR_MD2_CFG__PRE                                              0x50
#define    SIO_PDR_MD2_CFG_MODE__B                                         0
#define    SIO_PDR_MD2_CFG_MODE__W                                         3
#define    SIO_PDR_MD2_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD2_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD2_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD2_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD2_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD2_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD2_CFG_KEEP__B                                         6
#define    SIO_PDR_MD2_CFG_KEEP__W                                         2
#define    SIO_PDR_MD2_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD2_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD2_CFG_UIO__B                                          8
#define    SIO_PDR_MD2_CFG_UIO__W                                          1
#define    SIO_PDR_MD2_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD2_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD3_CFG__A                                                0x7F002D
#define  SIO_PDR_MD3_CFG__W                                                9
#define  SIO_PDR_MD3_CFG__M                                                0x1FF
#define  SIO_PDR_MD3_CFG__PRE                                              0x50
#define    SIO_PDR_MD3_CFG_MODE__B                                         0
#define    SIO_PDR_MD3_CFG_MODE__W                                         3
#define    SIO_PDR_MD3_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD3_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD3_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD3_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD3_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD3_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD3_CFG_KEEP__B                                         6
#define    SIO_PDR_MD3_CFG_KEEP__W                                         2
#define    SIO_PDR_MD3_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD3_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD3_CFG_UIO__B                                          8
#define    SIO_PDR_MD3_CFG_UIO__W                                          1
#define    SIO_PDR_MD3_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD3_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD4_CFG__A                                                0x7F002F
#define  SIO_PDR_MD4_CFG__W                                                9
#define  SIO_PDR_MD4_CFG__M                                                0x1FF
#define  SIO_PDR_MD4_CFG__PRE                                              0x50
#define    SIO_PDR_MD4_CFG_MODE__B                                         0
#define    SIO_PDR_MD4_CFG_MODE__W                                         3
#define    SIO_PDR_MD4_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD4_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD4_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD4_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD4_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD4_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD4_CFG_KEEP__B                                         6
#define    SIO_PDR_MD4_CFG_KEEP__W                                         2
#define    SIO_PDR_MD4_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD4_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD4_CFG_UIO__B                                          8
#define    SIO_PDR_MD4_CFG_UIO__W                                          1
#define    SIO_PDR_MD4_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD4_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD5_CFG__A                                                0x7F0030
#define  SIO_PDR_MD5_CFG__W                                                9
#define  SIO_PDR_MD5_CFG__M                                                0x1FF
#define  SIO_PDR_MD5_CFG__PRE                                              0x50
#define    SIO_PDR_MD5_CFG_MODE__B                                         0
#define    SIO_PDR_MD5_CFG_MODE__W                                         3
#define    SIO_PDR_MD5_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD5_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD5_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD5_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD5_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD5_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD5_CFG_KEEP__B                                         6
#define    SIO_PDR_MD5_CFG_KEEP__W                                         2
#define    SIO_PDR_MD5_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD5_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD5_CFG_UIO__B                                          8
#define    SIO_PDR_MD5_CFG_UIO__W                                          1
#define    SIO_PDR_MD5_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD5_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD6_CFG__A                                                0x7F0031
#define  SIO_PDR_MD6_CFG__W                                                9
#define  SIO_PDR_MD6_CFG__M                                                0x1FF
#define  SIO_PDR_MD6_CFG__PRE                                              0x50
#define    SIO_PDR_MD6_CFG_MODE__B                                         0
#define    SIO_PDR_MD6_CFG_MODE__W                                         3
#define    SIO_PDR_MD6_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD6_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD6_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD6_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD6_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD6_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD6_CFG_KEEP__B                                         6
#define    SIO_PDR_MD6_CFG_KEEP__W                                         2
#define    SIO_PDR_MD6_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD6_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD6_CFG_UIO__B                                          8
#define    SIO_PDR_MD6_CFG_UIO__W                                          1
#define    SIO_PDR_MD6_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD6_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_MD7_CFG__A                                                0x7F0032
#define  SIO_PDR_MD7_CFG__W                                                9
#define  SIO_PDR_MD7_CFG__M                                                0x1FF
#define  SIO_PDR_MD7_CFG__PRE                                              0x50
#define    SIO_PDR_MD7_CFG_MODE__B                                         0
#define    SIO_PDR_MD7_CFG_MODE__W                                         3
#define    SIO_PDR_MD7_CFG_MODE__M                                         0x7
#define    SIO_PDR_MD7_CFG_MODE__PRE                                       0x0
#define    SIO_PDR_MD7_CFG_DRIVE__B                                        3
#define    SIO_PDR_MD7_CFG_DRIVE__W                                        3
#define    SIO_PDR_MD7_CFG_DRIVE__M                                        0x38
#define    SIO_PDR_MD7_CFG_DRIVE__PRE                                      0x10
#define    SIO_PDR_MD7_CFG_KEEP__B                                         6
#define    SIO_PDR_MD7_CFG_KEEP__W                                         2
#define    SIO_PDR_MD7_CFG_KEEP__M                                         0xC0
#define    SIO_PDR_MD7_CFG_KEEP__PRE                                       0x40
#define    SIO_PDR_MD7_CFG_UIO__B                                          8
#define    SIO_PDR_MD7_CFG_UIO__W                                          1
#define    SIO_PDR_MD7_CFG_UIO__M                                          0x100
#define    SIO_PDR_MD7_CFG_UIO__PRE                                        0x0

#define  SIO_PDR_I2C_SCL1_CFG__A                                           0x7F0033
#define  SIO_PDR_I2C_SCL1_CFG__W                                           9
#define  SIO_PDR_I2C_SCL1_CFG__M                                           0x1FF
#define  SIO_PDR_I2C_SCL1_CFG__PRE                                         0x11
#define    SIO_PDR_I2C_SCL1_CFG_MODE__B                                    0
#define    SIO_PDR_I2C_SCL1_CFG_MODE__W                                    3
#define    SIO_PDR_I2C_SCL1_CFG_MODE__M                                    0x7
#define    SIO_PDR_I2C_SCL1_CFG_MODE__PRE                                  0x1
#define    SIO_PDR_I2C_SCL1_CFG_DRIVE__B                                   3
#define    SIO_PDR_I2C_SCL1_CFG_DRIVE__W                                   3
#define    SIO_PDR_I2C_SCL1_CFG_DRIVE__M                                   0x38
#define    SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE                                 0x10
#define    SIO_PDR_I2C_SCL1_CFG_KEEP__B                                    6
#define    SIO_PDR_I2C_SCL1_CFG_KEEP__W                                    2
#define    SIO_PDR_I2C_SCL1_CFG_KEEP__M                                    0xC0
#define    SIO_PDR_I2C_SCL1_CFG_KEEP__PRE                                  0x0
#define    SIO_PDR_I2C_SCL1_CFG_UIO__B                                     8
#define    SIO_PDR_I2C_SCL1_CFG_UIO__W                                     1
#define    SIO_PDR_I2C_SCL1_CFG_UIO__M                                     0x100
#define    SIO_PDR_I2C_SCL1_CFG_UIO__PRE                                   0x0

#define  SIO_PDR_I2C_SDA1_CFG__A                                           0x7F0034
#define  SIO_PDR_I2C_SDA1_CFG__W                                           9
#define  SIO_PDR_I2C_SDA1_CFG__M                                           0x1FF
#define  SIO_PDR_I2C_SDA1_CFG__PRE                                         0x11
#define    SIO_PDR_I2C_SDA1_CFG_MODE__B                                    0
#define    SIO_PDR_I2C_SDA1_CFG_MODE__W                                    3
#define    SIO_PDR_I2C_SDA1_CFG_MODE__M                                    0x7
#define    SIO_PDR_I2C_SDA1_CFG_MODE__PRE                                  0x1
#define    SIO_PDR_I2C_SDA1_CFG_DRIVE__B                                   3
#define    SIO_PDR_I2C_SDA1_CFG_DRIVE__W                                   3
#define    SIO_PDR_I2C_SDA1_CFG_DRIVE__M                                   0x38
#define    SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE                                 0x10
#define    SIO_PDR_I2C_SDA1_CFG_KEEP__B                                    6
#define    SIO_PDR_I2C_SDA1_CFG_KEEP__W                                    2
#define    SIO_PDR_I2C_SDA1_CFG_KEEP__M                                    0xC0
#define    SIO_PDR_I2C_SDA1_CFG_KEEP__PRE                                  0x0
#define    SIO_PDR_I2C_SDA1_CFG_UIO__B                                     8
#define    SIO_PDR_I2C_SDA1_CFG_UIO__W                                     1
#define    SIO_PDR_I2C_SDA1_CFG_UIO__M                                     0x100
#define    SIO_PDR_I2C_SDA1_CFG_UIO__PRE                                   0x0

#define  SIO_PDR_VSYNC_CFG__A                                              0x7F0036
#define  SIO_PDR_VSYNC_CFG__W                                              9
#define  SIO_PDR_VSYNC_CFG__M                                              0x1FF
#define  SIO_PDR_VSYNC_CFG__PRE                                            0x10
#define    SIO_PDR_VSYNC_CFG_MODE__B                                       0
#define    SIO_PDR_VSYNC_CFG_MODE__W                                       3
#define    SIO_PDR_VSYNC_CFG_MODE__M                                       0x7
#define    SIO_PDR_VSYNC_CFG_MODE__PRE                                     0x0
#define    SIO_PDR_VSYNC_CFG_DRIVE__B                                      3
#define    SIO_PDR_VSYNC_CFG_DRIVE__W                                      3
#define    SIO_PDR_VSYNC_CFG_DRIVE__M                                      0x38
#define    SIO_PDR_VSYNC_CFG_DRIVE__PRE                                    0x10
#define    SIO_PDR_VSYNC_CFG_KEEP__B                                       6
#define    SIO_PDR_VSYNC_CFG_KEEP__W                                       2
#define    SIO_PDR_VSYNC_CFG_KEEP__M                                       0xC0
#define    SIO_PDR_VSYNC_CFG_KEEP__PRE                                     0x0
#define    SIO_PDR_VSYNC_CFG_UIO__B                                        8
#define    SIO_PDR_VSYNC_CFG_UIO__W                                        1
#define    SIO_PDR_VSYNC_CFG_UIO__M                                        0x100
#define    SIO_PDR_VSYNC_CFG_UIO__PRE                                      0x0

#define  SIO_PDR_SMA_RX_CFG__A                                             0x7F0037
#define  SIO_PDR_SMA_RX_CFG__W                                             9
#define  SIO_PDR_SMA_RX_CFG__M                                             0x1FF
#define  SIO_PDR_SMA_RX_CFG__PRE                                           0x10
#define    SIO_PDR_SMA_RX_CFG_MODE__B                                      0
#define    SIO_PDR_SMA_RX_CFG_MODE__W                                      3
#define    SIO_PDR_SMA_RX_CFG_MODE__M                                      0x7
#define    SIO_PDR_SMA_RX_CFG_MODE__PRE                                    0x0
#define    SIO_PDR_SMA_RX_CFG_DRIVE__B                                     3
#define    SIO_PDR_SMA_RX_CFG_DRIVE__W                                     3
#define    SIO_PDR_SMA_RX_CFG_DRIVE__M                                     0x38
#define    SIO_PDR_SMA_RX_CFG_DRIVE__PRE                                   0x10
#define    SIO_PDR_SMA_RX_CFG_KEEP__B                                      6
#define    SIO_PDR_SMA_RX_CFG_KEEP__W                                      2
#define    SIO_PDR_SMA_RX_CFG_KEEP__M                                      0xC0
#define    SIO_PDR_SMA_RX_CFG_KEEP__PRE                                    0x0
#define    SIO_PDR_SMA_RX_CFG_UIO__B                                       8
#define    SIO_PDR_SMA_RX_CFG_UIO__W                                       1
#define    SIO_PDR_SMA_RX_CFG_UIO__M                                       0x100
#define    SIO_PDR_SMA_RX_CFG_UIO__PRE                                     0x0

#define  SIO_PDR_SMA_TX_CFG__A                                             0x7F0038
#define  SIO_PDR_SMA_TX_CFG__W                                             9
#define  SIO_PDR_SMA_TX_CFG__M                                             0x1FF
#define  SIO_PDR_SMA_TX_CFG__PRE                                           0x90
#define    SIO_PDR_SMA_TX_CFG_MODE__B                                      0
#define    SIO_PDR_SMA_TX_CFG_MODE__W                                      3
#define    SIO_PDR_SMA_TX_CFG_MODE__M                                      0x7
#define    SIO_PDR_SMA_TX_CFG_MODE__PRE                                    0x0
#define    SIO_PDR_SMA_TX_CFG_DRIVE__B                                     3
#define    SIO_PDR_SMA_TX_CFG_DRIVE__W                                     3
#define    SIO_PDR_SMA_TX_CFG_DRIVE__M                                     0x38
#define    SIO_PDR_SMA_TX_CFG_DRIVE__PRE                                   0x10
#define    SIO_PDR_SMA_TX_CFG_KEEP__B                                      6
#define    SIO_PDR_SMA_TX_CFG_KEEP__W                                      2
#define    SIO_PDR_SMA_TX_CFG_KEEP__M                                      0xC0
#define    SIO_PDR_SMA_TX_CFG_KEEP__PRE                                    0x80
#define    SIO_PDR_SMA_TX_CFG_UIO__B                                       8
#define    SIO_PDR_SMA_TX_CFG_UIO__W                                       1
#define    SIO_PDR_SMA_TX_CFG_UIO__M                                       0x100
#define    SIO_PDR_SMA_TX_CFG_UIO__PRE                                     0x0

#define  SIO_PDR_I2C_SDA2_CFG__A                                           0x7F003F
#define  SIO_PDR_I2C_SDA2_CFG__W                                           9
#define  SIO_PDR_I2C_SDA2_CFG__M                                           0x1FF
#define  SIO_PDR_I2C_SDA2_CFG__PRE                                         0x11
#define    SIO_PDR_I2C_SDA2_CFG_MODE__B                                    0
#define    SIO_PDR_I2C_SDA2_CFG_MODE__W                                    3
#define    SIO_PDR_I2C_SDA2_CFG_MODE__M                                    0x7
#define    SIO_PDR_I2C_SDA2_CFG_MODE__PRE                                  0x1
#define    SIO_PDR_I2C_SDA2_CFG_DRIVE__B                                   3
#define    SIO_PDR_I2C_SDA2_CFG_DRIVE__W                                   3
#define    SIO_PDR_I2C_SDA2_CFG_DRIVE__M                                   0x38
#define    SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE                                 0x10
#define    SIO_PDR_I2C_SDA2_CFG_KEEP__B                                    6
#define    SIO_PDR_I2C_SDA2_CFG_KEEP__W                                    2
#define    SIO_PDR_I2C_SDA2_CFG_KEEP__M                                    0xC0
#define    SIO_PDR_I2C_SDA2_CFG_KEEP__PRE                                  0x0
#define    SIO_PDR_I2C_SDA2_CFG_UIO__B                                     8
#define    SIO_PDR_I2C_SDA2_CFG_UIO__W                                     1
#define    SIO_PDR_I2C_SDA2_CFG_UIO__M                                     0x100
#define    SIO_PDR_I2C_SDA2_CFG_UIO__PRE                                   0x0

#define  SIO_PDR_I2C_SCL2_CFG__A                                           0x7F0040
#define  SIO_PDR_I2C_SCL2_CFG__W                                           9
#define  SIO_PDR_I2C_SCL2_CFG__M                                           0x1FF
#define  SIO_PDR_I2C_SCL2_CFG__PRE                                         0x11
#define    SIO_PDR_I2C_SCL2_CFG_MODE__B                                    0
#define    SIO_PDR_I2C_SCL2_CFG_MODE__W                                    3
#define    SIO_PDR_I2C_SCL2_CFG_MODE__M                                    0x7
#define    SIO_PDR_I2C_SCL2_CFG_MODE__PRE                                  0x1
#define    SIO_PDR_I2C_SCL2_CFG_DRIVE__B                                   3
#define    SIO_PDR_I2C_SCL2_CFG_DRIVE__W                                   3
#define    SIO_PDR_I2C_SCL2_CFG_DRIVE__M                                   0x38
#define    SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE                                 0x10
#define    SIO_PDR_I2C_SCL2_CFG_KEEP__B                                    6
#define    SIO_PDR_I2C_SCL2_CFG_KEEP__W                                    2
#define    SIO_PDR_I2C_SCL2_CFG_KEEP__M                                    0xC0
#define    SIO_PDR_I2C_SCL2_CFG_KEEP__PRE                                  0x0
#define    SIO_PDR_I2C_SCL2_CFG_UIO__B                                     8
#define    SIO_PDR_I2C_SCL2_CFG_UIO__W                                     1
#define    SIO_PDR_I2C_SCL2_CFG_UIO__M                                     0x100
#define    SIO_PDR_I2C_SCL2_CFG_UIO__PRE                                   0x0

#define  SIO_PDR_I2S_CL_CFG__A                                             0x7F0041
#define  SIO_PDR_I2S_CL_CFG__W                                             9
#define  SIO_PDR_I2S_CL_CFG__M                                             0x1FF
#define  SIO_PDR_I2S_CL_CFG__PRE                                           0x10
#define    SIO_PDR_I2S_CL_CFG_MODE__B                                      0
#define    SIO_PDR_I2S_CL_CFG_MODE__W                                      3
#define    SIO_PDR_I2S_CL_CFG_MODE__M                                      0x7
#define    SIO_PDR_I2S_CL_CFG_MODE__PRE                                    0x0
#define    SIO_PDR_I2S_CL_CFG_DRIVE__B                                     3
#define    SIO_PDR_I2S_CL_CFG_DRIVE__W                                     3
#define    SIO_PDR_I2S_CL_CFG_DRIVE__M                                     0x38
#define    SIO_PDR_I2S_CL_CFG_DRIVE__PRE                                   0x10
#define    SIO_PDR_I2S_CL_CFG_KEEP__B                                      6
#define    SIO_PDR_I2S_CL_CFG_KEEP__W                                      2
#define    SIO_PDR_I2S_CL_CFG_KEEP__M                                      0xC0
#define    SIO_PDR_I2S_CL_CFG_KEEP__PRE                                    0x0
#define    SIO_PDR_I2S_CL_CFG_UIO__B                                       8
#define    SIO_PDR_I2S_CL_CFG_UIO__W                                       1
#define    SIO_PDR_I2S_CL_CFG_UIO__M                                       0x100
#define    SIO_PDR_I2S_CL_CFG_UIO__PRE                                     0x0

#define  SIO_PDR_I2S_DA_CFG__A                                             0x7F0042
#define  SIO_PDR_I2S_DA_CFG__W                                             9
#define  SIO_PDR_I2S_DA_CFG__M                                             0x1FF
#define  SIO_PDR_I2S_DA_CFG__PRE                                           0x10
#define    SIO_PDR_I2S_DA_CFG_MODE__B                                      0
#define    SIO_PDR_I2S_DA_CFG_MODE__W                                      3
#define    SIO_PDR_I2S_DA_CFG_MODE__M                                      0x7
#define    SIO_PDR_I2S_DA_CFG_MODE__PRE                                    0x0
#define    SIO_PDR_I2S_DA_CFG_DRIVE__B                                     3
#define    SIO_PDR_I2S_DA_CFG_DRIVE__W                                     3
#define    SIO_PDR_I2S_DA_CFG_DRIVE__M                                     0x38
#define    SIO_PDR_I2S_DA_CFG_DRIVE__PRE                                   0x10
#define    SIO_PDR_I2S_DA_CFG_KEEP__B                                      6
#define    SIO_PDR_I2S_DA_CFG_KEEP__W                                      2
#define    SIO_PDR_I2S_DA_CFG_KEEP__M                                      0xC0
#define    SIO_PDR_I2S_DA_CFG_KEEP__PRE                                    0x0
#define    SIO_PDR_I2S_DA_CFG_UIO__B                                       8
#define    SIO_PDR_I2S_DA_CFG_UIO__W                                       1
#define    SIO_PDR_I2S_DA_CFG_UIO__M                                       0x100
#define    SIO_PDR_I2S_DA_CFG_UIO__PRE                                     0x0

#define  SIO_PDR_GPIO_GPIO_FNC__A                                          0x7F0050
#define  SIO_PDR_GPIO_GPIO_FNC__W                                          2
#define  SIO_PDR_GPIO_GPIO_FNC__M                                          0x3
#define  SIO_PDR_GPIO_GPIO_FNC__PRE                                        0x0
#define    SIO_PDR_GPIO_GPIO_FNC_SEL__B                                    0
#define    SIO_PDR_GPIO_GPIO_FNC_SEL__W                                    2
#define    SIO_PDR_GPIO_GPIO_FNC_SEL__M                                    0x3
#define    SIO_PDR_GPIO_GPIO_FNC_SEL__PRE                                  0x0

#define  SIO_PDR_MSTRT_GPIO_FNC__A                                         0x7F0052
#define  SIO_PDR_MSTRT_GPIO_FNC__W                                         2
#define  SIO_PDR_MSTRT_GPIO_FNC__M                                         0x3
#define  SIO_PDR_MSTRT_GPIO_FNC__PRE                                       0x0
#define    SIO_PDR_MSTRT_GPIO_FNC_SEL__B                                   0
#define    SIO_PDR_MSTRT_GPIO_FNC_SEL__W                                   2
#define    SIO_PDR_MSTRT_GPIO_FNC_SEL__M                                   0x3
#define    SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE                                 0x0

#define  SIO_PDR_MERR_GPIO_FNC__A                                          0x7F0053
#define  SIO_PDR_MERR_GPIO_FNC__W                                          2
#define  SIO_PDR_MERR_GPIO_FNC__M                                          0x3
#define  SIO_PDR_MERR_GPIO_FNC__PRE                                        0x0
#define    SIO_PDR_MERR_GPIO_FNC_SEL__B                                    0
#define    SIO_PDR_MERR_GPIO_FNC_SEL__W                                    2
#define    SIO_PDR_MERR_GPIO_FNC_SEL__M                                    0x3
#define    SIO_PDR_MERR_GPIO_FNC_SEL__PRE                                  0x0

#define  SIO_PDR_MCLK_GPIO_FNC__A                                          0x7F0054
#define  SIO_PDR_MCLK_GPIO_FNC__W                                          2
#define  SIO_PDR_MCLK_GPIO_FNC__M                                          0x3
#define  SIO_PDR_MCLK_GPIO_FNC__PRE                                        0x0
#define    SIO_PDR_MCLK_GPIO_FNC_SEL__B                                    0
#define    SIO_PDR_MCLK_GPIO_FNC_SEL__W                                    2
#define    SIO_PDR_MCLK_GPIO_FNC_SEL__M                                    0x3
#define    SIO_PDR_MCLK_GPIO_FNC_SEL__PRE                                  0x0

#define  SIO_PDR_MVAL_GPIO_FNC__A                                          0x7F0055
#define  SIO_PDR_MVAL_GPIO_FNC__W                                          2
#define  SIO_PDR_MVAL_GPIO_FNC__M                                          0x3
#define  SIO_PDR_MVAL_GPIO_FNC__PRE                                        0x0
#define    SIO_PDR_MVAL_GPIO_FNC_SEL__B                                    0
#define    SIO_PDR_MVAL_GPIO_FNC_SEL__W                                    2
#define    SIO_PDR_MVAL_GPIO_FNC_SEL__M                                    0x3
#define    SIO_PDR_MVAL_GPIO_FNC_SEL__PRE                                  0x0

#define  SIO_PDR_MD0_GPIO_FNC__A                                           0x7F0056
#define  SIO_PDR_MD0_GPIO_FNC__W                                           2
#define  SIO_PDR_MD0_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD0_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD0_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD0_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD0_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD0_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD1_GPIO_FNC__A                                           0x7F0057
#define  SIO_PDR_MD1_GPIO_FNC__W                                           2
#define  SIO_PDR_MD1_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD1_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD1_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD1_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD1_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD1_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD2_GPIO_FNC__A                                           0x7F0058
#define  SIO_PDR_MD2_GPIO_FNC__W                                           2
#define  SIO_PDR_MD2_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD2_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD2_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD2_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD2_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD2_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD3_GPIO_FNC__A                                           0x7F0059
#define  SIO_PDR_MD3_GPIO_FNC__W                                           2
#define  SIO_PDR_MD3_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD3_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD3_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD3_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD3_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD3_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD4_GPIO_FNC__A                                           0x7F005A
#define  SIO_PDR_MD4_GPIO_FNC__W                                           2
#define  SIO_PDR_MD4_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD4_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD4_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD4_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD4_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD4_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD5_GPIO_FNC__A                                           0x7F005B
#define  SIO_PDR_MD5_GPIO_FNC__W                                           2
#define  SIO_PDR_MD5_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD5_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD5_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD5_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD5_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD5_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD6_GPIO_FNC__A                                           0x7F005C
#define  SIO_PDR_MD6_GPIO_FNC__W                                           2
#define  SIO_PDR_MD6_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD6_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD6_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD6_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD6_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD6_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_MD7_GPIO_FNC__A                                           0x7F005D
#define  SIO_PDR_MD7_GPIO_FNC__W                                           2
#define  SIO_PDR_MD7_GPIO_FNC__M                                           0x3
#define  SIO_PDR_MD7_GPIO_FNC__PRE                                         0x0
#define    SIO_PDR_MD7_GPIO_FNC_SEL__B                                     0
#define    SIO_PDR_MD7_GPIO_FNC_SEL__W                                     2
#define    SIO_PDR_MD7_GPIO_FNC_SEL__M                                     0x3
#define    SIO_PDR_MD7_GPIO_FNC_SEL__PRE                                   0x0

#define  SIO_PDR_SMA_RX_GPIO_FNC__A                                        0x7F005E
#define  SIO_PDR_SMA_RX_GPIO_FNC__W                                        2
#define  SIO_PDR_SMA_RX_GPIO_FNC__M                                        0x3
#define  SIO_PDR_SMA_RX_GPIO_FNC__PRE                                      0x0
#define    SIO_PDR_SMA_RX_GPIO_FNC_SEL__B                                  0
#define    SIO_PDR_SMA_RX_GPIO_FNC_SEL__W                                  2
#define    SIO_PDR_SMA_RX_GPIO_FNC_SEL__M                                  0x3
#define    SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE                                0x0

#define  SIO_PDR_SMA_TX_GPIO_FNC__A                                        0x7F005F
#define  SIO_PDR_SMA_TX_GPIO_FNC__W                                        2
#define  SIO_PDR_SMA_TX_GPIO_FNC__M                                        0x3
#define  SIO_PDR_SMA_TX_GPIO_FNC__PRE                                      0x0
#define    SIO_PDR_SMA_TX_GPIO_FNC_SEL__B                                  0
#define    SIO_PDR_SMA_TX_GPIO_FNC_SEL__W                                  2
#define    SIO_PDR_SMA_TX_GPIO_FNC_SEL__M                                  0x3
#define    SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE                                0x0

#endif