cnic.c 139 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  29. #define BCM_VLAN 1
  30. #endif
  31. #include <net/ip.h>
  32. #include <net/tcp.h>
  33. #include <net/route.h>
  34. #include <net/ipv6.h>
  35. #include <net/ip6_route.h>
  36. #include <net/ip6_checksum.h>
  37. #include <scsi/iscsi_if.h>
  38. #include "cnic_if.h"
  39. #include "bnx2.h"
  40. #include "bnx2x/bnx2x_reg.h"
  41. #include "bnx2x/bnx2x_fw_defs.h"
  42. #include "bnx2x/bnx2x_hsi.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  44. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  45. #include "cnic.h"
  46. #include "cnic_defs.h"
  47. #define DRV_MODULE_NAME "cnic"
  48. static char version[] __devinitdata =
  49. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  50. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  51. "Chen (zongxi@broadcom.com");
  52. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  53. MODULE_LICENSE("GPL");
  54. MODULE_VERSION(CNIC_MODULE_VERSION);
  55. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  56. static LIST_HEAD(cnic_dev_list);
  57. static LIST_HEAD(cnic_udev_list);
  58. static DEFINE_RWLOCK(cnic_dev_lock);
  59. static DEFINE_MUTEX(cnic_lock);
  60. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  61. /* helper function, assuming cnic_lock is held */
  62. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  63. {
  64. return rcu_dereference_protected(cnic_ulp_tbl[type],
  65. lockdep_is_held(&cnic_lock));
  66. }
  67. static int cnic_service_bnx2(void *, void *);
  68. static int cnic_service_bnx2x(void *, void *);
  69. static int cnic_ctl(void *, struct cnic_ctl_info *);
  70. static struct cnic_ops cnic_bnx2_ops = {
  71. .cnic_owner = THIS_MODULE,
  72. .cnic_handler = cnic_service_bnx2,
  73. .cnic_ctl = cnic_ctl,
  74. };
  75. static struct cnic_ops cnic_bnx2x_ops = {
  76. .cnic_owner = THIS_MODULE,
  77. .cnic_handler = cnic_service_bnx2x,
  78. .cnic_ctl = cnic_ctl,
  79. };
  80. static struct workqueue_struct *cnic_wq;
  81. static void cnic_shutdown_rings(struct cnic_dev *);
  82. static void cnic_init_rings(struct cnic_dev *);
  83. static int cnic_cm_set_pg(struct cnic_sock *);
  84. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  85. {
  86. struct cnic_uio_dev *udev = uinfo->priv;
  87. struct cnic_dev *dev;
  88. if (!capable(CAP_NET_ADMIN))
  89. return -EPERM;
  90. if (udev->uio_dev != -1)
  91. return -EBUSY;
  92. rtnl_lock();
  93. dev = udev->dev;
  94. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  95. rtnl_unlock();
  96. return -ENODEV;
  97. }
  98. udev->uio_dev = iminor(inode);
  99. cnic_shutdown_rings(dev);
  100. cnic_init_rings(dev);
  101. rtnl_unlock();
  102. return 0;
  103. }
  104. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  105. {
  106. struct cnic_uio_dev *udev = uinfo->priv;
  107. udev->uio_dev = -1;
  108. return 0;
  109. }
  110. static inline void cnic_hold(struct cnic_dev *dev)
  111. {
  112. atomic_inc(&dev->ref_count);
  113. }
  114. static inline void cnic_put(struct cnic_dev *dev)
  115. {
  116. atomic_dec(&dev->ref_count);
  117. }
  118. static inline void csk_hold(struct cnic_sock *csk)
  119. {
  120. atomic_inc(&csk->ref_count);
  121. }
  122. static inline void csk_put(struct cnic_sock *csk)
  123. {
  124. atomic_dec(&csk->ref_count);
  125. }
  126. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  127. {
  128. struct cnic_dev *cdev;
  129. read_lock(&cnic_dev_lock);
  130. list_for_each_entry(cdev, &cnic_dev_list, list) {
  131. if (netdev == cdev->netdev) {
  132. cnic_hold(cdev);
  133. read_unlock(&cnic_dev_lock);
  134. return cdev;
  135. }
  136. }
  137. read_unlock(&cnic_dev_lock);
  138. return NULL;
  139. }
  140. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  141. {
  142. atomic_inc(&ulp_ops->ref_count);
  143. }
  144. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  145. {
  146. atomic_dec(&ulp_ops->ref_count);
  147. }
  148. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  149. {
  150. struct cnic_local *cp = dev->cnic_priv;
  151. struct cnic_eth_dev *ethdev = cp->ethdev;
  152. struct drv_ctl_info info;
  153. struct drv_ctl_io *io = &info.data.io;
  154. info.cmd = DRV_CTL_CTX_WR_CMD;
  155. io->cid_addr = cid_addr;
  156. io->offset = off;
  157. io->data = val;
  158. ethdev->drv_ctl(dev->netdev, &info);
  159. }
  160. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  161. {
  162. struct cnic_local *cp = dev->cnic_priv;
  163. struct cnic_eth_dev *ethdev = cp->ethdev;
  164. struct drv_ctl_info info;
  165. struct drv_ctl_io *io = &info.data.io;
  166. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  167. io->offset = off;
  168. io->dma_addr = addr;
  169. ethdev->drv_ctl(dev->netdev, &info);
  170. }
  171. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  172. {
  173. struct cnic_local *cp = dev->cnic_priv;
  174. struct cnic_eth_dev *ethdev = cp->ethdev;
  175. struct drv_ctl_info info;
  176. struct drv_ctl_l2_ring *ring = &info.data.ring;
  177. if (start)
  178. info.cmd = DRV_CTL_START_L2_CMD;
  179. else
  180. info.cmd = DRV_CTL_STOP_L2_CMD;
  181. ring->cid = cid;
  182. ring->client_id = cl_id;
  183. ethdev->drv_ctl(dev->netdev, &info);
  184. }
  185. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  186. {
  187. struct cnic_local *cp = dev->cnic_priv;
  188. struct cnic_eth_dev *ethdev = cp->ethdev;
  189. struct drv_ctl_info info;
  190. struct drv_ctl_io *io = &info.data.io;
  191. info.cmd = DRV_CTL_IO_WR_CMD;
  192. io->offset = off;
  193. io->data = val;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. }
  196. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  197. {
  198. struct cnic_local *cp = dev->cnic_priv;
  199. struct cnic_eth_dev *ethdev = cp->ethdev;
  200. struct drv_ctl_info info;
  201. struct drv_ctl_io *io = &info.data.io;
  202. info.cmd = DRV_CTL_IO_RD_CMD;
  203. io->offset = off;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. return io->data;
  206. }
  207. static int cnic_in_use(struct cnic_sock *csk)
  208. {
  209. return test_bit(SK_F_INUSE, &csk->flags);
  210. }
  211. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  212. {
  213. struct cnic_local *cp = dev->cnic_priv;
  214. struct cnic_eth_dev *ethdev = cp->ethdev;
  215. struct drv_ctl_info info;
  216. info.cmd = cmd;
  217. info.data.credit.credit_count = count;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  221. {
  222. u32 i;
  223. for (i = 0; i < cp->max_cid_space; i++) {
  224. if (cp->ctx_tbl[i].cid == cid) {
  225. *l5_cid = i;
  226. return 0;
  227. }
  228. }
  229. return -EINVAL;
  230. }
  231. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  232. struct cnic_sock *csk)
  233. {
  234. struct iscsi_path path_req;
  235. char *buf = NULL;
  236. u16 len = 0;
  237. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  238. struct cnic_ulp_ops *ulp_ops;
  239. struct cnic_uio_dev *udev = cp->udev;
  240. int rc = 0, retry = 0;
  241. if (!udev || udev->uio_dev == -1)
  242. return -ENODEV;
  243. if (csk) {
  244. len = sizeof(path_req);
  245. buf = (char *) &path_req;
  246. memset(&path_req, 0, len);
  247. msg_type = ISCSI_KEVENT_PATH_REQ;
  248. path_req.handle = (u64) csk->l5_cid;
  249. if (test_bit(SK_F_IPV6, &csk->flags)) {
  250. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  251. sizeof(struct in6_addr));
  252. path_req.ip_addr_len = 16;
  253. } else {
  254. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  255. sizeof(struct in_addr));
  256. path_req.ip_addr_len = 4;
  257. }
  258. path_req.vlan_id = csk->vlan_id;
  259. path_req.pmtu = csk->mtu;
  260. }
  261. while (retry < 3) {
  262. rc = 0;
  263. rcu_read_lock();
  264. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  265. if (ulp_ops)
  266. rc = ulp_ops->iscsi_nl_send_msg(
  267. cp->ulp_handle[CNIC_ULP_ISCSI],
  268. msg_type, buf, len);
  269. rcu_read_unlock();
  270. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  271. break;
  272. msleep(100);
  273. retry++;
  274. }
  275. return 0;
  276. }
  277. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  278. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  279. char *buf, u16 len)
  280. {
  281. int rc = -EINVAL;
  282. switch (msg_type) {
  283. case ISCSI_UEVENT_PATH_UPDATE: {
  284. struct cnic_local *cp;
  285. u32 l5_cid;
  286. struct cnic_sock *csk;
  287. struct iscsi_path *path_resp;
  288. if (len < sizeof(*path_resp))
  289. break;
  290. path_resp = (struct iscsi_path *) buf;
  291. cp = dev->cnic_priv;
  292. l5_cid = (u32) path_resp->handle;
  293. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  294. break;
  295. rcu_read_lock();
  296. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  297. rc = -ENODEV;
  298. rcu_read_unlock();
  299. break;
  300. }
  301. csk = &cp->csk_tbl[l5_cid];
  302. csk_hold(csk);
  303. if (cnic_in_use(csk) &&
  304. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  305. memcpy(csk->ha, path_resp->mac_addr, 6);
  306. if (test_bit(SK_F_IPV6, &csk->flags))
  307. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  308. sizeof(struct in6_addr));
  309. else
  310. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  311. sizeof(struct in_addr));
  312. if (is_valid_ether_addr(csk->ha)) {
  313. cnic_cm_set_pg(csk);
  314. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  315. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  316. cnic_cm_upcall(cp, csk,
  317. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  318. clear_bit(SK_F_CONNECT_START, &csk->flags);
  319. }
  320. }
  321. csk_put(csk);
  322. rcu_read_unlock();
  323. rc = 0;
  324. }
  325. }
  326. return rc;
  327. }
  328. static int cnic_offld_prep(struct cnic_sock *csk)
  329. {
  330. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  331. return 0;
  332. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  333. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  334. return 0;
  335. }
  336. return 1;
  337. }
  338. static int cnic_close_prep(struct cnic_sock *csk)
  339. {
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. smp_mb__after_clear_bit();
  342. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  343. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  344. msleep(1);
  345. return 1;
  346. }
  347. return 0;
  348. }
  349. static int cnic_abort_prep(struct cnic_sock *csk)
  350. {
  351. clear_bit(SK_F_CONNECT_START, &csk->flags);
  352. smp_mb__after_clear_bit();
  353. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  354. msleep(1);
  355. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  356. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  357. return 1;
  358. }
  359. return 0;
  360. }
  361. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  362. {
  363. struct cnic_dev *dev;
  364. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  365. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  366. return -EINVAL;
  367. }
  368. mutex_lock(&cnic_lock);
  369. if (cnic_ulp_tbl_prot(ulp_type)) {
  370. pr_err("%s: Type %d has already been registered\n",
  371. __func__, ulp_type);
  372. mutex_unlock(&cnic_lock);
  373. return -EBUSY;
  374. }
  375. read_lock(&cnic_dev_lock);
  376. list_for_each_entry(dev, &cnic_dev_list, list) {
  377. struct cnic_local *cp = dev->cnic_priv;
  378. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  379. }
  380. read_unlock(&cnic_dev_lock);
  381. atomic_set(&ulp_ops->ref_count, 0);
  382. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  383. mutex_unlock(&cnic_lock);
  384. /* Prevent race conditions with netdev_event */
  385. rtnl_lock();
  386. list_for_each_entry(dev, &cnic_dev_list, list) {
  387. struct cnic_local *cp = dev->cnic_priv;
  388. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  389. ulp_ops->cnic_init(dev);
  390. }
  391. rtnl_unlock();
  392. return 0;
  393. }
  394. int cnic_unregister_driver(int ulp_type)
  395. {
  396. struct cnic_dev *dev;
  397. struct cnic_ulp_ops *ulp_ops;
  398. int i = 0;
  399. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  400. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  401. return -EINVAL;
  402. }
  403. mutex_lock(&cnic_lock);
  404. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  405. if (!ulp_ops) {
  406. pr_err("%s: Type %d has not been registered\n",
  407. __func__, ulp_type);
  408. goto out_unlock;
  409. }
  410. read_lock(&cnic_dev_lock);
  411. list_for_each_entry(dev, &cnic_dev_list, list) {
  412. struct cnic_local *cp = dev->cnic_priv;
  413. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  414. pr_err("%s: Type %d still has devices registered\n",
  415. __func__, ulp_type);
  416. read_unlock(&cnic_dev_lock);
  417. goto out_unlock;
  418. }
  419. }
  420. read_unlock(&cnic_dev_lock);
  421. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  422. mutex_unlock(&cnic_lock);
  423. synchronize_rcu();
  424. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  425. msleep(100);
  426. i++;
  427. }
  428. if (atomic_read(&ulp_ops->ref_count) != 0)
  429. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  430. return 0;
  431. out_unlock:
  432. mutex_unlock(&cnic_lock);
  433. return -EINVAL;
  434. }
  435. static int cnic_start_hw(struct cnic_dev *);
  436. static void cnic_stop_hw(struct cnic_dev *);
  437. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  438. void *ulp_ctx)
  439. {
  440. struct cnic_local *cp = dev->cnic_priv;
  441. struct cnic_ulp_ops *ulp_ops;
  442. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  443. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  444. return -EINVAL;
  445. }
  446. mutex_lock(&cnic_lock);
  447. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  448. pr_err("%s: Driver with type %d has not been registered\n",
  449. __func__, ulp_type);
  450. mutex_unlock(&cnic_lock);
  451. return -EAGAIN;
  452. }
  453. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  454. pr_err("%s: Type %d has already been registered to this device\n",
  455. __func__, ulp_type);
  456. mutex_unlock(&cnic_lock);
  457. return -EBUSY;
  458. }
  459. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  460. cp->ulp_handle[ulp_type] = ulp_ctx;
  461. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  462. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  463. cnic_hold(dev);
  464. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  465. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  466. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  467. mutex_unlock(&cnic_lock);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL(cnic_register_driver);
  471. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  472. {
  473. struct cnic_local *cp = dev->cnic_priv;
  474. int i = 0;
  475. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  476. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  477. return -EINVAL;
  478. }
  479. mutex_lock(&cnic_lock);
  480. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  481. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  482. cnic_put(dev);
  483. } else {
  484. pr_err("%s: device not registered to this ulp type %d\n",
  485. __func__, ulp_type);
  486. mutex_unlock(&cnic_lock);
  487. return -EINVAL;
  488. }
  489. mutex_unlock(&cnic_lock);
  490. if (ulp_type == CNIC_ULP_ISCSI)
  491. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  492. synchronize_rcu();
  493. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  494. i < 20) {
  495. msleep(100);
  496. i++;
  497. }
  498. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  499. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(cnic_unregister_driver);
  503. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  504. u32 next)
  505. {
  506. id_tbl->start = start_id;
  507. id_tbl->max = size;
  508. id_tbl->next = next;
  509. spin_lock_init(&id_tbl->lock);
  510. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  511. if (!id_tbl->table)
  512. return -ENOMEM;
  513. return 0;
  514. }
  515. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  516. {
  517. kfree(id_tbl->table);
  518. id_tbl->table = NULL;
  519. }
  520. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  521. {
  522. int ret = -1;
  523. id -= id_tbl->start;
  524. if (id >= id_tbl->max)
  525. return ret;
  526. spin_lock(&id_tbl->lock);
  527. if (!test_bit(id, id_tbl->table)) {
  528. set_bit(id, id_tbl->table);
  529. ret = 0;
  530. }
  531. spin_unlock(&id_tbl->lock);
  532. return ret;
  533. }
  534. /* Returns -1 if not successful */
  535. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  536. {
  537. u32 id;
  538. spin_lock(&id_tbl->lock);
  539. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  540. if (id >= id_tbl->max) {
  541. id = -1;
  542. if (id_tbl->next != 0) {
  543. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  544. if (id >= id_tbl->next)
  545. id = -1;
  546. }
  547. }
  548. if (id < id_tbl->max) {
  549. set_bit(id, id_tbl->table);
  550. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  551. id += id_tbl->start;
  552. }
  553. spin_unlock(&id_tbl->lock);
  554. return id;
  555. }
  556. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  557. {
  558. if (id == -1)
  559. return;
  560. id -= id_tbl->start;
  561. if (id >= id_tbl->max)
  562. return;
  563. clear_bit(id, id_tbl->table);
  564. }
  565. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  566. {
  567. int i;
  568. if (!dma->pg_arr)
  569. return;
  570. for (i = 0; i < dma->num_pages; i++) {
  571. if (dma->pg_arr[i]) {
  572. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  573. dma->pg_arr[i], dma->pg_map_arr[i]);
  574. dma->pg_arr[i] = NULL;
  575. }
  576. }
  577. if (dma->pgtbl) {
  578. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  579. dma->pgtbl, dma->pgtbl_map);
  580. dma->pgtbl = NULL;
  581. }
  582. kfree(dma->pg_arr);
  583. dma->pg_arr = NULL;
  584. dma->num_pages = 0;
  585. }
  586. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  587. {
  588. int i;
  589. __le32 *page_table = (__le32 *) dma->pgtbl;
  590. for (i = 0; i < dma->num_pages; i++) {
  591. /* Each entry needs to be in big endian format. */
  592. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  593. page_table++;
  594. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  595. page_table++;
  596. }
  597. }
  598. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  599. {
  600. int i;
  601. __le32 *page_table = (__le32 *) dma->pgtbl;
  602. for (i = 0; i < dma->num_pages; i++) {
  603. /* Each entry needs to be in little endian format. */
  604. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  605. page_table++;
  606. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  607. page_table++;
  608. }
  609. }
  610. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  611. int pages, int use_pg_tbl)
  612. {
  613. int i, size;
  614. struct cnic_local *cp = dev->cnic_priv;
  615. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  616. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  617. if (dma->pg_arr == NULL)
  618. return -ENOMEM;
  619. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  620. dma->num_pages = pages;
  621. for (i = 0; i < pages; i++) {
  622. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  623. BCM_PAGE_SIZE,
  624. &dma->pg_map_arr[i],
  625. GFP_ATOMIC);
  626. if (dma->pg_arr[i] == NULL)
  627. goto error;
  628. }
  629. if (!use_pg_tbl)
  630. return 0;
  631. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  632. ~(BCM_PAGE_SIZE - 1);
  633. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  634. &dma->pgtbl_map, GFP_ATOMIC);
  635. if (dma->pgtbl == NULL)
  636. goto error;
  637. cp->setup_pgtbl(dev, dma);
  638. return 0;
  639. error:
  640. cnic_free_dma(dev, dma);
  641. return -ENOMEM;
  642. }
  643. static void cnic_free_context(struct cnic_dev *dev)
  644. {
  645. struct cnic_local *cp = dev->cnic_priv;
  646. int i;
  647. for (i = 0; i < cp->ctx_blks; i++) {
  648. if (cp->ctx_arr[i].ctx) {
  649. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  650. cp->ctx_arr[i].ctx,
  651. cp->ctx_arr[i].mapping);
  652. cp->ctx_arr[i].ctx = NULL;
  653. }
  654. }
  655. }
  656. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  657. {
  658. uio_unregister_device(&udev->cnic_uinfo);
  659. if (udev->l2_buf) {
  660. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  661. udev->l2_buf, udev->l2_buf_map);
  662. udev->l2_buf = NULL;
  663. }
  664. if (udev->l2_ring) {
  665. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  666. udev->l2_ring, udev->l2_ring_map);
  667. udev->l2_ring = NULL;
  668. }
  669. pci_dev_put(udev->pdev);
  670. kfree(udev);
  671. }
  672. static void cnic_free_uio(struct cnic_uio_dev *udev)
  673. {
  674. if (!udev)
  675. return;
  676. write_lock(&cnic_dev_lock);
  677. list_del_init(&udev->list);
  678. write_unlock(&cnic_dev_lock);
  679. __cnic_free_uio(udev);
  680. }
  681. static void cnic_free_resc(struct cnic_dev *dev)
  682. {
  683. struct cnic_local *cp = dev->cnic_priv;
  684. struct cnic_uio_dev *udev = cp->udev;
  685. if (udev) {
  686. udev->dev = NULL;
  687. cp->udev = NULL;
  688. }
  689. cnic_free_context(dev);
  690. kfree(cp->ctx_arr);
  691. cp->ctx_arr = NULL;
  692. cp->ctx_blks = 0;
  693. cnic_free_dma(dev, &cp->gbl_buf_info);
  694. cnic_free_dma(dev, &cp->kwq_info);
  695. cnic_free_dma(dev, &cp->kwq_16_data_info);
  696. cnic_free_dma(dev, &cp->kcq2.dma);
  697. cnic_free_dma(dev, &cp->kcq1.dma);
  698. kfree(cp->iscsi_tbl);
  699. cp->iscsi_tbl = NULL;
  700. kfree(cp->ctx_tbl);
  701. cp->ctx_tbl = NULL;
  702. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  703. cnic_free_id_tbl(&cp->cid_tbl);
  704. }
  705. static int cnic_alloc_context(struct cnic_dev *dev)
  706. {
  707. struct cnic_local *cp = dev->cnic_priv;
  708. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  709. int i, k, arr_size;
  710. cp->ctx_blk_size = BCM_PAGE_SIZE;
  711. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  712. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  713. sizeof(struct cnic_ctx);
  714. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  715. if (cp->ctx_arr == NULL)
  716. return -ENOMEM;
  717. k = 0;
  718. for (i = 0; i < 2; i++) {
  719. u32 j, reg, off, lo, hi;
  720. if (i == 0)
  721. off = BNX2_PG_CTX_MAP;
  722. else
  723. off = BNX2_ISCSI_CTX_MAP;
  724. reg = cnic_reg_rd_ind(dev, off);
  725. lo = reg >> 16;
  726. hi = reg & 0xffff;
  727. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  728. cp->ctx_arr[k].cid = j;
  729. }
  730. cp->ctx_blks = k;
  731. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  732. cp->ctx_blks = 0;
  733. return -ENOMEM;
  734. }
  735. for (i = 0; i < cp->ctx_blks; i++) {
  736. cp->ctx_arr[i].ctx =
  737. dma_alloc_coherent(&dev->pcidev->dev,
  738. BCM_PAGE_SIZE,
  739. &cp->ctx_arr[i].mapping,
  740. GFP_KERNEL);
  741. if (cp->ctx_arr[i].ctx == NULL)
  742. return -ENOMEM;
  743. }
  744. }
  745. return 0;
  746. }
  747. static u16 cnic_bnx2_next_idx(u16 idx)
  748. {
  749. return idx + 1;
  750. }
  751. static u16 cnic_bnx2_hw_idx(u16 idx)
  752. {
  753. return idx;
  754. }
  755. static u16 cnic_bnx2x_next_idx(u16 idx)
  756. {
  757. idx++;
  758. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  759. idx++;
  760. return idx;
  761. }
  762. static u16 cnic_bnx2x_hw_idx(u16 idx)
  763. {
  764. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  765. idx++;
  766. return idx;
  767. }
  768. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  769. bool use_pg_tbl)
  770. {
  771. int err, i, use_page_tbl = 0;
  772. struct kcqe **kcq;
  773. if (use_pg_tbl)
  774. use_page_tbl = 1;
  775. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  776. if (err)
  777. return err;
  778. kcq = (struct kcqe **) info->dma.pg_arr;
  779. info->kcq = kcq;
  780. info->next_idx = cnic_bnx2_next_idx;
  781. info->hw_idx = cnic_bnx2_hw_idx;
  782. if (use_pg_tbl)
  783. return 0;
  784. info->next_idx = cnic_bnx2x_next_idx;
  785. info->hw_idx = cnic_bnx2x_hw_idx;
  786. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  787. struct bnx2x_bd_chain_next *next =
  788. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  789. int j = i + 1;
  790. if (j >= KCQ_PAGE_CNT)
  791. j = 0;
  792. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  793. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  794. }
  795. return 0;
  796. }
  797. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  798. {
  799. struct cnic_local *cp = dev->cnic_priv;
  800. struct cnic_uio_dev *udev;
  801. read_lock(&cnic_dev_lock);
  802. list_for_each_entry(udev, &cnic_udev_list, list) {
  803. if (udev->pdev == dev->pcidev) {
  804. udev->dev = dev;
  805. cp->udev = udev;
  806. read_unlock(&cnic_dev_lock);
  807. return 0;
  808. }
  809. }
  810. read_unlock(&cnic_dev_lock);
  811. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  812. if (!udev)
  813. return -ENOMEM;
  814. udev->uio_dev = -1;
  815. udev->dev = dev;
  816. udev->pdev = dev->pcidev;
  817. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  818. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  819. &udev->l2_ring_map,
  820. GFP_KERNEL | __GFP_COMP);
  821. if (!udev->l2_ring)
  822. goto err_udev;
  823. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  824. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  825. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  826. &udev->l2_buf_map,
  827. GFP_KERNEL | __GFP_COMP);
  828. if (!udev->l2_buf)
  829. goto err_dma;
  830. write_lock(&cnic_dev_lock);
  831. list_add(&udev->list, &cnic_udev_list);
  832. write_unlock(&cnic_dev_lock);
  833. pci_dev_get(udev->pdev);
  834. cp->udev = udev;
  835. return 0;
  836. err_dma:
  837. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  838. udev->l2_ring, udev->l2_ring_map);
  839. err_udev:
  840. kfree(udev);
  841. return -ENOMEM;
  842. }
  843. static int cnic_init_uio(struct cnic_dev *dev)
  844. {
  845. struct cnic_local *cp = dev->cnic_priv;
  846. struct cnic_uio_dev *udev = cp->udev;
  847. struct uio_info *uinfo;
  848. int ret = 0;
  849. if (!udev)
  850. return -ENOMEM;
  851. uinfo = &udev->cnic_uinfo;
  852. uinfo->mem[0].addr = dev->netdev->base_addr;
  853. uinfo->mem[0].internal_addr = dev->regview;
  854. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  855. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  856. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  857. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  858. PAGE_MASK;
  859. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  860. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  861. else
  862. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  863. uinfo->name = "bnx2_cnic";
  864. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  865. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  866. PAGE_MASK;
  867. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  868. uinfo->name = "bnx2x_cnic";
  869. }
  870. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  871. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  872. uinfo->mem[2].size = udev->l2_ring_size;
  873. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  874. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  875. uinfo->mem[3].size = udev->l2_buf_size;
  876. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  877. uinfo->version = CNIC_MODULE_VERSION;
  878. uinfo->irq = UIO_IRQ_CUSTOM;
  879. uinfo->open = cnic_uio_open;
  880. uinfo->release = cnic_uio_close;
  881. if (udev->uio_dev == -1) {
  882. if (!uinfo->priv) {
  883. uinfo->priv = udev;
  884. ret = uio_register_device(&udev->pdev->dev, uinfo);
  885. }
  886. } else {
  887. cnic_init_rings(dev);
  888. }
  889. return ret;
  890. }
  891. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  892. {
  893. struct cnic_local *cp = dev->cnic_priv;
  894. int ret;
  895. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  896. if (ret)
  897. goto error;
  898. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  899. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  900. if (ret)
  901. goto error;
  902. ret = cnic_alloc_context(dev);
  903. if (ret)
  904. goto error;
  905. ret = cnic_alloc_uio_rings(dev, 2);
  906. if (ret)
  907. goto error;
  908. ret = cnic_init_uio(dev);
  909. if (ret)
  910. goto error;
  911. return 0;
  912. error:
  913. cnic_free_resc(dev);
  914. return ret;
  915. }
  916. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  917. {
  918. struct cnic_local *cp = dev->cnic_priv;
  919. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  920. int total_mem, blks, i;
  921. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  922. blks = total_mem / ctx_blk_size;
  923. if (total_mem % ctx_blk_size)
  924. blks++;
  925. if (blks > cp->ethdev->ctx_tbl_len)
  926. return -ENOMEM;
  927. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  928. if (cp->ctx_arr == NULL)
  929. return -ENOMEM;
  930. cp->ctx_blks = blks;
  931. cp->ctx_blk_size = ctx_blk_size;
  932. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  933. cp->ctx_align = 0;
  934. else
  935. cp->ctx_align = ctx_blk_size;
  936. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  937. for (i = 0; i < blks; i++) {
  938. cp->ctx_arr[i].ctx =
  939. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  940. &cp->ctx_arr[i].mapping,
  941. GFP_KERNEL);
  942. if (cp->ctx_arr[i].ctx == NULL)
  943. return -ENOMEM;
  944. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  945. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  946. cnic_free_context(dev);
  947. cp->ctx_blk_size += cp->ctx_align;
  948. i = -1;
  949. continue;
  950. }
  951. }
  952. }
  953. return 0;
  954. }
  955. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  956. {
  957. struct cnic_local *cp = dev->cnic_priv;
  958. struct cnic_eth_dev *ethdev = cp->ethdev;
  959. u32 start_cid = ethdev->starting_cid;
  960. int i, j, n, ret, pages;
  961. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  962. cp->iro_arr = ethdev->iro_arr;
  963. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  964. cp->iscsi_start_cid = start_cid;
  965. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  966. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  967. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  968. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  969. if (!cp->fcoe_init_cid)
  970. cp->fcoe_init_cid = 0x10;
  971. }
  972. if (start_cid < BNX2X_ISCSI_START_CID) {
  973. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  974. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  975. cp->fcoe_start_cid += delta;
  976. cp->max_cid_space += delta;
  977. }
  978. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  979. GFP_KERNEL);
  980. if (!cp->iscsi_tbl)
  981. goto error;
  982. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  983. cp->max_cid_space, GFP_KERNEL);
  984. if (!cp->ctx_tbl)
  985. goto error;
  986. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  987. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  988. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  989. }
  990. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  991. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  992. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  993. PAGE_SIZE;
  994. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  995. if (ret)
  996. return -ENOMEM;
  997. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  998. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  999. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1000. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1001. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1002. off;
  1003. if ((i % n) == (n - 1))
  1004. j++;
  1005. }
  1006. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1007. if (ret)
  1008. goto error;
  1009. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1010. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1011. if (ret)
  1012. goto error;
  1013. }
  1014. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1015. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1016. if (ret)
  1017. goto error;
  1018. ret = cnic_alloc_bnx2x_context(dev);
  1019. if (ret)
  1020. goto error;
  1021. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1022. cp->l2_rx_ring_size = 15;
  1023. ret = cnic_alloc_uio_rings(dev, 4);
  1024. if (ret)
  1025. goto error;
  1026. ret = cnic_init_uio(dev);
  1027. if (ret)
  1028. goto error;
  1029. return 0;
  1030. error:
  1031. cnic_free_resc(dev);
  1032. return -ENOMEM;
  1033. }
  1034. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1035. {
  1036. return cp->max_kwq_idx -
  1037. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1038. }
  1039. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1040. u32 num_wqes)
  1041. {
  1042. struct cnic_local *cp = dev->cnic_priv;
  1043. struct kwqe *prod_qe;
  1044. u16 prod, sw_prod, i;
  1045. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1046. return -EAGAIN; /* bnx2 is down */
  1047. spin_lock_bh(&cp->cnic_ulp_lock);
  1048. if (num_wqes > cnic_kwq_avail(cp) &&
  1049. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1050. spin_unlock_bh(&cp->cnic_ulp_lock);
  1051. return -EAGAIN;
  1052. }
  1053. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1054. prod = cp->kwq_prod_idx;
  1055. sw_prod = prod & MAX_KWQ_IDX;
  1056. for (i = 0; i < num_wqes; i++) {
  1057. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1058. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1059. prod++;
  1060. sw_prod = prod & MAX_KWQ_IDX;
  1061. }
  1062. cp->kwq_prod_idx = prod;
  1063. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1064. spin_unlock_bh(&cp->cnic_ulp_lock);
  1065. return 0;
  1066. }
  1067. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1068. union l5cm_specific_data *l5_data)
  1069. {
  1070. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1071. dma_addr_t map;
  1072. map = ctx->kwqe_data_mapping;
  1073. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1074. l5_data->phy_address.hi = (u64) map >> 32;
  1075. return ctx->kwqe_data;
  1076. }
  1077. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1078. u32 type, union l5cm_specific_data *l5_data)
  1079. {
  1080. struct cnic_local *cp = dev->cnic_priv;
  1081. struct l5cm_spe kwqe;
  1082. struct kwqe_16 *kwq[1];
  1083. u16 type_16;
  1084. int ret;
  1085. kwqe.hdr.conn_and_cmd_data =
  1086. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1087. BNX2X_HW_CID(cp, cid)));
  1088. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1089. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1090. SPE_HDR_FUNCTION_ID;
  1091. kwqe.hdr.type = cpu_to_le16(type_16);
  1092. kwqe.hdr.reserved1 = 0;
  1093. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1094. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1095. kwq[0] = (struct kwqe_16 *) &kwqe;
  1096. spin_lock_bh(&cp->cnic_ulp_lock);
  1097. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1098. spin_unlock_bh(&cp->cnic_ulp_lock);
  1099. if (ret == 1)
  1100. return 0;
  1101. return -EBUSY;
  1102. }
  1103. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1104. struct kcqe *cqes[], u32 num_cqes)
  1105. {
  1106. struct cnic_local *cp = dev->cnic_priv;
  1107. struct cnic_ulp_ops *ulp_ops;
  1108. rcu_read_lock();
  1109. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1110. if (likely(ulp_ops)) {
  1111. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1112. cqes, num_cqes);
  1113. }
  1114. rcu_read_unlock();
  1115. }
  1116. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1117. {
  1118. struct cnic_local *cp = dev->cnic_priv;
  1119. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1120. int hq_bds, pages;
  1121. u32 pfid = cp->pfid;
  1122. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1123. cp->num_ccells = req1->num_ccells_per_conn;
  1124. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1125. cp->num_iscsi_tasks;
  1126. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1127. BNX2X_ISCSI_R2TQE_SIZE;
  1128. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1129. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1130. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1131. cp->num_cqs = req1->num_cqs;
  1132. if (!dev->max_iscsi_conn)
  1133. return 0;
  1134. /* init Tstorm RAM */
  1135. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1136. req1->rq_num_wqes);
  1137. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1138. PAGE_SIZE);
  1139. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1140. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1141. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1142. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1143. req1->num_tasks_per_conn);
  1144. /* init Ustorm RAM */
  1145. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1146. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1147. req1->rq_buffer_size);
  1148. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1149. PAGE_SIZE);
  1150. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1151. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1152. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1153. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1154. req1->num_tasks_per_conn);
  1155. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1156. req1->rq_num_wqes);
  1157. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1158. req1->cq_num_wqes);
  1159. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1160. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1161. /* init Xstorm RAM */
  1162. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1163. PAGE_SIZE);
  1164. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1165. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1166. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1167. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1168. req1->num_tasks_per_conn);
  1169. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1170. hq_bds);
  1171. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1172. req1->num_tasks_per_conn);
  1173. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1174. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1175. /* init Cstorm RAM */
  1176. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1177. PAGE_SIZE);
  1178. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1179. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1180. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1181. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1182. req1->num_tasks_per_conn);
  1183. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1184. req1->cq_num_wqes);
  1185. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1186. hq_bds);
  1187. return 0;
  1188. }
  1189. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1190. {
  1191. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1192. struct cnic_local *cp = dev->cnic_priv;
  1193. u32 pfid = cp->pfid;
  1194. struct iscsi_kcqe kcqe;
  1195. struct kcqe *cqes[1];
  1196. memset(&kcqe, 0, sizeof(kcqe));
  1197. if (!dev->max_iscsi_conn) {
  1198. kcqe.completion_status =
  1199. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1200. goto done;
  1201. }
  1202. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1203. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1204. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1205. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1206. req2->error_bit_map[1]);
  1207. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1208. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1209. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1210. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1211. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1212. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1213. req2->error_bit_map[1]);
  1214. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1215. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1216. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1217. done:
  1218. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1219. cqes[0] = (struct kcqe *) &kcqe;
  1220. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1221. return 0;
  1222. }
  1223. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1224. {
  1225. struct cnic_local *cp = dev->cnic_priv;
  1226. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1227. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1228. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1229. cnic_free_dma(dev, &iscsi->hq_info);
  1230. cnic_free_dma(dev, &iscsi->r2tq_info);
  1231. cnic_free_dma(dev, &iscsi->task_array_info);
  1232. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1233. } else {
  1234. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1235. }
  1236. ctx->cid = 0;
  1237. }
  1238. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1239. {
  1240. u32 cid;
  1241. int ret, pages;
  1242. struct cnic_local *cp = dev->cnic_priv;
  1243. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1244. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1245. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1246. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1247. if (cid == -1) {
  1248. ret = -ENOMEM;
  1249. goto error;
  1250. }
  1251. ctx->cid = cid;
  1252. return 0;
  1253. }
  1254. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1255. if (cid == -1) {
  1256. ret = -ENOMEM;
  1257. goto error;
  1258. }
  1259. ctx->cid = cid;
  1260. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1261. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1262. if (ret)
  1263. goto error;
  1264. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1265. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1266. if (ret)
  1267. goto error;
  1268. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1269. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1270. if (ret)
  1271. goto error;
  1272. return 0;
  1273. error:
  1274. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1275. return ret;
  1276. }
  1277. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1278. struct regpair *ctx_addr)
  1279. {
  1280. struct cnic_local *cp = dev->cnic_priv;
  1281. struct cnic_eth_dev *ethdev = cp->ethdev;
  1282. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1283. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1284. unsigned long align_off = 0;
  1285. dma_addr_t ctx_map;
  1286. void *ctx;
  1287. if (cp->ctx_align) {
  1288. unsigned long mask = cp->ctx_align - 1;
  1289. if (cp->ctx_arr[blk].mapping & mask)
  1290. align_off = cp->ctx_align -
  1291. (cp->ctx_arr[blk].mapping & mask);
  1292. }
  1293. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1294. (off * BNX2X_CONTEXT_MEM_SIZE);
  1295. ctx = cp->ctx_arr[blk].ctx + align_off +
  1296. (off * BNX2X_CONTEXT_MEM_SIZE);
  1297. if (init)
  1298. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1299. ctx_addr->lo = ctx_map & 0xffffffff;
  1300. ctx_addr->hi = (u64) ctx_map >> 32;
  1301. return ctx;
  1302. }
  1303. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1304. u32 num)
  1305. {
  1306. struct cnic_local *cp = dev->cnic_priv;
  1307. struct iscsi_kwqe_conn_offload1 *req1 =
  1308. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1309. struct iscsi_kwqe_conn_offload2 *req2 =
  1310. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1311. struct iscsi_kwqe_conn_offload3 *req3;
  1312. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1313. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1314. u32 cid = ctx->cid;
  1315. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1316. struct iscsi_context *ictx;
  1317. struct regpair context_addr;
  1318. int i, j, n = 2, n_max;
  1319. u8 port = CNIC_PORT(cp);
  1320. ctx->ctx_flags = 0;
  1321. if (!req2->num_additional_wqes)
  1322. return -EINVAL;
  1323. n_max = req2->num_additional_wqes + 2;
  1324. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1325. if (ictx == NULL)
  1326. return -ENOMEM;
  1327. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1328. ictx->xstorm_ag_context.hq_prod = 1;
  1329. ictx->xstorm_st_context.iscsi.first_burst_length =
  1330. ISCSI_DEF_FIRST_BURST_LEN;
  1331. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1332. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1333. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1334. req1->sq_page_table_addr_lo;
  1335. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1336. req1->sq_page_table_addr_hi;
  1337. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1338. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1339. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1340. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1341. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1342. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1343. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1344. iscsi->hq_info.pgtbl[0];
  1345. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1346. iscsi->hq_info.pgtbl[1];
  1347. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1348. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1349. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1350. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1351. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1352. iscsi->r2tq_info.pgtbl[0];
  1353. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1354. iscsi->r2tq_info.pgtbl[1];
  1355. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1356. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1357. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1358. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1359. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1360. BNX2X_ISCSI_PBL_NOT_CACHED;
  1361. ictx->xstorm_st_context.iscsi.flags.flags |=
  1362. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1363. ictx->xstorm_st_context.iscsi.flags.flags |=
  1364. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1365. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1366. ETH_P_8021Q;
  1367. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1368. cp->port_mode == CHIP_2_PORT_MODE) {
  1369. port = 0;
  1370. }
  1371. ictx->xstorm_st_context.common.flags =
  1372. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1373. ictx->xstorm_st_context.common.flags =
  1374. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1375. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1376. /* TSTORM requires the base address of RQ DB & not PTE */
  1377. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1378. req2->rq_page_table_addr_lo & PAGE_MASK;
  1379. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1380. req2->rq_page_table_addr_hi;
  1381. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1382. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1383. ictx->tstorm_st_context.tcp.flags2 |=
  1384. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1385. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1386. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1387. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1388. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1389. req2->rq_page_table_addr_lo;
  1390. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1391. req2->rq_page_table_addr_hi;
  1392. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1393. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1394. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1395. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1396. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1397. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1398. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1399. iscsi->r2tq_info.pgtbl[0];
  1400. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1401. iscsi->r2tq_info.pgtbl[1];
  1402. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1403. req1->cq_page_table_addr_lo;
  1404. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1405. req1->cq_page_table_addr_hi;
  1406. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1407. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1408. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1409. ictx->ustorm_st_context.task_pbe_cache_index =
  1410. BNX2X_ISCSI_PBL_NOT_CACHED;
  1411. ictx->ustorm_st_context.task_pdu_cache_index =
  1412. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1413. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1414. if (j == 3) {
  1415. if (n >= n_max)
  1416. break;
  1417. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1418. j = 0;
  1419. }
  1420. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1421. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1422. req3->qp_first_pte[j].hi;
  1423. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1424. req3->qp_first_pte[j].lo;
  1425. }
  1426. ictx->ustorm_st_context.task_pbl_base.lo =
  1427. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1428. ictx->ustorm_st_context.task_pbl_base.hi =
  1429. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1430. ictx->ustorm_st_context.tce_phy_addr.lo =
  1431. iscsi->task_array_info.pgtbl[0];
  1432. ictx->ustorm_st_context.tce_phy_addr.hi =
  1433. iscsi->task_array_info.pgtbl[1];
  1434. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1435. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1436. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1437. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1438. ISCSI_DEF_MAX_BURST_LEN;
  1439. ictx->ustorm_st_context.negotiated_rx |=
  1440. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1441. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1442. ictx->cstorm_st_context.hq_pbl_base.lo =
  1443. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1444. ictx->cstorm_st_context.hq_pbl_base.hi =
  1445. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1446. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1447. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1448. ictx->cstorm_st_context.task_pbl_base.lo =
  1449. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1450. ictx->cstorm_st_context.task_pbl_base.hi =
  1451. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1452. /* CSTORM and USTORM initialization is different, CSTORM requires
  1453. * CQ DB base & not PTE addr */
  1454. ictx->cstorm_st_context.cq_db_base.lo =
  1455. req1->cq_page_table_addr_lo & PAGE_MASK;
  1456. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1457. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1458. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1459. for (i = 0; i < cp->num_cqs; i++) {
  1460. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1461. ISCSI_INITIAL_SN;
  1462. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1463. ISCSI_INITIAL_SN;
  1464. }
  1465. ictx->xstorm_ag_context.cdu_reserved =
  1466. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1467. ISCSI_CONNECTION_TYPE);
  1468. ictx->ustorm_ag_context.cdu_usage =
  1469. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1470. ISCSI_CONNECTION_TYPE);
  1471. return 0;
  1472. }
  1473. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1474. u32 num, int *work)
  1475. {
  1476. struct iscsi_kwqe_conn_offload1 *req1;
  1477. struct iscsi_kwqe_conn_offload2 *req2;
  1478. struct cnic_local *cp = dev->cnic_priv;
  1479. struct cnic_context *ctx;
  1480. struct iscsi_kcqe kcqe;
  1481. struct kcqe *cqes[1];
  1482. u32 l5_cid;
  1483. int ret = 0;
  1484. if (num < 2) {
  1485. *work = num;
  1486. return -EINVAL;
  1487. }
  1488. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1489. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1490. if ((num - 2) < req2->num_additional_wqes) {
  1491. *work = num;
  1492. return -EINVAL;
  1493. }
  1494. *work = 2 + req2->num_additional_wqes;
  1495. l5_cid = req1->iscsi_conn_id;
  1496. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1497. return -EINVAL;
  1498. memset(&kcqe, 0, sizeof(kcqe));
  1499. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1500. kcqe.iscsi_conn_id = l5_cid;
  1501. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1502. ctx = &cp->ctx_tbl[l5_cid];
  1503. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1504. kcqe.completion_status =
  1505. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1506. goto done;
  1507. }
  1508. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1509. atomic_dec(&cp->iscsi_conn);
  1510. goto done;
  1511. }
  1512. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1513. if (ret) {
  1514. atomic_dec(&cp->iscsi_conn);
  1515. ret = 0;
  1516. goto done;
  1517. }
  1518. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1519. if (ret < 0) {
  1520. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1521. atomic_dec(&cp->iscsi_conn);
  1522. goto done;
  1523. }
  1524. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1525. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1526. done:
  1527. cqes[0] = (struct kcqe *) &kcqe;
  1528. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1529. return ret;
  1530. }
  1531. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1532. {
  1533. struct cnic_local *cp = dev->cnic_priv;
  1534. struct iscsi_kwqe_conn_update *req =
  1535. (struct iscsi_kwqe_conn_update *) kwqe;
  1536. void *data;
  1537. union l5cm_specific_data l5_data;
  1538. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1539. int ret;
  1540. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1541. return -EINVAL;
  1542. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1543. if (!data)
  1544. return -ENOMEM;
  1545. memcpy(data, kwqe, sizeof(struct kwqe));
  1546. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1547. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1548. return ret;
  1549. }
  1550. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1551. {
  1552. struct cnic_local *cp = dev->cnic_priv;
  1553. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1554. union l5cm_specific_data l5_data;
  1555. int ret;
  1556. u32 hw_cid;
  1557. init_waitqueue_head(&ctx->waitq);
  1558. ctx->wait_cond = 0;
  1559. memset(&l5_data, 0, sizeof(l5_data));
  1560. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1561. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1562. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1563. if (ret == 0) {
  1564. wait_event(ctx->waitq, ctx->wait_cond);
  1565. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1566. return -EBUSY;
  1567. }
  1568. return ret;
  1569. }
  1570. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1571. {
  1572. struct cnic_local *cp = dev->cnic_priv;
  1573. struct iscsi_kwqe_conn_destroy *req =
  1574. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1575. u32 l5_cid = req->reserved0;
  1576. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1577. int ret = 0;
  1578. struct iscsi_kcqe kcqe;
  1579. struct kcqe *cqes[1];
  1580. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1581. goto skip_cfc_delete;
  1582. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1583. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1584. if (delta > (2 * HZ))
  1585. delta = 0;
  1586. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1587. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1588. goto destroy_reply;
  1589. }
  1590. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1591. skip_cfc_delete:
  1592. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1593. if (!ret) {
  1594. atomic_dec(&cp->iscsi_conn);
  1595. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1596. }
  1597. destroy_reply:
  1598. memset(&kcqe, 0, sizeof(kcqe));
  1599. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1600. kcqe.iscsi_conn_id = l5_cid;
  1601. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1602. kcqe.iscsi_conn_context_id = req->context_id;
  1603. cqes[0] = (struct kcqe *) &kcqe;
  1604. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1605. return ret;
  1606. }
  1607. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1608. struct l4_kwq_connect_req1 *kwqe1,
  1609. struct l4_kwq_connect_req3 *kwqe3,
  1610. struct l5cm_active_conn_buffer *conn_buf)
  1611. {
  1612. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1613. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1614. &conn_buf->xstorm_conn_buffer;
  1615. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1616. &conn_buf->tstorm_conn_buffer;
  1617. struct regpair context_addr;
  1618. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1619. struct in6_addr src_ip, dst_ip;
  1620. int i;
  1621. u32 *addrp;
  1622. addrp = (u32 *) &conn_addr->local_ip_addr;
  1623. for (i = 0; i < 4; i++, addrp++)
  1624. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1625. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1626. for (i = 0; i < 4; i++, addrp++)
  1627. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1628. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1629. xstorm_buf->context_addr.hi = context_addr.hi;
  1630. xstorm_buf->context_addr.lo = context_addr.lo;
  1631. xstorm_buf->mss = 0xffff;
  1632. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1633. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1634. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1635. xstorm_buf->pseudo_header_checksum =
  1636. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1637. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1638. tstorm_buf->params |=
  1639. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1640. if (kwqe3->ka_timeout) {
  1641. tstorm_buf->ka_enable = 1;
  1642. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1643. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1644. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1645. }
  1646. tstorm_buf->max_rt_time = 0xffffffff;
  1647. }
  1648. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1649. {
  1650. struct cnic_local *cp = dev->cnic_priv;
  1651. u32 pfid = cp->pfid;
  1652. u8 *mac = dev->mac_addr;
  1653. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1654. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1655. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1656. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1657. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1658. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1659. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1660. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1661. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1662. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1663. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1664. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1665. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1666. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1667. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1668. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1669. mac[4]);
  1670. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1671. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1672. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1673. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1674. mac[2]);
  1675. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1676. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1677. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1678. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1679. mac[0]);
  1680. }
  1681. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1682. {
  1683. struct cnic_local *cp = dev->cnic_priv;
  1684. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1685. u16 tstorm_flags = 0;
  1686. if (tcp_ts) {
  1687. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1688. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1689. }
  1690. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1691. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1692. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1693. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1694. }
  1695. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1696. u32 num, int *work)
  1697. {
  1698. struct cnic_local *cp = dev->cnic_priv;
  1699. struct l4_kwq_connect_req1 *kwqe1 =
  1700. (struct l4_kwq_connect_req1 *) wqes[0];
  1701. struct l4_kwq_connect_req3 *kwqe3;
  1702. struct l5cm_active_conn_buffer *conn_buf;
  1703. struct l5cm_conn_addr_params *conn_addr;
  1704. union l5cm_specific_data l5_data;
  1705. u32 l5_cid = kwqe1->pg_cid;
  1706. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1707. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1708. int ret;
  1709. if (num < 2) {
  1710. *work = num;
  1711. return -EINVAL;
  1712. }
  1713. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1714. *work = 3;
  1715. else
  1716. *work = 2;
  1717. if (num < *work) {
  1718. *work = num;
  1719. return -EINVAL;
  1720. }
  1721. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1722. netdev_err(dev->netdev, "conn_buf size too big\n");
  1723. return -ENOMEM;
  1724. }
  1725. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1726. if (!conn_buf)
  1727. return -ENOMEM;
  1728. memset(conn_buf, 0, sizeof(*conn_buf));
  1729. conn_addr = &conn_buf->conn_addr_buf;
  1730. conn_addr->remote_addr_0 = csk->ha[0];
  1731. conn_addr->remote_addr_1 = csk->ha[1];
  1732. conn_addr->remote_addr_2 = csk->ha[2];
  1733. conn_addr->remote_addr_3 = csk->ha[3];
  1734. conn_addr->remote_addr_4 = csk->ha[4];
  1735. conn_addr->remote_addr_5 = csk->ha[5];
  1736. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1737. struct l4_kwq_connect_req2 *kwqe2 =
  1738. (struct l4_kwq_connect_req2 *) wqes[1];
  1739. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1740. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1741. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1742. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1743. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1744. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1745. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1746. }
  1747. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1748. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1749. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1750. conn_addr->local_tcp_port = kwqe1->src_port;
  1751. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1752. conn_addr->pmtu = kwqe3->pmtu;
  1753. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1754. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1755. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1756. cnic_bnx2x_set_tcp_timestamp(dev,
  1757. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1758. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1759. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1760. if (!ret)
  1761. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1762. return ret;
  1763. }
  1764. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1765. {
  1766. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1767. union l5cm_specific_data l5_data;
  1768. int ret;
  1769. memset(&l5_data, 0, sizeof(l5_data));
  1770. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1771. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1772. return ret;
  1773. }
  1774. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1775. {
  1776. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1777. union l5cm_specific_data l5_data;
  1778. int ret;
  1779. memset(&l5_data, 0, sizeof(l5_data));
  1780. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1781. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1782. return ret;
  1783. }
  1784. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1785. {
  1786. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1787. struct l4_kcq kcqe;
  1788. struct kcqe *cqes[1];
  1789. memset(&kcqe, 0, sizeof(kcqe));
  1790. kcqe.pg_host_opaque = req->host_opaque;
  1791. kcqe.pg_cid = req->host_opaque;
  1792. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1793. cqes[0] = (struct kcqe *) &kcqe;
  1794. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1795. return 0;
  1796. }
  1797. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1798. {
  1799. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1800. struct l4_kcq kcqe;
  1801. struct kcqe *cqes[1];
  1802. memset(&kcqe, 0, sizeof(kcqe));
  1803. kcqe.pg_host_opaque = req->pg_host_opaque;
  1804. kcqe.pg_cid = req->pg_cid;
  1805. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1806. cqes[0] = (struct kcqe *) &kcqe;
  1807. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1808. return 0;
  1809. }
  1810. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1811. {
  1812. struct fcoe_kwqe_stat *req;
  1813. struct fcoe_stat_ramrod_params *fcoe_stat;
  1814. union l5cm_specific_data l5_data;
  1815. struct cnic_local *cp = dev->cnic_priv;
  1816. int ret;
  1817. u32 cid;
  1818. req = (struct fcoe_kwqe_stat *) kwqe;
  1819. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1820. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1821. if (!fcoe_stat)
  1822. return -ENOMEM;
  1823. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1824. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1825. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1826. FCOE_CONNECTION_TYPE, &l5_data);
  1827. return ret;
  1828. }
  1829. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1830. u32 num, int *work)
  1831. {
  1832. int ret;
  1833. struct cnic_local *cp = dev->cnic_priv;
  1834. u32 cid;
  1835. struct fcoe_init_ramrod_params *fcoe_init;
  1836. struct fcoe_kwqe_init1 *req1;
  1837. struct fcoe_kwqe_init2 *req2;
  1838. struct fcoe_kwqe_init3 *req3;
  1839. union l5cm_specific_data l5_data;
  1840. if (num < 3) {
  1841. *work = num;
  1842. return -EINVAL;
  1843. }
  1844. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1845. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1846. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1847. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1848. *work = 1;
  1849. return -EINVAL;
  1850. }
  1851. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1852. *work = 2;
  1853. return -EINVAL;
  1854. }
  1855. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1856. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1857. return -ENOMEM;
  1858. }
  1859. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1860. if (!fcoe_init)
  1861. return -ENOMEM;
  1862. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1863. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1864. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1865. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1866. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1867. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1868. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1869. fcoe_init->sb_num = cp->status_blk_num;
  1870. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1871. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1872. cp->kcq2.sw_prod_idx = 0;
  1873. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1874. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1875. FCOE_CONNECTION_TYPE, &l5_data);
  1876. *work = 3;
  1877. return ret;
  1878. }
  1879. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1880. u32 num, int *work)
  1881. {
  1882. int ret = 0;
  1883. u32 cid = -1, l5_cid;
  1884. struct cnic_local *cp = dev->cnic_priv;
  1885. struct fcoe_kwqe_conn_offload1 *req1;
  1886. struct fcoe_kwqe_conn_offload2 *req2;
  1887. struct fcoe_kwqe_conn_offload3 *req3;
  1888. struct fcoe_kwqe_conn_offload4 *req4;
  1889. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1890. struct cnic_context *ctx;
  1891. struct fcoe_context *fctx;
  1892. struct regpair ctx_addr;
  1893. union l5cm_specific_data l5_data;
  1894. struct fcoe_kcqe kcqe;
  1895. struct kcqe *cqes[1];
  1896. if (num < 4) {
  1897. *work = num;
  1898. return -EINVAL;
  1899. }
  1900. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1901. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1902. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1903. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1904. *work = 4;
  1905. l5_cid = req1->fcoe_conn_id;
  1906. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1907. goto err_reply;
  1908. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1909. ctx = &cp->ctx_tbl[l5_cid];
  1910. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1911. goto err_reply;
  1912. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1913. if (ret) {
  1914. ret = 0;
  1915. goto err_reply;
  1916. }
  1917. cid = ctx->cid;
  1918. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1919. if (fctx) {
  1920. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1921. u32 val;
  1922. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1923. FCOE_CONNECTION_TYPE);
  1924. fctx->xstorm_ag_context.cdu_reserved = val;
  1925. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1926. FCOE_CONNECTION_TYPE);
  1927. fctx->ustorm_ag_context.cdu_usage = val;
  1928. }
  1929. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1930. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1931. goto err_reply;
  1932. }
  1933. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1934. if (!fcoe_offload)
  1935. goto err_reply;
  1936. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1937. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1938. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1939. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1940. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1941. cid = BNX2X_HW_CID(cp, cid);
  1942. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1943. FCOE_CONNECTION_TYPE, &l5_data);
  1944. if (!ret)
  1945. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1946. return ret;
  1947. err_reply:
  1948. if (cid != -1)
  1949. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1950. memset(&kcqe, 0, sizeof(kcqe));
  1951. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1952. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1953. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1954. cqes[0] = (struct kcqe *) &kcqe;
  1955. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1956. return ret;
  1957. }
  1958. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1959. {
  1960. struct fcoe_kwqe_conn_enable_disable *req;
  1961. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1962. union l5cm_specific_data l5_data;
  1963. int ret;
  1964. u32 cid, l5_cid;
  1965. struct cnic_local *cp = dev->cnic_priv;
  1966. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1967. cid = req->context_id;
  1968. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1969. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1970. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1971. return -ENOMEM;
  1972. }
  1973. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1974. if (!fcoe_enable)
  1975. return -ENOMEM;
  1976. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1977. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1978. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1979. FCOE_CONNECTION_TYPE, &l5_data);
  1980. return ret;
  1981. }
  1982. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1983. {
  1984. struct fcoe_kwqe_conn_enable_disable *req;
  1985. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1986. union l5cm_specific_data l5_data;
  1987. int ret;
  1988. u32 cid, l5_cid;
  1989. struct cnic_local *cp = dev->cnic_priv;
  1990. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1991. cid = req->context_id;
  1992. l5_cid = req->conn_id;
  1993. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1994. return -EINVAL;
  1995. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1996. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1997. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1998. return -ENOMEM;
  1999. }
  2000. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2001. if (!fcoe_disable)
  2002. return -ENOMEM;
  2003. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2004. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2005. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2006. FCOE_CONNECTION_TYPE, &l5_data);
  2007. return ret;
  2008. }
  2009. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2010. {
  2011. struct fcoe_kwqe_conn_destroy *req;
  2012. union l5cm_specific_data l5_data;
  2013. int ret;
  2014. u32 cid, l5_cid;
  2015. struct cnic_local *cp = dev->cnic_priv;
  2016. struct cnic_context *ctx;
  2017. struct fcoe_kcqe kcqe;
  2018. struct kcqe *cqes[1];
  2019. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2020. cid = req->context_id;
  2021. l5_cid = req->conn_id;
  2022. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  2023. return -EINVAL;
  2024. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2025. ctx = &cp->ctx_tbl[l5_cid];
  2026. init_waitqueue_head(&ctx->waitq);
  2027. ctx->wait_cond = 0;
  2028. memset(&l5_data, 0, sizeof(l5_data));
  2029. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2030. FCOE_CONNECTION_TYPE, &l5_data);
  2031. if (ret == 0) {
  2032. wait_event(ctx->waitq, ctx->wait_cond);
  2033. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2034. queue_delayed_work(cnic_wq, &cp->delete_task,
  2035. msecs_to_jiffies(2000));
  2036. }
  2037. memset(&kcqe, 0, sizeof(kcqe));
  2038. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2039. kcqe.fcoe_conn_id = req->conn_id;
  2040. kcqe.fcoe_conn_context_id = cid;
  2041. cqes[0] = (struct kcqe *) &kcqe;
  2042. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2043. return ret;
  2044. }
  2045. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2046. {
  2047. struct fcoe_kwqe_destroy *req;
  2048. union l5cm_specific_data l5_data;
  2049. struct cnic_local *cp = dev->cnic_priv;
  2050. int ret;
  2051. u32 cid;
  2052. req = (struct fcoe_kwqe_destroy *) kwqe;
  2053. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2054. memset(&l5_data, 0, sizeof(l5_data));
  2055. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2056. FCOE_CONNECTION_TYPE, &l5_data);
  2057. return ret;
  2058. }
  2059. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2060. struct kwqe *wqes[], u32 num_wqes)
  2061. {
  2062. int i, work, ret;
  2063. u32 opcode;
  2064. struct kwqe *kwqe;
  2065. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2066. return -EAGAIN; /* bnx2 is down */
  2067. for (i = 0; i < num_wqes; ) {
  2068. kwqe = wqes[i];
  2069. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2070. work = 1;
  2071. switch (opcode) {
  2072. case ISCSI_KWQE_OPCODE_INIT1:
  2073. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2074. break;
  2075. case ISCSI_KWQE_OPCODE_INIT2:
  2076. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2077. break;
  2078. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2079. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2080. num_wqes - i, &work);
  2081. break;
  2082. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2083. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2084. break;
  2085. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2086. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2087. break;
  2088. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2089. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2090. &work);
  2091. break;
  2092. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2093. ret = cnic_bnx2x_close(dev, kwqe);
  2094. break;
  2095. case L4_KWQE_OPCODE_VALUE_RESET:
  2096. ret = cnic_bnx2x_reset(dev, kwqe);
  2097. break;
  2098. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2099. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2100. break;
  2101. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2102. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2103. break;
  2104. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2105. ret = 0;
  2106. break;
  2107. default:
  2108. ret = 0;
  2109. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2110. opcode);
  2111. break;
  2112. }
  2113. if (ret < 0)
  2114. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2115. opcode);
  2116. i += work;
  2117. }
  2118. return 0;
  2119. }
  2120. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2121. struct kwqe *wqes[], u32 num_wqes)
  2122. {
  2123. struct cnic_local *cp = dev->cnic_priv;
  2124. int i, work, ret;
  2125. u32 opcode;
  2126. struct kwqe *kwqe;
  2127. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2128. return -EAGAIN; /* bnx2 is down */
  2129. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2130. return -EINVAL;
  2131. for (i = 0; i < num_wqes; ) {
  2132. kwqe = wqes[i];
  2133. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2134. work = 1;
  2135. switch (opcode) {
  2136. case FCOE_KWQE_OPCODE_INIT1:
  2137. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2138. num_wqes - i, &work);
  2139. break;
  2140. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2141. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2142. num_wqes - i, &work);
  2143. break;
  2144. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2145. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2146. break;
  2147. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2148. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2149. break;
  2150. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2151. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2152. break;
  2153. case FCOE_KWQE_OPCODE_DESTROY:
  2154. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2155. break;
  2156. case FCOE_KWQE_OPCODE_STAT:
  2157. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2158. break;
  2159. default:
  2160. ret = 0;
  2161. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2162. opcode);
  2163. break;
  2164. }
  2165. if (ret < 0)
  2166. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2167. opcode);
  2168. i += work;
  2169. }
  2170. return 0;
  2171. }
  2172. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2173. u32 num_wqes)
  2174. {
  2175. int ret = -EINVAL;
  2176. u32 layer_code;
  2177. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2178. return -EAGAIN; /* bnx2x is down */
  2179. if (!num_wqes)
  2180. return 0;
  2181. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2182. switch (layer_code) {
  2183. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2184. case KWQE_FLAGS_LAYER_MASK_L4:
  2185. case KWQE_FLAGS_LAYER_MASK_L2:
  2186. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2187. break;
  2188. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2189. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2190. break;
  2191. }
  2192. return ret;
  2193. }
  2194. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2195. {
  2196. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2197. return KCQE_FLAGS_LAYER_MASK_L4;
  2198. return opflag & KCQE_FLAGS_LAYER_MASK;
  2199. }
  2200. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2201. {
  2202. struct cnic_local *cp = dev->cnic_priv;
  2203. int i, j, comp = 0;
  2204. i = 0;
  2205. j = 1;
  2206. while (num_cqes) {
  2207. struct cnic_ulp_ops *ulp_ops;
  2208. int ulp_type;
  2209. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2210. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2211. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2212. comp++;
  2213. while (j < num_cqes) {
  2214. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2215. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2216. break;
  2217. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2218. comp++;
  2219. j++;
  2220. }
  2221. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2222. ulp_type = CNIC_ULP_RDMA;
  2223. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2224. ulp_type = CNIC_ULP_ISCSI;
  2225. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2226. ulp_type = CNIC_ULP_FCOE;
  2227. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2228. ulp_type = CNIC_ULP_L4;
  2229. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2230. goto end;
  2231. else {
  2232. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2233. kcqe_op_flag);
  2234. goto end;
  2235. }
  2236. rcu_read_lock();
  2237. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2238. if (likely(ulp_ops)) {
  2239. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2240. cp->completed_kcq + i, j);
  2241. }
  2242. rcu_read_unlock();
  2243. end:
  2244. num_cqes -= j;
  2245. i += j;
  2246. j = 1;
  2247. }
  2248. if (unlikely(comp))
  2249. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2250. }
  2251. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2252. {
  2253. struct cnic_local *cp = dev->cnic_priv;
  2254. u16 i, ri, hw_prod, last;
  2255. struct kcqe *kcqe;
  2256. int kcqe_cnt = 0, last_cnt = 0;
  2257. i = ri = last = info->sw_prod_idx;
  2258. ri &= MAX_KCQ_IDX;
  2259. hw_prod = *info->hw_prod_idx_ptr;
  2260. hw_prod = info->hw_idx(hw_prod);
  2261. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2262. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2263. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2264. i = info->next_idx(i);
  2265. ri = i & MAX_KCQ_IDX;
  2266. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2267. last_cnt = kcqe_cnt;
  2268. last = i;
  2269. }
  2270. }
  2271. info->sw_prod_idx = last;
  2272. return last_cnt;
  2273. }
  2274. static int cnic_l2_completion(struct cnic_local *cp)
  2275. {
  2276. u16 hw_cons, sw_cons;
  2277. struct cnic_uio_dev *udev = cp->udev;
  2278. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2279. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2280. u32 cmd;
  2281. int comp = 0;
  2282. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2283. return 0;
  2284. hw_cons = *cp->rx_cons_ptr;
  2285. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2286. hw_cons++;
  2287. sw_cons = cp->rx_cons;
  2288. while (sw_cons != hw_cons) {
  2289. u8 cqe_fp_flags;
  2290. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2291. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2292. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2293. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2294. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2295. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2296. cmd == RAMROD_CMD_ID_ETH_HALT)
  2297. comp++;
  2298. }
  2299. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2300. }
  2301. return comp;
  2302. }
  2303. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2304. {
  2305. u16 rx_cons, tx_cons;
  2306. int comp = 0;
  2307. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2308. return;
  2309. rx_cons = *cp->rx_cons_ptr;
  2310. tx_cons = *cp->tx_cons_ptr;
  2311. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2312. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2313. comp = cnic_l2_completion(cp);
  2314. cp->tx_cons = tx_cons;
  2315. cp->rx_cons = rx_cons;
  2316. if (cp->udev)
  2317. uio_event_notify(&cp->udev->cnic_uinfo);
  2318. }
  2319. if (comp)
  2320. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2321. }
  2322. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2323. {
  2324. struct cnic_local *cp = dev->cnic_priv;
  2325. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2326. int kcqe_cnt;
  2327. /* status block index must be read before reading other fields */
  2328. rmb();
  2329. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2330. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2331. service_kcqes(dev, kcqe_cnt);
  2332. /* Tell compiler that status_blk fields can change. */
  2333. barrier();
  2334. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2335. /* status block index must be read first */
  2336. rmb();
  2337. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2338. }
  2339. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2340. cnic_chk_pkt_rings(cp);
  2341. return status_idx;
  2342. }
  2343. static int cnic_service_bnx2(void *data, void *status_blk)
  2344. {
  2345. struct cnic_dev *dev = data;
  2346. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2347. struct status_block *sblk = status_blk;
  2348. return sblk->status_idx;
  2349. }
  2350. return cnic_service_bnx2_queues(dev);
  2351. }
  2352. static void cnic_service_bnx2_msix(unsigned long data)
  2353. {
  2354. struct cnic_dev *dev = (struct cnic_dev *) data;
  2355. struct cnic_local *cp = dev->cnic_priv;
  2356. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2357. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2358. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2359. }
  2360. static void cnic_doirq(struct cnic_dev *dev)
  2361. {
  2362. struct cnic_local *cp = dev->cnic_priv;
  2363. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2364. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2365. prefetch(cp->status_blk.gen);
  2366. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2367. tasklet_schedule(&cp->cnic_irq_task);
  2368. }
  2369. }
  2370. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2371. {
  2372. struct cnic_dev *dev = dev_instance;
  2373. struct cnic_local *cp = dev->cnic_priv;
  2374. if (cp->ack_int)
  2375. cp->ack_int(dev);
  2376. cnic_doirq(dev);
  2377. return IRQ_HANDLED;
  2378. }
  2379. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2380. u16 index, u8 op, u8 update)
  2381. {
  2382. struct cnic_local *cp = dev->cnic_priv;
  2383. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2384. COMMAND_REG_INT_ACK);
  2385. struct igu_ack_register igu_ack;
  2386. igu_ack.status_block_index = index;
  2387. igu_ack.sb_id_and_flags =
  2388. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2389. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2390. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2391. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2392. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2393. }
  2394. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2395. u16 index, u8 op, u8 update)
  2396. {
  2397. struct igu_regular cmd_data;
  2398. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2399. cmd_data.sb_id_and_flags =
  2400. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2401. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2402. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2403. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2404. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2405. }
  2406. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2407. {
  2408. struct cnic_local *cp = dev->cnic_priv;
  2409. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2410. IGU_INT_DISABLE, 0);
  2411. }
  2412. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2413. {
  2414. struct cnic_local *cp = dev->cnic_priv;
  2415. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2416. IGU_INT_DISABLE, 0);
  2417. }
  2418. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2419. {
  2420. u32 last_status = *info->status_idx_ptr;
  2421. int kcqe_cnt;
  2422. /* status block index must be read before reading the KCQ */
  2423. rmb();
  2424. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2425. service_kcqes(dev, kcqe_cnt);
  2426. /* Tell compiler that sblk fields can change. */
  2427. barrier();
  2428. last_status = *info->status_idx_ptr;
  2429. /* status block index must be read before reading the KCQ */
  2430. rmb();
  2431. }
  2432. return last_status;
  2433. }
  2434. static void cnic_service_bnx2x_bh(unsigned long data)
  2435. {
  2436. struct cnic_dev *dev = (struct cnic_dev *) data;
  2437. struct cnic_local *cp = dev->cnic_priv;
  2438. u32 status_idx, new_status_idx;
  2439. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2440. return;
  2441. while (1) {
  2442. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2443. CNIC_WR16(dev, cp->kcq1.io_addr,
  2444. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2445. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2446. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2447. status_idx, IGU_INT_ENABLE, 1);
  2448. break;
  2449. }
  2450. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2451. if (new_status_idx != status_idx)
  2452. continue;
  2453. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2454. MAX_KCQ_IDX);
  2455. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2456. status_idx, IGU_INT_ENABLE, 1);
  2457. break;
  2458. }
  2459. }
  2460. static int cnic_service_bnx2x(void *data, void *status_blk)
  2461. {
  2462. struct cnic_dev *dev = data;
  2463. struct cnic_local *cp = dev->cnic_priv;
  2464. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2465. cnic_doirq(dev);
  2466. cnic_chk_pkt_rings(cp);
  2467. return 0;
  2468. }
  2469. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2470. {
  2471. struct cnic_ulp_ops *ulp_ops;
  2472. if (if_type == CNIC_ULP_ISCSI)
  2473. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2474. mutex_lock(&cnic_lock);
  2475. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2476. lockdep_is_held(&cnic_lock));
  2477. if (!ulp_ops) {
  2478. mutex_unlock(&cnic_lock);
  2479. return;
  2480. }
  2481. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2482. mutex_unlock(&cnic_lock);
  2483. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2484. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2485. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2486. }
  2487. static void cnic_ulp_stop(struct cnic_dev *dev)
  2488. {
  2489. struct cnic_local *cp = dev->cnic_priv;
  2490. int if_type;
  2491. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2492. cnic_ulp_stop_one(cp, if_type);
  2493. }
  2494. static void cnic_ulp_start(struct cnic_dev *dev)
  2495. {
  2496. struct cnic_local *cp = dev->cnic_priv;
  2497. int if_type;
  2498. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2499. struct cnic_ulp_ops *ulp_ops;
  2500. mutex_lock(&cnic_lock);
  2501. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2502. lockdep_is_held(&cnic_lock));
  2503. if (!ulp_ops || !ulp_ops->cnic_start) {
  2504. mutex_unlock(&cnic_lock);
  2505. continue;
  2506. }
  2507. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2508. mutex_unlock(&cnic_lock);
  2509. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2510. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2511. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2512. }
  2513. }
  2514. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2515. {
  2516. struct cnic_dev *dev = data;
  2517. switch (info->cmd) {
  2518. case CNIC_CTL_STOP_CMD:
  2519. cnic_hold(dev);
  2520. cnic_ulp_stop(dev);
  2521. cnic_stop_hw(dev);
  2522. cnic_put(dev);
  2523. break;
  2524. case CNIC_CTL_START_CMD:
  2525. cnic_hold(dev);
  2526. if (!cnic_start_hw(dev))
  2527. cnic_ulp_start(dev);
  2528. cnic_put(dev);
  2529. break;
  2530. case CNIC_CTL_STOP_ISCSI_CMD: {
  2531. struct cnic_local *cp = dev->cnic_priv;
  2532. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2533. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2534. break;
  2535. }
  2536. case CNIC_CTL_COMPLETION_CMD: {
  2537. struct cnic_ctl_completion *comp = &info->data.comp;
  2538. u32 cid = BNX2X_SW_CID(comp->cid);
  2539. u32 l5_cid;
  2540. struct cnic_local *cp = dev->cnic_priv;
  2541. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2542. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2543. if (unlikely(comp->error)) {
  2544. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2545. netdev_err(dev->netdev,
  2546. "CID %x CFC delete comp error %x\n",
  2547. cid, comp->error);
  2548. }
  2549. ctx->wait_cond = 1;
  2550. wake_up(&ctx->waitq);
  2551. }
  2552. break;
  2553. }
  2554. default:
  2555. return -EINVAL;
  2556. }
  2557. return 0;
  2558. }
  2559. static void cnic_ulp_init(struct cnic_dev *dev)
  2560. {
  2561. int i;
  2562. struct cnic_local *cp = dev->cnic_priv;
  2563. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2564. struct cnic_ulp_ops *ulp_ops;
  2565. mutex_lock(&cnic_lock);
  2566. ulp_ops = cnic_ulp_tbl_prot(i);
  2567. if (!ulp_ops || !ulp_ops->cnic_init) {
  2568. mutex_unlock(&cnic_lock);
  2569. continue;
  2570. }
  2571. ulp_get(ulp_ops);
  2572. mutex_unlock(&cnic_lock);
  2573. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2574. ulp_ops->cnic_init(dev);
  2575. ulp_put(ulp_ops);
  2576. }
  2577. }
  2578. static void cnic_ulp_exit(struct cnic_dev *dev)
  2579. {
  2580. int i;
  2581. struct cnic_local *cp = dev->cnic_priv;
  2582. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2583. struct cnic_ulp_ops *ulp_ops;
  2584. mutex_lock(&cnic_lock);
  2585. ulp_ops = cnic_ulp_tbl_prot(i);
  2586. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2587. mutex_unlock(&cnic_lock);
  2588. continue;
  2589. }
  2590. ulp_get(ulp_ops);
  2591. mutex_unlock(&cnic_lock);
  2592. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2593. ulp_ops->cnic_exit(dev);
  2594. ulp_put(ulp_ops);
  2595. }
  2596. }
  2597. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2598. {
  2599. struct cnic_dev *dev = csk->dev;
  2600. struct l4_kwq_offload_pg *l4kwqe;
  2601. struct kwqe *wqes[1];
  2602. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2603. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2604. wqes[0] = (struct kwqe *) l4kwqe;
  2605. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2606. l4kwqe->flags =
  2607. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2608. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2609. l4kwqe->da0 = csk->ha[0];
  2610. l4kwqe->da1 = csk->ha[1];
  2611. l4kwqe->da2 = csk->ha[2];
  2612. l4kwqe->da3 = csk->ha[3];
  2613. l4kwqe->da4 = csk->ha[4];
  2614. l4kwqe->da5 = csk->ha[5];
  2615. l4kwqe->sa0 = dev->mac_addr[0];
  2616. l4kwqe->sa1 = dev->mac_addr[1];
  2617. l4kwqe->sa2 = dev->mac_addr[2];
  2618. l4kwqe->sa3 = dev->mac_addr[3];
  2619. l4kwqe->sa4 = dev->mac_addr[4];
  2620. l4kwqe->sa5 = dev->mac_addr[5];
  2621. l4kwqe->etype = ETH_P_IP;
  2622. l4kwqe->ipid_start = DEF_IPID_START;
  2623. l4kwqe->host_opaque = csk->l5_cid;
  2624. if (csk->vlan_id) {
  2625. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2626. l4kwqe->vlan_tag = csk->vlan_id;
  2627. l4kwqe->l2hdr_nbytes += 4;
  2628. }
  2629. return dev->submit_kwqes(dev, wqes, 1);
  2630. }
  2631. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2632. {
  2633. struct cnic_dev *dev = csk->dev;
  2634. struct l4_kwq_update_pg *l4kwqe;
  2635. struct kwqe *wqes[1];
  2636. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2637. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2638. wqes[0] = (struct kwqe *) l4kwqe;
  2639. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2640. l4kwqe->flags =
  2641. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2642. l4kwqe->pg_cid = csk->pg_cid;
  2643. l4kwqe->da0 = csk->ha[0];
  2644. l4kwqe->da1 = csk->ha[1];
  2645. l4kwqe->da2 = csk->ha[2];
  2646. l4kwqe->da3 = csk->ha[3];
  2647. l4kwqe->da4 = csk->ha[4];
  2648. l4kwqe->da5 = csk->ha[5];
  2649. l4kwqe->pg_host_opaque = csk->l5_cid;
  2650. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2651. return dev->submit_kwqes(dev, wqes, 1);
  2652. }
  2653. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2654. {
  2655. struct cnic_dev *dev = csk->dev;
  2656. struct l4_kwq_upload *l4kwqe;
  2657. struct kwqe *wqes[1];
  2658. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2659. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2660. wqes[0] = (struct kwqe *) l4kwqe;
  2661. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2662. l4kwqe->flags =
  2663. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2664. l4kwqe->cid = csk->pg_cid;
  2665. return dev->submit_kwqes(dev, wqes, 1);
  2666. }
  2667. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2668. {
  2669. struct cnic_dev *dev = csk->dev;
  2670. struct l4_kwq_connect_req1 *l4kwqe1;
  2671. struct l4_kwq_connect_req2 *l4kwqe2;
  2672. struct l4_kwq_connect_req3 *l4kwqe3;
  2673. struct kwqe *wqes[3];
  2674. u8 tcp_flags = 0;
  2675. int num_wqes = 2;
  2676. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2677. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2678. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2679. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2680. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2681. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2682. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2683. l4kwqe3->flags =
  2684. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2685. l4kwqe3->ka_timeout = csk->ka_timeout;
  2686. l4kwqe3->ka_interval = csk->ka_interval;
  2687. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2688. l4kwqe3->tos = csk->tos;
  2689. l4kwqe3->ttl = csk->ttl;
  2690. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2691. l4kwqe3->pmtu = csk->mtu;
  2692. l4kwqe3->rcv_buf = csk->rcv_buf;
  2693. l4kwqe3->snd_buf = csk->snd_buf;
  2694. l4kwqe3->seed = csk->seed;
  2695. wqes[0] = (struct kwqe *) l4kwqe1;
  2696. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2697. wqes[1] = (struct kwqe *) l4kwqe2;
  2698. wqes[2] = (struct kwqe *) l4kwqe3;
  2699. num_wqes = 3;
  2700. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2701. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2702. l4kwqe2->flags =
  2703. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2704. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2705. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2706. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2707. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2708. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2709. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2710. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2711. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2712. sizeof(struct tcphdr);
  2713. } else {
  2714. wqes[1] = (struct kwqe *) l4kwqe3;
  2715. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2716. sizeof(struct tcphdr);
  2717. }
  2718. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2719. l4kwqe1->flags =
  2720. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2721. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2722. l4kwqe1->cid = csk->cid;
  2723. l4kwqe1->pg_cid = csk->pg_cid;
  2724. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2725. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2726. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2727. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2728. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2729. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2730. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2731. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2732. if (csk->tcp_flags & SK_TCP_NAGLE)
  2733. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2734. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2735. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2736. if (csk->tcp_flags & SK_TCP_SACK)
  2737. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2738. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2739. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2740. l4kwqe1->tcp_flags = tcp_flags;
  2741. return dev->submit_kwqes(dev, wqes, num_wqes);
  2742. }
  2743. static int cnic_cm_close_req(struct cnic_sock *csk)
  2744. {
  2745. struct cnic_dev *dev = csk->dev;
  2746. struct l4_kwq_close_req *l4kwqe;
  2747. struct kwqe *wqes[1];
  2748. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2749. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2750. wqes[0] = (struct kwqe *) l4kwqe;
  2751. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2752. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2753. l4kwqe->cid = csk->cid;
  2754. return dev->submit_kwqes(dev, wqes, 1);
  2755. }
  2756. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2757. {
  2758. struct cnic_dev *dev = csk->dev;
  2759. struct l4_kwq_reset_req *l4kwqe;
  2760. struct kwqe *wqes[1];
  2761. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2762. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2763. wqes[0] = (struct kwqe *) l4kwqe;
  2764. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2765. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2766. l4kwqe->cid = csk->cid;
  2767. return dev->submit_kwqes(dev, wqes, 1);
  2768. }
  2769. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2770. u32 l5_cid, struct cnic_sock **csk, void *context)
  2771. {
  2772. struct cnic_local *cp = dev->cnic_priv;
  2773. struct cnic_sock *csk1;
  2774. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2775. return -EINVAL;
  2776. if (cp->ctx_tbl) {
  2777. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2778. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2779. return -EAGAIN;
  2780. }
  2781. csk1 = &cp->csk_tbl[l5_cid];
  2782. if (atomic_read(&csk1->ref_count))
  2783. return -EAGAIN;
  2784. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2785. return -EBUSY;
  2786. csk1->dev = dev;
  2787. csk1->cid = cid;
  2788. csk1->l5_cid = l5_cid;
  2789. csk1->ulp_type = ulp_type;
  2790. csk1->context = context;
  2791. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2792. csk1->ka_interval = DEF_KA_INTERVAL;
  2793. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2794. csk1->tos = DEF_TOS;
  2795. csk1->ttl = DEF_TTL;
  2796. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2797. csk1->rcv_buf = DEF_RCV_BUF;
  2798. csk1->snd_buf = DEF_SND_BUF;
  2799. csk1->seed = DEF_SEED;
  2800. *csk = csk1;
  2801. return 0;
  2802. }
  2803. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2804. {
  2805. if (csk->src_port) {
  2806. struct cnic_dev *dev = csk->dev;
  2807. struct cnic_local *cp = dev->cnic_priv;
  2808. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2809. csk->src_port = 0;
  2810. }
  2811. }
  2812. static void cnic_close_conn(struct cnic_sock *csk)
  2813. {
  2814. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2815. cnic_cm_upload_pg(csk);
  2816. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2817. }
  2818. cnic_cm_cleanup(csk);
  2819. }
  2820. static int cnic_cm_destroy(struct cnic_sock *csk)
  2821. {
  2822. if (!cnic_in_use(csk))
  2823. return -EINVAL;
  2824. csk_hold(csk);
  2825. clear_bit(SK_F_INUSE, &csk->flags);
  2826. smp_mb__after_clear_bit();
  2827. while (atomic_read(&csk->ref_count) != 1)
  2828. msleep(1);
  2829. cnic_cm_cleanup(csk);
  2830. csk->flags = 0;
  2831. csk_put(csk);
  2832. return 0;
  2833. }
  2834. static inline u16 cnic_get_vlan(struct net_device *dev,
  2835. struct net_device **vlan_dev)
  2836. {
  2837. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2838. *vlan_dev = vlan_dev_real_dev(dev);
  2839. return vlan_dev_vlan_id(dev);
  2840. }
  2841. *vlan_dev = dev;
  2842. return 0;
  2843. }
  2844. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2845. struct dst_entry **dst)
  2846. {
  2847. #if defined(CONFIG_INET)
  2848. struct rtable *rt;
  2849. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2850. if (!IS_ERR(rt)) {
  2851. *dst = &rt->dst;
  2852. return 0;
  2853. }
  2854. return PTR_ERR(rt);
  2855. #else
  2856. return -ENETUNREACH;
  2857. #endif
  2858. }
  2859. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2860. struct dst_entry **dst)
  2861. {
  2862. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2863. struct flowi6 fl6;
  2864. memset(&fl6, 0, sizeof(fl6));
  2865. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2866. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2867. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2868. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2869. if (*dst)
  2870. return 0;
  2871. #endif
  2872. return -ENETUNREACH;
  2873. }
  2874. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2875. int ulp_type)
  2876. {
  2877. struct cnic_dev *dev = NULL;
  2878. struct dst_entry *dst;
  2879. struct net_device *netdev = NULL;
  2880. int err = -ENETUNREACH;
  2881. if (dst_addr->sin_family == AF_INET)
  2882. err = cnic_get_v4_route(dst_addr, &dst);
  2883. else if (dst_addr->sin_family == AF_INET6) {
  2884. struct sockaddr_in6 *dst_addr6 =
  2885. (struct sockaddr_in6 *) dst_addr;
  2886. err = cnic_get_v6_route(dst_addr6, &dst);
  2887. } else
  2888. return NULL;
  2889. if (err)
  2890. return NULL;
  2891. if (!dst->dev)
  2892. goto done;
  2893. cnic_get_vlan(dst->dev, &netdev);
  2894. dev = cnic_from_netdev(netdev);
  2895. done:
  2896. dst_release(dst);
  2897. if (dev)
  2898. cnic_put(dev);
  2899. return dev;
  2900. }
  2901. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2902. {
  2903. struct cnic_dev *dev = csk->dev;
  2904. struct cnic_local *cp = dev->cnic_priv;
  2905. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2906. }
  2907. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2908. {
  2909. struct cnic_dev *dev = csk->dev;
  2910. struct cnic_local *cp = dev->cnic_priv;
  2911. int is_v6, rc = 0;
  2912. struct dst_entry *dst = NULL;
  2913. struct net_device *realdev;
  2914. __be16 local_port;
  2915. u32 port_id;
  2916. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2917. saddr->remote.v6.sin6_family == AF_INET6)
  2918. is_v6 = 1;
  2919. else if (saddr->local.v4.sin_family == AF_INET &&
  2920. saddr->remote.v4.sin_family == AF_INET)
  2921. is_v6 = 0;
  2922. else
  2923. return -EINVAL;
  2924. clear_bit(SK_F_IPV6, &csk->flags);
  2925. if (is_v6) {
  2926. set_bit(SK_F_IPV6, &csk->flags);
  2927. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2928. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2929. sizeof(struct in6_addr));
  2930. csk->dst_port = saddr->remote.v6.sin6_port;
  2931. local_port = saddr->local.v6.sin6_port;
  2932. } else {
  2933. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2934. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2935. csk->dst_port = saddr->remote.v4.sin_port;
  2936. local_port = saddr->local.v4.sin_port;
  2937. }
  2938. csk->vlan_id = 0;
  2939. csk->mtu = dev->netdev->mtu;
  2940. if (dst && dst->dev) {
  2941. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2942. if (realdev == dev->netdev) {
  2943. csk->vlan_id = vlan;
  2944. csk->mtu = dst_mtu(dst);
  2945. }
  2946. }
  2947. port_id = be16_to_cpu(local_port);
  2948. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2949. port_id < CNIC_LOCAL_PORT_MAX) {
  2950. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2951. port_id = 0;
  2952. } else
  2953. port_id = 0;
  2954. if (!port_id) {
  2955. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2956. if (port_id == -1) {
  2957. rc = -ENOMEM;
  2958. goto err_out;
  2959. }
  2960. local_port = cpu_to_be16(port_id);
  2961. }
  2962. csk->src_port = local_port;
  2963. err_out:
  2964. dst_release(dst);
  2965. return rc;
  2966. }
  2967. static void cnic_init_csk_state(struct cnic_sock *csk)
  2968. {
  2969. csk->state = 0;
  2970. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2971. clear_bit(SK_F_CLOSING, &csk->flags);
  2972. }
  2973. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2974. {
  2975. struct cnic_local *cp = csk->dev->cnic_priv;
  2976. int err = 0;
  2977. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  2978. return -EOPNOTSUPP;
  2979. if (!cnic_in_use(csk))
  2980. return -EINVAL;
  2981. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2982. return -EINVAL;
  2983. cnic_init_csk_state(csk);
  2984. err = cnic_get_route(csk, saddr);
  2985. if (err)
  2986. goto err_out;
  2987. err = cnic_resolve_addr(csk, saddr);
  2988. if (!err)
  2989. return 0;
  2990. err_out:
  2991. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2992. return err;
  2993. }
  2994. static int cnic_cm_abort(struct cnic_sock *csk)
  2995. {
  2996. struct cnic_local *cp = csk->dev->cnic_priv;
  2997. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2998. if (!cnic_in_use(csk))
  2999. return -EINVAL;
  3000. if (cnic_abort_prep(csk))
  3001. return cnic_cm_abort_req(csk);
  3002. /* Getting here means that we haven't started connect, or
  3003. * connect was not successful.
  3004. */
  3005. cp->close_conn(csk, opcode);
  3006. if (csk->state != opcode)
  3007. return -EALREADY;
  3008. return 0;
  3009. }
  3010. static int cnic_cm_close(struct cnic_sock *csk)
  3011. {
  3012. if (!cnic_in_use(csk))
  3013. return -EINVAL;
  3014. if (cnic_close_prep(csk)) {
  3015. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3016. return cnic_cm_close_req(csk);
  3017. } else {
  3018. return -EALREADY;
  3019. }
  3020. return 0;
  3021. }
  3022. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3023. u8 opcode)
  3024. {
  3025. struct cnic_ulp_ops *ulp_ops;
  3026. int ulp_type = csk->ulp_type;
  3027. rcu_read_lock();
  3028. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3029. if (ulp_ops) {
  3030. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3031. ulp_ops->cm_connect_complete(csk);
  3032. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3033. ulp_ops->cm_close_complete(csk);
  3034. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3035. ulp_ops->cm_remote_abort(csk);
  3036. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3037. ulp_ops->cm_abort_complete(csk);
  3038. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3039. ulp_ops->cm_remote_close(csk);
  3040. }
  3041. rcu_read_unlock();
  3042. }
  3043. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3044. {
  3045. if (cnic_offld_prep(csk)) {
  3046. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3047. cnic_cm_update_pg(csk);
  3048. else
  3049. cnic_cm_offload_pg(csk);
  3050. }
  3051. return 0;
  3052. }
  3053. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3054. {
  3055. struct cnic_local *cp = dev->cnic_priv;
  3056. u32 l5_cid = kcqe->pg_host_opaque;
  3057. u8 opcode = kcqe->op_code;
  3058. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3059. csk_hold(csk);
  3060. if (!cnic_in_use(csk))
  3061. goto done;
  3062. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3063. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3064. goto done;
  3065. }
  3066. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3067. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3068. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3069. cnic_cm_upcall(cp, csk,
  3070. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3071. goto done;
  3072. }
  3073. csk->pg_cid = kcqe->pg_cid;
  3074. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3075. cnic_cm_conn_req(csk);
  3076. done:
  3077. csk_put(csk);
  3078. }
  3079. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3080. {
  3081. struct cnic_local *cp = dev->cnic_priv;
  3082. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3083. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3084. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3085. ctx->timestamp = jiffies;
  3086. ctx->wait_cond = 1;
  3087. wake_up(&ctx->waitq);
  3088. }
  3089. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3090. {
  3091. struct cnic_local *cp = dev->cnic_priv;
  3092. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3093. u8 opcode = l4kcqe->op_code;
  3094. u32 l5_cid;
  3095. struct cnic_sock *csk;
  3096. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3097. cnic_process_fcoe_term_conn(dev, kcqe);
  3098. return;
  3099. }
  3100. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3101. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3102. cnic_cm_process_offld_pg(dev, l4kcqe);
  3103. return;
  3104. }
  3105. l5_cid = l4kcqe->conn_id;
  3106. if (opcode & 0x80)
  3107. l5_cid = l4kcqe->cid;
  3108. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3109. return;
  3110. csk = &cp->csk_tbl[l5_cid];
  3111. csk_hold(csk);
  3112. if (!cnic_in_use(csk)) {
  3113. csk_put(csk);
  3114. return;
  3115. }
  3116. switch (opcode) {
  3117. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3118. if (l4kcqe->status != 0) {
  3119. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3120. cnic_cm_upcall(cp, csk,
  3121. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3122. }
  3123. break;
  3124. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3125. if (l4kcqe->status == 0)
  3126. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3127. smp_mb__before_clear_bit();
  3128. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3129. cnic_cm_upcall(cp, csk, opcode);
  3130. break;
  3131. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3132. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3133. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3134. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3135. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3136. cp->close_conn(csk, opcode);
  3137. break;
  3138. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3139. /* after we already sent CLOSE_REQ */
  3140. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3141. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3142. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3143. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3144. else
  3145. cnic_cm_upcall(cp, csk, opcode);
  3146. break;
  3147. }
  3148. csk_put(csk);
  3149. }
  3150. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3151. {
  3152. struct cnic_dev *dev = data;
  3153. int i;
  3154. for (i = 0; i < num; i++)
  3155. cnic_cm_process_kcqe(dev, kcqe[i]);
  3156. }
  3157. static struct cnic_ulp_ops cm_ulp_ops = {
  3158. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3159. };
  3160. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3161. {
  3162. struct cnic_local *cp = dev->cnic_priv;
  3163. kfree(cp->csk_tbl);
  3164. cp->csk_tbl = NULL;
  3165. cnic_free_id_tbl(&cp->csk_port_tbl);
  3166. }
  3167. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3168. {
  3169. struct cnic_local *cp = dev->cnic_priv;
  3170. u32 port_id;
  3171. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3172. GFP_KERNEL);
  3173. if (!cp->csk_tbl)
  3174. return -ENOMEM;
  3175. get_random_bytes(&port_id, sizeof(port_id));
  3176. port_id %= CNIC_LOCAL_PORT_RANGE;
  3177. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3178. CNIC_LOCAL_PORT_MIN, port_id)) {
  3179. cnic_cm_free_mem(dev);
  3180. return -ENOMEM;
  3181. }
  3182. return 0;
  3183. }
  3184. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3185. {
  3186. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3187. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3188. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3189. csk->state = opcode;
  3190. }
  3191. /* 1. If event opcode matches the expected event in csk->state
  3192. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3193. * event
  3194. * 3. If the expected event is 0, meaning the connection was never
  3195. * never established, we accept the opcode from cm_abort.
  3196. */
  3197. if (opcode == csk->state || csk->state == 0 ||
  3198. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3199. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3200. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3201. if (csk->state == 0)
  3202. csk->state = opcode;
  3203. return 1;
  3204. }
  3205. }
  3206. return 0;
  3207. }
  3208. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3209. {
  3210. struct cnic_dev *dev = csk->dev;
  3211. struct cnic_local *cp = dev->cnic_priv;
  3212. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3213. cnic_cm_upcall(cp, csk, opcode);
  3214. return;
  3215. }
  3216. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3217. cnic_close_conn(csk);
  3218. csk->state = opcode;
  3219. cnic_cm_upcall(cp, csk, opcode);
  3220. }
  3221. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3222. {
  3223. }
  3224. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3225. {
  3226. u32 seed;
  3227. get_random_bytes(&seed, 4);
  3228. cnic_ctx_wr(dev, 45, 0, seed);
  3229. return 0;
  3230. }
  3231. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3232. {
  3233. struct cnic_dev *dev = csk->dev;
  3234. struct cnic_local *cp = dev->cnic_priv;
  3235. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3236. union l5cm_specific_data l5_data;
  3237. u32 cmd = 0;
  3238. int close_complete = 0;
  3239. switch (opcode) {
  3240. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3241. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3242. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3243. if (cnic_ready_to_close(csk, opcode)) {
  3244. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3245. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3246. else
  3247. close_complete = 1;
  3248. }
  3249. break;
  3250. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3251. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3252. break;
  3253. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3254. close_complete = 1;
  3255. break;
  3256. }
  3257. if (cmd) {
  3258. memset(&l5_data, 0, sizeof(l5_data));
  3259. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3260. &l5_data);
  3261. } else if (close_complete) {
  3262. ctx->timestamp = jiffies;
  3263. cnic_close_conn(csk);
  3264. cnic_cm_upcall(cp, csk, csk->state);
  3265. }
  3266. }
  3267. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3268. {
  3269. struct cnic_local *cp = dev->cnic_priv;
  3270. int i;
  3271. if (!cp->ctx_tbl)
  3272. return;
  3273. if (!netif_running(dev->netdev))
  3274. return;
  3275. for (i = 0; i < cp->max_cid_space; i++) {
  3276. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3277. int j;
  3278. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3279. msleep(10);
  3280. for (j = 0; j < 5; j++) {
  3281. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3282. break;
  3283. msleep(20);
  3284. }
  3285. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3286. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3287. ctx->cid);
  3288. }
  3289. cancel_delayed_work(&cp->delete_task);
  3290. flush_workqueue(cnic_wq);
  3291. if (atomic_read(&cp->iscsi_conn) != 0)
  3292. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3293. atomic_read(&cp->iscsi_conn));
  3294. }
  3295. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3296. {
  3297. struct cnic_local *cp = dev->cnic_priv;
  3298. u32 pfid = cp->pfid;
  3299. u32 port = CNIC_PORT(cp);
  3300. cnic_init_bnx2x_mac(dev);
  3301. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3302. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3303. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3304. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3305. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3306. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3307. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3308. DEF_MAX_DA_COUNT);
  3309. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3310. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3311. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3312. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3313. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3314. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3315. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3316. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3317. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3318. DEF_MAX_CWND);
  3319. return 0;
  3320. }
  3321. static void cnic_delete_task(struct work_struct *work)
  3322. {
  3323. struct cnic_local *cp;
  3324. struct cnic_dev *dev;
  3325. u32 i;
  3326. int need_resched = 0;
  3327. cp = container_of(work, struct cnic_local, delete_task.work);
  3328. dev = cp->dev;
  3329. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3330. struct drv_ctl_info info;
  3331. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3332. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3333. cp->ethdev->drv_ctl(dev->netdev, &info);
  3334. }
  3335. for (i = 0; i < cp->max_cid_space; i++) {
  3336. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3337. int err;
  3338. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3339. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3340. continue;
  3341. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3342. need_resched = 1;
  3343. continue;
  3344. }
  3345. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3346. continue;
  3347. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3348. cnic_free_bnx2x_conn_resc(dev, i);
  3349. if (!err) {
  3350. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3351. atomic_dec(&cp->iscsi_conn);
  3352. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3353. }
  3354. }
  3355. if (need_resched)
  3356. queue_delayed_work(cnic_wq, &cp->delete_task,
  3357. msecs_to_jiffies(10));
  3358. }
  3359. static int cnic_cm_open(struct cnic_dev *dev)
  3360. {
  3361. struct cnic_local *cp = dev->cnic_priv;
  3362. int err;
  3363. err = cnic_cm_alloc_mem(dev);
  3364. if (err)
  3365. return err;
  3366. err = cp->start_cm(dev);
  3367. if (err)
  3368. goto err_out;
  3369. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3370. dev->cm_create = cnic_cm_create;
  3371. dev->cm_destroy = cnic_cm_destroy;
  3372. dev->cm_connect = cnic_cm_connect;
  3373. dev->cm_abort = cnic_cm_abort;
  3374. dev->cm_close = cnic_cm_close;
  3375. dev->cm_select_dev = cnic_cm_select_dev;
  3376. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3377. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3378. return 0;
  3379. err_out:
  3380. cnic_cm_free_mem(dev);
  3381. return err;
  3382. }
  3383. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3384. {
  3385. struct cnic_local *cp = dev->cnic_priv;
  3386. int i;
  3387. cp->stop_cm(dev);
  3388. if (!cp->csk_tbl)
  3389. return 0;
  3390. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3391. struct cnic_sock *csk = &cp->csk_tbl[i];
  3392. clear_bit(SK_F_INUSE, &csk->flags);
  3393. cnic_cm_cleanup(csk);
  3394. }
  3395. cnic_cm_free_mem(dev);
  3396. return 0;
  3397. }
  3398. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3399. {
  3400. u32 cid_addr;
  3401. int i;
  3402. cid_addr = GET_CID_ADDR(cid);
  3403. for (i = 0; i < CTX_SIZE; i += 4)
  3404. cnic_ctx_wr(dev, cid_addr, i, 0);
  3405. }
  3406. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3407. {
  3408. struct cnic_local *cp = dev->cnic_priv;
  3409. int ret = 0, i;
  3410. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3411. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3412. return 0;
  3413. for (i = 0; i < cp->ctx_blks; i++) {
  3414. int j;
  3415. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3416. u32 val;
  3417. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3418. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3419. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3420. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3421. (u64) cp->ctx_arr[i].mapping >> 32);
  3422. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3423. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3424. for (j = 0; j < 10; j++) {
  3425. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3426. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3427. break;
  3428. udelay(5);
  3429. }
  3430. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3431. ret = -EBUSY;
  3432. break;
  3433. }
  3434. }
  3435. return ret;
  3436. }
  3437. static void cnic_free_irq(struct cnic_dev *dev)
  3438. {
  3439. struct cnic_local *cp = dev->cnic_priv;
  3440. struct cnic_eth_dev *ethdev = cp->ethdev;
  3441. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3442. cp->disable_int_sync(dev);
  3443. tasklet_kill(&cp->cnic_irq_task);
  3444. free_irq(ethdev->irq_arr[0].vector, dev);
  3445. }
  3446. }
  3447. static int cnic_request_irq(struct cnic_dev *dev)
  3448. {
  3449. struct cnic_local *cp = dev->cnic_priv;
  3450. struct cnic_eth_dev *ethdev = cp->ethdev;
  3451. int err;
  3452. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3453. if (err)
  3454. tasklet_disable(&cp->cnic_irq_task);
  3455. return err;
  3456. }
  3457. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3458. {
  3459. struct cnic_local *cp = dev->cnic_priv;
  3460. struct cnic_eth_dev *ethdev = cp->ethdev;
  3461. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3462. int err, i = 0;
  3463. int sblk_num = cp->status_blk_num;
  3464. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3465. BNX2_HC_SB_CONFIG_1;
  3466. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3467. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3468. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3469. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3470. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3471. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3472. (unsigned long) dev);
  3473. err = cnic_request_irq(dev);
  3474. if (err)
  3475. return err;
  3476. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3477. i < 10) {
  3478. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3479. 1 << (11 + sblk_num));
  3480. udelay(10);
  3481. i++;
  3482. barrier();
  3483. }
  3484. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3485. cnic_free_irq(dev);
  3486. goto failed;
  3487. }
  3488. } else {
  3489. struct status_block *sblk = cp->status_blk.gen;
  3490. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3491. int i = 0;
  3492. while (sblk->status_completion_producer_index && i < 10) {
  3493. CNIC_WR(dev, BNX2_HC_COMMAND,
  3494. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3495. udelay(10);
  3496. i++;
  3497. barrier();
  3498. }
  3499. if (sblk->status_completion_producer_index)
  3500. goto failed;
  3501. }
  3502. return 0;
  3503. failed:
  3504. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3505. return -EBUSY;
  3506. }
  3507. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3508. {
  3509. struct cnic_local *cp = dev->cnic_priv;
  3510. struct cnic_eth_dev *ethdev = cp->ethdev;
  3511. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3512. return;
  3513. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3514. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3515. }
  3516. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3517. {
  3518. struct cnic_local *cp = dev->cnic_priv;
  3519. struct cnic_eth_dev *ethdev = cp->ethdev;
  3520. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3521. return;
  3522. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3523. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3524. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3525. synchronize_irq(ethdev->irq_arr[0].vector);
  3526. }
  3527. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3528. {
  3529. struct cnic_local *cp = dev->cnic_priv;
  3530. struct cnic_eth_dev *ethdev = cp->ethdev;
  3531. struct cnic_uio_dev *udev = cp->udev;
  3532. u32 cid_addr, tx_cid, sb_id;
  3533. u32 val, offset0, offset1, offset2, offset3;
  3534. int i;
  3535. struct tx_bd *txbd;
  3536. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3537. struct status_block *s_blk = cp->status_blk.gen;
  3538. sb_id = cp->status_blk_num;
  3539. tx_cid = 20;
  3540. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3541. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3542. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3543. tx_cid = TX_TSS_CID + sb_id - 1;
  3544. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3545. (TX_TSS_CID << 7));
  3546. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3547. }
  3548. cp->tx_cons = *cp->tx_cons_ptr;
  3549. cid_addr = GET_CID_ADDR(tx_cid);
  3550. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3551. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3552. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3553. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3554. offset0 = BNX2_L2CTX_TYPE_XI;
  3555. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3556. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3557. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3558. } else {
  3559. cnic_init_context(dev, tx_cid);
  3560. cnic_init_context(dev, tx_cid + 1);
  3561. offset0 = BNX2_L2CTX_TYPE;
  3562. offset1 = BNX2_L2CTX_CMD_TYPE;
  3563. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3564. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3565. }
  3566. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3567. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3568. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3569. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3570. txbd = udev->l2_ring;
  3571. buf_map = udev->l2_buf_map;
  3572. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3573. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3574. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3575. }
  3576. val = (u64) ring_map >> 32;
  3577. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3578. txbd->tx_bd_haddr_hi = val;
  3579. val = (u64) ring_map & 0xffffffff;
  3580. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3581. txbd->tx_bd_haddr_lo = val;
  3582. }
  3583. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3584. {
  3585. struct cnic_local *cp = dev->cnic_priv;
  3586. struct cnic_eth_dev *ethdev = cp->ethdev;
  3587. struct cnic_uio_dev *udev = cp->udev;
  3588. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3589. int i;
  3590. struct rx_bd *rxbd;
  3591. struct status_block *s_blk = cp->status_blk.gen;
  3592. dma_addr_t ring_map = udev->l2_ring_map;
  3593. sb_id = cp->status_blk_num;
  3594. cnic_init_context(dev, 2);
  3595. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3596. coal_reg = BNX2_HC_COMMAND;
  3597. coal_val = CNIC_RD(dev, coal_reg);
  3598. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3599. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3600. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3601. coal_reg = BNX2_HC_COALESCE_NOW;
  3602. coal_val = 1 << (11 + sb_id);
  3603. }
  3604. i = 0;
  3605. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3606. CNIC_WR(dev, coal_reg, coal_val);
  3607. udelay(10);
  3608. i++;
  3609. barrier();
  3610. }
  3611. cp->rx_cons = *cp->rx_cons_ptr;
  3612. cid_addr = GET_CID_ADDR(2);
  3613. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3614. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3615. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3616. if (sb_id == 0)
  3617. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3618. else
  3619. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3620. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3621. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3622. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3623. dma_addr_t buf_map;
  3624. int n = (i % cp->l2_rx_ring_size) + 1;
  3625. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3626. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3627. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3628. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3629. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3630. }
  3631. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3632. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3633. rxbd->rx_bd_haddr_hi = val;
  3634. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3635. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3636. rxbd->rx_bd_haddr_lo = val;
  3637. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3638. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3639. }
  3640. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3641. {
  3642. struct kwqe *wqes[1], l2kwqe;
  3643. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3644. wqes[0] = &l2kwqe;
  3645. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3646. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3647. KWQE_OPCODE_SHIFT) | 2;
  3648. dev->submit_kwqes(dev, wqes, 1);
  3649. }
  3650. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3651. {
  3652. struct cnic_local *cp = dev->cnic_priv;
  3653. u32 val;
  3654. val = cp->func << 2;
  3655. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3656. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3657. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3658. dev->mac_addr[0] = (u8) (val >> 8);
  3659. dev->mac_addr[1] = (u8) val;
  3660. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3661. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3662. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3663. dev->mac_addr[2] = (u8) (val >> 24);
  3664. dev->mac_addr[3] = (u8) (val >> 16);
  3665. dev->mac_addr[4] = (u8) (val >> 8);
  3666. dev->mac_addr[5] = (u8) val;
  3667. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3668. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3669. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3670. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3671. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3672. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3673. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3674. }
  3675. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3676. {
  3677. struct cnic_local *cp = dev->cnic_priv;
  3678. struct cnic_eth_dev *ethdev = cp->ethdev;
  3679. struct status_block *sblk = cp->status_blk.gen;
  3680. u32 val, kcq_cid_addr, kwq_cid_addr;
  3681. int err;
  3682. cnic_set_bnx2_mac(dev);
  3683. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3684. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3685. if (BCM_PAGE_BITS > 12)
  3686. val |= (12 - 8) << 4;
  3687. else
  3688. val |= (BCM_PAGE_BITS - 8) << 4;
  3689. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3690. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3691. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3692. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3693. err = cnic_setup_5709_context(dev, 1);
  3694. if (err)
  3695. return err;
  3696. cnic_init_context(dev, KWQ_CID);
  3697. cnic_init_context(dev, KCQ_CID);
  3698. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3699. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3700. cp->max_kwq_idx = MAX_KWQ_IDX;
  3701. cp->kwq_prod_idx = 0;
  3702. cp->kwq_con_idx = 0;
  3703. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3704. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3705. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3706. else
  3707. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3708. /* Initialize the kernel work queue context. */
  3709. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3710. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3711. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3712. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3713. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3714. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3715. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3716. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3717. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3718. val = (u32) cp->kwq_info.pgtbl_map;
  3719. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3720. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3721. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3722. cp->kcq1.sw_prod_idx = 0;
  3723. cp->kcq1.hw_prod_idx_ptr =
  3724. (u16 *) &sblk->status_completion_producer_index;
  3725. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3726. /* Initialize the kernel complete queue context. */
  3727. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3728. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3729. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3730. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3731. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3732. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3733. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3734. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3735. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3736. val = (u32) cp->kcq1.dma.pgtbl_map;
  3737. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3738. cp->int_num = 0;
  3739. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3740. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3741. u32 sb_id = cp->status_blk_num;
  3742. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3743. cp->kcq1.hw_prod_idx_ptr =
  3744. (u16 *) &msblk->status_completion_producer_index;
  3745. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3746. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3747. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3748. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3749. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3750. }
  3751. /* Enable Commnad Scheduler notification when we write to the
  3752. * host producer index of the kernel contexts. */
  3753. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3754. /* Enable Command Scheduler notification when we write to either
  3755. * the Send Queue or Receive Queue producer indexes of the kernel
  3756. * bypass contexts. */
  3757. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3758. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3759. /* Notify COM when the driver post an application buffer. */
  3760. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3761. /* Set the CP and COM doorbells. These two processors polls the
  3762. * doorbell for a non zero value before running. This must be done
  3763. * after setting up the kernel queue contexts. */
  3764. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3765. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3766. cnic_init_bnx2_tx_ring(dev);
  3767. cnic_init_bnx2_rx_ring(dev);
  3768. err = cnic_init_bnx2_irq(dev);
  3769. if (err) {
  3770. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3771. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3772. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3773. return err;
  3774. }
  3775. return 0;
  3776. }
  3777. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3778. {
  3779. struct cnic_local *cp = dev->cnic_priv;
  3780. struct cnic_eth_dev *ethdev = cp->ethdev;
  3781. u32 start_offset = ethdev->ctx_tbl_offset;
  3782. int i;
  3783. for (i = 0; i < cp->ctx_blks; i++) {
  3784. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3785. dma_addr_t map = ctx->mapping;
  3786. if (cp->ctx_align) {
  3787. unsigned long mask = cp->ctx_align - 1;
  3788. map = (map + mask) & ~mask;
  3789. }
  3790. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3791. }
  3792. }
  3793. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3794. {
  3795. struct cnic_local *cp = dev->cnic_priv;
  3796. struct cnic_eth_dev *ethdev = cp->ethdev;
  3797. int err = 0;
  3798. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3799. (unsigned long) dev);
  3800. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3801. err = cnic_request_irq(dev);
  3802. return err;
  3803. }
  3804. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3805. u16 sb_id, u8 sb_index,
  3806. u8 disable)
  3807. {
  3808. u32 addr = BAR_CSTRORM_INTMEM +
  3809. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3810. offsetof(struct hc_status_block_data_e1x, index_data) +
  3811. sizeof(struct hc_index_data)*sb_index +
  3812. offsetof(struct hc_index_data, flags);
  3813. u16 flags = CNIC_RD16(dev, addr);
  3814. /* clear and set */
  3815. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3816. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3817. HC_INDEX_DATA_HC_ENABLED);
  3818. CNIC_WR16(dev, addr, flags);
  3819. }
  3820. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3821. {
  3822. struct cnic_local *cp = dev->cnic_priv;
  3823. u8 sb_id = cp->status_blk_num;
  3824. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3825. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3826. offsetof(struct hc_status_block_data_e1x, index_data) +
  3827. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3828. offsetof(struct hc_index_data, timeout), 64 / 4);
  3829. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3830. }
  3831. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3832. {
  3833. }
  3834. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3835. struct client_init_ramrod_data *data)
  3836. {
  3837. struct cnic_local *cp = dev->cnic_priv;
  3838. struct cnic_uio_dev *udev = cp->udev;
  3839. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3840. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3841. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3842. int i;
  3843. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3844. u32 val;
  3845. memset(txbd, 0, BCM_PAGE_SIZE);
  3846. buf_map = udev->l2_buf_map;
  3847. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3848. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3849. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3850. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3851. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3852. reg_bd->addr_hi = start_bd->addr_hi;
  3853. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3854. start_bd->nbytes = cpu_to_le16(0x10);
  3855. start_bd->nbd = cpu_to_le16(3);
  3856. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3857. start_bd->general_data = (UNICAST_ADDRESS <<
  3858. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3859. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3860. }
  3861. val = (u64) ring_map >> 32;
  3862. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3863. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3864. val = (u64) ring_map & 0xffffffff;
  3865. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3866. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3867. /* Other ramrod params */
  3868. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3869. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3870. /* reset xstorm per client statistics */
  3871. if (cli < MAX_STAT_COUNTER_ID) {
  3872. data->general.statistics_zero_flg = 1;
  3873. data->general.statistics_en_flg = 1;
  3874. data->general.statistics_counter_id = cli;
  3875. }
  3876. cp->tx_cons_ptr =
  3877. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3878. }
  3879. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3880. struct client_init_ramrod_data *data)
  3881. {
  3882. struct cnic_local *cp = dev->cnic_priv;
  3883. struct cnic_uio_dev *udev = cp->udev;
  3884. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3885. BCM_PAGE_SIZE);
  3886. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3887. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3888. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3889. int i;
  3890. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3891. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3892. u32 val;
  3893. dma_addr_t ring_map = udev->l2_ring_map;
  3894. /* General data */
  3895. data->general.client_id = cli;
  3896. data->general.activate_flg = 1;
  3897. data->general.sp_client_id = cli;
  3898. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3899. data->general.func_id = cp->pfid;
  3900. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3901. dma_addr_t buf_map;
  3902. int n = (i % cp->l2_rx_ring_size) + 1;
  3903. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3904. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3905. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3906. }
  3907. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3908. rxbd->addr_hi = cpu_to_le32(val);
  3909. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3910. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3911. rxbd->addr_lo = cpu_to_le32(val);
  3912. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3913. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3914. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3915. rxcqe->addr_hi = cpu_to_le32(val);
  3916. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3917. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3918. rxcqe->addr_lo = cpu_to_le32(val);
  3919. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3920. /* Other ramrod params */
  3921. data->rx.client_qzone_id = cl_qzone_id;
  3922. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3923. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3924. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3925. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  3926. data->rx.outer_vlan_removal_enable_flg = 1;
  3927. data->rx.silent_vlan_removal_flg = 1;
  3928. data->rx.silent_vlan_value = 0;
  3929. data->rx.silent_vlan_mask = 0xffff;
  3930. cp->rx_cons_ptr =
  3931. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3932. cp->rx_cons = *cp->rx_cons_ptr;
  3933. }
  3934. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3935. {
  3936. struct cnic_local *cp = dev->cnic_priv;
  3937. u32 pfid = cp->pfid;
  3938. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3939. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3940. cp->kcq1.sw_prod_idx = 0;
  3941. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3942. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3943. cp->kcq1.hw_prod_idx_ptr =
  3944. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3945. cp->kcq1.status_idx_ptr =
  3946. &sb->sb.running_index[SM_RX_ID];
  3947. } else {
  3948. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3949. cp->kcq1.hw_prod_idx_ptr =
  3950. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3951. cp->kcq1.status_idx_ptr =
  3952. &sb->sb.running_index[SM_RX_ID];
  3953. }
  3954. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3955. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3956. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3957. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3958. cp->kcq2.sw_prod_idx = 0;
  3959. cp->kcq2.hw_prod_idx_ptr =
  3960. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3961. cp->kcq2.status_idx_ptr =
  3962. &sb->sb.running_index[SM_RX_ID];
  3963. }
  3964. }
  3965. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3966. {
  3967. struct cnic_local *cp = dev->cnic_priv;
  3968. struct cnic_eth_dev *ethdev = cp->ethdev;
  3969. int func = CNIC_FUNC(cp), ret;
  3970. u32 pfid;
  3971. cp->port_mode = CHIP_PORT_MODE_NONE;
  3972. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3973. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3974. if (!(val & 1))
  3975. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3976. else
  3977. val = (val >> 1) & 1;
  3978. if (val) {
  3979. cp->port_mode = CHIP_4_PORT_MODE;
  3980. cp->pfid = func >> 1;
  3981. } else {
  3982. cp->port_mode = CHIP_4_PORT_MODE;
  3983. cp->pfid = func & 0x6;
  3984. }
  3985. } else {
  3986. cp->pfid = func;
  3987. }
  3988. pfid = cp->pfid;
  3989. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3990. cp->iscsi_start_cid, 0);
  3991. if (ret)
  3992. return -ENOMEM;
  3993. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3994. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  3995. BNX2X_FCOE_NUM_CONNECTIONS,
  3996. cp->fcoe_start_cid, 0);
  3997. if (ret)
  3998. return -ENOMEM;
  3999. }
  4000. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4001. cnic_init_bnx2x_kcq(dev);
  4002. /* Only 1 EQ */
  4003. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4004. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4005. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4006. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4007. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4008. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4009. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4010. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4011. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4012. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4013. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4014. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4015. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4016. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4017. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4018. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4019. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4020. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4021. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4022. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4023. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4024. HC_INDEX_ISCSI_EQ_CONS);
  4025. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4026. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4027. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4028. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4029. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4030. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4031. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4032. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4033. cnic_setup_bnx2x_context(dev);
  4034. ret = cnic_init_bnx2x_irq(dev);
  4035. if (ret)
  4036. return ret;
  4037. return 0;
  4038. }
  4039. static void cnic_init_rings(struct cnic_dev *dev)
  4040. {
  4041. struct cnic_local *cp = dev->cnic_priv;
  4042. struct cnic_uio_dev *udev = cp->udev;
  4043. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4044. return;
  4045. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4046. cnic_init_bnx2_tx_ring(dev);
  4047. cnic_init_bnx2_rx_ring(dev);
  4048. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4049. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4050. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4051. u32 cid = cp->ethdev->iscsi_l2_cid;
  4052. u32 cl_qzone_id;
  4053. struct client_init_ramrod_data *data;
  4054. union l5cm_specific_data l5_data;
  4055. struct ustorm_eth_rx_producers rx_prods = {0};
  4056. u32 off, i;
  4057. rx_prods.bd_prod = 0;
  4058. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4059. barrier();
  4060. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4061. off = BAR_USTRORM_INTMEM +
  4062. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4063. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4064. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4065. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4066. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4067. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4068. data = udev->l2_buf;
  4069. memset(data, 0, sizeof(*data));
  4070. cnic_init_bnx2x_tx_ring(dev, data);
  4071. cnic_init_bnx2x_rx_ring(dev, data);
  4072. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4073. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4074. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4075. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4076. cid, ETH_CONNECTION_TYPE, &l5_data);
  4077. i = 0;
  4078. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4079. ++i < 10)
  4080. msleep(1);
  4081. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4082. netdev_err(dev->netdev,
  4083. "iSCSI CLIENT_SETUP did not complete\n");
  4084. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4085. cnic_ring_ctl(dev, cid, cli, 1);
  4086. }
  4087. }
  4088. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4089. {
  4090. struct cnic_local *cp = dev->cnic_priv;
  4091. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4092. return;
  4093. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4094. cnic_shutdown_bnx2_rx_ring(dev);
  4095. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4096. struct cnic_local *cp = dev->cnic_priv;
  4097. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4098. u32 cid = cp->ethdev->iscsi_l2_cid;
  4099. union l5cm_specific_data l5_data;
  4100. int i;
  4101. cnic_ring_ctl(dev, cid, cli, 0);
  4102. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4103. l5_data.phy_address.lo = cli;
  4104. l5_data.phy_address.hi = 0;
  4105. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4106. cid, ETH_CONNECTION_TYPE, &l5_data);
  4107. i = 0;
  4108. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4109. ++i < 10)
  4110. msleep(1);
  4111. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4112. netdev_err(dev->netdev,
  4113. "iSCSI CLIENT_HALT did not complete\n");
  4114. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4115. memset(&l5_data, 0, sizeof(l5_data));
  4116. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4117. cid, NONE_CONNECTION_TYPE, &l5_data);
  4118. msleep(10);
  4119. }
  4120. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4121. }
  4122. static int cnic_register_netdev(struct cnic_dev *dev)
  4123. {
  4124. struct cnic_local *cp = dev->cnic_priv;
  4125. struct cnic_eth_dev *ethdev = cp->ethdev;
  4126. int err;
  4127. if (!ethdev)
  4128. return -ENODEV;
  4129. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4130. return 0;
  4131. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4132. if (err)
  4133. netdev_err(dev->netdev, "register_cnic failed\n");
  4134. return err;
  4135. }
  4136. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4137. {
  4138. struct cnic_local *cp = dev->cnic_priv;
  4139. struct cnic_eth_dev *ethdev = cp->ethdev;
  4140. if (!ethdev)
  4141. return;
  4142. ethdev->drv_unregister_cnic(dev->netdev);
  4143. }
  4144. static int cnic_start_hw(struct cnic_dev *dev)
  4145. {
  4146. struct cnic_local *cp = dev->cnic_priv;
  4147. struct cnic_eth_dev *ethdev = cp->ethdev;
  4148. int err;
  4149. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4150. return -EALREADY;
  4151. dev->regview = ethdev->io_base;
  4152. pci_dev_get(dev->pcidev);
  4153. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4154. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4155. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4156. err = cp->alloc_resc(dev);
  4157. if (err) {
  4158. netdev_err(dev->netdev, "allocate resource failure\n");
  4159. goto err1;
  4160. }
  4161. err = cp->start_hw(dev);
  4162. if (err)
  4163. goto err1;
  4164. err = cnic_cm_open(dev);
  4165. if (err)
  4166. goto err1;
  4167. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4168. cp->enable_int(dev);
  4169. return 0;
  4170. err1:
  4171. cp->free_resc(dev);
  4172. pci_dev_put(dev->pcidev);
  4173. return err;
  4174. }
  4175. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4176. {
  4177. cnic_disable_bnx2_int_sync(dev);
  4178. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4179. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4180. cnic_init_context(dev, KWQ_CID);
  4181. cnic_init_context(dev, KCQ_CID);
  4182. cnic_setup_5709_context(dev, 0);
  4183. cnic_free_irq(dev);
  4184. cnic_free_resc(dev);
  4185. }
  4186. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4187. {
  4188. struct cnic_local *cp = dev->cnic_priv;
  4189. cnic_free_irq(dev);
  4190. *cp->kcq1.hw_prod_idx_ptr = 0;
  4191. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4192. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4193. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4194. cnic_free_resc(dev);
  4195. }
  4196. static void cnic_stop_hw(struct cnic_dev *dev)
  4197. {
  4198. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4199. struct cnic_local *cp = dev->cnic_priv;
  4200. int i = 0;
  4201. /* Need to wait for the ring shutdown event to complete
  4202. * before clearing the CNIC_UP flag.
  4203. */
  4204. while (cp->udev->uio_dev != -1 && i < 15) {
  4205. msleep(100);
  4206. i++;
  4207. }
  4208. cnic_shutdown_rings(dev);
  4209. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4210. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4211. synchronize_rcu();
  4212. cnic_cm_shutdown(dev);
  4213. cp->stop_hw(dev);
  4214. pci_dev_put(dev->pcidev);
  4215. }
  4216. }
  4217. static void cnic_free_dev(struct cnic_dev *dev)
  4218. {
  4219. int i = 0;
  4220. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4221. msleep(100);
  4222. i++;
  4223. }
  4224. if (atomic_read(&dev->ref_count) != 0)
  4225. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4226. netdev_info(dev->netdev, "Removed CNIC device\n");
  4227. dev_put(dev->netdev);
  4228. kfree(dev);
  4229. }
  4230. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4231. struct pci_dev *pdev)
  4232. {
  4233. struct cnic_dev *cdev;
  4234. struct cnic_local *cp;
  4235. int alloc_size;
  4236. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4237. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4238. if (cdev == NULL) {
  4239. netdev_err(dev, "allocate dev struct failure\n");
  4240. return NULL;
  4241. }
  4242. cdev->netdev = dev;
  4243. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4244. cdev->register_device = cnic_register_device;
  4245. cdev->unregister_device = cnic_unregister_device;
  4246. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4247. cp = cdev->cnic_priv;
  4248. cp->dev = cdev;
  4249. cp->l2_single_buf_size = 0x400;
  4250. cp->l2_rx_ring_size = 3;
  4251. spin_lock_init(&cp->cnic_ulp_lock);
  4252. netdev_info(dev, "Added CNIC device\n");
  4253. return cdev;
  4254. }
  4255. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4256. {
  4257. struct pci_dev *pdev;
  4258. struct cnic_dev *cdev;
  4259. struct cnic_local *cp;
  4260. struct cnic_eth_dev *ethdev = NULL;
  4261. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4262. probe = symbol_get(bnx2_cnic_probe);
  4263. if (probe) {
  4264. ethdev = (*probe)(dev);
  4265. symbol_put(bnx2_cnic_probe);
  4266. }
  4267. if (!ethdev)
  4268. return NULL;
  4269. pdev = ethdev->pdev;
  4270. if (!pdev)
  4271. return NULL;
  4272. dev_hold(dev);
  4273. pci_dev_get(pdev);
  4274. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4275. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4276. (pdev->revision < 0x10)) {
  4277. pci_dev_put(pdev);
  4278. goto cnic_err;
  4279. }
  4280. pci_dev_put(pdev);
  4281. cdev = cnic_alloc_dev(dev, pdev);
  4282. if (cdev == NULL)
  4283. goto cnic_err;
  4284. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4285. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4286. cp = cdev->cnic_priv;
  4287. cp->ethdev = ethdev;
  4288. cdev->pcidev = pdev;
  4289. cp->chip_id = ethdev->chip_id;
  4290. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4291. cp->cnic_ops = &cnic_bnx2_ops;
  4292. cp->start_hw = cnic_start_bnx2_hw;
  4293. cp->stop_hw = cnic_stop_bnx2_hw;
  4294. cp->setup_pgtbl = cnic_setup_page_tbl;
  4295. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4296. cp->free_resc = cnic_free_resc;
  4297. cp->start_cm = cnic_cm_init_bnx2_hw;
  4298. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4299. cp->enable_int = cnic_enable_bnx2_int;
  4300. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4301. cp->close_conn = cnic_close_bnx2_conn;
  4302. return cdev;
  4303. cnic_err:
  4304. dev_put(dev);
  4305. return NULL;
  4306. }
  4307. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4308. {
  4309. struct pci_dev *pdev;
  4310. struct cnic_dev *cdev;
  4311. struct cnic_local *cp;
  4312. struct cnic_eth_dev *ethdev = NULL;
  4313. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4314. probe = symbol_get(bnx2x_cnic_probe);
  4315. if (probe) {
  4316. ethdev = (*probe)(dev);
  4317. symbol_put(bnx2x_cnic_probe);
  4318. }
  4319. if (!ethdev)
  4320. return NULL;
  4321. pdev = ethdev->pdev;
  4322. if (!pdev)
  4323. return NULL;
  4324. dev_hold(dev);
  4325. cdev = cnic_alloc_dev(dev, pdev);
  4326. if (cdev == NULL) {
  4327. dev_put(dev);
  4328. return NULL;
  4329. }
  4330. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4331. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4332. cp = cdev->cnic_priv;
  4333. cp->ethdev = ethdev;
  4334. cdev->pcidev = pdev;
  4335. cp->chip_id = ethdev->chip_id;
  4336. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4337. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4338. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4339. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4340. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4341. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4342. cp->cnic_ops = &cnic_bnx2x_ops;
  4343. cp->start_hw = cnic_start_bnx2x_hw;
  4344. cp->stop_hw = cnic_stop_bnx2x_hw;
  4345. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4346. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4347. cp->free_resc = cnic_free_resc;
  4348. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4349. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4350. cp->enable_int = cnic_enable_bnx2x_int;
  4351. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4352. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4353. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4354. else
  4355. cp->ack_int = cnic_ack_bnx2x_msix;
  4356. cp->close_conn = cnic_close_bnx2x_conn;
  4357. return cdev;
  4358. }
  4359. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4360. {
  4361. struct ethtool_drvinfo drvinfo;
  4362. struct cnic_dev *cdev = NULL;
  4363. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4364. memset(&drvinfo, 0, sizeof(drvinfo));
  4365. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4366. if (!strcmp(drvinfo.driver, "bnx2"))
  4367. cdev = init_bnx2_cnic(dev);
  4368. if (!strcmp(drvinfo.driver, "bnx2x"))
  4369. cdev = init_bnx2x_cnic(dev);
  4370. if (cdev) {
  4371. write_lock(&cnic_dev_lock);
  4372. list_add(&cdev->list, &cnic_dev_list);
  4373. write_unlock(&cnic_dev_lock);
  4374. }
  4375. }
  4376. return cdev;
  4377. }
  4378. /**
  4379. * netdev event handler
  4380. */
  4381. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4382. void *ptr)
  4383. {
  4384. struct net_device *netdev = ptr;
  4385. struct cnic_dev *dev;
  4386. int if_type;
  4387. int new_dev = 0;
  4388. dev = cnic_from_netdev(netdev);
  4389. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4390. /* Check for the hot-plug device */
  4391. dev = is_cnic_dev(netdev);
  4392. if (dev) {
  4393. new_dev = 1;
  4394. cnic_hold(dev);
  4395. }
  4396. }
  4397. if (dev) {
  4398. struct cnic_local *cp = dev->cnic_priv;
  4399. if (new_dev)
  4400. cnic_ulp_init(dev);
  4401. else if (event == NETDEV_UNREGISTER)
  4402. cnic_ulp_exit(dev);
  4403. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4404. if (cnic_register_netdev(dev) != 0) {
  4405. cnic_put(dev);
  4406. goto done;
  4407. }
  4408. if (!cnic_start_hw(dev))
  4409. cnic_ulp_start(dev);
  4410. }
  4411. rcu_read_lock();
  4412. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4413. struct cnic_ulp_ops *ulp_ops;
  4414. void *ctx;
  4415. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4416. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4417. continue;
  4418. ctx = cp->ulp_handle[if_type];
  4419. ulp_ops->indicate_netevent(ctx, event);
  4420. }
  4421. rcu_read_unlock();
  4422. if (event == NETDEV_GOING_DOWN) {
  4423. cnic_ulp_stop(dev);
  4424. cnic_stop_hw(dev);
  4425. cnic_unregister_netdev(dev);
  4426. } else if (event == NETDEV_UNREGISTER) {
  4427. write_lock(&cnic_dev_lock);
  4428. list_del_init(&dev->list);
  4429. write_unlock(&cnic_dev_lock);
  4430. cnic_put(dev);
  4431. cnic_free_dev(dev);
  4432. goto done;
  4433. }
  4434. cnic_put(dev);
  4435. }
  4436. done:
  4437. return NOTIFY_DONE;
  4438. }
  4439. static struct notifier_block cnic_netdev_notifier = {
  4440. .notifier_call = cnic_netdev_event
  4441. };
  4442. static void cnic_release(void)
  4443. {
  4444. struct cnic_dev *dev;
  4445. struct cnic_uio_dev *udev;
  4446. while (!list_empty(&cnic_dev_list)) {
  4447. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4448. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4449. cnic_ulp_stop(dev);
  4450. cnic_stop_hw(dev);
  4451. }
  4452. cnic_ulp_exit(dev);
  4453. cnic_unregister_netdev(dev);
  4454. list_del_init(&dev->list);
  4455. cnic_free_dev(dev);
  4456. }
  4457. while (!list_empty(&cnic_udev_list)) {
  4458. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4459. list);
  4460. cnic_free_uio(udev);
  4461. }
  4462. }
  4463. static int __init cnic_init(void)
  4464. {
  4465. int rc = 0;
  4466. pr_info("%s", version);
  4467. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4468. if (rc) {
  4469. cnic_release();
  4470. return rc;
  4471. }
  4472. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4473. if (!cnic_wq) {
  4474. cnic_release();
  4475. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4476. return -ENOMEM;
  4477. }
  4478. return 0;
  4479. }
  4480. static void __exit cnic_exit(void)
  4481. {
  4482. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4483. cnic_release();
  4484. destroy_workqueue(cnic_wq);
  4485. }
  4486. module_init(cnic_init);
  4487. module_exit(cnic_exit);