intel_display.c 131 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include "drmP.h"
  31. #include "intel_drv.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include "intel_dp.h"
  35. #include "drm_crtc_helper.h"
  36. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  37. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  38. static void intel_update_watermarks(struct drm_device *dev);
  39. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  40. typedef struct {
  41. /* given values */
  42. int n;
  43. int m1, m2;
  44. int p1, p2;
  45. /* derived values */
  46. int dot;
  47. int vco;
  48. int m;
  49. int p;
  50. } intel_clock_t;
  51. typedef struct {
  52. int min, max;
  53. } intel_range_t;
  54. typedef struct {
  55. int dot_limit;
  56. int p2_slow, p2_fast;
  57. } intel_p2_t;
  58. #define INTEL_P2_NUM 2
  59. typedef struct intel_limit intel_limit_t;
  60. struct intel_limit {
  61. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  62. intel_p2_t p2;
  63. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  64. int, int, intel_clock_t *);
  65. bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  66. int, int, intel_clock_t *);
  67. };
  68. #define I8XX_DOT_MIN 25000
  69. #define I8XX_DOT_MAX 350000
  70. #define I8XX_VCO_MIN 930000
  71. #define I8XX_VCO_MAX 1400000
  72. #define I8XX_N_MIN 3
  73. #define I8XX_N_MAX 16
  74. #define I8XX_M_MIN 96
  75. #define I8XX_M_MAX 140
  76. #define I8XX_M1_MIN 18
  77. #define I8XX_M1_MAX 26
  78. #define I8XX_M2_MIN 6
  79. #define I8XX_M2_MAX 16
  80. #define I8XX_P_MIN 4
  81. #define I8XX_P_MAX 128
  82. #define I8XX_P1_MIN 2
  83. #define I8XX_P1_MAX 33
  84. #define I8XX_P1_LVDS_MIN 1
  85. #define I8XX_P1_LVDS_MAX 6
  86. #define I8XX_P2_SLOW 4
  87. #define I8XX_P2_FAST 2
  88. #define I8XX_P2_LVDS_SLOW 14
  89. #define I8XX_P2_LVDS_FAST 7
  90. #define I8XX_P2_SLOW_LIMIT 165000
  91. #define I9XX_DOT_MIN 20000
  92. #define I9XX_DOT_MAX 400000
  93. #define I9XX_VCO_MIN 1400000
  94. #define I9XX_VCO_MAX 2800000
  95. #define IGD_VCO_MIN 1700000
  96. #define IGD_VCO_MAX 3500000
  97. #define I9XX_N_MIN 1
  98. #define I9XX_N_MAX 6
  99. /* IGD's Ncounter is a ring counter */
  100. #define IGD_N_MIN 3
  101. #define IGD_N_MAX 6
  102. #define I9XX_M_MIN 70
  103. #define I9XX_M_MAX 120
  104. #define IGD_M_MIN 2
  105. #define IGD_M_MAX 256
  106. #define I9XX_M1_MIN 10
  107. #define I9XX_M1_MAX 22
  108. #define I9XX_M2_MIN 5
  109. #define I9XX_M2_MAX 9
  110. /* IGD M1 is reserved, and must be 0 */
  111. #define IGD_M1_MIN 0
  112. #define IGD_M1_MAX 0
  113. #define IGD_M2_MIN 0
  114. #define IGD_M2_MAX 254
  115. #define I9XX_P_SDVO_DAC_MIN 5
  116. #define I9XX_P_SDVO_DAC_MAX 80
  117. #define I9XX_P_LVDS_MIN 7
  118. #define I9XX_P_LVDS_MAX 98
  119. #define IGD_P_LVDS_MIN 7
  120. #define IGD_P_LVDS_MAX 112
  121. #define I9XX_P1_MIN 1
  122. #define I9XX_P1_MAX 8
  123. #define I9XX_P2_SDVO_DAC_SLOW 10
  124. #define I9XX_P2_SDVO_DAC_FAST 5
  125. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  126. #define I9XX_P2_LVDS_SLOW 14
  127. #define I9XX_P2_LVDS_FAST 7
  128. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  129. /*The parameter is for SDVO on G4x platform*/
  130. #define G4X_DOT_SDVO_MIN 25000
  131. #define G4X_DOT_SDVO_MAX 270000
  132. #define G4X_VCO_MIN 1750000
  133. #define G4X_VCO_MAX 3500000
  134. #define G4X_N_SDVO_MIN 1
  135. #define G4X_N_SDVO_MAX 4
  136. #define G4X_M_SDVO_MIN 104
  137. #define G4X_M_SDVO_MAX 138
  138. #define G4X_M1_SDVO_MIN 17
  139. #define G4X_M1_SDVO_MAX 23
  140. #define G4X_M2_SDVO_MIN 5
  141. #define G4X_M2_SDVO_MAX 11
  142. #define G4X_P_SDVO_MIN 10
  143. #define G4X_P_SDVO_MAX 30
  144. #define G4X_P1_SDVO_MIN 1
  145. #define G4X_P1_SDVO_MAX 3
  146. #define G4X_P2_SDVO_SLOW 10
  147. #define G4X_P2_SDVO_FAST 10
  148. #define G4X_P2_SDVO_LIMIT 270000
  149. /*The parameter is for HDMI_DAC on G4x platform*/
  150. #define G4X_DOT_HDMI_DAC_MIN 22000
  151. #define G4X_DOT_HDMI_DAC_MAX 400000
  152. #define G4X_N_HDMI_DAC_MIN 1
  153. #define G4X_N_HDMI_DAC_MAX 4
  154. #define G4X_M_HDMI_DAC_MIN 104
  155. #define G4X_M_HDMI_DAC_MAX 138
  156. #define G4X_M1_HDMI_DAC_MIN 16
  157. #define G4X_M1_HDMI_DAC_MAX 23
  158. #define G4X_M2_HDMI_DAC_MIN 5
  159. #define G4X_M2_HDMI_DAC_MAX 11
  160. #define G4X_P_HDMI_DAC_MIN 5
  161. #define G4X_P_HDMI_DAC_MAX 80
  162. #define G4X_P1_HDMI_DAC_MIN 1
  163. #define G4X_P1_HDMI_DAC_MAX 8
  164. #define G4X_P2_HDMI_DAC_SLOW 10
  165. #define G4X_P2_HDMI_DAC_FAST 5
  166. #define G4X_P2_HDMI_DAC_LIMIT 165000
  167. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  168. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  169. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  170. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  171. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  172. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  173. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  174. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  175. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  176. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  177. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  178. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  179. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  180. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  181. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  182. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  183. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  184. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  185. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  186. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  187. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  188. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  189. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  190. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  191. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  192. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  193. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  194. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  195. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  196. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  197. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  198. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  199. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  200. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  201. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  202. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  203. /*The parameter is for DISPLAY PORT on G4x platform*/
  204. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  205. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  206. #define G4X_N_DISPLAY_PORT_MIN 1
  207. #define G4X_N_DISPLAY_PORT_MAX 2
  208. #define G4X_M_DISPLAY_PORT_MIN 97
  209. #define G4X_M_DISPLAY_PORT_MAX 108
  210. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  211. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  212. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  213. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  214. #define G4X_P_DISPLAY_PORT_MIN 10
  215. #define G4X_P_DISPLAY_PORT_MAX 20
  216. #define G4X_P1_DISPLAY_PORT_MIN 1
  217. #define G4X_P1_DISPLAY_PORT_MAX 2
  218. #define G4X_P2_DISPLAY_PORT_SLOW 10
  219. #define G4X_P2_DISPLAY_PORT_FAST 10
  220. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  221. /* IGDNG */
  222. /* as we calculate clock using (register_value + 2) for
  223. N/M1/M2, so here the range value for them is (actual_value-2).
  224. */
  225. #define IGDNG_DOT_MIN 25000
  226. #define IGDNG_DOT_MAX 350000
  227. #define IGDNG_VCO_MIN 1760000
  228. #define IGDNG_VCO_MAX 3510000
  229. #define IGDNG_N_MIN 1
  230. #define IGDNG_N_MAX 5
  231. #define IGDNG_M_MIN 79
  232. #define IGDNG_M_MAX 118
  233. #define IGDNG_M1_MIN 12
  234. #define IGDNG_M1_MAX 23
  235. #define IGDNG_M2_MIN 5
  236. #define IGDNG_M2_MAX 9
  237. #define IGDNG_P_SDVO_DAC_MIN 5
  238. #define IGDNG_P_SDVO_DAC_MAX 80
  239. #define IGDNG_P_LVDS_MIN 28
  240. #define IGDNG_P_LVDS_MAX 112
  241. #define IGDNG_P1_MIN 1
  242. #define IGDNG_P1_MAX 8
  243. #define IGDNG_P2_SDVO_DAC_SLOW 10
  244. #define IGDNG_P2_SDVO_DAC_FAST 5
  245. #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
  246. #define IGDNG_P2_LVDS_FAST 7 /* double channel */
  247. #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
  248. static bool
  249. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  250. int target, int refclk, intel_clock_t *best_clock);
  251. static bool
  252. intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  253. int target, int refclk, intel_clock_t *best_clock);
  254. static bool
  255. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  256. int target, int refclk, intel_clock_t *best_clock);
  257. static bool
  258. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  259. int target, int refclk, intel_clock_t *best_clock);
  260. static bool
  261. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  262. int target, int refclk, intel_clock_t *best_clock);
  263. static bool
  264. intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
  265. int target, int refclk, intel_clock_t *best_clock);
  266. static const intel_limit_t intel_limits_i8xx_dvo = {
  267. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  268. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  269. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  270. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  271. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  272. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  273. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  274. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  275. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  276. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  277. .find_pll = intel_find_best_PLL,
  278. .find_reduced_pll = intel_find_best_reduced_PLL,
  279. };
  280. static const intel_limit_t intel_limits_i8xx_lvds = {
  281. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  282. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  283. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  284. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  285. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  286. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  287. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  288. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  289. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  290. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  291. .find_pll = intel_find_best_PLL,
  292. .find_reduced_pll = intel_find_best_reduced_PLL,
  293. };
  294. static const intel_limit_t intel_limits_i9xx_sdvo = {
  295. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  296. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  297. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  298. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  299. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  300. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  301. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  302. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  303. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  304. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  305. .find_pll = intel_find_best_PLL,
  306. .find_reduced_pll = intel_find_best_reduced_PLL,
  307. };
  308. static const intel_limit_t intel_limits_i9xx_lvds = {
  309. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  310. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  311. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  312. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  313. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  314. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  315. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  316. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  317. /* The single-channel range is 25-112Mhz, and dual-channel
  318. * is 80-224Mhz. Prefer single channel as much as possible.
  319. */
  320. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  321. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  322. .find_pll = intel_find_best_PLL,
  323. .find_reduced_pll = intel_find_best_reduced_PLL,
  324. };
  325. /* below parameter and function is for G4X Chipset Family*/
  326. static const intel_limit_t intel_limits_g4x_sdvo = {
  327. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  328. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  329. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  330. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  331. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  332. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  333. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  334. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  335. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  336. .p2_slow = G4X_P2_SDVO_SLOW,
  337. .p2_fast = G4X_P2_SDVO_FAST
  338. },
  339. .find_pll = intel_g4x_find_best_PLL,
  340. .find_reduced_pll = intel_g4x_find_best_PLL,
  341. };
  342. static const intel_limit_t intel_limits_g4x_hdmi = {
  343. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  344. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  345. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  346. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  347. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  348. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  349. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  350. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  351. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  352. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  353. .p2_fast = G4X_P2_HDMI_DAC_FAST
  354. },
  355. .find_pll = intel_g4x_find_best_PLL,
  356. .find_reduced_pll = intel_g4x_find_best_PLL,
  357. };
  358. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  359. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  360. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  361. .vco = { .min = G4X_VCO_MIN,
  362. .max = G4X_VCO_MAX },
  363. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  364. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  365. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  366. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  367. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  368. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  369. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  370. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  371. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  372. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  373. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  374. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  375. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  376. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  377. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  378. },
  379. .find_pll = intel_g4x_find_best_PLL,
  380. .find_reduced_pll = intel_g4x_find_best_PLL,
  381. };
  382. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  383. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  384. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  385. .vco = { .min = G4X_VCO_MIN,
  386. .max = G4X_VCO_MAX },
  387. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  388. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  389. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  390. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  391. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  392. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  393. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  394. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  395. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  396. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  397. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  398. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  399. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  400. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  401. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  402. },
  403. .find_pll = intel_g4x_find_best_PLL,
  404. .find_reduced_pll = intel_g4x_find_best_PLL,
  405. };
  406. static const intel_limit_t intel_limits_g4x_display_port = {
  407. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  408. .max = G4X_DOT_DISPLAY_PORT_MAX },
  409. .vco = { .min = G4X_VCO_MIN,
  410. .max = G4X_VCO_MAX},
  411. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  412. .max = G4X_N_DISPLAY_PORT_MAX },
  413. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  414. .max = G4X_M_DISPLAY_PORT_MAX },
  415. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  416. .max = G4X_M1_DISPLAY_PORT_MAX },
  417. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  418. .max = G4X_M2_DISPLAY_PORT_MAX },
  419. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  420. .max = G4X_P_DISPLAY_PORT_MAX },
  421. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  422. .max = G4X_P1_DISPLAY_PORT_MAX},
  423. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  424. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  425. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  426. .find_pll = intel_find_pll_g4x_dp,
  427. };
  428. static const intel_limit_t intel_limits_igd_sdvo = {
  429. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  430. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  431. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  432. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  433. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  434. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  435. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  436. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  437. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  438. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  439. .find_pll = intel_find_best_PLL,
  440. .find_reduced_pll = intel_find_best_reduced_PLL,
  441. };
  442. static const intel_limit_t intel_limits_igd_lvds = {
  443. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  444. .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
  445. .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
  446. .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
  447. .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
  448. .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
  449. .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
  450. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  451. /* IGD only supports single-channel mode. */
  452. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  453. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  454. .find_pll = intel_find_best_PLL,
  455. .find_reduced_pll = intel_find_best_reduced_PLL,
  456. };
  457. static const intel_limit_t intel_limits_igdng_sdvo = {
  458. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  459. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  460. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  461. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  462. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  463. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  464. .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
  465. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  466. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  467. .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
  468. .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
  469. .find_pll = intel_igdng_find_best_PLL,
  470. };
  471. static const intel_limit_t intel_limits_igdng_lvds = {
  472. .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
  473. .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
  474. .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
  475. .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
  476. .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
  477. .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
  478. .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
  479. .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
  480. .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
  481. .p2_slow = IGDNG_P2_LVDS_SLOW,
  482. .p2_fast = IGDNG_P2_LVDS_FAST },
  483. .find_pll = intel_igdng_find_best_PLL,
  484. };
  485. static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
  486. {
  487. const intel_limit_t *limit;
  488. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  489. limit = &intel_limits_igdng_lvds;
  490. else
  491. limit = &intel_limits_igdng_sdvo;
  492. return limit;
  493. }
  494. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  495. {
  496. struct drm_device *dev = crtc->dev;
  497. struct drm_i915_private *dev_priv = dev->dev_private;
  498. const intel_limit_t *limit;
  499. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  500. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  501. LVDS_CLKB_POWER_UP)
  502. /* LVDS with dual channel */
  503. limit = &intel_limits_g4x_dual_channel_lvds;
  504. else
  505. /* LVDS with dual channel */
  506. limit = &intel_limits_g4x_single_channel_lvds;
  507. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  508. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  509. limit = &intel_limits_g4x_hdmi;
  510. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  511. limit = &intel_limits_g4x_sdvo;
  512. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  513. limit = &intel_limits_g4x_display_port;
  514. } else /* The option is for other outputs */
  515. limit = &intel_limits_i9xx_sdvo;
  516. return limit;
  517. }
  518. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  519. {
  520. struct drm_device *dev = crtc->dev;
  521. const intel_limit_t *limit;
  522. if (IS_IGDNG(dev))
  523. limit = intel_igdng_limit(crtc);
  524. else if (IS_G4X(dev)) {
  525. limit = intel_g4x_limit(crtc);
  526. } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
  527. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  528. limit = &intel_limits_i9xx_lvds;
  529. else
  530. limit = &intel_limits_i9xx_sdvo;
  531. } else if (IS_IGD(dev)) {
  532. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  533. limit = &intel_limits_igd_lvds;
  534. else
  535. limit = &intel_limits_igd_sdvo;
  536. } else {
  537. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  538. limit = &intel_limits_i8xx_lvds;
  539. else
  540. limit = &intel_limits_i8xx_dvo;
  541. }
  542. return limit;
  543. }
  544. /* m1 is reserved as 0 in IGD, n is a ring counter */
  545. static void igd_clock(int refclk, intel_clock_t *clock)
  546. {
  547. clock->m = clock->m2 + 2;
  548. clock->p = clock->p1 * clock->p2;
  549. clock->vco = refclk * clock->m / clock->n;
  550. clock->dot = clock->vco / clock->p;
  551. }
  552. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  553. {
  554. if (IS_IGD(dev)) {
  555. igd_clock(refclk, clock);
  556. return;
  557. }
  558. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  559. clock->p = clock->p1 * clock->p2;
  560. clock->vco = refclk * clock->m / (clock->n + 2);
  561. clock->dot = clock->vco / clock->p;
  562. }
  563. /**
  564. * Returns whether any output on the specified pipe is of the specified type
  565. */
  566. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  567. {
  568. struct drm_device *dev = crtc->dev;
  569. struct drm_mode_config *mode_config = &dev->mode_config;
  570. struct drm_connector *l_entry;
  571. list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  572. if (l_entry->encoder &&
  573. l_entry->encoder->crtc == crtc) {
  574. struct intel_output *intel_output = to_intel_output(l_entry);
  575. if (intel_output->type == type)
  576. return true;
  577. }
  578. }
  579. return false;
  580. }
  581. struct drm_connector *
  582. intel_pipe_get_output (struct drm_crtc *crtc)
  583. {
  584. struct drm_device *dev = crtc->dev;
  585. struct drm_mode_config *mode_config = &dev->mode_config;
  586. struct drm_connector *l_entry, *ret = NULL;
  587. list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  588. if (l_entry->encoder &&
  589. l_entry->encoder->crtc == crtc) {
  590. ret = l_entry;
  591. break;
  592. }
  593. }
  594. return ret;
  595. }
  596. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  597. /**
  598. * Returns whether the given set of divisors are valid for a given refclk with
  599. * the given connectors.
  600. */
  601. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  602. {
  603. const intel_limit_t *limit = intel_limit (crtc);
  604. struct drm_device *dev = crtc->dev;
  605. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  606. INTELPllInvalid ("p1 out of range\n");
  607. if (clock->p < limit->p.min || limit->p.max < clock->p)
  608. INTELPllInvalid ("p out of range\n");
  609. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  610. INTELPllInvalid ("m2 out of range\n");
  611. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  612. INTELPllInvalid ("m1 out of range\n");
  613. if (clock->m1 <= clock->m2 && !IS_IGD(dev))
  614. INTELPllInvalid ("m1 <= m2\n");
  615. if (clock->m < limit->m.min || limit->m.max < clock->m)
  616. INTELPllInvalid ("m out of range\n");
  617. if (clock->n < limit->n.min || limit->n.max < clock->n)
  618. INTELPllInvalid ("n out of range\n");
  619. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  620. INTELPllInvalid ("vco out of range\n");
  621. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  622. * connector, etc., rather than just a single range.
  623. */
  624. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  625. INTELPllInvalid ("dot out of range\n");
  626. return true;
  627. }
  628. static bool
  629. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  630. int target, int refclk, intel_clock_t *best_clock)
  631. {
  632. struct drm_device *dev = crtc->dev;
  633. struct drm_i915_private *dev_priv = dev->dev_private;
  634. intel_clock_t clock;
  635. int err = target;
  636. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  637. (I915_READ(LVDS)) != 0) {
  638. /*
  639. * For LVDS, if the panel is on, just rely on its current
  640. * settings for dual-channel. We haven't figured out how to
  641. * reliably set up different single/dual channel state, if we
  642. * even can.
  643. */
  644. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  645. LVDS_CLKB_POWER_UP)
  646. clock.p2 = limit->p2.p2_fast;
  647. else
  648. clock.p2 = limit->p2.p2_slow;
  649. } else {
  650. if (target < limit->p2.dot_limit)
  651. clock.p2 = limit->p2.p2_slow;
  652. else
  653. clock.p2 = limit->p2.p2_fast;
  654. }
  655. memset (best_clock, 0, sizeof (*best_clock));
  656. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  657. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  658. clock.m1++) {
  659. for (clock.m2 = limit->m2.min;
  660. clock.m2 <= limit->m2.max; clock.m2++) {
  661. /* m1 is always 0 in IGD */
  662. if (clock.m2 >= clock.m1 && !IS_IGD(dev))
  663. break;
  664. for (clock.n = limit->n.min;
  665. clock.n <= limit->n.max; clock.n++) {
  666. int this_err;
  667. intel_clock(dev, refclk, &clock);
  668. if (!intel_PLL_is_valid(crtc, &clock))
  669. continue;
  670. this_err = abs(clock.dot - target);
  671. if (this_err < err) {
  672. *best_clock = clock;
  673. err = this_err;
  674. }
  675. }
  676. }
  677. }
  678. }
  679. return (err != target);
  680. }
  681. static bool
  682. intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  683. int target, int refclk, intel_clock_t *best_clock)
  684. {
  685. struct drm_device *dev = crtc->dev;
  686. intel_clock_t clock;
  687. int err = target;
  688. bool found = false;
  689. memcpy(&clock, best_clock, sizeof(intel_clock_t));
  690. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  691. for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
  692. /* m1 is always 0 in IGD */
  693. if (clock.m2 >= clock.m1 && !IS_IGD(dev))
  694. break;
  695. for (clock.n = limit->n.min; clock.n <= limit->n.max;
  696. clock.n++) {
  697. int this_err;
  698. intel_clock(dev, refclk, &clock);
  699. if (!intel_PLL_is_valid(crtc, &clock))
  700. continue;
  701. this_err = abs(clock.dot - target);
  702. if (this_err < err) {
  703. *best_clock = clock;
  704. err = this_err;
  705. found = true;
  706. }
  707. }
  708. }
  709. }
  710. return found;
  711. }
  712. static bool
  713. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  714. int target, int refclk, intel_clock_t *best_clock)
  715. {
  716. struct drm_device *dev = crtc->dev;
  717. struct drm_i915_private *dev_priv = dev->dev_private;
  718. intel_clock_t clock;
  719. int max_n;
  720. bool found;
  721. /* approximately equals target * 0.00488 */
  722. int err_most = (target >> 8) + (target >> 10);
  723. found = false;
  724. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  725. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  726. LVDS_CLKB_POWER_UP)
  727. clock.p2 = limit->p2.p2_fast;
  728. else
  729. clock.p2 = limit->p2.p2_slow;
  730. } else {
  731. if (target < limit->p2.dot_limit)
  732. clock.p2 = limit->p2.p2_slow;
  733. else
  734. clock.p2 = limit->p2.p2_fast;
  735. }
  736. memset(best_clock, 0, sizeof(*best_clock));
  737. max_n = limit->n.max;
  738. /* based on hardware requriment prefer smaller n to precision */
  739. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  740. /* based on hardware requirment prefere larger m1,m2 */
  741. for (clock.m1 = limit->m1.max;
  742. clock.m1 >= limit->m1.min; clock.m1--) {
  743. for (clock.m2 = limit->m2.max;
  744. clock.m2 >= limit->m2.min; clock.m2--) {
  745. for (clock.p1 = limit->p1.max;
  746. clock.p1 >= limit->p1.min; clock.p1--) {
  747. int this_err;
  748. intel_clock(dev, refclk, &clock);
  749. if (!intel_PLL_is_valid(crtc, &clock))
  750. continue;
  751. this_err = abs(clock.dot - target) ;
  752. if (this_err < err_most) {
  753. *best_clock = clock;
  754. err_most = this_err;
  755. max_n = clock.n;
  756. found = true;
  757. }
  758. }
  759. }
  760. }
  761. }
  762. return found;
  763. }
  764. static bool
  765. intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  766. int target, int refclk, intel_clock_t *best_clock)
  767. {
  768. struct drm_device *dev = crtc->dev;
  769. intel_clock_t clock;
  770. if (target < 200000) {
  771. clock.n = 1;
  772. clock.p1 = 2;
  773. clock.p2 = 10;
  774. clock.m1 = 12;
  775. clock.m2 = 9;
  776. } else {
  777. clock.n = 2;
  778. clock.p1 = 1;
  779. clock.p2 = 10;
  780. clock.m1 = 14;
  781. clock.m2 = 8;
  782. }
  783. intel_clock(dev, refclk, &clock);
  784. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  785. return true;
  786. }
  787. static bool
  788. intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  789. int target, int refclk, intel_clock_t *best_clock)
  790. {
  791. struct drm_device *dev = crtc->dev;
  792. struct drm_i915_private *dev_priv = dev->dev_private;
  793. intel_clock_t clock;
  794. int err_most = 47;
  795. int err_min = 10000;
  796. /* eDP has only 2 clock choice, no n/m/p setting */
  797. if (HAS_eDP)
  798. return true;
  799. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  800. return intel_find_pll_igdng_dp(limit, crtc, target,
  801. refclk, best_clock);
  802. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  803. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  804. LVDS_CLKB_POWER_UP)
  805. clock.p2 = limit->p2.p2_fast;
  806. else
  807. clock.p2 = limit->p2.p2_slow;
  808. } else {
  809. if (target < limit->p2.dot_limit)
  810. clock.p2 = limit->p2.p2_slow;
  811. else
  812. clock.p2 = limit->p2.p2_fast;
  813. }
  814. memset(best_clock, 0, sizeof(*best_clock));
  815. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  816. /* based on hardware requriment prefer smaller n to precision */
  817. for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
  818. /* based on hardware requirment prefere larger m1,m2 */
  819. for (clock.m1 = limit->m1.max;
  820. clock.m1 >= limit->m1.min; clock.m1--) {
  821. for (clock.m2 = limit->m2.max;
  822. clock.m2 >= limit->m2.min; clock.m2--) {
  823. int this_err;
  824. intel_clock(dev, refclk, &clock);
  825. if (!intel_PLL_is_valid(crtc, &clock))
  826. continue;
  827. this_err = abs((10000 - (target*10000/clock.dot)));
  828. if (this_err < err_most) {
  829. *best_clock = clock;
  830. /* found on first matching */
  831. goto out;
  832. } else if (this_err < err_min) {
  833. *best_clock = clock;
  834. err_min = this_err;
  835. }
  836. }
  837. }
  838. }
  839. }
  840. out:
  841. return true;
  842. }
  843. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  844. static bool
  845. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  846. int target, int refclk, intel_clock_t *best_clock)
  847. {
  848. intel_clock_t clock;
  849. if (target < 200000) {
  850. clock.p1 = 2;
  851. clock.p2 = 10;
  852. clock.n = 2;
  853. clock.m1 = 23;
  854. clock.m2 = 8;
  855. } else {
  856. clock.p1 = 1;
  857. clock.p2 = 10;
  858. clock.n = 1;
  859. clock.m1 = 14;
  860. clock.m2 = 2;
  861. }
  862. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  863. clock.p = (clock.p1 * clock.p2);
  864. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  865. clock.vco = 0;
  866. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  867. return true;
  868. }
  869. void
  870. intel_wait_for_vblank(struct drm_device *dev)
  871. {
  872. /* Wait for 20ms, i.e. one cycle at 50hz. */
  873. mdelay(20);
  874. }
  875. /* Parameters have changed, update FBC info */
  876. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  877. {
  878. struct drm_device *dev = crtc->dev;
  879. struct drm_i915_private *dev_priv = dev->dev_private;
  880. struct drm_framebuffer *fb = crtc->fb;
  881. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  882. struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
  883. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  884. int plane, i;
  885. u32 fbc_ctl, fbc_ctl2;
  886. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  887. if (fb->pitch < dev_priv->cfb_pitch)
  888. dev_priv->cfb_pitch = fb->pitch;
  889. /* FBC_CTL wants 64B units */
  890. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  891. dev_priv->cfb_fence = obj_priv->fence_reg;
  892. dev_priv->cfb_plane = intel_crtc->plane;
  893. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  894. /* Clear old tags */
  895. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  896. I915_WRITE(FBC_TAG + (i * 4), 0);
  897. /* Set it up... */
  898. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  899. if (obj_priv->tiling_mode != I915_TILING_NONE)
  900. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  901. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  902. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  903. /* enable it... */
  904. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  905. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  906. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  907. if (obj_priv->tiling_mode != I915_TILING_NONE)
  908. fbc_ctl |= dev_priv->cfb_fence;
  909. I915_WRITE(FBC_CONTROL, fbc_ctl);
  910. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  911. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  912. }
  913. void i8xx_disable_fbc(struct drm_device *dev)
  914. {
  915. struct drm_i915_private *dev_priv = dev->dev_private;
  916. u32 fbc_ctl;
  917. if (!I915_HAS_FBC(dev))
  918. return;
  919. /* Disable compression */
  920. fbc_ctl = I915_READ(FBC_CONTROL);
  921. fbc_ctl &= ~FBC_CTL_EN;
  922. I915_WRITE(FBC_CONTROL, fbc_ctl);
  923. /* Wait for compressing bit to clear */
  924. while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
  925. ; /* nothing */
  926. intel_wait_for_vblank(dev);
  927. DRM_DEBUG_KMS("disabled FBC\n");
  928. }
  929. static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
  930. {
  931. struct drm_device *dev = crtc->dev;
  932. struct drm_i915_private *dev_priv = dev->dev_private;
  933. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  934. }
  935. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  936. {
  937. struct drm_device *dev = crtc->dev;
  938. struct drm_i915_private *dev_priv = dev->dev_private;
  939. struct drm_framebuffer *fb = crtc->fb;
  940. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  941. struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
  942. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  943. int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
  944. DPFC_CTL_PLANEB);
  945. unsigned long stall_watermark = 200;
  946. u32 dpfc_ctl;
  947. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  948. dev_priv->cfb_fence = obj_priv->fence_reg;
  949. dev_priv->cfb_plane = intel_crtc->plane;
  950. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  951. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  952. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  953. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  954. } else {
  955. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  956. }
  957. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  958. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  959. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  960. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  961. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  962. /* enable it... */
  963. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  964. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  965. }
  966. void g4x_disable_fbc(struct drm_device *dev)
  967. {
  968. struct drm_i915_private *dev_priv = dev->dev_private;
  969. u32 dpfc_ctl;
  970. /* Disable compression */
  971. dpfc_ctl = I915_READ(DPFC_CONTROL);
  972. dpfc_ctl &= ~DPFC_CTL_EN;
  973. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  974. intel_wait_for_vblank(dev);
  975. DRM_DEBUG_KMS("disabled FBC\n");
  976. }
  977. static bool g4x_fbc_enabled(struct drm_crtc *crtc)
  978. {
  979. struct drm_device *dev = crtc->dev;
  980. struct drm_i915_private *dev_priv = dev->dev_private;
  981. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  982. }
  983. /**
  984. * intel_update_fbc - enable/disable FBC as needed
  985. * @crtc: CRTC to point the compressor at
  986. * @mode: mode in use
  987. *
  988. * Set up the framebuffer compression hardware at mode set time. We
  989. * enable it if possible:
  990. * - plane A only (on pre-965)
  991. * - no pixel mulitply/line duplication
  992. * - no alpha buffer discard
  993. * - no dual wide
  994. * - framebuffer <= 2048 in width, 1536 in height
  995. *
  996. * We can't assume that any compression will take place (worst case),
  997. * so the compressed buffer has to be the same size as the uncompressed
  998. * one. It also must reside (along with the line length buffer) in
  999. * stolen memory.
  1000. *
  1001. * We need to enable/disable FBC on a global basis.
  1002. */
  1003. static void intel_update_fbc(struct drm_crtc *crtc,
  1004. struct drm_display_mode *mode)
  1005. {
  1006. struct drm_device *dev = crtc->dev;
  1007. struct drm_i915_private *dev_priv = dev->dev_private;
  1008. struct drm_framebuffer *fb = crtc->fb;
  1009. struct intel_framebuffer *intel_fb;
  1010. struct drm_i915_gem_object *obj_priv;
  1011. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1012. int plane = intel_crtc->plane;
  1013. if (!i915_powersave)
  1014. return;
  1015. if (!dev_priv->display.fbc_enabled ||
  1016. !dev_priv->display.enable_fbc ||
  1017. !dev_priv->display.disable_fbc)
  1018. return;
  1019. if (!crtc->fb)
  1020. return;
  1021. intel_fb = to_intel_framebuffer(fb);
  1022. obj_priv = intel_fb->obj->driver_private;
  1023. /*
  1024. * If FBC is already on, we just have to verify that we can
  1025. * keep it that way...
  1026. * Need to disable if:
  1027. * - changing FBC params (stride, fence, mode)
  1028. * - new fb is too large to fit in compressed buffer
  1029. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1030. */
  1031. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1032. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1033. "compression\n");
  1034. goto out_disable;
  1035. }
  1036. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  1037. (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
  1038. DRM_DEBUG_KMS("mode incompatible with compression, "
  1039. "disabling\n");
  1040. goto out_disable;
  1041. }
  1042. if ((mode->hdisplay > 2048) ||
  1043. (mode->vdisplay > 1536)) {
  1044. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1045. goto out_disable;
  1046. }
  1047. if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
  1048. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1049. goto out_disable;
  1050. }
  1051. if (obj_priv->tiling_mode != I915_TILING_X) {
  1052. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1053. goto out_disable;
  1054. }
  1055. if (dev_priv->display.fbc_enabled(crtc)) {
  1056. /* We can re-enable it in this case, but need to update pitch */
  1057. if (fb->pitch > dev_priv->cfb_pitch)
  1058. dev_priv->display.disable_fbc(dev);
  1059. if (obj_priv->fence_reg != dev_priv->cfb_fence)
  1060. dev_priv->display.disable_fbc(dev);
  1061. if (plane != dev_priv->cfb_plane)
  1062. dev_priv->display.disable_fbc(dev);
  1063. }
  1064. if (!dev_priv->display.fbc_enabled(crtc)) {
  1065. /* Now try to turn it back on if possible */
  1066. dev_priv->display.enable_fbc(crtc, 500);
  1067. }
  1068. return;
  1069. out_disable:
  1070. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1071. /* Multiple disables should be harmless */
  1072. if (dev_priv->display.fbc_enabled(crtc))
  1073. dev_priv->display.disable_fbc(dev);
  1074. }
  1075. static int
  1076. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1077. struct drm_framebuffer *old_fb)
  1078. {
  1079. struct drm_device *dev = crtc->dev;
  1080. struct drm_i915_private *dev_priv = dev->dev_private;
  1081. struct drm_i915_master_private *master_priv;
  1082. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1083. struct intel_framebuffer *intel_fb;
  1084. struct drm_i915_gem_object *obj_priv;
  1085. struct drm_gem_object *obj;
  1086. int pipe = intel_crtc->pipe;
  1087. int plane = intel_crtc->plane;
  1088. unsigned long Start, Offset;
  1089. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1090. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1091. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1092. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1093. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1094. u32 dspcntr, alignment;
  1095. int ret;
  1096. /* no fb bound */
  1097. if (!crtc->fb) {
  1098. DRM_DEBUG_KMS("No FB bound\n");
  1099. return 0;
  1100. }
  1101. switch (plane) {
  1102. case 0:
  1103. case 1:
  1104. break;
  1105. default:
  1106. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1107. return -EINVAL;
  1108. }
  1109. intel_fb = to_intel_framebuffer(crtc->fb);
  1110. obj = intel_fb->obj;
  1111. obj_priv = obj->driver_private;
  1112. switch (obj_priv->tiling_mode) {
  1113. case I915_TILING_NONE:
  1114. alignment = 64 * 1024;
  1115. break;
  1116. case I915_TILING_X:
  1117. /* pin() will align the object as required by fence */
  1118. alignment = 0;
  1119. break;
  1120. case I915_TILING_Y:
  1121. /* FIXME: Is this true? */
  1122. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1123. return -EINVAL;
  1124. default:
  1125. BUG();
  1126. }
  1127. mutex_lock(&dev->struct_mutex);
  1128. ret = i915_gem_object_pin(obj, alignment);
  1129. if (ret != 0) {
  1130. mutex_unlock(&dev->struct_mutex);
  1131. return ret;
  1132. }
  1133. ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  1134. if (ret != 0) {
  1135. i915_gem_object_unpin(obj);
  1136. mutex_unlock(&dev->struct_mutex);
  1137. return ret;
  1138. }
  1139. /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
  1140. * whereas 965+ only requires a fence if using framebuffer compression.
  1141. * For simplicity, we always install a fence as the cost is not that onerous.
  1142. */
  1143. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1144. obj_priv->tiling_mode != I915_TILING_NONE) {
  1145. ret = i915_gem_object_get_fence_reg(obj);
  1146. if (ret != 0) {
  1147. i915_gem_object_unpin(obj);
  1148. mutex_unlock(&dev->struct_mutex);
  1149. return ret;
  1150. }
  1151. }
  1152. dspcntr = I915_READ(dspcntr_reg);
  1153. /* Mask out pixel format bits in case we change it */
  1154. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1155. switch (crtc->fb->bits_per_pixel) {
  1156. case 8:
  1157. dspcntr |= DISPPLANE_8BPP;
  1158. break;
  1159. case 16:
  1160. if (crtc->fb->depth == 15)
  1161. dspcntr |= DISPPLANE_15_16BPP;
  1162. else
  1163. dspcntr |= DISPPLANE_16BPP;
  1164. break;
  1165. case 24:
  1166. case 32:
  1167. if (crtc->fb->depth == 30)
  1168. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1169. else
  1170. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1171. break;
  1172. default:
  1173. DRM_ERROR("Unknown color depth\n");
  1174. i915_gem_object_unpin(obj);
  1175. mutex_unlock(&dev->struct_mutex);
  1176. return -EINVAL;
  1177. }
  1178. if (IS_I965G(dev)) {
  1179. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1180. dspcntr |= DISPPLANE_TILED;
  1181. else
  1182. dspcntr &= ~DISPPLANE_TILED;
  1183. }
  1184. if (IS_IGDNG(dev))
  1185. /* must disable */
  1186. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1187. I915_WRITE(dspcntr_reg, dspcntr);
  1188. Start = obj_priv->gtt_offset;
  1189. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  1190. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
  1191. I915_WRITE(dspstride, crtc->fb->pitch);
  1192. if (IS_I965G(dev)) {
  1193. I915_WRITE(dspbase, Offset);
  1194. I915_READ(dspbase);
  1195. I915_WRITE(dspsurf, Start);
  1196. I915_READ(dspsurf);
  1197. I915_WRITE(dsptileoff, (y << 16) | x);
  1198. } else {
  1199. I915_WRITE(dspbase, Start + Offset);
  1200. I915_READ(dspbase);
  1201. }
  1202. if ((IS_I965G(dev) || plane == 0))
  1203. intel_update_fbc(crtc, &crtc->mode);
  1204. intel_wait_for_vblank(dev);
  1205. if (old_fb) {
  1206. intel_fb = to_intel_framebuffer(old_fb);
  1207. obj_priv = intel_fb->obj->driver_private;
  1208. i915_gem_object_unpin(intel_fb->obj);
  1209. }
  1210. intel_increase_pllclock(crtc, true);
  1211. mutex_unlock(&dev->struct_mutex);
  1212. if (!dev->primary->master)
  1213. return 0;
  1214. master_priv = dev->primary->master->driver_priv;
  1215. if (!master_priv->sarea_priv)
  1216. return 0;
  1217. if (pipe) {
  1218. master_priv->sarea_priv->pipeB_x = x;
  1219. master_priv->sarea_priv->pipeB_y = y;
  1220. } else {
  1221. master_priv->sarea_priv->pipeA_x = x;
  1222. master_priv->sarea_priv->pipeA_y = y;
  1223. }
  1224. return 0;
  1225. }
  1226. /* Disable the VGA plane that we never use */
  1227. static void i915_disable_vga (struct drm_device *dev)
  1228. {
  1229. struct drm_i915_private *dev_priv = dev->dev_private;
  1230. u8 sr1;
  1231. u32 vga_reg;
  1232. if (IS_IGDNG(dev))
  1233. vga_reg = CPU_VGACNTRL;
  1234. else
  1235. vga_reg = VGACNTRL;
  1236. if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
  1237. return;
  1238. I915_WRITE8(VGA_SR_INDEX, 1);
  1239. sr1 = I915_READ8(VGA_SR_DATA);
  1240. I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
  1241. udelay(100);
  1242. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  1243. }
  1244. static void igdng_disable_pll_edp (struct drm_crtc *crtc)
  1245. {
  1246. struct drm_device *dev = crtc->dev;
  1247. struct drm_i915_private *dev_priv = dev->dev_private;
  1248. u32 dpa_ctl;
  1249. DRM_DEBUG_KMS("\n");
  1250. dpa_ctl = I915_READ(DP_A);
  1251. dpa_ctl &= ~DP_PLL_ENABLE;
  1252. I915_WRITE(DP_A, dpa_ctl);
  1253. }
  1254. static void igdng_enable_pll_edp (struct drm_crtc *crtc)
  1255. {
  1256. struct drm_device *dev = crtc->dev;
  1257. struct drm_i915_private *dev_priv = dev->dev_private;
  1258. u32 dpa_ctl;
  1259. dpa_ctl = I915_READ(DP_A);
  1260. dpa_ctl |= DP_PLL_ENABLE;
  1261. I915_WRITE(DP_A, dpa_ctl);
  1262. udelay(200);
  1263. }
  1264. static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
  1265. {
  1266. struct drm_device *dev = crtc->dev;
  1267. struct drm_i915_private *dev_priv = dev->dev_private;
  1268. u32 dpa_ctl;
  1269. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1270. dpa_ctl = I915_READ(DP_A);
  1271. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1272. if (clock < 200000) {
  1273. u32 temp;
  1274. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1275. /* workaround for 160Mhz:
  1276. 1) program 0x4600c bits 15:0 = 0x8124
  1277. 2) program 0x46010 bit 0 = 1
  1278. 3) program 0x46034 bit 24 = 1
  1279. 4) program 0x64000 bit 14 = 1
  1280. */
  1281. temp = I915_READ(0x4600c);
  1282. temp &= 0xffff0000;
  1283. I915_WRITE(0x4600c, temp | 0x8124);
  1284. temp = I915_READ(0x46010);
  1285. I915_WRITE(0x46010, temp | 1);
  1286. temp = I915_READ(0x46034);
  1287. I915_WRITE(0x46034, temp | (1 << 24));
  1288. } else {
  1289. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1290. }
  1291. I915_WRITE(DP_A, dpa_ctl);
  1292. udelay(500);
  1293. }
  1294. static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
  1295. {
  1296. struct drm_device *dev = crtc->dev;
  1297. struct drm_i915_private *dev_priv = dev->dev_private;
  1298. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1299. int pipe = intel_crtc->pipe;
  1300. int plane = intel_crtc->plane;
  1301. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1302. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1303. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1304. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1305. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1306. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1307. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1308. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1309. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1310. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  1311. int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
  1312. int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
  1313. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1314. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1315. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1316. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1317. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1318. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1319. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  1320. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  1321. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  1322. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  1323. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  1324. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  1325. u32 temp;
  1326. int tries = 5, j, n;
  1327. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1328. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1329. */
  1330. switch (mode) {
  1331. case DRM_MODE_DPMS_ON:
  1332. case DRM_MODE_DPMS_STANDBY:
  1333. case DRM_MODE_DPMS_SUSPEND:
  1334. DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
  1335. if (HAS_eDP) {
  1336. /* enable eDP PLL */
  1337. igdng_enable_pll_edp(crtc);
  1338. } else {
  1339. /* enable PCH DPLL */
  1340. temp = I915_READ(pch_dpll_reg);
  1341. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1342. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  1343. I915_READ(pch_dpll_reg);
  1344. }
  1345. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1346. temp = I915_READ(fdi_rx_reg);
  1347. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
  1348. FDI_SEL_PCDCLK |
  1349. FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
  1350. I915_READ(fdi_rx_reg);
  1351. udelay(200);
  1352. /* Enable CPU FDI TX PLL, always on for IGDNG */
  1353. temp = I915_READ(fdi_tx_reg);
  1354. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1355. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  1356. I915_READ(fdi_tx_reg);
  1357. udelay(100);
  1358. }
  1359. }
  1360. /* Enable panel fitting for LVDS */
  1361. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1362. temp = I915_READ(pf_ctl_reg);
  1363. I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
  1364. /* currently full aspect */
  1365. I915_WRITE(pf_win_pos, 0);
  1366. I915_WRITE(pf_win_size,
  1367. (dev_priv->panel_fixed_mode->hdisplay << 16) |
  1368. (dev_priv->panel_fixed_mode->vdisplay));
  1369. }
  1370. /* Enable CPU pipe */
  1371. temp = I915_READ(pipeconf_reg);
  1372. if ((temp & PIPEACONF_ENABLE) == 0) {
  1373. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1374. I915_READ(pipeconf_reg);
  1375. udelay(100);
  1376. }
  1377. /* configure and enable CPU plane */
  1378. temp = I915_READ(dspcntr_reg);
  1379. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1380. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1381. /* Flush the plane changes */
  1382. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1383. }
  1384. if (!HAS_eDP) {
  1385. /* enable CPU FDI TX and PCH FDI RX */
  1386. temp = I915_READ(fdi_tx_reg);
  1387. temp |= FDI_TX_ENABLE;
  1388. temp |= FDI_DP_PORT_WIDTH_X4; /* default */
  1389. temp &= ~FDI_LINK_TRAIN_NONE;
  1390. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1391. I915_WRITE(fdi_tx_reg, temp);
  1392. I915_READ(fdi_tx_reg);
  1393. temp = I915_READ(fdi_rx_reg);
  1394. temp &= ~FDI_LINK_TRAIN_NONE;
  1395. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1396. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1397. I915_READ(fdi_rx_reg);
  1398. udelay(150);
  1399. /* Train FDI. */
  1400. /* umask FDI RX Interrupt symbol_lock and bit_lock bit
  1401. for train result */
  1402. temp = I915_READ(fdi_rx_imr_reg);
  1403. temp &= ~FDI_RX_SYMBOL_LOCK;
  1404. temp &= ~FDI_RX_BIT_LOCK;
  1405. I915_WRITE(fdi_rx_imr_reg, temp);
  1406. I915_READ(fdi_rx_imr_reg);
  1407. udelay(150);
  1408. temp = I915_READ(fdi_rx_iir_reg);
  1409. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1410. if ((temp & FDI_RX_BIT_LOCK) == 0) {
  1411. for (j = 0; j < tries; j++) {
  1412. temp = I915_READ(fdi_rx_iir_reg);
  1413. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
  1414. temp);
  1415. if (temp & FDI_RX_BIT_LOCK)
  1416. break;
  1417. udelay(200);
  1418. }
  1419. if (j != tries)
  1420. I915_WRITE(fdi_rx_iir_reg,
  1421. temp | FDI_RX_BIT_LOCK);
  1422. else
  1423. DRM_DEBUG_KMS("train 1 fail\n");
  1424. } else {
  1425. I915_WRITE(fdi_rx_iir_reg,
  1426. temp | FDI_RX_BIT_LOCK);
  1427. DRM_DEBUG_KMS("train 1 ok 2!\n");
  1428. }
  1429. temp = I915_READ(fdi_tx_reg);
  1430. temp &= ~FDI_LINK_TRAIN_NONE;
  1431. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1432. I915_WRITE(fdi_tx_reg, temp);
  1433. temp = I915_READ(fdi_rx_reg);
  1434. temp &= ~FDI_LINK_TRAIN_NONE;
  1435. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1436. I915_WRITE(fdi_rx_reg, temp);
  1437. udelay(150);
  1438. temp = I915_READ(fdi_rx_iir_reg);
  1439. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1440. if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
  1441. for (j = 0; j < tries; j++) {
  1442. temp = I915_READ(fdi_rx_iir_reg);
  1443. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
  1444. temp);
  1445. if (temp & FDI_RX_SYMBOL_LOCK)
  1446. break;
  1447. udelay(200);
  1448. }
  1449. if (j != tries) {
  1450. I915_WRITE(fdi_rx_iir_reg,
  1451. temp | FDI_RX_SYMBOL_LOCK);
  1452. DRM_DEBUG_KMS("train 2 ok 1!\n");
  1453. } else
  1454. DRM_DEBUG_KMS("train 2 fail\n");
  1455. } else {
  1456. I915_WRITE(fdi_rx_iir_reg,
  1457. temp | FDI_RX_SYMBOL_LOCK);
  1458. DRM_DEBUG_KMS("train 2 ok 2!\n");
  1459. }
  1460. DRM_DEBUG_KMS("train done\n");
  1461. /* set transcoder timing */
  1462. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1463. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1464. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1465. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1466. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1467. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1468. /* enable PCH transcoder */
  1469. temp = I915_READ(transconf_reg);
  1470. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1471. I915_READ(transconf_reg);
  1472. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1473. ;
  1474. /* enable normal */
  1475. temp = I915_READ(fdi_tx_reg);
  1476. temp &= ~FDI_LINK_TRAIN_NONE;
  1477. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1478. FDI_TX_ENHANCE_FRAME_ENABLE);
  1479. I915_READ(fdi_tx_reg);
  1480. temp = I915_READ(fdi_rx_reg);
  1481. temp &= ~FDI_LINK_TRAIN_NONE;
  1482. I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
  1483. FDI_RX_ENHANCE_FRAME_ENABLE);
  1484. I915_READ(fdi_rx_reg);
  1485. /* wait one idle pattern time */
  1486. udelay(100);
  1487. }
  1488. intel_crtc_load_lut(crtc);
  1489. break;
  1490. case DRM_MODE_DPMS_OFF:
  1491. DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
  1492. i915_disable_vga(dev);
  1493. /* Disable display plane */
  1494. temp = I915_READ(dspcntr_reg);
  1495. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1496. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1497. /* Flush the plane changes */
  1498. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1499. I915_READ(dspbase_reg);
  1500. }
  1501. /* disable cpu pipe, disable after all planes disabled */
  1502. temp = I915_READ(pipeconf_reg);
  1503. if ((temp & PIPEACONF_ENABLE) != 0) {
  1504. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1505. I915_READ(pipeconf_reg);
  1506. n = 0;
  1507. /* wait for cpu pipe off, pipe state */
  1508. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
  1509. n++;
  1510. if (n < 60) {
  1511. udelay(500);
  1512. continue;
  1513. } else {
  1514. DRM_DEBUG_KMS("pipe %d off delay\n",
  1515. pipe);
  1516. break;
  1517. }
  1518. }
  1519. } else
  1520. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  1521. if (HAS_eDP) {
  1522. igdng_disable_pll_edp(crtc);
  1523. }
  1524. /* disable CPU FDI tx and PCH FDI rx */
  1525. temp = I915_READ(fdi_tx_reg);
  1526. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1527. I915_READ(fdi_tx_reg);
  1528. temp = I915_READ(fdi_rx_reg);
  1529. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1530. I915_READ(fdi_rx_reg);
  1531. udelay(100);
  1532. /* still set train pattern 1 */
  1533. temp = I915_READ(fdi_tx_reg);
  1534. temp &= ~FDI_LINK_TRAIN_NONE;
  1535. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1536. I915_WRITE(fdi_tx_reg, temp);
  1537. temp = I915_READ(fdi_rx_reg);
  1538. temp &= ~FDI_LINK_TRAIN_NONE;
  1539. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1540. I915_WRITE(fdi_rx_reg, temp);
  1541. udelay(100);
  1542. /* disable PCH transcoder */
  1543. temp = I915_READ(transconf_reg);
  1544. if ((temp & TRANS_ENABLE) != 0) {
  1545. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1546. I915_READ(transconf_reg);
  1547. n = 0;
  1548. /* wait for PCH transcoder off, transcoder state */
  1549. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
  1550. n++;
  1551. if (n < 60) {
  1552. udelay(500);
  1553. continue;
  1554. } else {
  1555. DRM_DEBUG_KMS("transcoder %d off "
  1556. "delay\n", pipe);
  1557. break;
  1558. }
  1559. }
  1560. }
  1561. /* disable PCH DPLL */
  1562. temp = I915_READ(pch_dpll_reg);
  1563. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1564. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1565. I915_READ(pch_dpll_reg);
  1566. }
  1567. temp = I915_READ(fdi_rx_reg);
  1568. if ((temp & FDI_RX_PLL_ENABLE) != 0) {
  1569. temp &= ~FDI_SEL_PCDCLK;
  1570. temp &= ~FDI_RX_PLL_ENABLE;
  1571. I915_WRITE(fdi_rx_reg, temp);
  1572. I915_READ(fdi_rx_reg);
  1573. }
  1574. /* Disable CPU FDI TX PLL */
  1575. temp = I915_READ(fdi_tx_reg);
  1576. if ((temp & FDI_TX_PLL_ENABLE) != 0) {
  1577. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
  1578. I915_READ(fdi_tx_reg);
  1579. udelay(100);
  1580. }
  1581. /* Disable PF */
  1582. temp = I915_READ(pf_ctl_reg);
  1583. if ((temp & PF_ENABLE) != 0) {
  1584. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1585. I915_READ(pf_ctl_reg);
  1586. }
  1587. I915_WRITE(pf_win_size, 0);
  1588. /* Wait for the clocks to turn off. */
  1589. udelay(150);
  1590. break;
  1591. }
  1592. }
  1593. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  1594. {
  1595. struct intel_overlay *overlay;
  1596. int ret;
  1597. if (!enable && intel_crtc->overlay) {
  1598. overlay = intel_crtc->overlay;
  1599. mutex_lock(&overlay->dev->struct_mutex);
  1600. for (;;) {
  1601. ret = intel_overlay_switch_off(overlay);
  1602. if (ret == 0)
  1603. break;
  1604. ret = intel_overlay_recover_from_interrupt(overlay, 0);
  1605. if (ret != 0) {
  1606. /* overlay doesn't react anymore. Usually
  1607. * results in a black screen and an unkillable
  1608. * X server. */
  1609. BUG();
  1610. overlay->hw_wedged = HW_WEDGED;
  1611. break;
  1612. }
  1613. }
  1614. mutex_unlock(&overlay->dev->struct_mutex);
  1615. }
  1616. /* Let userspace switch the overlay on again. In most cases userspace
  1617. * has to recompute where to put it anyway. */
  1618. return;
  1619. }
  1620. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  1621. {
  1622. struct drm_device *dev = crtc->dev;
  1623. struct drm_i915_private *dev_priv = dev->dev_private;
  1624. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1625. int pipe = intel_crtc->pipe;
  1626. int plane = intel_crtc->plane;
  1627. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1628. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1629. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1630. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1631. u32 temp;
  1632. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1633. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1634. */
  1635. switch (mode) {
  1636. case DRM_MODE_DPMS_ON:
  1637. case DRM_MODE_DPMS_STANDBY:
  1638. case DRM_MODE_DPMS_SUSPEND:
  1639. intel_update_watermarks(dev);
  1640. /* Enable the DPLL */
  1641. temp = I915_READ(dpll_reg);
  1642. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1643. I915_WRITE(dpll_reg, temp);
  1644. I915_READ(dpll_reg);
  1645. /* Wait for the clocks to stabilize. */
  1646. udelay(150);
  1647. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1648. I915_READ(dpll_reg);
  1649. /* Wait for the clocks to stabilize. */
  1650. udelay(150);
  1651. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1652. I915_READ(dpll_reg);
  1653. /* Wait for the clocks to stabilize. */
  1654. udelay(150);
  1655. }
  1656. /* Enable the pipe */
  1657. temp = I915_READ(pipeconf_reg);
  1658. if ((temp & PIPEACONF_ENABLE) == 0)
  1659. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1660. /* Enable the plane */
  1661. temp = I915_READ(dspcntr_reg);
  1662. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1663. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1664. /* Flush the plane changes */
  1665. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1666. }
  1667. intel_crtc_load_lut(crtc);
  1668. if ((IS_I965G(dev) || plane == 0))
  1669. intel_update_fbc(crtc, &crtc->mode);
  1670. /* Give the overlay scaler a chance to enable if it's on this pipe */
  1671. intel_crtc_dpms_overlay(intel_crtc, true);
  1672. break;
  1673. case DRM_MODE_DPMS_OFF:
  1674. intel_update_watermarks(dev);
  1675. /* Give the overlay scaler a chance to disable if it's on this pipe */
  1676. intel_crtc_dpms_overlay(intel_crtc, false);
  1677. if (dev_priv->cfb_plane == plane &&
  1678. dev_priv->display.disable_fbc)
  1679. dev_priv->display.disable_fbc(dev);
  1680. /* Disable the VGA plane that we never use */
  1681. i915_disable_vga(dev);
  1682. /* Disable display plane */
  1683. temp = I915_READ(dspcntr_reg);
  1684. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1685. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1686. /* Flush the plane changes */
  1687. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1688. I915_READ(dspbase_reg);
  1689. }
  1690. if (!IS_I9XX(dev)) {
  1691. /* Wait for vblank for the disable to take effect */
  1692. intel_wait_for_vblank(dev);
  1693. }
  1694. /* Next, disable display pipes */
  1695. temp = I915_READ(pipeconf_reg);
  1696. if ((temp & PIPEACONF_ENABLE) != 0) {
  1697. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1698. I915_READ(pipeconf_reg);
  1699. }
  1700. /* Wait for vblank for the disable to take effect. */
  1701. intel_wait_for_vblank(dev);
  1702. temp = I915_READ(dpll_reg);
  1703. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1704. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1705. I915_READ(dpll_reg);
  1706. }
  1707. /* Wait for the clocks to turn off. */
  1708. udelay(150);
  1709. break;
  1710. }
  1711. }
  1712. /**
  1713. * Sets the power management mode of the pipe and plane.
  1714. *
  1715. * This code should probably grow support for turning the cursor off and back
  1716. * on appropriately at the same time as we're turning the pipe off/on.
  1717. */
  1718. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  1719. {
  1720. struct drm_device *dev = crtc->dev;
  1721. struct drm_i915_private *dev_priv = dev->dev_private;
  1722. struct drm_i915_master_private *master_priv;
  1723. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1724. int pipe = intel_crtc->pipe;
  1725. bool enabled;
  1726. dev_priv->display.dpms(crtc, mode);
  1727. intel_crtc->dpms_mode = mode;
  1728. if (!dev->primary->master)
  1729. return;
  1730. master_priv = dev->primary->master->driver_priv;
  1731. if (!master_priv->sarea_priv)
  1732. return;
  1733. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  1734. switch (pipe) {
  1735. case 0:
  1736. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  1737. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  1738. break;
  1739. case 1:
  1740. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  1741. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  1742. break;
  1743. default:
  1744. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  1745. break;
  1746. }
  1747. }
  1748. static void intel_crtc_prepare (struct drm_crtc *crtc)
  1749. {
  1750. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1751. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  1752. }
  1753. static void intel_crtc_commit (struct drm_crtc *crtc)
  1754. {
  1755. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  1756. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  1757. }
  1758. void intel_encoder_prepare (struct drm_encoder *encoder)
  1759. {
  1760. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1761. /* lvds has its own version of prepare see intel_lvds_prepare */
  1762. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  1763. }
  1764. void intel_encoder_commit (struct drm_encoder *encoder)
  1765. {
  1766. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  1767. /* lvds has its own version of commit see intel_lvds_commit */
  1768. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  1769. }
  1770. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  1771. struct drm_display_mode *mode,
  1772. struct drm_display_mode *adjusted_mode)
  1773. {
  1774. struct drm_device *dev = crtc->dev;
  1775. if (IS_IGDNG(dev)) {
  1776. /* FDI link clock is fixed at 2.7G */
  1777. if (mode->clock * 3 > 27000 * 4)
  1778. return MODE_CLOCK_HIGH;
  1779. }
  1780. return true;
  1781. }
  1782. static int i945_get_display_clock_speed(struct drm_device *dev)
  1783. {
  1784. return 400000;
  1785. }
  1786. static int i915_get_display_clock_speed(struct drm_device *dev)
  1787. {
  1788. return 333000;
  1789. }
  1790. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  1791. {
  1792. return 200000;
  1793. }
  1794. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  1795. {
  1796. u16 gcfgc = 0;
  1797. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  1798. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  1799. return 133000;
  1800. else {
  1801. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  1802. case GC_DISPLAY_CLOCK_333_MHZ:
  1803. return 333000;
  1804. default:
  1805. case GC_DISPLAY_CLOCK_190_200_MHZ:
  1806. return 190000;
  1807. }
  1808. }
  1809. }
  1810. static int i865_get_display_clock_speed(struct drm_device *dev)
  1811. {
  1812. return 266000;
  1813. }
  1814. static int i855_get_display_clock_speed(struct drm_device *dev)
  1815. {
  1816. u16 hpllcc = 0;
  1817. /* Assume that the hardware is in the high speed state. This
  1818. * should be the default.
  1819. */
  1820. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  1821. case GC_CLOCK_133_200:
  1822. case GC_CLOCK_100_200:
  1823. return 200000;
  1824. case GC_CLOCK_166_250:
  1825. return 250000;
  1826. case GC_CLOCK_100_133:
  1827. return 133000;
  1828. }
  1829. /* Shouldn't happen */
  1830. return 0;
  1831. }
  1832. static int i830_get_display_clock_speed(struct drm_device *dev)
  1833. {
  1834. return 133000;
  1835. }
  1836. /**
  1837. * Return the pipe currently connected to the panel fitter,
  1838. * or -1 if the panel fitter is not present or not in use
  1839. */
  1840. int intel_panel_fitter_pipe (struct drm_device *dev)
  1841. {
  1842. struct drm_i915_private *dev_priv = dev->dev_private;
  1843. u32 pfit_control;
  1844. /* i830 doesn't have a panel fitter */
  1845. if (IS_I830(dev))
  1846. return -1;
  1847. pfit_control = I915_READ(PFIT_CONTROL);
  1848. /* See if the panel fitter is in use */
  1849. if ((pfit_control & PFIT_ENABLE) == 0)
  1850. return -1;
  1851. /* 965 can place panel fitter on either pipe */
  1852. if (IS_I965G(dev))
  1853. return (pfit_control >> 29) & 0x3;
  1854. /* older chips can only use pipe 1 */
  1855. return 1;
  1856. }
  1857. struct fdi_m_n {
  1858. u32 tu;
  1859. u32 gmch_m;
  1860. u32 gmch_n;
  1861. u32 link_m;
  1862. u32 link_n;
  1863. };
  1864. static void
  1865. fdi_reduce_ratio(u32 *num, u32 *den)
  1866. {
  1867. while (*num > 0xffffff || *den > 0xffffff) {
  1868. *num >>= 1;
  1869. *den >>= 1;
  1870. }
  1871. }
  1872. #define DATA_N 0x800000
  1873. #define LINK_N 0x80000
  1874. static void
  1875. igdng_compute_m_n(int bits_per_pixel, int nlanes,
  1876. int pixel_clock, int link_clock,
  1877. struct fdi_m_n *m_n)
  1878. {
  1879. u64 temp;
  1880. m_n->tu = 64; /* default size */
  1881. temp = (u64) DATA_N * pixel_clock;
  1882. temp = div_u64(temp, link_clock);
  1883. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  1884. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  1885. m_n->gmch_n = DATA_N;
  1886. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  1887. temp = (u64) LINK_N * pixel_clock;
  1888. m_n->link_m = div_u64(temp, link_clock);
  1889. m_n->link_n = LINK_N;
  1890. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  1891. }
  1892. struct intel_watermark_params {
  1893. unsigned long fifo_size;
  1894. unsigned long max_wm;
  1895. unsigned long default_wm;
  1896. unsigned long guard_size;
  1897. unsigned long cacheline_size;
  1898. };
  1899. /* IGD has different values for various configs */
  1900. static struct intel_watermark_params igd_display_wm = {
  1901. IGD_DISPLAY_FIFO,
  1902. IGD_MAX_WM,
  1903. IGD_DFT_WM,
  1904. IGD_GUARD_WM,
  1905. IGD_FIFO_LINE_SIZE
  1906. };
  1907. static struct intel_watermark_params igd_display_hplloff_wm = {
  1908. IGD_DISPLAY_FIFO,
  1909. IGD_MAX_WM,
  1910. IGD_DFT_HPLLOFF_WM,
  1911. IGD_GUARD_WM,
  1912. IGD_FIFO_LINE_SIZE
  1913. };
  1914. static struct intel_watermark_params igd_cursor_wm = {
  1915. IGD_CURSOR_FIFO,
  1916. IGD_CURSOR_MAX_WM,
  1917. IGD_CURSOR_DFT_WM,
  1918. IGD_CURSOR_GUARD_WM,
  1919. IGD_FIFO_LINE_SIZE,
  1920. };
  1921. static struct intel_watermark_params igd_cursor_hplloff_wm = {
  1922. IGD_CURSOR_FIFO,
  1923. IGD_CURSOR_MAX_WM,
  1924. IGD_CURSOR_DFT_WM,
  1925. IGD_CURSOR_GUARD_WM,
  1926. IGD_FIFO_LINE_SIZE
  1927. };
  1928. static struct intel_watermark_params g4x_wm_info = {
  1929. G4X_FIFO_SIZE,
  1930. G4X_MAX_WM,
  1931. G4X_MAX_WM,
  1932. 2,
  1933. G4X_FIFO_LINE_SIZE,
  1934. };
  1935. static struct intel_watermark_params i945_wm_info = {
  1936. I945_FIFO_SIZE,
  1937. I915_MAX_WM,
  1938. 1,
  1939. 2,
  1940. I915_FIFO_LINE_SIZE
  1941. };
  1942. static struct intel_watermark_params i915_wm_info = {
  1943. I915_FIFO_SIZE,
  1944. I915_MAX_WM,
  1945. 1,
  1946. 2,
  1947. I915_FIFO_LINE_SIZE
  1948. };
  1949. static struct intel_watermark_params i855_wm_info = {
  1950. I855GM_FIFO_SIZE,
  1951. I915_MAX_WM,
  1952. 1,
  1953. 2,
  1954. I830_FIFO_LINE_SIZE
  1955. };
  1956. static struct intel_watermark_params i830_wm_info = {
  1957. I830_FIFO_SIZE,
  1958. I915_MAX_WM,
  1959. 1,
  1960. 2,
  1961. I830_FIFO_LINE_SIZE
  1962. };
  1963. /**
  1964. * intel_calculate_wm - calculate watermark level
  1965. * @clock_in_khz: pixel clock
  1966. * @wm: chip FIFO params
  1967. * @pixel_size: display pixel size
  1968. * @latency_ns: memory latency for the platform
  1969. *
  1970. * Calculate the watermark level (the level at which the display plane will
  1971. * start fetching from memory again). Each chip has a different display
  1972. * FIFO size and allocation, so the caller needs to figure that out and pass
  1973. * in the correct intel_watermark_params structure.
  1974. *
  1975. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  1976. * on the pixel size. When it reaches the watermark level, it'll start
  1977. * fetching FIFO line sized based chunks from memory until the FIFO fills
  1978. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  1979. * will occur, and a display engine hang could result.
  1980. */
  1981. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  1982. struct intel_watermark_params *wm,
  1983. int pixel_size,
  1984. unsigned long latency_ns)
  1985. {
  1986. long entries_required, wm_size;
  1987. /*
  1988. * Note: we need to make sure we don't overflow for various clock &
  1989. * latency values.
  1990. * clocks go from a few thousand to several hundred thousand.
  1991. * latency is usually a few thousand
  1992. */
  1993. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  1994. 1000;
  1995. entries_required /= wm->cacheline_size;
  1996. DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
  1997. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  1998. DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
  1999. /* Don't promote wm_size to unsigned... */
  2000. if (wm_size > (long)wm->max_wm)
  2001. wm_size = wm->max_wm;
  2002. if (wm_size <= 0)
  2003. wm_size = wm->default_wm;
  2004. return wm_size;
  2005. }
  2006. struct cxsr_latency {
  2007. int is_desktop;
  2008. unsigned long fsb_freq;
  2009. unsigned long mem_freq;
  2010. unsigned long display_sr;
  2011. unsigned long display_hpll_disable;
  2012. unsigned long cursor_sr;
  2013. unsigned long cursor_hpll_disable;
  2014. };
  2015. static struct cxsr_latency cxsr_latency_table[] = {
  2016. {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2017. {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2018. {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2019. {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2020. {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2021. {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2022. {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2023. {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2024. {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2025. {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2026. {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2027. {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2028. {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2029. {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2030. {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2031. {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2032. {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2033. {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2034. };
  2035. static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
  2036. int mem)
  2037. {
  2038. int i;
  2039. struct cxsr_latency *latency;
  2040. if (fsb == 0 || mem == 0)
  2041. return NULL;
  2042. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2043. latency = &cxsr_latency_table[i];
  2044. if (is_desktop == latency->is_desktop &&
  2045. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2046. return latency;
  2047. }
  2048. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2049. return NULL;
  2050. }
  2051. static void igd_disable_cxsr(struct drm_device *dev)
  2052. {
  2053. struct drm_i915_private *dev_priv = dev->dev_private;
  2054. u32 reg;
  2055. /* deactivate cxsr */
  2056. reg = I915_READ(DSPFW3);
  2057. reg &= ~(IGD_SELF_REFRESH_EN);
  2058. I915_WRITE(DSPFW3, reg);
  2059. DRM_INFO("Big FIFO is disabled\n");
  2060. }
  2061. static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
  2062. int pixel_size)
  2063. {
  2064. struct drm_i915_private *dev_priv = dev->dev_private;
  2065. u32 reg;
  2066. unsigned long wm;
  2067. struct cxsr_latency *latency;
  2068. latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
  2069. dev_priv->mem_freq);
  2070. if (!latency) {
  2071. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2072. igd_disable_cxsr(dev);
  2073. return;
  2074. }
  2075. /* Display SR */
  2076. wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
  2077. latency->display_sr);
  2078. reg = I915_READ(DSPFW1);
  2079. reg &= 0x7fffff;
  2080. reg |= wm << 23;
  2081. I915_WRITE(DSPFW1, reg);
  2082. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  2083. /* cursor SR */
  2084. wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
  2085. latency->cursor_sr);
  2086. reg = I915_READ(DSPFW3);
  2087. reg &= ~(0x3f << 24);
  2088. reg |= (wm & 0x3f) << 24;
  2089. I915_WRITE(DSPFW3, reg);
  2090. /* Display HPLL off SR */
  2091. wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
  2092. latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
  2093. reg = I915_READ(DSPFW3);
  2094. reg &= 0xfffffe00;
  2095. reg |= wm & 0x1ff;
  2096. I915_WRITE(DSPFW3, reg);
  2097. /* cursor HPLL off SR */
  2098. wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
  2099. latency->cursor_hpll_disable);
  2100. reg = I915_READ(DSPFW3);
  2101. reg &= ~(0x3f << 16);
  2102. reg |= (wm & 0x3f) << 16;
  2103. I915_WRITE(DSPFW3, reg);
  2104. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  2105. /* activate cxsr */
  2106. reg = I915_READ(DSPFW3);
  2107. reg |= IGD_SELF_REFRESH_EN;
  2108. I915_WRITE(DSPFW3, reg);
  2109. DRM_INFO("Big FIFO is enabled\n");
  2110. return;
  2111. }
  2112. /*
  2113. * Latency for FIFO fetches is dependent on several factors:
  2114. * - memory configuration (speed, channels)
  2115. * - chipset
  2116. * - current MCH state
  2117. * It can be fairly high in some situations, so here we assume a fairly
  2118. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2119. * set this value too high, the FIFO will fetch frequently to stay full)
  2120. * and power consumption (set it too low to save power and we might see
  2121. * FIFO underruns and display "flicker").
  2122. *
  2123. * A value of 5us seems to be a good balance; safe for very low end
  2124. * platforms but not overly aggressive on lower latency configs.
  2125. */
  2126. const static int latency_ns = 5000;
  2127. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2128. {
  2129. struct drm_i915_private *dev_priv = dev->dev_private;
  2130. uint32_t dsparb = I915_READ(DSPARB);
  2131. int size;
  2132. if (plane == 0)
  2133. size = dsparb & 0x7f;
  2134. else
  2135. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
  2136. (dsparb & 0x7f);
  2137. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2138. plane ? "B" : "A", size);
  2139. return size;
  2140. }
  2141. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2142. {
  2143. struct drm_i915_private *dev_priv = dev->dev_private;
  2144. uint32_t dsparb = I915_READ(DSPARB);
  2145. int size;
  2146. if (plane == 0)
  2147. size = dsparb & 0x1ff;
  2148. else
  2149. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
  2150. (dsparb & 0x1ff);
  2151. size >>= 1; /* Convert to cachelines */
  2152. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2153. plane ? "B" : "A", size);
  2154. return size;
  2155. }
  2156. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2157. {
  2158. struct drm_i915_private *dev_priv = dev->dev_private;
  2159. uint32_t dsparb = I915_READ(DSPARB);
  2160. int size;
  2161. size = dsparb & 0x7f;
  2162. size >>= 2; /* Convert to cachelines */
  2163. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2164. plane ? "B" : "A",
  2165. size);
  2166. return size;
  2167. }
  2168. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2169. {
  2170. struct drm_i915_private *dev_priv = dev->dev_private;
  2171. uint32_t dsparb = I915_READ(DSPARB);
  2172. int size;
  2173. size = dsparb & 0x7f;
  2174. size >>= 1; /* Convert to cachelines */
  2175. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2176. plane ? "B" : "A", size);
  2177. return size;
  2178. }
  2179. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2180. int planeb_clock, int sr_hdisplay, int pixel_size)
  2181. {
  2182. struct drm_i915_private *dev_priv = dev->dev_private;
  2183. int total_size, cacheline_size;
  2184. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2185. struct intel_watermark_params planea_params, planeb_params;
  2186. unsigned long line_time_us;
  2187. int sr_clock, sr_entries = 0, entries_required;
  2188. /* Create copies of the base settings for each pipe */
  2189. planea_params = planeb_params = g4x_wm_info;
  2190. /* Grab a couple of global values before we overwrite them */
  2191. total_size = planea_params.fifo_size;
  2192. cacheline_size = planea_params.cacheline_size;
  2193. /*
  2194. * Note: we need to make sure we don't overflow for various clock &
  2195. * latency values.
  2196. * clocks go from a few thousand to several hundred thousand.
  2197. * latency is usually a few thousand
  2198. */
  2199. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2200. 1000;
  2201. entries_required /= G4X_FIFO_LINE_SIZE;
  2202. planea_wm = entries_required + planea_params.guard_size;
  2203. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2204. 1000;
  2205. entries_required /= G4X_FIFO_LINE_SIZE;
  2206. planeb_wm = entries_required + planeb_params.guard_size;
  2207. cursora_wm = cursorb_wm = 16;
  2208. cursor_sr = 32;
  2209. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2210. /* Calc sr entries for one plane configs */
  2211. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2212. /* self-refresh has much higher latency */
  2213. const static int sr_latency_ns = 12000;
  2214. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2215. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2216. /* Use ns/us then divide to preserve precision */
  2217. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2218. pixel_size * sr_hdisplay) / 1000;
  2219. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2220. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2221. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2222. }
  2223. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2224. planea_wm, planeb_wm, sr_entries);
  2225. planea_wm &= 0x3f;
  2226. planeb_wm &= 0x3f;
  2227. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2228. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2229. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2230. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2231. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2232. /* HPLL off in SR has some issues on G4x... disable it */
  2233. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2234. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2235. }
  2236. static void i965_update_wm(struct drm_device *dev, int planea_clock,
  2237. int planeb_clock, int sr_hdisplay, int pixel_size)
  2238. {
  2239. struct drm_i915_private *dev_priv = dev->dev_private;
  2240. unsigned long line_time_us;
  2241. int sr_clock, sr_entries, srwm = 1;
  2242. /* Calc sr entries for one plane configs */
  2243. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2244. /* self-refresh has much higher latency */
  2245. const static int sr_latency_ns = 12000;
  2246. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2247. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2248. /* Use ns/us then divide to preserve precision */
  2249. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2250. pixel_size * sr_hdisplay) / 1000;
  2251. sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
  2252. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2253. srwm = I945_FIFO_SIZE - sr_entries;
  2254. if (srwm < 0)
  2255. srwm = 1;
  2256. srwm &= 0x3f;
  2257. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2258. }
  2259. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  2260. srwm);
  2261. /* 965 has limitations... */
  2262. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
  2263. (8 << 0));
  2264. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2265. }
  2266. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2267. int planeb_clock, int sr_hdisplay, int pixel_size)
  2268. {
  2269. struct drm_i915_private *dev_priv = dev->dev_private;
  2270. uint32_t fwater_lo;
  2271. uint32_t fwater_hi;
  2272. int total_size, cacheline_size, cwm, srwm = 1;
  2273. int planea_wm, planeb_wm;
  2274. struct intel_watermark_params planea_params, planeb_params;
  2275. unsigned long line_time_us;
  2276. int sr_clock, sr_entries = 0;
  2277. /* Create copies of the base settings for each pipe */
  2278. if (IS_I965GM(dev) || IS_I945GM(dev))
  2279. planea_params = planeb_params = i945_wm_info;
  2280. else if (IS_I9XX(dev))
  2281. planea_params = planeb_params = i915_wm_info;
  2282. else
  2283. planea_params = planeb_params = i855_wm_info;
  2284. /* Grab a couple of global values before we overwrite them */
  2285. total_size = planea_params.fifo_size;
  2286. cacheline_size = planea_params.cacheline_size;
  2287. /* Update per-plane FIFO sizes */
  2288. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2289. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2290. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2291. pixel_size, latency_ns);
  2292. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2293. pixel_size, latency_ns);
  2294. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2295. /*
  2296. * Overlay gets an aggressive default since video jitter is bad.
  2297. */
  2298. cwm = 2;
  2299. /* Calc sr entries for one plane configs */
  2300. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2301. (!planea_clock || !planeb_clock)) {
  2302. /* self-refresh has much higher latency */
  2303. const static int sr_latency_ns = 6000;
  2304. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2305. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2306. /* Use ns/us then divide to preserve precision */
  2307. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2308. pixel_size * sr_hdisplay) / 1000;
  2309. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2310. DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
  2311. srwm = total_size - sr_entries;
  2312. if (srwm < 0)
  2313. srwm = 1;
  2314. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
  2315. }
  2316. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2317. planea_wm, planeb_wm, cwm, srwm);
  2318. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2319. fwater_hi = (cwm & 0x1f);
  2320. /* Set request length to 8 cachelines per fetch */
  2321. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2322. fwater_hi = fwater_hi | (1 << 8);
  2323. I915_WRITE(FW_BLC, fwater_lo);
  2324. I915_WRITE(FW_BLC2, fwater_hi);
  2325. }
  2326. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2327. int unused2, int pixel_size)
  2328. {
  2329. struct drm_i915_private *dev_priv = dev->dev_private;
  2330. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2331. int planea_wm;
  2332. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2333. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2334. pixel_size, latency_ns);
  2335. fwater_lo |= (3<<8) | planea_wm;
  2336. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  2337. I915_WRITE(FW_BLC, fwater_lo);
  2338. }
  2339. /**
  2340. * intel_update_watermarks - update FIFO watermark values based on current modes
  2341. *
  2342. * Calculate watermark values for the various WM regs based on current mode
  2343. * and plane configuration.
  2344. *
  2345. * There are several cases to deal with here:
  2346. * - normal (i.e. non-self-refresh)
  2347. * - self-refresh (SR) mode
  2348. * - lines are large relative to FIFO size (buffer can hold up to 2)
  2349. * - lines are small relative to FIFO size (buffer can hold more than 2
  2350. * lines), so need to account for TLB latency
  2351. *
  2352. * The normal calculation is:
  2353. * watermark = dotclock * bytes per pixel * latency
  2354. * where latency is platform & configuration dependent (we assume pessimal
  2355. * values here).
  2356. *
  2357. * The SR calculation is:
  2358. * watermark = (trunc(latency/line time)+1) * surface width *
  2359. * bytes per pixel
  2360. * where
  2361. * line time = htotal / dotclock
  2362. * and latency is assumed to be high, as above.
  2363. *
  2364. * The final value programmed to the register should always be rounded up,
  2365. * and include an extra 2 entries to account for clock crossings.
  2366. *
  2367. * We don't use the sprite, so we can ignore that. And on Crestline we have
  2368. * to set the non-SR watermarks to 8.
  2369. */
  2370. static void intel_update_watermarks(struct drm_device *dev)
  2371. {
  2372. struct drm_i915_private *dev_priv = dev->dev_private;
  2373. struct drm_crtc *crtc;
  2374. struct intel_crtc *intel_crtc;
  2375. int sr_hdisplay = 0;
  2376. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  2377. int enabled = 0, pixel_size = 0;
  2378. if (!dev_priv->display.update_wm)
  2379. return;
  2380. /* Get the clock config from both planes */
  2381. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2382. intel_crtc = to_intel_crtc(crtc);
  2383. if (crtc->enabled) {
  2384. enabled++;
  2385. if (intel_crtc->plane == 0) {
  2386. DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
  2387. intel_crtc->pipe, crtc->mode.clock);
  2388. planea_clock = crtc->mode.clock;
  2389. } else {
  2390. DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
  2391. intel_crtc->pipe, crtc->mode.clock);
  2392. planeb_clock = crtc->mode.clock;
  2393. }
  2394. sr_hdisplay = crtc->mode.hdisplay;
  2395. sr_clock = crtc->mode.clock;
  2396. if (crtc->fb)
  2397. pixel_size = crtc->fb->bits_per_pixel / 8;
  2398. else
  2399. pixel_size = 4; /* by default */
  2400. }
  2401. }
  2402. if (enabled <= 0)
  2403. return;
  2404. /* Single plane configs can enable self refresh */
  2405. if (enabled == 1 && IS_IGD(dev))
  2406. igd_enable_cxsr(dev, sr_clock, pixel_size);
  2407. else if (IS_IGD(dev))
  2408. igd_disable_cxsr(dev);
  2409. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  2410. sr_hdisplay, pixel_size);
  2411. }
  2412. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  2413. struct drm_display_mode *mode,
  2414. struct drm_display_mode *adjusted_mode,
  2415. int x, int y,
  2416. struct drm_framebuffer *old_fb)
  2417. {
  2418. struct drm_device *dev = crtc->dev;
  2419. struct drm_i915_private *dev_priv = dev->dev_private;
  2420. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2421. int pipe = intel_crtc->pipe;
  2422. int plane = intel_crtc->plane;
  2423. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  2424. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2425. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  2426. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2427. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2428. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  2429. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  2430. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  2431. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  2432. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  2433. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  2434. int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
  2435. int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
  2436. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  2437. int refclk, num_outputs = 0;
  2438. intel_clock_t clock, reduced_clock;
  2439. u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
  2440. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  2441. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  2442. bool is_edp = false;
  2443. struct drm_mode_config *mode_config = &dev->mode_config;
  2444. struct drm_connector *connector;
  2445. const intel_limit_t *limit;
  2446. int ret;
  2447. struct fdi_m_n m_n = {0};
  2448. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  2449. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  2450. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  2451. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  2452. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  2453. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  2454. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  2455. int lvds_reg = LVDS;
  2456. u32 temp;
  2457. int sdvo_pixel_multiply;
  2458. int target_clock;
  2459. drm_vblank_pre_modeset(dev, pipe);
  2460. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2461. struct intel_output *intel_output = to_intel_output(connector);
  2462. if (!connector->encoder || connector->encoder->crtc != crtc)
  2463. continue;
  2464. switch (intel_output->type) {
  2465. case INTEL_OUTPUT_LVDS:
  2466. is_lvds = true;
  2467. break;
  2468. case INTEL_OUTPUT_SDVO:
  2469. case INTEL_OUTPUT_HDMI:
  2470. is_sdvo = true;
  2471. if (intel_output->needs_tv_clock)
  2472. is_tv = true;
  2473. break;
  2474. case INTEL_OUTPUT_DVO:
  2475. is_dvo = true;
  2476. break;
  2477. case INTEL_OUTPUT_TVOUT:
  2478. is_tv = true;
  2479. break;
  2480. case INTEL_OUTPUT_ANALOG:
  2481. is_crt = true;
  2482. break;
  2483. case INTEL_OUTPUT_DISPLAYPORT:
  2484. is_dp = true;
  2485. break;
  2486. case INTEL_OUTPUT_EDP:
  2487. is_edp = true;
  2488. break;
  2489. }
  2490. num_outputs++;
  2491. }
  2492. if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
  2493. refclk = dev_priv->lvds_ssc_freq * 1000;
  2494. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  2495. refclk / 1000);
  2496. } else if (IS_I9XX(dev)) {
  2497. refclk = 96000;
  2498. if (IS_IGDNG(dev))
  2499. refclk = 120000; /* 120Mhz refclk */
  2500. } else {
  2501. refclk = 48000;
  2502. }
  2503. /*
  2504. * Returns a set of divisors for the desired target clock with the given
  2505. * refclk, or FALSE. The returned values represent the clock equation:
  2506. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  2507. */
  2508. limit = intel_limit(crtc);
  2509. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  2510. if (!ok) {
  2511. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  2512. drm_vblank_post_modeset(dev, pipe);
  2513. return -EINVAL;
  2514. }
  2515. if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
  2516. memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
  2517. has_reduced_clock = limit->find_reduced_pll(limit, crtc,
  2518. (adjusted_mode->clock*3/4),
  2519. refclk,
  2520. &reduced_clock);
  2521. }
  2522. /* SDVO TV has fixed PLL values depend on its clock range,
  2523. this mirrors vbios setting. */
  2524. if (is_sdvo && is_tv) {
  2525. if (adjusted_mode->clock >= 100000
  2526. && adjusted_mode->clock < 140500) {
  2527. clock.p1 = 2;
  2528. clock.p2 = 10;
  2529. clock.n = 3;
  2530. clock.m1 = 16;
  2531. clock.m2 = 8;
  2532. } else if (adjusted_mode->clock >= 140500
  2533. && adjusted_mode->clock <= 200000) {
  2534. clock.p1 = 1;
  2535. clock.p2 = 10;
  2536. clock.n = 6;
  2537. clock.m1 = 12;
  2538. clock.m2 = 8;
  2539. }
  2540. }
  2541. /* FDI link */
  2542. if (IS_IGDNG(dev)) {
  2543. int lane, link_bw, bpp;
  2544. /* eDP doesn't require FDI link, so just set DP M/N
  2545. according to current link config */
  2546. if (is_edp) {
  2547. struct drm_connector *edp;
  2548. target_clock = mode->clock;
  2549. edp = intel_pipe_get_output(crtc);
  2550. intel_edp_link_config(to_intel_output(edp),
  2551. &lane, &link_bw);
  2552. } else {
  2553. /* DP over FDI requires target mode clock
  2554. instead of link clock */
  2555. if (is_dp)
  2556. target_clock = mode->clock;
  2557. else
  2558. target_clock = adjusted_mode->clock;
  2559. lane = 4;
  2560. link_bw = 270000;
  2561. }
  2562. /* determine panel color depth */
  2563. temp = I915_READ(pipeconf_reg);
  2564. switch (temp & PIPE_BPC_MASK) {
  2565. case PIPE_8BPC:
  2566. bpp = 24;
  2567. break;
  2568. case PIPE_10BPC:
  2569. bpp = 30;
  2570. break;
  2571. case PIPE_6BPC:
  2572. bpp = 18;
  2573. break;
  2574. case PIPE_12BPC:
  2575. bpp = 36;
  2576. break;
  2577. default:
  2578. DRM_ERROR("unknown pipe bpc value\n");
  2579. bpp = 24;
  2580. }
  2581. igdng_compute_m_n(bpp, lane, target_clock,
  2582. link_bw, &m_n);
  2583. }
  2584. /* Ironlake: try to setup display ref clock before DPLL
  2585. * enabling. This is only under driver's control after
  2586. * PCH B stepping, previous chipset stepping should be
  2587. * ignoring this setting.
  2588. */
  2589. if (IS_IGDNG(dev)) {
  2590. temp = I915_READ(PCH_DREF_CONTROL);
  2591. /* Always enable nonspread source */
  2592. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  2593. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  2594. I915_WRITE(PCH_DREF_CONTROL, temp);
  2595. POSTING_READ(PCH_DREF_CONTROL);
  2596. temp &= ~DREF_SSC_SOURCE_MASK;
  2597. temp |= DREF_SSC_SOURCE_ENABLE;
  2598. I915_WRITE(PCH_DREF_CONTROL, temp);
  2599. POSTING_READ(PCH_DREF_CONTROL);
  2600. udelay(200);
  2601. if (is_edp) {
  2602. if (dev_priv->lvds_use_ssc) {
  2603. temp |= DREF_SSC1_ENABLE;
  2604. I915_WRITE(PCH_DREF_CONTROL, temp);
  2605. POSTING_READ(PCH_DREF_CONTROL);
  2606. udelay(200);
  2607. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  2608. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  2609. I915_WRITE(PCH_DREF_CONTROL, temp);
  2610. POSTING_READ(PCH_DREF_CONTROL);
  2611. } else {
  2612. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  2613. I915_WRITE(PCH_DREF_CONTROL, temp);
  2614. POSTING_READ(PCH_DREF_CONTROL);
  2615. }
  2616. }
  2617. }
  2618. if (IS_IGD(dev)) {
  2619. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  2620. if (has_reduced_clock)
  2621. fp2 = (1 << reduced_clock.n) << 16 |
  2622. reduced_clock.m1 << 8 | reduced_clock.m2;
  2623. } else {
  2624. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  2625. if (has_reduced_clock)
  2626. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  2627. reduced_clock.m2;
  2628. }
  2629. if (!IS_IGDNG(dev))
  2630. dpll = DPLL_VGA_MODE_DIS;
  2631. if (IS_I9XX(dev)) {
  2632. if (is_lvds)
  2633. dpll |= DPLLB_MODE_LVDS;
  2634. else
  2635. dpll |= DPLLB_MODE_DAC_SERIAL;
  2636. if (is_sdvo) {
  2637. dpll |= DPLL_DVO_HIGH_SPEED;
  2638. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  2639. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  2640. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  2641. else if (IS_IGDNG(dev))
  2642. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  2643. }
  2644. if (is_dp)
  2645. dpll |= DPLL_DVO_HIGH_SPEED;
  2646. /* compute bitmask from p1 value */
  2647. if (IS_IGD(dev))
  2648. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
  2649. else {
  2650. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  2651. /* also FPA1 */
  2652. if (IS_IGDNG(dev))
  2653. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  2654. if (IS_G4X(dev) && has_reduced_clock)
  2655. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  2656. }
  2657. switch (clock.p2) {
  2658. case 5:
  2659. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  2660. break;
  2661. case 7:
  2662. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  2663. break;
  2664. case 10:
  2665. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  2666. break;
  2667. case 14:
  2668. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  2669. break;
  2670. }
  2671. if (IS_I965G(dev) && !IS_IGDNG(dev))
  2672. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  2673. } else {
  2674. if (is_lvds) {
  2675. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  2676. } else {
  2677. if (clock.p1 == 2)
  2678. dpll |= PLL_P1_DIVIDE_BY_TWO;
  2679. else
  2680. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  2681. if (clock.p2 == 4)
  2682. dpll |= PLL_P2_DIVIDE_BY_4;
  2683. }
  2684. }
  2685. if (is_sdvo && is_tv)
  2686. dpll |= PLL_REF_INPUT_TVCLKINBC;
  2687. else if (is_tv)
  2688. /* XXX: just matching BIOS for now */
  2689. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  2690. dpll |= 3;
  2691. else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
  2692. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  2693. else
  2694. dpll |= PLL_REF_INPUT_DREFCLK;
  2695. /* setup pipeconf */
  2696. pipeconf = I915_READ(pipeconf_reg);
  2697. /* Set up the display plane register */
  2698. dspcntr = DISPPLANE_GAMMA_ENABLE;
  2699. /* IGDNG's plane is forced to pipe, bit 24 is to
  2700. enable color space conversion */
  2701. if (!IS_IGDNG(dev)) {
  2702. if (pipe == 0)
  2703. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  2704. else
  2705. dspcntr |= DISPPLANE_SEL_PIPE_B;
  2706. }
  2707. if (pipe == 0 && !IS_I965G(dev)) {
  2708. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  2709. * core speed.
  2710. *
  2711. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  2712. * pipe == 0 check?
  2713. */
  2714. if (mode->clock >
  2715. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  2716. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  2717. else
  2718. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  2719. }
  2720. dspcntr |= DISPLAY_PLANE_ENABLE;
  2721. pipeconf |= PIPEACONF_ENABLE;
  2722. dpll |= DPLL_VCO_ENABLE;
  2723. /* Disable the panel fitter if it was on our pipe */
  2724. if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
  2725. I915_WRITE(PFIT_CONTROL, 0);
  2726. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  2727. drm_mode_debug_printmodeline(mode);
  2728. /* assign to IGDNG registers */
  2729. if (IS_IGDNG(dev)) {
  2730. fp_reg = pch_fp_reg;
  2731. dpll_reg = pch_dpll_reg;
  2732. }
  2733. if (is_edp) {
  2734. igdng_disable_pll_edp(crtc);
  2735. } else if ((dpll & DPLL_VCO_ENABLE)) {
  2736. I915_WRITE(fp_reg, fp);
  2737. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  2738. I915_READ(dpll_reg);
  2739. udelay(150);
  2740. }
  2741. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  2742. * This is an exception to the general rule that mode_set doesn't turn
  2743. * things on.
  2744. */
  2745. if (is_lvds) {
  2746. u32 lvds;
  2747. if (IS_IGDNG(dev))
  2748. lvds_reg = PCH_LVDS;
  2749. lvds = I915_READ(lvds_reg);
  2750. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
  2751. /* set the corresponsding LVDS_BORDER bit */
  2752. lvds |= dev_priv->lvds_border_bits;
  2753. /* Set the B0-B3 data pairs corresponding to whether we're going to
  2754. * set the DPLLs for dual-channel mode or not.
  2755. */
  2756. if (clock.p2 == 7)
  2757. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  2758. else
  2759. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  2760. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  2761. * appropriately here, but we need to look more thoroughly into how
  2762. * panels behave in the two modes.
  2763. */
  2764. I915_WRITE(lvds_reg, lvds);
  2765. I915_READ(lvds_reg);
  2766. }
  2767. if (is_dp)
  2768. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  2769. if (!is_edp) {
  2770. I915_WRITE(fp_reg, fp);
  2771. I915_WRITE(dpll_reg, dpll);
  2772. I915_READ(dpll_reg);
  2773. /* Wait for the clocks to stabilize. */
  2774. udelay(150);
  2775. if (IS_I965G(dev) && !IS_IGDNG(dev)) {
  2776. if (is_sdvo) {
  2777. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  2778. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  2779. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  2780. } else
  2781. I915_WRITE(dpll_md_reg, 0);
  2782. } else {
  2783. /* write it again -- the BIOS does, after all */
  2784. I915_WRITE(dpll_reg, dpll);
  2785. }
  2786. I915_READ(dpll_reg);
  2787. /* Wait for the clocks to stabilize. */
  2788. udelay(150);
  2789. }
  2790. if (is_lvds && has_reduced_clock && i915_powersave) {
  2791. I915_WRITE(fp_reg + 4, fp2);
  2792. intel_crtc->lowfreq_avail = true;
  2793. if (HAS_PIPE_CXSR(dev)) {
  2794. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  2795. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  2796. }
  2797. } else {
  2798. I915_WRITE(fp_reg + 4, fp);
  2799. intel_crtc->lowfreq_avail = false;
  2800. if (HAS_PIPE_CXSR(dev)) {
  2801. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  2802. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  2803. }
  2804. }
  2805. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  2806. ((adjusted_mode->crtc_htotal - 1) << 16));
  2807. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  2808. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  2809. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  2810. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  2811. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  2812. ((adjusted_mode->crtc_vtotal - 1) << 16));
  2813. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  2814. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  2815. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  2816. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  2817. /* pipesrc and dspsize control the size that is scaled from, which should
  2818. * always be the user's requested size.
  2819. */
  2820. if (!IS_IGDNG(dev)) {
  2821. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  2822. (mode->hdisplay - 1));
  2823. I915_WRITE(dsppos_reg, 0);
  2824. }
  2825. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  2826. if (IS_IGDNG(dev)) {
  2827. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  2828. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  2829. I915_WRITE(link_m1_reg, m_n.link_m);
  2830. I915_WRITE(link_n1_reg, m_n.link_n);
  2831. if (is_edp) {
  2832. igdng_set_pll_edp(crtc, adjusted_mode->clock);
  2833. } else {
  2834. /* enable FDI RX PLL too */
  2835. temp = I915_READ(fdi_rx_reg);
  2836. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  2837. udelay(200);
  2838. }
  2839. }
  2840. I915_WRITE(pipeconf_reg, pipeconf);
  2841. I915_READ(pipeconf_reg);
  2842. intel_wait_for_vblank(dev);
  2843. if (IS_IGDNG(dev)) {
  2844. /* enable address swizzle for tiling buffer */
  2845. temp = I915_READ(DISP_ARB_CTL);
  2846. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  2847. }
  2848. I915_WRITE(dspcntr_reg, dspcntr);
  2849. /* Flush the plane changes */
  2850. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  2851. if ((IS_I965G(dev) || plane == 0))
  2852. intel_update_fbc(crtc, &crtc->mode);
  2853. intel_update_watermarks(dev);
  2854. drm_vblank_post_modeset(dev, pipe);
  2855. return ret;
  2856. }
  2857. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  2858. void intel_crtc_load_lut(struct drm_crtc *crtc)
  2859. {
  2860. struct drm_device *dev = crtc->dev;
  2861. struct drm_i915_private *dev_priv = dev->dev_private;
  2862. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2863. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  2864. int i;
  2865. /* The clocks have to be on to load the palette. */
  2866. if (!crtc->enabled)
  2867. return;
  2868. /* use legacy palette for IGDNG */
  2869. if (IS_IGDNG(dev))
  2870. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  2871. LGC_PALETTE_B;
  2872. for (i = 0; i < 256; i++) {
  2873. I915_WRITE(palreg + 4 * i,
  2874. (intel_crtc->lut_r[i] << 16) |
  2875. (intel_crtc->lut_g[i] << 8) |
  2876. intel_crtc->lut_b[i]);
  2877. }
  2878. }
  2879. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  2880. struct drm_file *file_priv,
  2881. uint32_t handle,
  2882. uint32_t width, uint32_t height)
  2883. {
  2884. struct drm_device *dev = crtc->dev;
  2885. struct drm_i915_private *dev_priv = dev->dev_private;
  2886. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2887. struct drm_gem_object *bo;
  2888. struct drm_i915_gem_object *obj_priv;
  2889. int pipe = intel_crtc->pipe;
  2890. uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
  2891. uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
  2892. uint32_t temp = I915_READ(control);
  2893. size_t addr;
  2894. int ret;
  2895. DRM_DEBUG_KMS("\n");
  2896. /* if we want to turn off the cursor ignore width and height */
  2897. if (!handle) {
  2898. DRM_DEBUG_KMS("cursor off\n");
  2899. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  2900. temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  2901. temp |= CURSOR_MODE_DISABLE;
  2902. } else {
  2903. temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  2904. }
  2905. addr = 0;
  2906. bo = NULL;
  2907. mutex_lock(&dev->struct_mutex);
  2908. goto finish;
  2909. }
  2910. /* Currently we only support 64x64 cursors */
  2911. if (width != 64 || height != 64) {
  2912. DRM_ERROR("we currently only support 64x64 cursors\n");
  2913. return -EINVAL;
  2914. }
  2915. bo = drm_gem_object_lookup(dev, file_priv, handle);
  2916. if (!bo)
  2917. return -ENOENT;
  2918. obj_priv = bo->driver_private;
  2919. if (bo->size < width * height * 4) {
  2920. DRM_ERROR("buffer is to small\n");
  2921. ret = -ENOMEM;
  2922. goto fail;
  2923. }
  2924. /* we only need to pin inside GTT if cursor is non-phy */
  2925. mutex_lock(&dev->struct_mutex);
  2926. if (!dev_priv->cursor_needs_physical) {
  2927. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  2928. if (ret) {
  2929. DRM_ERROR("failed to pin cursor bo\n");
  2930. goto fail_locked;
  2931. }
  2932. addr = obj_priv->gtt_offset;
  2933. } else {
  2934. ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  2935. if (ret) {
  2936. DRM_ERROR("failed to attach phys object\n");
  2937. goto fail_locked;
  2938. }
  2939. addr = obj_priv->phys_obj->handle->busaddr;
  2940. }
  2941. if (!IS_I9XX(dev))
  2942. I915_WRITE(CURSIZE, (height << 12) | width);
  2943. /* Hooray for CUR*CNTR differences */
  2944. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  2945. temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  2946. temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  2947. temp |= (pipe << 28); /* Connect to correct pipe */
  2948. } else {
  2949. temp &= ~(CURSOR_FORMAT_MASK);
  2950. temp |= CURSOR_ENABLE;
  2951. temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  2952. }
  2953. finish:
  2954. I915_WRITE(control, temp);
  2955. I915_WRITE(base, addr);
  2956. if (intel_crtc->cursor_bo) {
  2957. if (dev_priv->cursor_needs_physical) {
  2958. if (intel_crtc->cursor_bo != bo)
  2959. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  2960. } else
  2961. i915_gem_object_unpin(intel_crtc->cursor_bo);
  2962. drm_gem_object_unreference(intel_crtc->cursor_bo);
  2963. }
  2964. mutex_unlock(&dev->struct_mutex);
  2965. intel_crtc->cursor_addr = addr;
  2966. intel_crtc->cursor_bo = bo;
  2967. return 0;
  2968. fail:
  2969. mutex_lock(&dev->struct_mutex);
  2970. fail_locked:
  2971. drm_gem_object_unreference(bo);
  2972. mutex_unlock(&dev->struct_mutex);
  2973. return ret;
  2974. }
  2975. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  2976. {
  2977. struct drm_device *dev = crtc->dev;
  2978. struct drm_i915_private *dev_priv = dev->dev_private;
  2979. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2980. struct intel_framebuffer *intel_fb;
  2981. int pipe = intel_crtc->pipe;
  2982. uint32_t temp = 0;
  2983. uint32_t adder;
  2984. if (crtc->fb) {
  2985. intel_fb = to_intel_framebuffer(crtc->fb);
  2986. intel_mark_busy(dev, intel_fb->obj);
  2987. }
  2988. if (x < 0) {
  2989. temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  2990. x = -x;
  2991. }
  2992. if (y < 0) {
  2993. temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  2994. y = -y;
  2995. }
  2996. temp |= x << CURSOR_X_SHIFT;
  2997. temp |= y << CURSOR_Y_SHIFT;
  2998. adder = intel_crtc->cursor_addr;
  2999. I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
  3000. I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
  3001. return 0;
  3002. }
  3003. /** Sets the color ramps on behalf of RandR */
  3004. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  3005. u16 blue, int regno)
  3006. {
  3007. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3008. intel_crtc->lut_r[regno] = red >> 8;
  3009. intel_crtc->lut_g[regno] = green >> 8;
  3010. intel_crtc->lut_b[regno] = blue >> 8;
  3011. }
  3012. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  3013. u16 *blue, int regno)
  3014. {
  3015. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3016. *red = intel_crtc->lut_r[regno] << 8;
  3017. *green = intel_crtc->lut_g[regno] << 8;
  3018. *blue = intel_crtc->lut_b[regno] << 8;
  3019. }
  3020. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  3021. u16 *blue, uint32_t size)
  3022. {
  3023. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3024. int i;
  3025. if (size != 256)
  3026. return;
  3027. for (i = 0; i < 256; i++) {
  3028. intel_crtc->lut_r[i] = red[i] >> 8;
  3029. intel_crtc->lut_g[i] = green[i] >> 8;
  3030. intel_crtc->lut_b[i] = blue[i] >> 8;
  3031. }
  3032. intel_crtc_load_lut(crtc);
  3033. }
  3034. /**
  3035. * Get a pipe with a simple mode set on it for doing load-based monitor
  3036. * detection.
  3037. *
  3038. * It will be up to the load-detect code to adjust the pipe as appropriate for
  3039. * its requirements. The pipe will be connected to no other outputs.
  3040. *
  3041. * Currently this code will only succeed if there is a pipe with no outputs
  3042. * configured for it. In the future, it could choose to temporarily disable
  3043. * some outputs to free up a pipe for its use.
  3044. *
  3045. * \return crtc, or NULL if no pipes are available.
  3046. */
  3047. /* VESA 640x480x72Hz mode to set on the pipe */
  3048. static struct drm_display_mode load_detect_mode = {
  3049. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  3050. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  3051. };
  3052. struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
  3053. struct drm_display_mode *mode,
  3054. int *dpms_mode)
  3055. {
  3056. struct intel_crtc *intel_crtc;
  3057. struct drm_crtc *possible_crtc;
  3058. struct drm_crtc *supported_crtc =NULL;
  3059. struct drm_encoder *encoder = &intel_output->enc;
  3060. struct drm_crtc *crtc = NULL;
  3061. struct drm_device *dev = encoder->dev;
  3062. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3063. struct drm_crtc_helper_funcs *crtc_funcs;
  3064. int i = -1;
  3065. /*
  3066. * Algorithm gets a little messy:
  3067. * - if the connector already has an assigned crtc, use it (but make
  3068. * sure it's on first)
  3069. * - try to find the first unused crtc that can drive this connector,
  3070. * and use that if we find one
  3071. * - if there are no unused crtcs available, try to use the first
  3072. * one we found that supports the connector
  3073. */
  3074. /* See if we already have a CRTC for this connector */
  3075. if (encoder->crtc) {
  3076. crtc = encoder->crtc;
  3077. /* Make sure the crtc and connector are running */
  3078. intel_crtc = to_intel_crtc(crtc);
  3079. *dpms_mode = intel_crtc->dpms_mode;
  3080. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3081. crtc_funcs = crtc->helper_private;
  3082. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3083. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3084. }
  3085. return crtc;
  3086. }
  3087. /* Find an unused one (if possible) */
  3088. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3089. i++;
  3090. if (!(encoder->possible_crtcs & (1 << i)))
  3091. continue;
  3092. if (!possible_crtc->enabled) {
  3093. crtc = possible_crtc;
  3094. break;
  3095. }
  3096. if (!supported_crtc)
  3097. supported_crtc = possible_crtc;
  3098. }
  3099. /*
  3100. * If we didn't find an unused CRTC, don't use any.
  3101. */
  3102. if (!crtc) {
  3103. return NULL;
  3104. }
  3105. encoder->crtc = crtc;
  3106. intel_output->base.encoder = encoder;
  3107. intel_output->load_detect_temp = true;
  3108. intel_crtc = to_intel_crtc(crtc);
  3109. *dpms_mode = intel_crtc->dpms_mode;
  3110. if (!crtc->enabled) {
  3111. if (!mode)
  3112. mode = &load_detect_mode;
  3113. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  3114. } else {
  3115. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3116. crtc_funcs = crtc->helper_private;
  3117. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3118. }
  3119. /* Add this connector to the crtc */
  3120. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  3121. encoder_funcs->commit(encoder);
  3122. }
  3123. /* let the connector get through one full cycle before testing */
  3124. intel_wait_for_vblank(dev);
  3125. return crtc;
  3126. }
  3127. void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
  3128. {
  3129. struct drm_encoder *encoder = &intel_output->enc;
  3130. struct drm_device *dev = encoder->dev;
  3131. struct drm_crtc *crtc = encoder->crtc;
  3132. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3133. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  3134. if (intel_output->load_detect_temp) {
  3135. encoder->crtc = NULL;
  3136. intel_output->base.encoder = NULL;
  3137. intel_output->load_detect_temp = false;
  3138. crtc->enabled = drm_helper_crtc_in_use(crtc);
  3139. drm_helper_disable_unused_functions(dev);
  3140. }
  3141. /* Switch crtc and output back off if necessary */
  3142. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  3143. if (encoder->crtc == crtc)
  3144. encoder_funcs->dpms(encoder, dpms_mode);
  3145. crtc_funcs->dpms(crtc, dpms_mode);
  3146. }
  3147. }
  3148. /* Returns the clock of the currently programmed mode of the given pipe. */
  3149. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  3150. {
  3151. struct drm_i915_private *dev_priv = dev->dev_private;
  3152. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3153. int pipe = intel_crtc->pipe;
  3154. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  3155. u32 fp;
  3156. intel_clock_t clock;
  3157. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  3158. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  3159. else
  3160. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  3161. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  3162. if (IS_IGD(dev)) {
  3163. clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  3164. clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3165. } else {
  3166. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  3167. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3168. }
  3169. if (IS_I9XX(dev)) {
  3170. if (IS_IGD(dev))
  3171. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
  3172. DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
  3173. else
  3174. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  3175. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3176. switch (dpll & DPLL_MODE_MASK) {
  3177. case DPLLB_MODE_DAC_SERIAL:
  3178. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  3179. 5 : 10;
  3180. break;
  3181. case DPLLB_MODE_LVDS:
  3182. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  3183. 7 : 14;
  3184. break;
  3185. default:
  3186. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  3187. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  3188. return 0;
  3189. }
  3190. /* XXX: Handle the 100Mhz refclk */
  3191. intel_clock(dev, 96000, &clock);
  3192. } else {
  3193. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  3194. if (is_lvds) {
  3195. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  3196. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3197. clock.p2 = 14;
  3198. if ((dpll & PLL_REF_INPUT_MASK) ==
  3199. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  3200. /* XXX: might not be 66MHz */
  3201. intel_clock(dev, 66000, &clock);
  3202. } else
  3203. intel_clock(dev, 48000, &clock);
  3204. } else {
  3205. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  3206. clock.p1 = 2;
  3207. else {
  3208. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  3209. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  3210. }
  3211. if (dpll & PLL_P2_DIVIDE_BY_4)
  3212. clock.p2 = 4;
  3213. else
  3214. clock.p2 = 2;
  3215. intel_clock(dev, 48000, &clock);
  3216. }
  3217. }
  3218. /* XXX: It would be nice to validate the clocks, but we can't reuse
  3219. * i830PllIsValid() because it relies on the xf86_config connector
  3220. * configuration being accurate, which it isn't necessarily.
  3221. */
  3222. return clock.dot;
  3223. }
  3224. /** Returns the currently programmed mode of the given pipe. */
  3225. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  3226. struct drm_crtc *crtc)
  3227. {
  3228. struct drm_i915_private *dev_priv = dev->dev_private;
  3229. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3230. int pipe = intel_crtc->pipe;
  3231. struct drm_display_mode *mode;
  3232. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  3233. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  3234. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  3235. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  3236. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  3237. if (!mode)
  3238. return NULL;
  3239. mode->clock = intel_crtc_clock_get(dev, crtc);
  3240. mode->hdisplay = (htot & 0xffff) + 1;
  3241. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  3242. mode->hsync_start = (hsync & 0xffff) + 1;
  3243. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  3244. mode->vdisplay = (vtot & 0xffff) + 1;
  3245. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  3246. mode->vsync_start = (vsync & 0xffff) + 1;
  3247. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  3248. drm_mode_set_name(mode);
  3249. drm_mode_set_crtcinfo(mode, 0);
  3250. return mode;
  3251. }
  3252. #define GPU_IDLE_TIMEOUT 500 /* ms */
  3253. /* When this timer fires, we've been idle for awhile */
  3254. static void intel_gpu_idle_timer(unsigned long arg)
  3255. {
  3256. struct drm_device *dev = (struct drm_device *)arg;
  3257. drm_i915_private_t *dev_priv = dev->dev_private;
  3258. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  3259. dev_priv->busy = false;
  3260. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3261. }
  3262. void intel_increase_renderclock(struct drm_device *dev, bool schedule)
  3263. {
  3264. drm_i915_private_t *dev_priv = dev->dev_private;
  3265. if (IS_IGDNG(dev))
  3266. return;
  3267. if (!dev_priv->render_reclock_avail) {
  3268. DRM_DEBUG_DRIVER("not reclocking render clock\n");
  3269. return;
  3270. }
  3271. /* Restore render clock frequency to original value */
  3272. if (IS_G4X(dev) || IS_I9XX(dev))
  3273. pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
  3274. else if (IS_I85X(dev))
  3275. pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
  3276. DRM_DEBUG_DRIVER("increasing render clock frequency\n");
  3277. /* Schedule downclock */
  3278. if (schedule)
  3279. mod_timer(&dev_priv->idle_timer, jiffies +
  3280. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  3281. }
  3282. void intel_decrease_renderclock(struct drm_device *dev)
  3283. {
  3284. drm_i915_private_t *dev_priv = dev->dev_private;
  3285. if (IS_IGDNG(dev))
  3286. return;
  3287. if (!dev_priv->render_reclock_avail) {
  3288. DRM_DEBUG_DRIVER("not reclocking render clock\n");
  3289. return;
  3290. }
  3291. if (IS_G4X(dev)) {
  3292. u16 gcfgc;
  3293. /* Adjust render clock... */
  3294. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3295. /* Down to minimum... */
  3296. gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
  3297. gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
  3298. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3299. } else if (IS_I965G(dev)) {
  3300. u16 gcfgc;
  3301. /* Adjust render clock... */
  3302. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3303. /* Down to minimum... */
  3304. gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
  3305. gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
  3306. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3307. } else if (IS_I945G(dev) || IS_I945GM(dev)) {
  3308. u16 gcfgc;
  3309. /* Adjust render clock... */
  3310. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3311. /* Down to minimum... */
  3312. gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
  3313. gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
  3314. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3315. } else if (IS_I915G(dev)) {
  3316. u16 gcfgc;
  3317. /* Adjust render clock... */
  3318. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3319. /* Down to minimum... */
  3320. gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
  3321. gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
  3322. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3323. } else if (IS_I85X(dev)) {
  3324. u16 hpllcc;
  3325. /* Adjust render clock... */
  3326. pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
  3327. /* Up to maximum... */
  3328. hpllcc &= ~GC_CLOCK_CONTROL_MASK;
  3329. hpllcc |= GC_CLOCK_133_200;
  3330. pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
  3331. }
  3332. DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
  3333. }
  3334. /* Note that no increase function is needed for this - increase_renderclock()
  3335. * will also rewrite these bits
  3336. */
  3337. void intel_decrease_displayclock(struct drm_device *dev)
  3338. {
  3339. if (IS_IGDNG(dev))
  3340. return;
  3341. if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
  3342. IS_I915GM(dev)) {
  3343. u16 gcfgc;
  3344. /* Adjust render clock... */
  3345. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3346. /* Down to minimum... */
  3347. gcfgc &= ~0xf0;
  3348. gcfgc |= 0x80;
  3349. pci_write_config_word(dev->pdev, GCFGC, gcfgc);
  3350. }
  3351. }
  3352. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  3353. static void intel_crtc_idle_timer(unsigned long arg)
  3354. {
  3355. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  3356. struct drm_crtc *crtc = &intel_crtc->base;
  3357. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  3358. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  3359. intel_crtc->busy = false;
  3360. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3361. }
  3362. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
  3363. {
  3364. struct drm_device *dev = crtc->dev;
  3365. drm_i915_private_t *dev_priv = dev->dev_private;
  3366. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3367. int pipe = intel_crtc->pipe;
  3368. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3369. int dpll = I915_READ(dpll_reg);
  3370. if (IS_IGDNG(dev))
  3371. return;
  3372. if (!dev_priv->lvds_downclock_avail)
  3373. return;
  3374. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  3375. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  3376. /* Unlock panel regs */
  3377. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3378. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  3379. I915_WRITE(dpll_reg, dpll);
  3380. dpll = I915_READ(dpll_reg);
  3381. intel_wait_for_vblank(dev);
  3382. dpll = I915_READ(dpll_reg);
  3383. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  3384. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  3385. /* ...and lock them again */
  3386. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3387. }
  3388. /* Schedule downclock */
  3389. if (schedule)
  3390. mod_timer(&intel_crtc->idle_timer, jiffies +
  3391. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3392. }
  3393. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  3394. {
  3395. struct drm_device *dev = crtc->dev;
  3396. drm_i915_private_t *dev_priv = dev->dev_private;
  3397. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3398. int pipe = intel_crtc->pipe;
  3399. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3400. int dpll = I915_READ(dpll_reg);
  3401. if (IS_IGDNG(dev))
  3402. return;
  3403. if (!dev_priv->lvds_downclock_avail)
  3404. return;
  3405. /*
  3406. * Since this is called by a timer, we should never get here in
  3407. * the manual case.
  3408. */
  3409. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  3410. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  3411. /* Unlock panel regs */
  3412. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3413. dpll |= DISPLAY_RATE_SELECT_FPA1;
  3414. I915_WRITE(dpll_reg, dpll);
  3415. dpll = I915_READ(dpll_reg);
  3416. intel_wait_for_vblank(dev);
  3417. dpll = I915_READ(dpll_reg);
  3418. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  3419. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  3420. /* ...and lock them again */
  3421. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3422. }
  3423. }
  3424. /**
  3425. * intel_idle_update - adjust clocks for idleness
  3426. * @work: work struct
  3427. *
  3428. * Either the GPU or display (or both) went idle. Check the busy status
  3429. * here and adjust the CRTC and GPU clocks as necessary.
  3430. */
  3431. static void intel_idle_update(struct work_struct *work)
  3432. {
  3433. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  3434. idle_work);
  3435. struct drm_device *dev = dev_priv->dev;
  3436. struct drm_crtc *crtc;
  3437. struct intel_crtc *intel_crtc;
  3438. if (!i915_powersave)
  3439. return;
  3440. mutex_lock(&dev->struct_mutex);
  3441. /* GPU isn't processing, downclock it. */
  3442. if (!dev_priv->busy) {
  3443. intel_decrease_renderclock(dev);
  3444. intel_decrease_displayclock(dev);
  3445. }
  3446. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3447. /* Skip inactive CRTCs */
  3448. if (!crtc->fb)
  3449. continue;
  3450. intel_crtc = to_intel_crtc(crtc);
  3451. if (!intel_crtc->busy)
  3452. intel_decrease_pllclock(crtc);
  3453. }
  3454. mutex_unlock(&dev->struct_mutex);
  3455. }
  3456. /**
  3457. * intel_mark_busy - mark the GPU and possibly the display busy
  3458. * @dev: drm device
  3459. * @obj: object we're operating on
  3460. *
  3461. * Callers can use this function to indicate that the GPU is busy processing
  3462. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  3463. * buffer), we'll also mark the display as busy, so we know to increase its
  3464. * clock frequency.
  3465. */
  3466. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  3467. {
  3468. drm_i915_private_t *dev_priv = dev->dev_private;
  3469. struct drm_crtc *crtc = NULL;
  3470. struct intel_framebuffer *intel_fb;
  3471. struct intel_crtc *intel_crtc;
  3472. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  3473. return;
  3474. dev_priv->busy = true;
  3475. intel_increase_renderclock(dev, true);
  3476. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3477. if (!crtc->fb)
  3478. continue;
  3479. intel_crtc = to_intel_crtc(crtc);
  3480. intel_fb = to_intel_framebuffer(crtc->fb);
  3481. if (intel_fb->obj == obj) {
  3482. if (!intel_crtc->busy) {
  3483. /* Non-busy -> busy, upclock */
  3484. intel_increase_pllclock(crtc, true);
  3485. intel_crtc->busy = true;
  3486. } else {
  3487. /* Busy -> busy, put off timer */
  3488. mod_timer(&intel_crtc->idle_timer, jiffies +
  3489. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3490. }
  3491. }
  3492. }
  3493. }
  3494. static void intel_crtc_destroy(struct drm_crtc *crtc)
  3495. {
  3496. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3497. drm_crtc_cleanup(crtc);
  3498. kfree(intel_crtc);
  3499. }
  3500. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  3501. .dpms = intel_crtc_dpms,
  3502. .mode_fixup = intel_crtc_mode_fixup,
  3503. .mode_set = intel_crtc_mode_set,
  3504. .mode_set_base = intel_pipe_set_base,
  3505. .prepare = intel_crtc_prepare,
  3506. .commit = intel_crtc_commit,
  3507. .load_lut = intel_crtc_load_lut,
  3508. };
  3509. static const struct drm_crtc_funcs intel_crtc_funcs = {
  3510. .cursor_set = intel_crtc_cursor_set,
  3511. .cursor_move = intel_crtc_cursor_move,
  3512. .gamma_set = intel_crtc_gamma_set,
  3513. .set_config = drm_crtc_helper_set_config,
  3514. .destroy = intel_crtc_destroy,
  3515. };
  3516. static void intel_crtc_init(struct drm_device *dev, int pipe)
  3517. {
  3518. struct intel_crtc *intel_crtc;
  3519. int i;
  3520. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  3521. if (intel_crtc == NULL)
  3522. return;
  3523. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  3524. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  3525. intel_crtc->pipe = pipe;
  3526. intel_crtc->plane = pipe;
  3527. for (i = 0; i < 256; i++) {
  3528. intel_crtc->lut_r[i] = i;
  3529. intel_crtc->lut_g[i] = i;
  3530. intel_crtc->lut_b[i] = i;
  3531. }
  3532. /* Swap pipes & planes for FBC on pre-965 */
  3533. intel_crtc->pipe = pipe;
  3534. intel_crtc->plane = pipe;
  3535. if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
  3536. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  3537. intel_crtc->plane = ((pipe == 0) ? 1 : 0);
  3538. }
  3539. intel_crtc->cursor_addr = 0;
  3540. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  3541. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  3542. intel_crtc->busy = false;
  3543. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  3544. (unsigned long)intel_crtc);
  3545. }
  3546. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  3547. struct drm_file *file_priv)
  3548. {
  3549. drm_i915_private_t *dev_priv = dev->dev_private;
  3550. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  3551. struct drm_mode_object *drmmode_obj;
  3552. struct intel_crtc *crtc;
  3553. if (!dev_priv) {
  3554. DRM_ERROR("called with no initialization\n");
  3555. return -EINVAL;
  3556. }
  3557. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  3558. DRM_MODE_OBJECT_CRTC);
  3559. if (!drmmode_obj) {
  3560. DRM_ERROR("no such CRTC id\n");
  3561. return -EINVAL;
  3562. }
  3563. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  3564. pipe_from_crtc_id->pipe = crtc->pipe;
  3565. return 0;
  3566. }
  3567. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  3568. {
  3569. struct drm_crtc *crtc = NULL;
  3570. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3571. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3572. if (intel_crtc->pipe == pipe)
  3573. break;
  3574. }
  3575. return crtc;
  3576. }
  3577. static int intel_connector_clones(struct drm_device *dev, int type_mask)
  3578. {
  3579. int index_mask = 0;
  3580. struct drm_connector *connector;
  3581. int entry = 0;
  3582. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3583. struct intel_output *intel_output = to_intel_output(connector);
  3584. if (type_mask & intel_output->clone_mask)
  3585. index_mask |= (1 << entry);
  3586. entry++;
  3587. }
  3588. return index_mask;
  3589. }
  3590. static void intel_setup_outputs(struct drm_device *dev)
  3591. {
  3592. struct drm_i915_private *dev_priv = dev->dev_private;
  3593. struct drm_connector *connector;
  3594. intel_crt_init(dev);
  3595. /* Set up integrated LVDS */
  3596. if (IS_MOBILE(dev) && !IS_I830(dev))
  3597. intel_lvds_init(dev);
  3598. if (IS_IGDNG(dev)) {
  3599. int found;
  3600. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  3601. intel_dp_init(dev, DP_A);
  3602. if (I915_READ(HDMIB) & PORT_DETECTED) {
  3603. /* check SDVOB */
  3604. /* found = intel_sdvo_init(dev, HDMIB); */
  3605. found = 0;
  3606. if (!found)
  3607. intel_hdmi_init(dev, HDMIB);
  3608. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  3609. intel_dp_init(dev, PCH_DP_B);
  3610. }
  3611. if (I915_READ(HDMIC) & PORT_DETECTED)
  3612. intel_hdmi_init(dev, HDMIC);
  3613. if (I915_READ(HDMID) & PORT_DETECTED)
  3614. intel_hdmi_init(dev, HDMID);
  3615. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  3616. intel_dp_init(dev, PCH_DP_C);
  3617. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  3618. intel_dp_init(dev, PCH_DP_D);
  3619. } else if (IS_I9XX(dev)) {
  3620. bool found = false;
  3621. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  3622. found = intel_sdvo_init(dev, SDVOB);
  3623. if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
  3624. intel_hdmi_init(dev, SDVOB);
  3625. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  3626. intel_dp_init(dev, DP_B);
  3627. }
  3628. /* Before G4X SDVOC doesn't have its own detect register */
  3629. if (I915_READ(SDVOB) & SDVO_DETECTED)
  3630. found = intel_sdvo_init(dev, SDVOC);
  3631. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  3632. if (SUPPORTS_INTEGRATED_HDMI(dev))
  3633. intel_hdmi_init(dev, SDVOC);
  3634. if (SUPPORTS_INTEGRATED_DP(dev))
  3635. intel_dp_init(dev, DP_C);
  3636. }
  3637. if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
  3638. intel_dp_init(dev, DP_D);
  3639. } else
  3640. intel_dvo_init(dev);
  3641. if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
  3642. intel_tv_init(dev);
  3643. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3644. struct intel_output *intel_output = to_intel_output(connector);
  3645. struct drm_encoder *encoder = &intel_output->enc;
  3646. encoder->possible_crtcs = intel_output->crtc_mask;
  3647. encoder->possible_clones = intel_connector_clones(dev,
  3648. intel_output->clone_mask);
  3649. }
  3650. }
  3651. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  3652. {
  3653. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  3654. struct drm_device *dev = fb->dev;
  3655. if (fb->fbdev)
  3656. intelfb_remove(dev, fb);
  3657. drm_framebuffer_cleanup(fb);
  3658. mutex_lock(&dev->struct_mutex);
  3659. drm_gem_object_unreference(intel_fb->obj);
  3660. mutex_unlock(&dev->struct_mutex);
  3661. kfree(intel_fb);
  3662. }
  3663. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  3664. struct drm_file *file_priv,
  3665. unsigned int *handle)
  3666. {
  3667. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  3668. struct drm_gem_object *object = intel_fb->obj;
  3669. return drm_gem_handle_create(file_priv, object, handle);
  3670. }
  3671. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  3672. .destroy = intel_user_framebuffer_destroy,
  3673. .create_handle = intel_user_framebuffer_create_handle,
  3674. };
  3675. int intel_framebuffer_create(struct drm_device *dev,
  3676. struct drm_mode_fb_cmd *mode_cmd,
  3677. struct drm_framebuffer **fb,
  3678. struct drm_gem_object *obj)
  3679. {
  3680. struct intel_framebuffer *intel_fb;
  3681. int ret;
  3682. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  3683. if (!intel_fb)
  3684. return -ENOMEM;
  3685. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  3686. if (ret) {
  3687. DRM_ERROR("framebuffer init failed %d\n", ret);
  3688. return ret;
  3689. }
  3690. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  3691. intel_fb->obj = obj;
  3692. *fb = &intel_fb->base;
  3693. return 0;
  3694. }
  3695. static struct drm_framebuffer *
  3696. intel_user_framebuffer_create(struct drm_device *dev,
  3697. struct drm_file *filp,
  3698. struct drm_mode_fb_cmd *mode_cmd)
  3699. {
  3700. struct drm_gem_object *obj;
  3701. struct drm_framebuffer *fb;
  3702. int ret;
  3703. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  3704. if (!obj)
  3705. return NULL;
  3706. ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
  3707. if (ret) {
  3708. mutex_lock(&dev->struct_mutex);
  3709. drm_gem_object_unreference(obj);
  3710. mutex_unlock(&dev->struct_mutex);
  3711. return NULL;
  3712. }
  3713. return fb;
  3714. }
  3715. static const struct drm_mode_config_funcs intel_mode_funcs = {
  3716. .fb_create = intel_user_framebuffer_create,
  3717. .fb_changed = intelfb_probe,
  3718. };
  3719. void intel_init_clock_gating(struct drm_device *dev)
  3720. {
  3721. struct drm_i915_private *dev_priv = dev->dev_private;
  3722. /*
  3723. * Disable clock gating reported to work incorrectly according to the
  3724. * specs, but enable as much else as we can.
  3725. */
  3726. if (IS_IGDNG(dev)) {
  3727. return;
  3728. } else if (IS_G4X(dev)) {
  3729. uint32_t dspclk_gate;
  3730. I915_WRITE(RENCLK_GATE_D1, 0);
  3731. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  3732. GS_UNIT_CLOCK_GATE_DISABLE |
  3733. CL_UNIT_CLOCK_GATE_DISABLE);
  3734. I915_WRITE(RAMCLK_GATE_D, 0);
  3735. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  3736. OVRUNIT_CLOCK_GATE_DISABLE |
  3737. OVCUNIT_CLOCK_GATE_DISABLE;
  3738. if (IS_GM45(dev))
  3739. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  3740. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  3741. } else if (IS_I965GM(dev)) {
  3742. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  3743. I915_WRITE(RENCLK_GATE_D2, 0);
  3744. I915_WRITE(DSPCLK_GATE_D, 0);
  3745. I915_WRITE(RAMCLK_GATE_D, 0);
  3746. I915_WRITE16(DEUC, 0);
  3747. } else if (IS_I965G(dev)) {
  3748. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  3749. I965_RCC_CLOCK_GATE_DISABLE |
  3750. I965_RCPB_CLOCK_GATE_DISABLE |
  3751. I965_ISC_CLOCK_GATE_DISABLE |
  3752. I965_FBC_CLOCK_GATE_DISABLE);
  3753. I915_WRITE(RENCLK_GATE_D2, 0);
  3754. } else if (IS_I9XX(dev)) {
  3755. u32 dstate = I915_READ(D_STATE);
  3756. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  3757. DSTATE_DOT_CLOCK_GATING;
  3758. I915_WRITE(D_STATE, dstate);
  3759. } else if (IS_I85X(dev) || IS_I865G(dev)) {
  3760. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  3761. } else if (IS_I830(dev)) {
  3762. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  3763. }
  3764. /*
  3765. * GPU can automatically power down the render unit if given a page
  3766. * to save state.
  3767. */
  3768. if (I915_HAS_RC6(dev)) {
  3769. struct drm_gem_object *pwrctx;
  3770. struct drm_i915_gem_object *obj_priv;
  3771. int ret;
  3772. pwrctx = drm_gem_object_alloc(dev, 4096);
  3773. if (!pwrctx) {
  3774. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  3775. goto out;
  3776. }
  3777. ret = i915_gem_object_pin(pwrctx, 4096);
  3778. if (ret) {
  3779. DRM_ERROR("failed to pin power context: %d\n", ret);
  3780. drm_gem_object_unreference(pwrctx);
  3781. goto out;
  3782. }
  3783. i915_gem_object_set_to_gtt_domain(pwrctx, 1);
  3784. obj_priv = pwrctx->driver_private;
  3785. I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
  3786. I915_WRITE(MCHBAR_RENDER_STANDBY,
  3787. I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
  3788. dev_priv->pwrctx = pwrctx;
  3789. }
  3790. out:
  3791. return;
  3792. }
  3793. /* Set up chip specific display functions */
  3794. static void intel_init_display(struct drm_device *dev)
  3795. {
  3796. struct drm_i915_private *dev_priv = dev->dev_private;
  3797. /* We always want a DPMS function */
  3798. if (IS_IGDNG(dev))
  3799. dev_priv->display.dpms = igdng_crtc_dpms;
  3800. else
  3801. dev_priv->display.dpms = i9xx_crtc_dpms;
  3802. /* Only mobile has FBC, leave pointers NULL for other chips */
  3803. if (IS_MOBILE(dev)) {
  3804. if (IS_GM45(dev)) {
  3805. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  3806. dev_priv->display.enable_fbc = g4x_enable_fbc;
  3807. dev_priv->display.disable_fbc = g4x_disable_fbc;
  3808. } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
  3809. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  3810. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  3811. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  3812. }
  3813. /* 855GM needs testing */
  3814. }
  3815. /* Returns the core display clock speed */
  3816. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_IGDGM(dev)))
  3817. dev_priv->display.get_display_clock_speed =
  3818. i945_get_display_clock_speed;
  3819. else if (IS_I915G(dev))
  3820. dev_priv->display.get_display_clock_speed =
  3821. i915_get_display_clock_speed;
  3822. else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
  3823. dev_priv->display.get_display_clock_speed =
  3824. i9xx_misc_get_display_clock_speed;
  3825. else if (IS_I915GM(dev))
  3826. dev_priv->display.get_display_clock_speed =
  3827. i915gm_get_display_clock_speed;
  3828. else if (IS_I865G(dev))
  3829. dev_priv->display.get_display_clock_speed =
  3830. i865_get_display_clock_speed;
  3831. else if (IS_I85X(dev))
  3832. dev_priv->display.get_display_clock_speed =
  3833. i855_get_display_clock_speed;
  3834. else /* 852, 830 */
  3835. dev_priv->display.get_display_clock_speed =
  3836. i830_get_display_clock_speed;
  3837. /* For FIFO watermark updates */
  3838. if (IS_IGDNG(dev))
  3839. dev_priv->display.update_wm = NULL;
  3840. else if (IS_G4X(dev))
  3841. dev_priv->display.update_wm = g4x_update_wm;
  3842. else if (IS_I965G(dev))
  3843. dev_priv->display.update_wm = i965_update_wm;
  3844. else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
  3845. dev_priv->display.update_wm = i9xx_update_wm;
  3846. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  3847. } else {
  3848. if (IS_I85X(dev))
  3849. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  3850. else if (IS_845G(dev))
  3851. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  3852. else
  3853. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  3854. dev_priv->display.update_wm = i830_update_wm;
  3855. }
  3856. }
  3857. void intel_modeset_init(struct drm_device *dev)
  3858. {
  3859. struct drm_i915_private *dev_priv = dev->dev_private;
  3860. int num_pipe;
  3861. int i;
  3862. drm_mode_config_init(dev);
  3863. dev->mode_config.min_width = 0;
  3864. dev->mode_config.min_height = 0;
  3865. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  3866. intel_init_display(dev);
  3867. if (IS_I965G(dev)) {
  3868. dev->mode_config.max_width = 8192;
  3869. dev->mode_config.max_height = 8192;
  3870. } else if (IS_I9XX(dev)) {
  3871. dev->mode_config.max_width = 4096;
  3872. dev->mode_config.max_height = 4096;
  3873. } else {
  3874. dev->mode_config.max_width = 2048;
  3875. dev->mode_config.max_height = 2048;
  3876. }
  3877. /* set memory base */
  3878. if (IS_I9XX(dev))
  3879. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  3880. else
  3881. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  3882. if (IS_MOBILE(dev) || IS_I9XX(dev))
  3883. num_pipe = 2;
  3884. else
  3885. num_pipe = 1;
  3886. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  3887. num_pipe, num_pipe > 1 ? "s" : "");
  3888. if (IS_I85X(dev))
  3889. pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
  3890. else if (IS_I9XX(dev) || IS_G4X(dev))
  3891. pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
  3892. for (i = 0; i < num_pipe; i++) {
  3893. intel_crtc_init(dev, i);
  3894. }
  3895. intel_setup_outputs(dev);
  3896. intel_init_clock_gating(dev);
  3897. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  3898. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  3899. (unsigned long)dev);
  3900. intel_setup_overlay(dev);
  3901. }
  3902. void intel_modeset_cleanup(struct drm_device *dev)
  3903. {
  3904. struct drm_i915_private *dev_priv = dev->dev_private;
  3905. struct drm_crtc *crtc;
  3906. struct intel_crtc *intel_crtc;
  3907. mutex_lock(&dev->struct_mutex);
  3908. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3909. /* Skip inactive CRTCs */
  3910. if (!crtc->fb)
  3911. continue;
  3912. intel_crtc = to_intel_crtc(crtc);
  3913. intel_increase_pllclock(crtc, false);
  3914. del_timer_sync(&intel_crtc->idle_timer);
  3915. }
  3916. intel_increase_renderclock(dev, false);
  3917. del_timer_sync(&dev_priv->idle_timer);
  3918. mutex_unlock(&dev->struct_mutex);
  3919. if (dev_priv->display.disable_fbc)
  3920. dev_priv->display.disable_fbc(dev);
  3921. if (dev_priv->pwrctx) {
  3922. i915_gem_object_unpin(dev_priv->pwrctx);
  3923. drm_gem_object_unreference(dev_priv->pwrctx);
  3924. }
  3925. drm_mode_config_cleanup(dev);
  3926. }
  3927. /* current intel driver doesn't take advantage of encoders
  3928. always give back the encoder for the connector
  3929. */
  3930. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  3931. {
  3932. struct intel_output *intel_output = to_intel_output(connector);
  3933. return &intel_output->enc;
  3934. }
  3935. /*
  3936. * set vga decode state - true == enable VGA decode
  3937. */
  3938. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  3939. {
  3940. struct drm_i915_private *dev_priv = dev->dev_private;
  3941. u16 gmch_ctrl;
  3942. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  3943. if (state)
  3944. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  3945. else
  3946. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  3947. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  3948. return 0;
  3949. }