s5p_mfc.c 37 KB

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  1. /*
  2. * Samsung S5P Multi Format Codec v 5.1
  3. *
  4. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  5. * Kamil Debski, <k.debski@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/sched.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <media/v4l2-event.h>
  22. #include <linux/workqueue.h>
  23. #include <media/videobuf2-core.h>
  24. #include "s5p_mfc_common.h"
  25. #include "s5p_mfc_ctrl.h"
  26. #include "s5p_mfc_debug.h"
  27. #include "s5p_mfc_dec.h"
  28. #include "s5p_mfc_enc.h"
  29. #include "s5p_mfc_intr.h"
  30. #include "s5p_mfc_opr.h"
  31. #include "s5p_mfc_cmd.h"
  32. #include "s5p_mfc_pm.h"
  33. #define S5P_MFC_NAME "s5p-mfc"
  34. #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
  35. #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
  36. int debug;
  37. module_param(debug, int, S_IRUGO | S_IWUSR);
  38. MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
  39. /* Helper functions for interrupt processing */
  40. /* Remove from hw execution round robin */
  41. void clear_work_bit(struct s5p_mfc_ctx *ctx)
  42. {
  43. struct s5p_mfc_dev *dev = ctx->dev;
  44. spin_lock(&dev->condlock);
  45. __clear_bit(ctx->num, &dev->ctx_work_bits);
  46. spin_unlock(&dev->condlock);
  47. }
  48. /* Add to hw execution round robin */
  49. void set_work_bit(struct s5p_mfc_ctx *ctx)
  50. {
  51. struct s5p_mfc_dev *dev = ctx->dev;
  52. spin_lock(&dev->condlock);
  53. __set_bit(ctx->num, &dev->ctx_work_bits);
  54. spin_unlock(&dev->condlock);
  55. }
  56. /* Remove from hw execution round robin */
  57. void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  58. {
  59. struct s5p_mfc_dev *dev = ctx->dev;
  60. unsigned long flags;
  61. spin_lock_irqsave(&dev->condlock, flags);
  62. __clear_bit(ctx->num, &dev->ctx_work_bits);
  63. spin_unlock_irqrestore(&dev->condlock, flags);
  64. }
  65. /* Add to hw execution round robin */
  66. void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
  67. {
  68. struct s5p_mfc_dev *dev = ctx->dev;
  69. unsigned long flags;
  70. spin_lock_irqsave(&dev->condlock, flags);
  71. __set_bit(ctx->num, &dev->ctx_work_bits);
  72. spin_unlock_irqrestore(&dev->condlock, flags);
  73. }
  74. /* Wake up context wait_queue */
  75. static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
  76. unsigned int err)
  77. {
  78. ctx->int_cond = 1;
  79. ctx->int_type = reason;
  80. ctx->int_err = err;
  81. wake_up(&ctx->queue);
  82. }
  83. /* Wake up device wait_queue */
  84. static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
  85. unsigned int err)
  86. {
  87. dev->int_cond = 1;
  88. dev->int_type = reason;
  89. dev->int_err = err;
  90. wake_up(&dev->queue);
  91. }
  92. static void s5p_mfc_watchdog(unsigned long arg)
  93. {
  94. struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
  95. if (test_bit(0, &dev->hw_lock))
  96. atomic_inc(&dev->watchdog_cnt);
  97. if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
  98. /* This means that hw is busy and no interrupts were
  99. * generated by hw for the Nth time of running this
  100. * watchdog timer. This usually means a serious hw
  101. * error. Now it is time to kill all instances and
  102. * reset the MFC. */
  103. mfc_err("Time out during waiting for HW\n");
  104. queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
  105. }
  106. dev->watchdog_timer.expires = jiffies +
  107. msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
  108. add_timer(&dev->watchdog_timer);
  109. }
  110. static void s5p_mfc_watchdog_worker(struct work_struct *work)
  111. {
  112. struct s5p_mfc_dev *dev;
  113. struct s5p_mfc_ctx *ctx;
  114. unsigned long flags;
  115. int mutex_locked;
  116. int i, ret;
  117. dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
  118. mfc_err("Driver timeout error handling\n");
  119. /* Lock the mutex that protects open and release.
  120. * This is necessary as they may load and unload firmware. */
  121. mutex_locked = mutex_trylock(&dev->mfc_mutex);
  122. if (!mutex_locked)
  123. mfc_err("Error: some instance may be closing/opening\n");
  124. spin_lock_irqsave(&dev->irqlock, flags);
  125. s5p_mfc_clock_off();
  126. for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
  127. ctx = dev->ctx[i];
  128. if (!ctx)
  129. continue;
  130. ctx->state = MFCINST_ERROR;
  131. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
  132. &ctx->vq_dst);
  133. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
  134. &ctx->vq_src);
  135. clear_work_bit(ctx);
  136. wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
  137. }
  138. clear_bit(0, &dev->hw_lock);
  139. spin_unlock_irqrestore(&dev->irqlock, flags);
  140. /* Double check if there is at least one instance running.
  141. * If no instance is in memory than no firmware should be present */
  142. if (dev->num_inst > 0) {
  143. ret = s5p_mfc_reload_firmware(dev);
  144. if (ret) {
  145. mfc_err("Failed to reload FW\n");
  146. goto unlock;
  147. }
  148. s5p_mfc_clock_on();
  149. ret = s5p_mfc_init_hw(dev);
  150. if (ret)
  151. mfc_err("Failed to reinit FW\n");
  152. }
  153. unlock:
  154. if (mutex_locked)
  155. mutex_unlock(&dev->mfc_mutex);
  156. }
  157. static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
  158. {
  159. struct video_device *vdev = video_devdata(file);
  160. if (!vdev) {
  161. mfc_err("failed to get video_device");
  162. return MFCNODE_INVALID;
  163. }
  164. if (vdev->index == 0)
  165. return MFCNODE_DECODER;
  166. else if (vdev->index == 1)
  167. return MFCNODE_ENCODER;
  168. return MFCNODE_INVALID;
  169. }
  170. static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
  171. {
  172. mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
  173. mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
  174. mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
  175. }
  176. static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
  177. {
  178. struct s5p_mfc_buf *dst_buf;
  179. struct s5p_mfc_dev *dev = ctx->dev;
  180. ctx->state = MFCINST_FINISHED;
  181. ctx->sequence++;
  182. while (!list_empty(&ctx->dst_queue)) {
  183. dst_buf = list_entry(ctx->dst_queue.next,
  184. struct s5p_mfc_buf, list);
  185. mfc_debug(2, "Cleaning up buffer: %d\n",
  186. dst_buf->b->v4l2_buf.index);
  187. vb2_set_plane_payload(dst_buf->b, 0, 0);
  188. vb2_set_plane_payload(dst_buf->b, 1, 0);
  189. list_del(&dst_buf->list);
  190. ctx->dst_queue_cnt--;
  191. dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
  192. if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
  193. s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
  194. dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
  195. else
  196. dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
  197. ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
  198. vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
  199. }
  200. }
  201. static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
  202. {
  203. struct s5p_mfc_dev *dev = ctx->dev;
  204. struct s5p_mfc_buf *dst_buf, *src_buf;
  205. size_t dec_y_addr;
  206. unsigned int frame_type;
  207. dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
  208. frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
  209. /* Copy timestamp / timecode from decoded src to dst and set
  210. appropraite flags */
  211. src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
  212. list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
  213. if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
  214. memcpy(&dst_buf->b->v4l2_buf.timecode,
  215. &src_buf->b->v4l2_buf.timecode,
  216. sizeof(struct v4l2_timecode));
  217. memcpy(&dst_buf->b->v4l2_buf.timestamp,
  218. &src_buf->b->v4l2_buf.timestamp,
  219. sizeof(struct timeval));
  220. switch (frame_type) {
  221. case S5P_FIMV_DECODE_FRAME_I_FRAME:
  222. dst_buf->b->v4l2_buf.flags |=
  223. V4L2_BUF_FLAG_KEYFRAME;
  224. break;
  225. case S5P_FIMV_DECODE_FRAME_P_FRAME:
  226. dst_buf->b->v4l2_buf.flags |=
  227. V4L2_BUF_FLAG_PFRAME;
  228. break;
  229. case S5P_FIMV_DECODE_FRAME_B_FRAME:
  230. dst_buf->b->v4l2_buf.flags |=
  231. V4L2_BUF_FLAG_BFRAME;
  232. break;
  233. }
  234. break;
  235. }
  236. }
  237. }
  238. static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
  239. {
  240. struct s5p_mfc_dev *dev = ctx->dev;
  241. struct s5p_mfc_buf *dst_buf;
  242. size_t dspl_y_addr;
  243. unsigned int frame_type;
  244. unsigned int index;
  245. dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
  246. frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
  247. /* If frame is same as previous then skip and do not dequeue */
  248. if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
  249. if (!ctx->after_packed_pb)
  250. ctx->sequence++;
  251. ctx->after_packed_pb = 0;
  252. return;
  253. }
  254. ctx->sequence++;
  255. /* The MFC returns address of the buffer, now we have to
  256. * check which videobuf does it correspond to */
  257. list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
  258. /* Check if this is the buffer we're looking for */
  259. if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
  260. list_del(&dst_buf->list);
  261. ctx->dst_queue_cnt--;
  262. dst_buf->b->v4l2_buf.sequence = ctx->sequence;
  263. if (s5p_mfc_hw_call(dev->mfc_ops,
  264. get_pic_type_top, ctx) ==
  265. s5p_mfc_hw_call(dev->mfc_ops,
  266. get_pic_type_bot, ctx))
  267. dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
  268. else
  269. dst_buf->b->v4l2_buf.field =
  270. V4L2_FIELD_INTERLACED;
  271. vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
  272. vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
  273. clear_bit(dst_buf->b->v4l2_buf.index,
  274. &ctx->dec_dst_flag);
  275. vb2_buffer_done(dst_buf->b,
  276. err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  277. index = dst_buf->b->v4l2_buf.index;
  278. break;
  279. }
  280. }
  281. }
  282. /* Handle frame decoding interrupt */
  283. static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
  284. unsigned int reason, unsigned int err)
  285. {
  286. struct s5p_mfc_dev *dev = ctx->dev;
  287. unsigned int dst_frame_status;
  288. struct s5p_mfc_buf *src_buf;
  289. unsigned long flags;
  290. unsigned int res_change;
  291. unsigned int index;
  292. dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
  293. & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
  294. res_change = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
  295. & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK;
  296. mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
  297. if (ctx->state == MFCINST_RES_CHANGE_INIT)
  298. ctx->state = MFCINST_RES_CHANGE_FLUSH;
  299. if (res_change) {
  300. ctx->state = MFCINST_RES_CHANGE_INIT;
  301. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  302. wake_up_ctx(ctx, reason, err);
  303. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  304. BUG();
  305. s5p_mfc_clock_off();
  306. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  307. return;
  308. }
  309. if (ctx->dpb_flush_flag)
  310. ctx->dpb_flush_flag = 0;
  311. spin_lock_irqsave(&dev->irqlock, flags);
  312. /* All frames remaining in the buffer have been extracted */
  313. if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
  314. if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
  315. s5p_mfc_handle_frame_all_extracted(ctx);
  316. ctx->state = MFCINST_RES_CHANGE_END;
  317. goto leave_handle_frame;
  318. } else {
  319. s5p_mfc_handle_frame_all_extracted(ctx);
  320. }
  321. }
  322. if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
  323. dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
  324. s5p_mfc_handle_frame_copy_time(ctx);
  325. /* A frame has been decoded and is in the buffer */
  326. if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
  327. dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
  328. s5p_mfc_handle_frame_new(ctx, err);
  329. } else {
  330. mfc_debug(2, "No frame decode\n");
  331. }
  332. /* Mark source buffer as complete */
  333. if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
  334. && !list_empty(&ctx->src_queue)) {
  335. src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
  336. list);
  337. ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
  338. get_consumed_stream, dev);
  339. if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
  340. s5p_mfc_hw_call(dev->mfc_ops,
  341. get_dec_frame_type, dev) ==
  342. S5P_FIMV_DECODE_FRAME_P_FRAME
  343. && ctx->consumed_stream + STUFF_BYTE <
  344. src_buf->b->v4l2_planes[0].bytesused) {
  345. /* Run MFC again on the same buffer */
  346. mfc_debug(2, "Running again the same buffer\n");
  347. ctx->after_packed_pb = 1;
  348. } else {
  349. index = src_buf->b->v4l2_buf.index;
  350. mfc_debug(2, "MFC needs next buffer\n");
  351. ctx->consumed_stream = 0;
  352. list_del(&src_buf->list);
  353. ctx->src_queue_cnt--;
  354. if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
  355. vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
  356. else
  357. vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
  358. }
  359. }
  360. leave_handle_frame:
  361. spin_unlock_irqrestore(&dev->irqlock, flags);
  362. if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
  363. || ctx->dst_queue_cnt < ctx->dpb_count)
  364. clear_work_bit(ctx);
  365. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  366. wake_up_ctx(ctx, reason, err);
  367. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  368. BUG();
  369. s5p_mfc_clock_off();
  370. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  371. }
  372. /* Error handling for interrupt */
  373. static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx,
  374. unsigned int reason, unsigned int err)
  375. {
  376. struct s5p_mfc_dev *dev;
  377. unsigned long flags;
  378. /* If no context is available then all necessary
  379. * processing has been done. */
  380. if (ctx == NULL)
  381. return;
  382. dev = ctx->dev;
  383. mfc_err("Interrupt Error: %08x\n", err);
  384. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  385. wake_up_dev(dev, reason, err);
  386. /* Error recovery is dependent on the state of context */
  387. switch (ctx->state) {
  388. case MFCINST_INIT:
  389. /* This error had to happen while acquireing instance */
  390. case MFCINST_GOT_INST:
  391. /* This error had to happen while parsing the header */
  392. case MFCINST_HEAD_PARSED:
  393. /* This error had to happen while setting dst buffers */
  394. case MFCINST_RETURN_INST:
  395. /* This error had to happen while releasing instance */
  396. clear_work_bit(ctx);
  397. wake_up_ctx(ctx, reason, err);
  398. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  399. BUG();
  400. s5p_mfc_clock_off();
  401. ctx->state = MFCINST_ERROR;
  402. break;
  403. case MFCINST_FINISHING:
  404. case MFCINST_FINISHED:
  405. case MFCINST_RUNNING:
  406. /* It is higly probable that an error occured
  407. * while decoding a frame */
  408. clear_work_bit(ctx);
  409. ctx->state = MFCINST_ERROR;
  410. /* Mark all dst buffers as having an error */
  411. spin_lock_irqsave(&dev->irqlock, flags);
  412. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
  413. &ctx->vq_dst);
  414. /* Mark all src buffers as having an error */
  415. s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
  416. &ctx->vq_src);
  417. spin_unlock_irqrestore(&dev->irqlock, flags);
  418. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  419. BUG();
  420. s5p_mfc_clock_off();
  421. break;
  422. default:
  423. mfc_err("Encountered an error interrupt which had not been handled\n");
  424. break;
  425. }
  426. return;
  427. }
  428. /* Header parsing interrupt handling */
  429. static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
  430. unsigned int reason, unsigned int err)
  431. {
  432. struct s5p_mfc_dev *dev;
  433. unsigned int guard_width, guard_height;
  434. if (ctx == NULL)
  435. return;
  436. dev = ctx->dev;
  437. if (ctx->c_ops->post_seq_start) {
  438. if (ctx->c_ops->post_seq_start(ctx))
  439. mfc_err("post_seq_start() failed\n");
  440. } else {
  441. ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
  442. dev);
  443. ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
  444. dev);
  445. ctx->buf_width = ALIGN(ctx->img_width,
  446. S5P_FIMV_NV12MT_HALIGN);
  447. ctx->buf_height = ALIGN(ctx->img_height,
  448. S5P_FIMV_NV12MT_VALIGN);
  449. mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, "
  450. "buffer dimensions: %dx%d\n", ctx->img_width,
  451. ctx->img_height, ctx->buf_width,
  452. ctx->buf_height);
  453. if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) {
  454. ctx->luma_size = ALIGN(ctx->buf_width *
  455. ctx->buf_height, S5P_FIMV_DEC_BUF_ALIGN);
  456. ctx->chroma_size = ALIGN(ctx->buf_width *
  457. ALIGN((ctx->img_height >> 1),
  458. S5P_FIMV_NV12MT_VALIGN),
  459. S5P_FIMV_DEC_BUF_ALIGN);
  460. ctx->mv_size = ALIGN(ctx->buf_width *
  461. ALIGN((ctx->buf_height >> 2),
  462. S5P_FIMV_NV12MT_VALIGN),
  463. S5P_FIMV_DEC_BUF_ALIGN);
  464. } else {
  465. guard_width = ALIGN(ctx->img_width + 24,
  466. S5P_FIMV_NV12MT_HALIGN);
  467. guard_height = ALIGN(ctx->img_height + 16,
  468. S5P_FIMV_NV12MT_VALIGN);
  469. ctx->luma_size = ALIGN(guard_width *
  470. guard_height, S5P_FIMV_DEC_BUF_ALIGN);
  471. guard_width = ALIGN(ctx->img_width + 16,
  472. S5P_FIMV_NV12MT_HALIGN);
  473. guard_height = ALIGN((ctx->img_height >> 1) + 4,
  474. S5P_FIMV_NV12MT_VALIGN);
  475. ctx->chroma_size = ALIGN(guard_width *
  476. guard_height, S5P_FIMV_DEC_BUF_ALIGN);
  477. ctx->mv_size = 0;
  478. }
  479. ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
  480. dev);
  481. if (ctx->img_width == 0 || ctx->img_height == 0)
  482. ctx->state = MFCINST_ERROR;
  483. else
  484. ctx->state = MFCINST_HEAD_PARSED;
  485. }
  486. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  487. clear_work_bit(ctx);
  488. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  489. BUG();
  490. s5p_mfc_clock_off();
  491. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  492. wake_up_ctx(ctx, reason, err);
  493. }
  494. /* Header parsing interrupt handling */
  495. static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
  496. unsigned int reason, unsigned int err)
  497. {
  498. struct s5p_mfc_buf *src_buf;
  499. struct s5p_mfc_dev *dev;
  500. unsigned long flags;
  501. if (ctx == NULL)
  502. return;
  503. dev = ctx->dev;
  504. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  505. ctx->int_type = reason;
  506. ctx->int_err = err;
  507. ctx->int_cond = 1;
  508. clear_work_bit(ctx);
  509. if (err == 0) {
  510. ctx->state = MFCINST_RUNNING;
  511. if (!ctx->dpb_flush_flag) {
  512. spin_lock_irqsave(&dev->irqlock, flags);
  513. if (!list_empty(&ctx->src_queue)) {
  514. src_buf = list_entry(ctx->src_queue.next,
  515. struct s5p_mfc_buf, list);
  516. list_del(&src_buf->list);
  517. ctx->src_queue_cnt--;
  518. vb2_buffer_done(src_buf->b,
  519. VB2_BUF_STATE_DONE);
  520. }
  521. spin_unlock_irqrestore(&dev->irqlock, flags);
  522. } else {
  523. ctx->dpb_flush_flag = 0;
  524. }
  525. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  526. BUG();
  527. s5p_mfc_clock_off();
  528. wake_up(&ctx->queue);
  529. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  530. } else {
  531. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  532. BUG();
  533. s5p_mfc_clock_off();
  534. wake_up(&ctx->queue);
  535. }
  536. }
  537. static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
  538. unsigned int reason, unsigned int err)
  539. {
  540. struct s5p_mfc_dev *dev = ctx->dev;
  541. struct s5p_mfc_buf *mb_entry;
  542. mfc_debug(2, "Stream completed");
  543. s5p_mfc_clear_int_flags(dev);
  544. ctx->int_type = reason;
  545. ctx->int_err = err;
  546. ctx->state = MFCINST_FINISHED;
  547. spin_lock(&dev->irqlock);
  548. if (!list_empty(&ctx->dst_queue)) {
  549. mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
  550. list);
  551. list_del(&mb_entry->list);
  552. ctx->dst_queue_cnt--;
  553. vb2_set_plane_payload(mb_entry->b, 0, 0);
  554. vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
  555. }
  556. spin_unlock(&dev->irqlock);
  557. clear_work_bit(ctx);
  558. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  559. WARN_ON(1);
  560. s5p_mfc_clock_off();
  561. wake_up(&ctx->queue);
  562. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  563. }
  564. /* Interrupt processing */
  565. static irqreturn_t s5p_mfc_irq(int irq, void *priv)
  566. {
  567. struct s5p_mfc_dev *dev = priv;
  568. struct s5p_mfc_ctx *ctx;
  569. unsigned int reason;
  570. unsigned int err;
  571. mfc_debug_enter();
  572. /* Reset the timeout watchdog */
  573. atomic_set(&dev->watchdog_cnt, 0);
  574. ctx = dev->ctx[dev->curr_ctx];
  575. /* Get the reason of interrupt and the error code */
  576. reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
  577. err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
  578. mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
  579. switch (reason) {
  580. case S5P_MFC_R2H_CMD_ERR_RET:
  581. /* An error has occured */
  582. if (ctx->state == MFCINST_RUNNING &&
  583. s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
  584. dev->warn_start)
  585. s5p_mfc_handle_frame(ctx, reason, err);
  586. else
  587. s5p_mfc_handle_error(ctx, reason, err);
  588. clear_bit(0, &dev->enter_suspend);
  589. break;
  590. case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
  591. case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
  592. case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
  593. if (ctx->c_ops->post_frame_start) {
  594. if (ctx->c_ops->post_frame_start(ctx))
  595. mfc_err("post_frame_start() failed\n");
  596. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  597. wake_up_ctx(ctx, reason, err);
  598. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  599. BUG();
  600. s5p_mfc_clock_off();
  601. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  602. } else {
  603. s5p_mfc_handle_frame(ctx, reason, err);
  604. }
  605. break;
  606. case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
  607. s5p_mfc_handle_seq_done(ctx, reason, err);
  608. break;
  609. case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
  610. ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
  611. ctx->state = MFCINST_GOT_INST;
  612. clear_work_bit(ctx);
  613. wake_up(&ctx->queue);
  614. goto irq_cleanup_hw;
  615. case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
  616. clear_work_bit(ctx);
  617. ctx->state = MFCINST_FREE;
  618. wake_up(&ctx->queue);
  619. goto irq_cleanup_hw;
  620. case S5P_MFC_R2H_CMD_SYS_INIT_RET:
  621. case S5P_MFC_R2H_CMD_FW_STATUS_RET:
  622. case S5P_MFC_R2H_CMD_SLEEP_RET:
  623. case S5P_MFC_R2H_CMD_WAKEUP_RET:
  624. if (ctx)
  625. clear_work_bit(ctx);
  626. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  627. wake_up_dev(dev, reason, err);
  628. clear_bit(0, &dev->hw_lock);
  629. clear_bit(0, &dev->enter_suspend);
  630. break;
  631. case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
  632. s5p_mfc_handle_init_buffers(ctx, reason, err);
  633. break;
  634. case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
  635. s5p_mfc_handle_stream_complete(ctx, reason, err);
  636. break;
  637. default:
  638. mfc_debug(2, "Unknown int reason\n");
  639. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  640. }
  641. mfc_debug_leave();
  642. return IRQ_HANDLED;
  643. irq_cleanup_hw:
  644. s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
  645. ctx->int_type = reason;
  646. ctx->int_err = err;
  647. ctx->int_cond = 1;
  648. if (test_and_clear_bit(0, &dev->hw_lock) == 0)
  649. mfc_err("Failed to unlock hw\n");
  650. s5p_mfc_clock_off();
  651. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  652. mfc_debug(2, "Exit via irq_cleanup_hw\n");
  653. return IRQ_HANDLED;
  654. }
  655. /* Open an MFC node */
  656. static int s5p_mfc_open(struct file *file)
  657. {
  658. struct s5p_mfc_dev *dev = video_drvdata(file);
  659. struct s5p_mfc_ctx *ctx = NULL;
  660. struct vb2_queue *q;
  661. int ret = 0;
  662. mfc_debug_enter();
  663. if (mutex_lock_interruptible(&dev->mfc_mutex))
  664. return -ERESTARTSYS;
  665. dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
  666. /* Allocate memory for context */
  667. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  668. if (!ctx) {
  669. mfc_err("Not enough memory\n");
  670. ret = -ENOMEM;
  671. goto err_alloc;
  672. }
  673. v4l2_fh_init(&ctx->fh, video_devdata(file));
  674. file->private_data = &ctx->fh;
  675. v4l2_fh_add(&ctx->fh);
  676. ctx->dev = dev;
  677. INIT_LIST_HEAD(&ctx->src_queue);
  678. INIT_LIST_HEAD(&ctx->dst_queue);
  679. ctx->src_queue_cnt = 0;
  680. ctx->dst_queue_cnt = 0;
  681. /* Get context number */
  682. ctx->num = 0;
  683. while (dev->ctx[ctx->num]) {
  684. ctx->num++;
  685. if (ctx->num >= MFC_NUM_CONTEXTS) {
  686. mfc_err("Too many open contexts\n");
  687. ret = -EBUSY;
  688. goto err_no_ctx;
  689. }
  690. }
  691. /* Mark context as idle */
  692. clear_work_bit_irqsave(ctx);
  693. dev->ctx[ctx->num] = ctx;
  694. if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
  695. ctx->type = MFCINST_DECODER;
  696. ctx->c_ops = get_dec_codec_ops();
  697. s5p_mfc_dec_init(ctx);
  698. /* Setup ctrl handler */
  699. ret = s5p_mfc_dec_ctrls_setup(ctx);
  700. if (ret) {
  701. mfc_err("Failed to setup mfc controls\n");
  702. goto err_ctrls_setup;
  703. }
  704. } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
  705. ctx->type = MFCINST_ENCODER;
  706. ctx->c_ops = get_enc_codec_ops();
  707. /* only for encoder */
  708. INIT_LIST_HEAD(&ctx->ref_queue);
  709. ctx->ref_queue_cnt = 0;
  710. s5p_mfc_enc_init(ctx);
  711. /* Setup ctrl handler */
  712. ret = s5p_mfc_enc_ctrls_setup(ctx);
  713. if (ret) {
  714. mfc_err("Failed to setup mfc controls\n");
  715. goto err_ctrls_setup;
  716. }
  717. } else {
  718. ret = -ENOENT;
  719. goto err_bad_node;
  720. }
  721. ctx->fh.ctrl_handler = &ctx->ctrl_handler;
  722. ctx->inst_no = -1;
  723. /* Load firmware if this is the first instance */
  724. if (dev->num_inst == 1) {
  725. dev->watchdog_timer.expires = jiffies +
  726. msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
  727. add_timer(&dev->watchdog_timer);
  728. ret = s5p_mfc_power_on();
  729. if (ret < 0) {
  730. mfc_err("power on failed\n");
  731. goto err_pwr_enable;
  732. }
  733. s5p_mfc_clock_on();
  734. ret = s5p_mfc_alloc_and_load_firmware(dev);
  735. if (ret)
  736. goto err_alloc_fw;
  737. /* Init the FW */
  738. ret = s5p_mfc_init_hw(dev);
  739. if (ret)
  740. goto err_init_hw;
  741. s5p_mfc_clock_off();
  742. }
  743. /* Init videobuf2 queue for CAPTURE */
  744. q = &ctx->vq_dst;
  745. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  746. q->drv_priv = &ctx->fh;
  747. if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
  748. q->io_modes = VB2_MMAP;
  749. q->ops = get_dec_queue_ops();
  750. } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
  751. q->io_modes = VB2_MMAP | VB2_USERPTR;
  752. q->ops = get_enc_queue_ops();
  753. } else {
  754. ret = -ENOENT;
  755. goto err_queue_init;
  756. }
  757. q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
  758. ret = vb2_queue_init(q);
  759. if (ret) {
  760. mfc_err("Failed to initialize videobuf2 queue(capture)\n");
  761. goto err_queue_init;
  762. }
  763. /* Init videobuf2 queue for OUTPUT */
  764. q = &ctx->vq_src;
  765. q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
  766. q->io_modes = VB2_MMAP;
  767. q->drv_priv = &ctx->fh;
  768. if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
  769. q->io_modes = VB2_MMAP;
  770. q->ops = get_dec_queue_ops();
  771. } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
  772. q->io_modes = VB2_MMAP | VB2_USERPTR;
  773. q->ops = get_enc_queue_ops();
  774. } else {
  775. ret = -ENOENT;
  776. goto err_queue_init;
  777. }
  778. q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
  779. ret = vb2_queue_init(q);
  780. if (ret) {
  781. mfc_err("Failed to initialize videobuf2 queue(output)\n");
  782. goto err_queue_init;
  783. }
  784. init_waitqueue_head(&ctx->queue);
  785. mutex_unlock(&dev->mfc_mutex);
  786. mfc_debug_leave();
  787. return ret;
  788. /* Deinit when failure occured */
  789. err_queue_init:
  790. err_init_hw:
  791. s5p_mfc_release_firmware(dev);
  792. err_alloc_fw:
  793. dev->ctx[ctx->num] = NULL;
  794. del_timer_sync(&dev->watchdog_timer);
  795. s5p_mfc_clock_off();
  796. err_pwr_enable:
  797. if (dev->num_inst == 1) {
  798. if (s5p_mfc_power_off() < 0)
  799. mfc_err("power off failed\n");
  800. s5p_mfc_release_firmware(dev);
  801. }
  802. err_ctrls_setup:
  803. s5p_mfc_dec_ctrls_delete(ctx);
  804. err_bad_node:
  805. err_no_ctx:
  806. v4l2_fh_del(&ctx->fh);
  807. v4l2_fh_exit(&ctx->fh);
  808. kfree(ctx);
  809. err_alloc:
  810. dev->num_inst--;
  811. mutex_unlock(&dev->mfc_mutex);
  812. mfc_debug_leave();
  813. return ret;
  814. }
  815. /* Release MFC context */
  816. static int s5p_mfc_release(struct file *file)
  817. {
  818. struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
  819. struct s5p_mfc_dev *dev = ctx->dev;
  820. mfc_debug_enter();
  821. mutex_lock(&dev->mfc_mutex);
  822. s5p_mfc_clock_on();
  823. vb2_queue_release(&ctx->vq_src);
  824. vb2_queue_release(&ctx->vq_dst);
  825. /* Mark context as idle */
  826. clear_work_bit_irqsave(ctx);
  827. /* If instance was initialised then
  828. * return instance and free reosurces */
  829. if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
  830. mfc_debug(2, "Has to free instance\n");
  831. ctx->state = MFCINST_RETURN_INST;
  832. set_work_bit_irqsave(ctx);
  833. s5p_mfc_clean_ctx_int_flags(ctx);
  834. s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
  835. /* Wait until instance is returned or timeout occured */
  836. if (s5p_mfc_wait_for_done_ctx
  837. (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
  838. s5p_mfc_clock_off();
  839. mfc_err("Err returning instance\n");
  840. }
  841. mfc_debug(2, "After free instance\n");
  842. /* Free resources */
  843. s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
  844. s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
  845. if (ctx->type == MFCINST_DECODER)
  846. s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
  847. ctx);
  848. ctx->inst_no = MFC_NO_INSTANCE_SET;
  849. }
  850. /* hardware locking scheme */
  851. if (dev->curr_ctx == ctx->num)
  852. clear_bit(0, &dev->hw_lock);
  853. dev->num_inst--;
  854. if (dev->num_inst == 0) {
  855. mfc_debug(2, "Last instance - release firmware\n");
  856. /* reset <-> F/W release */
  857. s5p_mfc_reset(dev);
  858. s5p_mfc_deinit_hw(dev);
  859. s5p_mfc_release_firmware(dev);
  860. del_timer_sync(&dev->watchdog_timer);
  861. if (s5p_mfc_power_off() < 0)
  862. mfc_err("Power off failed\n");
  863. }
  864. mfc_debug(2, "Shutting down clock\n");
  865. s5p_mfc_clock_off();
  866. dev->ctx[ctx->num] = NULL;
  867. s5p_mfc_dec_ctrls_delete(ctx);
  868. v4l2_fh_del(&ctx->fh);
  869. v4l2_fh_exit(&ctx->fh);
  870. kfree(ctx);
  871. mfc_debug_leave();
  872. mutex_unlock(&dev->mfc_mutex);
  873. return 0;
  874. }
  875. /* Poll */
  876. static unsigned int s5p_mfc_poll(struct file *file,
  877. struct poll_table_struct *wait)
  878. {
  879. struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
  880. struct s5p_mfc_dev *dev = ctx->dev;
  881. struct vb2_queue *src_q, *dst_q;
  882. struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
  883. unsigned int rc = 0;
  884. unsigned long flags;
  885. mutex_lock(&dev->mfc_mutex);
  886. src_q = &ctx->vq_src;
  887. dst_q = &ctx->vq_dst;
  888. /*
  889. * There has to be at least one buffer queued on each queued_list, which
  890. * means either in driver already or waiting for driver to claim it
  891. * and start processing.
  892. */
  893. if ((!src_q->streaming || list_empty(&src_q->queued_list))
  894. && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
  895. rc = POLLERR;
  896. goto end;
  897. }
  898. mutex_unlock(&dev->mfc_mutex);
  899. poll_wait(file, &ctx->fh.wait, wait);
  900. poll_wait(file, &src_q->done_wq, wait);
  901. poll_wait(file, &dst_q->done_wq, wait);
  902. mutex_lock(&dev->mfc_mutex);
  903. if (v4l2_event_pending(&ctx->fh))
  904. rc |= POLLPRI;
  905. spin_lock_irqsave(&src_q->done_lock, flags);
  906. if (!list_empty(&src_q->done_list))
  907. src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
  908. done_entry);
  909. if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
  910. || src_vb->state == VB2_BUF_STATE_ERROR))
  911. rc |= POLLOUT | POLLWRNORM;
  912. spin_unlock_irqrestore(&src_q->done_lock, flags);
  913. spin_lock_irqsave(&dst_q->done_lock, flags);
  914. if (!list_empty(&dst_q->done_list))
  915. dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
  916. done_entry);
  917. if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
  918. || dst_vb->state == VB2_BUF_STATE_ERROR))
  919. rc |= POLLIN | POLLRDNORM;
  920. spin_unlock_irqrestore(&dst_q->done_lock, flags);
  921. end:
  922. mutex_unlock(&dev->mfc_mutex);
  923. return rc;
  924. }
  925. /* Mmap */
  926. static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
  927. {
  928. struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
  929. struct s5p_mfc_dev *dev = ctx->dev;
  930. unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
  931. int ret;
  932. if (mutex_lock_interruptible(&dev->mfc_mutex))
  933. return -ERESTARTSYS;
  934. if (offset < DST_QUEUE_OFF_BASE) {
  935. mfc_debug(2, "mmaping source\n");
  936. ret = vb2_mmap(&ctx->vq_src, vma);
  937. } else { /* capture */
  938. mfc_debug(2, "mmaping destination\n");
  939. vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
  940. ret = vb2_mmap(&ctx->vq_dst, vma);
  941. }
  942. mutex_unlock(&dev->mfc_mutex);
  943. return ret;
  944. }
  945. /* v4l2 ops */
  946. static const struct v4l2_file_operations s5p_mfc_fops = {
  947. .owner = THIS_MODULE,
  948. .open = s5p_mfc_open,
  949. .release = s5p_mfc_release,
  950. .poll = s5p_mfc_poll,
  951. .unlocked_ioctl = video_ioctl2,
  952. .mmap = s5p_mfc_mmap,
  953. };
  954. static int match_child(struct device *dev, void *data)
  955. {
  956. if (!dev_name(dev))
  957. return 0;
  958. return !strcmp(dev_name(dev), (char *)data);
  959. }
  960. /* MFC probe function */
  961. static int s5p_mfc_probe(struct platform_device *pdev)
  962. {
  963. struct s5p_mfc_dev *dev;
  964. struct video_device *vfd;
  965. struct resource *res;
  966. int ret;
  967. pr_debug("%s++\n", __func__);
  968. dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
  969. if (!dev) {
  970. dev_err(&pdev->dev, "Not enough memory for MFC device\n");
  971. return -ENOMEM;
  972. }
  973. spin_lock_init(&dev->irqlock);
  974. spin_lock_init(&dev->condlock);
  975. dev->plat_dev = pdev;
  976. if (!dev->plat_dev) {
  977. dev_err(&pdev->dev, "No platform data specified\n");
  978. return -ENODEV;
  979. }
  980. ret = s5p_mfc_init_pm(dev);
  981. if (ret < 0) {
  982. dev_err(&pdev->dev, "failed to get mfc clock source\n");
  983. return ret;
  984. }
  985. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  986. dev->regs_base = devm_request_and_ioremap(&pdev->dev, res);
  987. if (dev->regs_base == NULL) {
  988. dev_err(&pdev->dev, "Failed to obtain io memory\n");
  989. return -ENOENT;
  990. }
  991. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  992. if (res == NULL) {
  993. dev_err(&pdev->dev, "failed to get irq resource\n");
  994. ret = -ENOENT;
  995. goto err_res;
  996. }
  997. dev->irq = res->start;
  998. ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
  999. IRQF_DISABLED, pdev->name, dev);
  1000. if (ret) {
  1001. dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
  1002. goto err_res;
  1003. }
  1004. dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, "s5p-mfc-l",
  1005. match_child);
  1006. if (!dev->mem_dev_l) {
  1007. mfc_err("Mem child (L) device get failed\n");
  1008. ret = -ENODEV;
  1009. goto err_res;
  1010. }
  1011. dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, "s5p-mfc-r",
  1012. match_child);
  1013. if (!dev->mem_dev_r) {
  1014. mfc_err("Mem child (R) device get failed\n");
  1015. ret = -ENODEV;
  1016. goto err_res;
  1017. }
  1018. dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
  1019. if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
  1020. ret = PTR_ERR(dev->alloc_ctx[0]);
  1021. goto err_res;
  1022. }
  1023. dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
  1024. if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) {
  1025. ret = PTR_ERR(dev->alloc_ctx[1]);
  1026. goto err_mem_init_ctx_1;
  1027. }
  1028. mutex_init(&dev->mfc_mutex);
  1029. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1030. if (ret)
  1031. goto err_v4l2_dev_reg;
  1032. init_waitqueue_head(&dev->queue);
  1033. /* decoder */
  1034. vfd = video_device_alloc();
  1035. if (!vfd) {
  1036. v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
  1037. ret = -ENOMEM;
  1038. goto err_dec_alloc;
  1039. }
  1040. vfd->fops = &s5p_mfc_fops,
  1041. vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
  1042. vfd->release = video_device_release,
  1043. vfd->lock = &dev->mfc_mutex;
  1044. vfd->v4l2_dev = &dev->v4l2_dev;
  1045. vfd->vfl_dir = VFL_DIR_M2M;
  1046. snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
  1047. dev->vfd_dec = vfd;
  1048. ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
  1049. if (ret) {
  1050. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1051. video_device_release(vfd);
  1052. goto err_dec_reg;
  1053. }
  1054. v4l2_info(&dev->v4l2_dev,
  1055. "decoder registered as /dev/video%d\n", vfd->num);
  1056. video_set_drvdata(vfd, dev);
  1057. /* encoder */
  1058. vfd = video_device_alloc();
  1059. if (!vfd) {
  1060. v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
  1061. ret = -ENOMEM;
  1062. goto err_enc_alloc;
  1063. }
  1064. vfd->fops = &s5p_mfc_fops,
  1065. vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
  1066. vfd->release = video_device_release,
  1067. vfd->lock = &dev->mfc_mutex;
  1068. vfd->v4l2_dev = &dev->v4l2_dev;
  1069. snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
  1070. dev->vfd_enc = vfd;
  1071. ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
  1072. if (ret) {
  1073. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1074. video_device_release(vfd);
  1075. goto err_enc_reg;
  1076. }
  1077. v4l2_info(&dev->v4l2_dev,
  1078. "encoder registered as /dev/video%d\n", vfd->num);
  1079. video_set_drvdata(vfd, dev);
  1080. platform_set_drvdata(pdev, dev);
  1081. dev->hw_lock = 0;
  1082. dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
  1083. INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
  1084. atomic_set(&dev->watchdog_cnt, 0);
  1085. init_timer(&dev->watchdog_timer);
  1086. dev->watchdog_timer.data = (unsigned long)dev;
  1087. dev->watchdog_timer.function = s5p_mfc_watchdog;
  1088. /* Initialize HW ops and commands based on MFC version */
  1089. s5p_mfc_init_hw_ops(dev);
  1090. s5p_mfc_init_hw_cmds(dev);
  1091. pr_debug("%s--\n", __func__);
  1092. return 0;
  1093. /* Deinit MFC if probe had failed */
  1094. err_enc_reg:
  1095. video_device_release(dev->vfd_enc);
  1096. err_enc_alloc:
  1097. video_unregister_device(dev->vfd_dec);
  1098. err_dec_reg:
  1099. video_device_release(dev->vfd_dec);
  1100. err_dec_alloc:
  1101. v4l2_device_unregister(&dev->v4l2_dev);
  1102. err_v4l2_dev_reg:
  1103. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
  1104. err_mem_init_ctx_1:
  1105. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
  1106. err_res:
  1107. s5p_mfc_final_pm(dev);
  1108. pr_debug("%s-- with error\n", __func__);
  1109. return ret;
  1110. }
  1111. /* Remove the driver */
  1112. static int __devexit s5p_mfc_remove(struct platform_device *pdev)
  1113. {
  1114. struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
  1115. v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
  1116. del_timer_sync(&dev->watchdog_timer);
  1117. flush_workqueue(dev->watchdog_workqueue);
  1118. destroy_workqueue(dev->watchdog_workqueue);
  1119. video_unregister_device(dev->vfd_enc);
  1120. video_unregister_device(dev->vfd_dec);
  1121. v4l2_device_unregister(&dev->v4l2_dev);
  1122. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
  1123. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
  1124. s5p_mfc_final_pm(dev);
  1125. return 0;
  1126. }
  1127. #ifdef CONFIG_PM_SLEEP
  1128. static int s5p_mfc_suspend(struct device *dev)
  1129. {
  1130. struct platform_device *pdev = to_platform_device(dev);
  1131. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1132. int ret;
  1133. if (m_dev->num_inst == 0)
  1134. return 0;
  1135. if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
  1136. mfc_err("Error: going to suspend for a second time\n");
  1137. return -EIO;
  1138. }
  1139. /* Check if we're processing then wait if it necessary. */
  1140. while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
  1141. /* Try and lock the HW */
  1142. /* Wait on the interrupt waitqueue */
  1143. ret = wait_event_interruptible_timeout(m_dev->queue,
  1144. m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
  1145. msecs_to_jiffies(MFC_INT_TIMEOUT));
  1146. if (ret == 0) {
  1147. mfc_err("Waiting for hardware to finish timed out\n");
  1148. return -EIO;
  1149. }
  1150. }
  1151. return s5p_mfc_sleep(m_dev);
  1152. }
  1153. static int s5p_mfc_resume(struct device *dev)
  1154. {
  1155. struct platform_device *pdev = to_platform_device(dev);
  1156. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1157. if (m_dev->num_inst == 0)
  1158. return 0;
  1159. return s5p_mfc_wakeup(m_dev);
  1160. }
  1161. #endif
  1162. #ifdef CONFIG_PM_RUNTIME
  1163. static int s5p_mfc_runtime_suspend(struct device *dev)
  1164. {
  1165. struct platform_device *pdev = to_platform_device(dev);
  1166. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1167. atomic_set(&m_dev->pm.power, 0);
  1168. return 0;
  1169. }
  1170. static int s5p_mfc_runtime_resume(struct device *dev)
  1171. {
  1172. struct platform_device *pdev = to_platform_device(dev);
  1173. struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
  1174. int pre_power;
  1175. if (!m_dev->alloc_ctx)
  1176. return 0;
  1177. pre_power = atomic_read(&m_dev->pm.power);
  1178. atomic_set(&m_dev->pm.power, 1);
  1179. return 0;
  1180. }
  1181. #endif
  1182. /* Power management */
  1183. static const struct dev_pm_ops s5p_mfc_pm_ops = {
  1184. SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
  1185. SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
  1186. NULL)
  1187. };
  1188. static struct platform_driver s5p_mfc_driver = {
  1189. .probe = s5p_mfc_probe,
  1190. .remove = __devexit_p(s5p_mfc_remove),
  1191. .driver = {
  1192. .name = S5P_MFC_NAME,
  1193. .owner = THIS_MODULE,
  1194. .pm = &s5p_mfc_pm_ops
  1195. },
  1196. };
  1197. module_platform_driver(s5p_mfc_driver);
  1198. MODULE_LICENSE("GPL");
  1199. MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
  1200. MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");