cnic.c 141 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521
  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  55. static LIST_HEAD(cnic_dev_list);
  56. static LIST_HEAD(cnic_udev_list);
  57. static DEFINE_RWLOCK(cnic_dev_lock);
  58. static DEFINE_MUTEX(cnic_lock);
  59. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  60. static int cnic_service_bnx2(void *, void *);
  61. static int cnic_service_bnx2x(void *, void *);
  62. static int cnic_ctl(void *, struct cnic_ctl_info *);
  63. static struct cnic_ops cnic_bnx2_ops = {
  64. .cnic_owner = THIS_MODULE,
  65. .cnic_handler = cnic_service_bnx2,
  66. .cnic_ctl = cnic_ctl,
  67. };
  68. static struct cnic_ops cnic_bnx2x_ops = {
  69. .cnic_owner = THIS_MODULE,
  70. .cnic_handler = cnic_service_bnx2x,
  71. .cnic_ctl = cnic_ctl,
  72. };
  73. static struct workqueue_struct *cnic_wq;
  74. static void cnic_shutdown_rings(struct cnic_dev *);
  75. static void cnic_init_rings(struct cnic_dev *);
  76. static int cnic_cm_set_pg(struct cnic_sock *);
  77. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  78. {
  79. struct cnic_uio_dev *udev = uinfo->priv;
  80. struct cnic_dev *dev;
  81. if (!capable(CAP_NET_ADMIN))
  82. return -EPERM;
  83. if (udev->uio_dev != -1)
  84. return -EBUSY;
  85. rtnl_lock();
  86. dev = udev->dev;
  87. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  88. rtnl_unlock();
  89. return -ENODEV;
  90. }
  91. udev->uio_dev = iminor(inode);
  92. cnic_shutdown_rings(dev);
  93. cnic_init_rings(dev);
  94. rtnl_unlock();
  95. return 0;
  96. }
  97. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  98. {
  99. struct cnic_uio_dev *udev = uinfo->priv;
  100. udev->uio_dev = -1;
  101. return 0;
  102. }
  103. static inline void cnic_hold(struct cnic_dev *dev)
  104. {
  105. atomic_inc(&dev->ref_count);
  106. }
  107. static inline void cnic_put(struct cnic_dev *dev)
  108. {
  109. atomic_dec(&dev->ref_count);
  110. }
  111. static inline void csk_hold(struct cnic_sock *csk)
  112. {
  113. atomic_inc(&csk->ref_count);
  114. }
  115. static inline void csk_put(struct cnic_sock *csk)
  116. {
  117. atomic_dec(&csk->ref_count);
  118. }
  119. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  120. {
  121. struct cnic_dev *cdev;
  122. read_lock(&cnic_dev_lock);
  123. list_for_each_entry(cdev, &cnic_dev_list, list) {
  124. if (netdev == cdev->netdev) {
  125. cnic_hold(cdev);
  126. read_unlock(&cnic_dev_lock);
  127. return cdev;
  128. }
  129. }
  130. read_unlock(&cnic_dev_lock);
  131. return NULL;
  132. }
  133. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  134. {
  135. atomic_inc(&ulp_ops->ref_count);
  136. }
  137. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  138. {
  139. atomic_dec(&ulp_ops->ref_count);
  140. }
  141. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  142. {
  143. struct cnic_local *cp = dev->cnic_priv;
  144. struct cnic_eth_dev *ethdev = cp->ethdev;
  145. struct drv_ctl_info info;
  146. struct drv_ctl_io *io = &info.data.io;
  147. info.cmd = DRV_CTL_CTX_WR_CMD;
  148. io->cid_addr = cid_addr;
  149. io->offset = off;
  150. io->data = val;
  151. ethdev->drv_ctl(dev->netdev, &info);
  152. }
  153. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  154. {
  155. struct cnic_local *cp = dev->cnic_priv;
  156. struct cnic_eth_dev *ethdev = cp->ethdev;
  157. struct drv_ctl_info info;
  158. struct drv_ctl_io *io = &info.data.io;
  159. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  160. io->offset = off;
  161. io->dma_addr = addr;
  162. ethdev->drv_ctl(dev->netdev, &info);
  163. }
  164. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  165. {
  166. struct cnic_local *cp = dev->cnic_priv;
  167. struct cnic_eth_dev *ethdev = cp->ethdev;
  168. struct drv_ctl_info info;
  169. struct drv_ctl_l2_ring *ring = &info.data.ring;
  170. if (start)
  171. info.cmd = DRV_CTL_START_L2_CMD;
  172. else
  173. info.cmd = DRV_CTL_STOP_L2_CMD;
  174. ring->cid = cid;
  175. ring->client_id = cl_id;
  176. ethdev->drv_ctl(dev->netdev, &info);
  177. }
  178. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  179. {
  180. struct cnic_local *cp = dev->cnic_priv;
  181. struct cnic_eth_dev *ethdev = cp->ethdev;
  182. struct drv_ctl_info info;
  183. struct drv_ctl_io *io = &info.data.io;
  184. info.cmd = DRV_CTL_IO_WR_CMD;
  185. io->offset = off;
  186. io->data = val;
  187. ethdev->drv_ctl(dev->netdev, &info);
  188. }
  189. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  190. {
  191. struct cnic_local *cp = dev->cnic_priv;
  192. struct cnic_eth_dev *ethdev = cp->ethdev;
  193. struct drv_ctl_info info;
  194. struct drv_ctl_io *io = &info.data.io;
  195. info.cmd = DRV_CTL_IO_RD_CMD;
  196. io->offset = off;
  197. ethdev->drv_ctl(dev->netdev, &info);
  198. return io->data;
  199. }
  200. static int cnic_in_use(struct cnic_sock *csk)
  201. {
  202. return test_bit(SK_F_INUSE, &csk->flags);
  203. }
  204. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  205. {
  206. struct cnic_local *cp = dev->cnic_priv;
  207. struct cnic_eth_dev *ethdev = cp->ethdev;
  208. struct drv_ctl_info info;
  209. info.cmd = cmd;
  210. info.data.credit.credit_count = count;
  211. ethdev->drv_ctl(dev->netdev, &info);
  212. }
  213. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  214. {
  215. u32 i;
  216. for (i = 0; i < cp->max_cid_space; i++) {
  217. if (cp->ctx_tbl[i].cid == cid) {
  218. *l5_cid = i;
  219. return 0;
  220. }
  221. }
  222. return -EINVAL;
  223. }
  224. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  225. struct cnic_sock *csk)
  226. {
  227. struct iscsi_path path_req;
  228. char *buf = NULL;
  229. u16 len = 0;
  230. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  231. struct cnic_ulp_ops *ulp_ops;
  232. struct cnic_uio_dev *udev = cp->udev;
  233. int rc = 0, retry = 0;
  234. if (!udev || udev->uio_dev == -1)
  235. return -ENODEV;
  236. if (csk) {
  237. len = sizeof(path_req);
  238. buf = (char *) &path_req;
  239. memset(&path_req, 0, len);
  240. msg_type = ISCSI_KEVENT_PATH_REQ;
  241. path_req.handle = (u64) csk->l5_cid;
  242. if (test_bit(SK_F_IPV6, &csk->flags)) {
  243. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  244. sizeof(struct in6_addr));
  245. path_req.ip_addr_len = 16;
  246. } else {
  247. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  248. sizeof(struct in_addr));
  249. path_req.ip_addr_len = 4;
  250. }
  251. path_req.vlan_id = csk->vlan_id;
  252. path_req.pmtu = csk->mtu;
  253. }
  254. while (retry < 3) {
  255. rc = 0;
  256. rcu_read_lock();
  257. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  258. if (ulp_ops)
  259. rc = ulp_ops->iscsi_nl_send_msg(
  260. cp->ulp_handle[CNIC_ULP_ISCSI],
  261. msg_type, buf, len);
  262. rcu_read_unlock();
  263. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  264. break;
  265. msleep(100);
  266. retry++;
  267. }
  268. return 0;
  269. }
  270. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  271. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  272. char *buf, u16 len)
  273. {
  274. int rc = -EINVAL;
  275. switch (msg_type) {
  276. case ISCSI_UEVENT_PATH_UPDATE: {
  277. struct cnic_local *cp;
  278. u32 l5_cid;
  279. struct cnic_sock *csk;
  280. struct iscsi_path *path_resp;
  281. if (len < sizeof(*path_resp))
  282. break;
  283. path_resp = (struct iscsi_path *) buf;
  284. cp = dev->cnic_priv;
  285. l5_cid = (u32) path_resp->handle;
  286. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  287. break;
  288. rcu_read_lock();
  289. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  290. rc = -ENODEV;
  291. rcu_read_unlock();
  292. break;
  293. }
  294. csk = &cp->csk_tbl[l5_cid];
  295. csk_hold(csk);
  296. if (cnic_in_use(csk) &&
  297. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  298. memcpy(csk->ha, path_resp->mac_addr, 6);
  299. if (test_bit(SK_F_IPV6, &csk->flags))
  300. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  301. sizeof(struct in6_addr));
  302. else
  303. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  304. sizeof(struct in_addr));
  305. if (is_valid_ether_addr(csk->ha)) {
  306. cnic_cm_set_pg(csk);
  307. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  308. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  309. cnic_cm_upcall(cp, csk,
  310. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  311. clear_bit(SK_F_CONNECT_START, &csk->flags);
  312. }
  313. }
  314. csk_put(csk);
  315. rcu_read_unlock();
  316. rc = 0;
  317. }
  318. }
  319. return rc;
  320. }
  321. static int cnic_offld_prep(struct cnic_sock *csk)
  322. {
  323. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  324. return 0;
  325. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  326. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  327. return 0;
  328. }
  329. return 1;
  330. }
  331. static int cnic_close_prep(struct cnic_sock *csk)
  332. {
  333. clear_bit(SK_F_CONNECT_START, &csk->flags);
  334. smp_mb__after_clear_bit();
  335. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  336. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  337. msleep(1);
  338. return 1;
  339. }
  340. return 0;
  341. }
  342. static int cnic_abort_prep(struct cnic_sock *csk)
  343. {
  344. clear_bit(SK_F_CONNECT_START, &csk->flags);
  345. smp_mb__after_clear_bit();
  346. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  347. msleep(1);
  348. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  349. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  350. return 1;
  351. }
  352. return 0;
  353. }
  354. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  355. {
  356. struct cnic_dev *dev;
  357. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  358. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  359. return -EINVAL;
  360. }
  361. mutex_lock(&cnic_lock);
  362. if (cnic_ulp_tbl[ulp_type]) {
  363. pr_err("%s: Type %d has already been registered\n",
  364. __func__, ulp_type);
  365. mutex_unlock(&cnic_lock);
  366. return -EBUSY;
  367. }
  368. read_lock(&cnic_dev_lock);
  369. list_for_each_entry(dev, &cnic_dev_list, list) {
  370. struct cnic_local *cp = dev->cnic_priv;
  371. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  372. }
  373. read_unlock(&cnic_dev_lock);
  374. atomic_set(&ulp_ops->ref_count, 0);
  375. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  376. mutex_unlock(&cnic_lock);
  377. /* Prevent race conditions with netdev_event */
  378. rtnl_lock();
  379. list_for_each_entry(dev, &cnic_dev_list, list) {
  380. struct cnic_local *cp = dev->cnic_priv;
  381. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  382. ulp_ops->cnic_init(dev);
  383. }
  384. rtnl_unlock();
  385. return 0;
  386. }
  387. int cnic_unregister_driver(int ulp_type)
  388. {
  389. struct cnic_dev *dev;
  390. struct cnic_ulp_ops *ulp_ops;
  391. int i = 0;
  392. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  393. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  394. return -EINVAL;
  395. }
  396. mutex_lock(&cnic_lock);
  397. ulp_ops = cnic_ulp_tbl[ulp_type];
  398. if (!ulp_ops) {
  399. pr_err("%s: Type %d has not been registered\n",
  400. __func__, ulp_type);
  401. goto out_unlock;
  402. }
  403. read_lock(&cnic_dev_lock);
  404. list_for_each_entry(dev, &cnic_dev_list, list) {
  405. struct cnic_local *cp = dev->cnic_priv;
  406. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  407. pr_err("%s: Type %d still has devices registered\n",
  408. __func__, ulp_type);
  409. read_unlock(&cnic_dev_lock);
  410. goto out_unlock;
  411. }
  412. }
  413. read_unlock(&cnic_dev_lock);
  414. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  415. mutex_unlock(&cnic_lock);
  416. synchronize_rcu();
  417. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  418. msleep(100);
  419. i++;
  420. }
  421. if (atomic_read(&ulp_ops->ref_count) != 0)
  422. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  423. return 0;
  424. out_unlock:
  425. mutex_unlock(&cnic_lock);
  426. return -EINVAL;
  427. }
  428. static int cnic_start_hw(struct cnic_dev *);
  429. static void cnic_stop_hw(struct cnic_dev *);
  430. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  431. void *ulp_ctx)
  432. {
  433. struct cnic_local *cp = dev->cnic_priv;
  434. struct cnic_ulp_ops *ulp_ops;
  435. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  436. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  437. return -EINVAL;
  438. }
  439. mutex_lock(&cnic_lock);
  440. if (cnic_ulp_tbl[ulp_type] == NULL) {
  441. pr_err("%s: Driver with type %d has not been registered\n",
  442. __func__, ulp_type);
  443. mutex_unlock(&cnic_lock);
  444. return -EAGAIN;
  445. }
  446. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  447. pr_err("%s: Type %d has already been registered to this device\n",
  448. __func__, ulp_type);
  449. mutex_unlock(&cnic_lock);
  450. return -EBUSY;
  451. }
  452. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  453. cp->ulp_handle[ulp_type] = ulp_ctx;
  454. ulp_ops = cnic_ulp_tbl[ulp_type];
  455. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  456. cnic_hold(dev);
  457. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  458. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  459. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  460. mutex_unlock(&cnic_lock);
  461. return 0;
  462. }
  463. EXPORT_SYMBOL(cnic_register_driver);
  464. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  465. {
  466. struct cnic_local *cp = dev->cnic_priv;
  467. int i = 0;
  468. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  469. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  470. return -EINVAL;
  471. }
  472. mutex_lock(&cnic_lock);
  473. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  474. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  475. cnic_put(dev);
  476. } else {
  477. pr_err("%s: device not registered to this ulp type %d\n",
  478. __func__, ulp_type);
  479. mutex_unlock(&cnic_lock);
  480. return -EINVAL;
  481. }
  482. mutex_unlock(&cnic_lock);
  483. if (ulp_type == CNIC_ULP_ISCSI)
  484. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  485. synchronize_rcu();
  486. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  487. i < 20) {
  488. msleep(100);
  489. i++;
  490. }
  491. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  492. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  493. return 0;
  494. }
  495. EXPORT_SYMBOL(cnic_unregister_driver);
  496. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  497. {
  498. id_tbl->start = start_id;
  499. id_tbl->max = size;
  500. id_tbl->next = 0;
  501. spin_lock_init(&id_tbl->lock);
  502. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  503. if (!id_tbl->table)
  504. return -ENOMEM;
  505. return 0;
  506. }
  507. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  508. {
  509. kfree(id_tbl->table);
  510. id_tbl->table = NULL;
  511. }
  512. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  513. {
  514. int ret = -1;
  515. id -= id_tbl->start;
  516. if (id >= id_tbl->max)
  517. return ret;
  518. spin_lock(&id_tbl->lock);
  519. if (!test_bit(id, id_tbl->table)) {
  520. set_bit(id, id_tbl->table);
  521. ret = 0;
  522. }
  523. spin_unlock(&id_tbl->lock);
  524. return ret;
  525. }
  526. /* Returns -1 if not successful */
  527. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  528. {
  529. u32 id;
  530. spin_lock(&id_tbl->lock);
  531. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  532. if (id >= id_tbl->max) {
  533. id = -1;
  534. if (id_tbl->next != 0) {
  535. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  536. if (id >= id_tbl->next)
  537. id = -1;
  538. }
  539. }
  540. if (id < id_tbl->max) {
  541. set_bit(id, id_tbl->table);
  542. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  543. id += id_tbl->start;
  544. }
  545. spin_unlock(&id_tbl->lock);
  546. return id;
  547. }
  548. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  549. {
  550. if (id == -1)
  551. return;
  552. id -= id_tbl->start;
  553. if (id >= id_tbl->max)
  554. return;
  555. clear_bit(id, id_tbl->table);
  556. }
  557. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  558. {
  559. int i;
  560. if (!dma->pg_arr)
  561. return;
  562. for (i = 0; i < dma->num_pages; i++) {
  563. if (dma->pg_arr[i]) {
  564. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  565. dma->pg_arr[i], dma->pg_map_arr[i]);
  566. dma->pg_arr[i] = NULL;
  567. }
  568. }
  569. if (dma->pgtbl) {
  570. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  571. dma->pgtbl, dma->pgtbl_map);
  572. dma->pgtbl = NULL;
  573. }
  574. kfree(dma->pg_arr);
  575. dma->pg_arr = NULL;
  576. dma->num_pages = 0;
  577. }
  578. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  579. {
  580. int i;
  581. u32 *page_table = dma->pgtbl;
  582. for (i = 0; i < dma->num_pages; i++) {
  583. /* Each entry needs to be in big endian format. */
  584. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  585. page_table++;
  586. *page_table = (u32) dma->pg_map_arr[i];
  587. page_table++;
  588. }
  589. }
  590. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  591. {
  592. int i;
  593. u32 *page_table = dma->pgtbl;
  594. for (i = 0; i < dma->num_pages; i++) {
  595. /* Each entry needs to be in little endian format. */
  596. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  597. page_table++;
  598. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  599. page_table++;
  600. }
  601. }
  602. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  603. int pages, int use_pg_tbl)
  604. {
  605. int i, size;
  606. struct cnic_local *cp = dev->cnic_priv;
  607. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  608. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  609. if (dma->pg_arr == NULL)
  610. return -ENOMEM;
  611. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  612. dma->num_pages = pages;
  613. for (i = 0; i < pages; i++) {
  614. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  615. BCM_PAGE_SIZE,
  616. &dma->pg_map_arr[i],
  617. GFP_ATOMIC);
  618. if (dma->pg_arr[i] == NULL)
  619. goto error;
  620. }
  621. if (!use_pg_tbl)
  622. return 0;
  623. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  624. ~(BCM_PAGE_SIZE - 1);
  625. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  626. &dma->pgtbl_map, GFP_ATOMIC);
  627. if (dma->pgtbl == NULL)
  628. goto error;
  629. cp->setup_pgtbl(dev, dma);
  630. return 0;
  631. error:
  632. cnic_free_dma(dev, dma);
  633. return -ENOMEM;
  634. }
  635. static void cnic_free_context(struct cnic_dev *dev)
  636. {
  637. struct cnic_local *cp = dev->cnic_priv;
  638. int i;
  639. for (i = 0; i < cp->ctx_blks; i++) {
  640. if (cp->ctx_arr[i].ctx) {
  641. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  642. cp->ctx_arr[i].ctx,
  643. cp->ctx_arr[i].mapping);
  644. cp->ctx_arr[i].ctx = NULL;
  645. }
  646. }
  647. }
  648. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  649. {
  650. uio_unregister_device(&udev->cnic_uinfo);
  651. if (udev->l2_buf) {
  652. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  653. udev->l2_buf, udev->l2_buf_map);
  654. udev->l2_buf = NULL;
  655. }
  656. if (udev->l2_ring) {
  657. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  658. udev->l2_ring, udev->l2_ring_map);
  659. udev->l2_ring = NULL;
  660. }
  661. pci_dev_put(udev->pdev);
  662. kfree(udev);
  663. }
  664. static void cnic_free_uio(struct cnic_uio_dev *udev)
  665. {
  666. if (!udev)
  667. return;
  668. write_lock(&cnic_dev_lock);
  669. list_del_init(&udev->list);
  670. write_unlock(&cnic_dev_lock);
  671. __cnic_free_uio(udev);
  672. }
  673. static void cnic_free_resc(struct cnic_dev *dev)
  674. {
  675. struct cnic_local *cp = dev->cnic_priv;
  676. struct cnic_uio_dev *udev = cp->udev;
  677. if (udev) {
  678. udev->dev = NULL;
  679. cp->udev = NULL;
  680. }
  681. cnic_free_context(dev);
  682. kfree(cp->ctx_arr);
  683. cp->ctx_arr = NULL;
  684. cp->ctx_blks = 0;
  685. cnic_free_dma(dev, &cp->gbl_buf_info);
  686. cnic_free_dma(dev, &cp->conn_buf_info);
  687. cnic_free_dma(dev, &cp->kwq_info);
  688. cnic_free_dma(dev, &cp->kwq_16_data_info);
  689. cnic_free_dma(dev, &cp->kcq2.dma);
  690. cnic_free_dma(dev, &cp->kcq1.dma);
  691. kfree(cp->iscsi_tbl);
  692. cp->iscsi_tbl = NULL;
  693. kfree(cp->ctx_tbl);
  694. cp->ctx_tbl = NULL;
  695. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  696. cnic_free_id_tbl(&cp->cid_tbl);
  697. }
  698. static int cnic_alloc_context(struct cnic_dev *dev)
  699. {
  700. struct cnic_local *cp = dev->cnic_priv;
  701. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  702. int i, k, arr_size;
  703. cp->ctx_blk_size = BCM_PAGE_SIZE;
  704. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  705. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  706. sizeof(struct cnic_ctx);
  707. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  708. if (cp->ctx_arr == NULL)
  709. return -ENOMEM;
  710. k = 0;
  711. for (i = 0; i < 2; i++) {
  712. u32 j, reg, off, lo, hi;
  713. if (i == 0)
  714. off = BNX2_PG_CTX_MAP;
  715. else
  716. off = BNX2_ISCSI_CTX_MAP;
  717. reg = cnic_reg_rd_ind(dev, off);
  718. lo = reg >> 16;
  719. hi = reg & 0xffff;
  720. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  721. cp->ctx_arr[k].cid = j;
  722. }
  723. cp->ctx_blks = k;
  724. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  725. cp->ctx_blks = 0;
  726. return -ENOMEM;
  727. }
  728. for (i = 0; i < cp->ctx_blks; i++) {
  729. cp->ctx_arr[i].ctx =
  730. dma_alloc_coherent(&dev->pcidev->dev,
  731. BCM_PAGE_SIZE,
  732. &cp->ctx_arr[i].mapping,
  733. GFP_KERNEL);
  734. if (cp->ctx_arr[i].ctx == NULL)
  735. return -ENOMEM;
  736. }
  737. }
  738. return 0;
  739. }
  740. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  741. {
  742. int err, i, is_bnx2 = 0;
  743. struct kcqe **kcq;
  744. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  745. is_bnx2 = 1;
  746. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  747. if (err)
  748. return err;
  749. kcq = (struct kcqe **) info->dma.pg_arr;
  750. info->kcq = kcq;
  751. if (is_bnx2)
  752. return 0;
  753. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  754. struct bnx2x_bd_chain_next *next =
  755. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  756. int j = i + 1;
  757. if (j >= KCQ_PAGE_CNT)
  758. j = 0;
  759. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  760. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  761. }
  762. return 0;
  763. }
  764. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  765. {
  766. struct cnic_local *cp = dev->cnic_priv;
  767. struct cnic_uio_dev *udev;
  768. read_lock(&cnic_dev_lock);
  769. list_for_each_entry(udev, &cnic_udev_list, list) {
  770. if (udev->pdev == dev->pcidev) {
  771. udev->dev = dev;
  772. cp->udev = udev;
  773. read_unlock(&cnic_dev_lock);
  774. return 0;
  775. }
  776. }
  777. read_unlock(&cnic_dev_lock);
  778. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  779. if (!udev)
  780. return -ENOMEM;
  781. udev->uio_dev = -1;
  782. udev->dev = dev;
  783. udev->pdev = dev->pcidev;
  784. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  785. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  786. &udev->l2_ring_map,
  787. GFP_KERNEL | __GFP_COMP);
  788. if (!udev->l2_ring)
  789. return -ENOMEM;
  790. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  791. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  792. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  793. &udev->l2_buf_map,
  794. GFP_KERNEL | __GFP_COMP);
  795. if (!udev->l2_buf)
  796. return -ENOMEM;
  797. write_lock(&cnic_dev_lock);
  798. list_add(&udev->list, &cnic_udev_list);
  799. write_unlock(&cnic_dev_lock);
  800. pci_dev_get(udev->pdev);
  801. cp->udev = udev;
  802. return 0;
  803. }
  804. static int cnic_init_uio(struct cnic_dev *dev)
  805. {
  806. struct cnic_local *cp = dev->cnic_priv;
  807. struct cnic_uio_dev *udev = cp->udev;
  808. struct uio_info *uinfo;
  809. int ret = 0;
  810. if (!udev)
  811. return -ENOMEM;
  812. uinfo = &udev->cnic_uinfo;
  813. uinfo->mem[0].addr = dev->netdev->base_addr;
  814. uinfo->mem[0].internal_addr = dev->regview;
  815. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  816. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  817. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  818. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  819. PAGE_MASK;
  820. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  821. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  822. else
  823. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  824. uinfo->name = "bnx2_cnic";
  825. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  826. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  827. PAGE_MASK;
  828. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  829. uinfo->name = "bnx2x_cnic";
  830. }
  831. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  832. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  833. uinfo->mem[2].size = udev->l2_ring_size;
  834. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  835. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  836. uinfo->mem[3].size = udev->l2_buf_size;
  837. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  838. uinfo->version = CNIC_MODULE_VERSION;
  839. uinfo->irq = UIO_IRQ_CUSTOM;
  840. uinfo->open = cnic_uio_open;
  841. uinfo->release = cnic_uio_close;
  842. if (udev->uio_dev == -1) {
  843. if (!uinfo->priv) {
  844. uinfo->priv = udev;
  845. ret = uio_register_device(&udev->pdev->dev, uinfo);
  846. }
  847. } else {
  848. cnic_init_rings(dev);
  849. }
  850. return ret;
  851. }
  852. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  853. {
  854. struct cnic_local *cp = dev->cnic_priv;
  855. int ret;
  856. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  857. if (ret)
  858. goto error;
  859. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  860. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  861. if (ret)
  862. goto error;
  863. ret = cnic_alloc_context(dev);
  864. if (ret)
  865. goto error;
  866. ret = cnic_alloc_uio_rings(dev, 2);
  867. if (ret)
  868. goto error;
  869. ret = cnic_init_uio(dev);
  870. if (ret)
  871. goto error;
  872. return 0;
  873. error:
  874. cnic_free_resc(dev);
  875. return ret;
  876. }
  877. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  878. {
  879. struct cnic_local *cp = dev->cnic_priv;
  880. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  881. int total_mem, blks, i;
  882. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  883. blks = total_mem / ctx_blk_size;
  884. if (total_mem % ctx_blk_size)
  885. blks++;
  886. if (blks > cp->ethdev->ctx_tbl_len)
  887. return -ENOMEM;
  888. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  889. if (cp->ctx_arr == NULL)
  890. return -ENOMEM;
  891. cp->ctx_blks = blks;
  892. cp->ctx_blk_size = ctx_blk_size;
  893. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  894. cp->ctx_align = 0;
  895. else
  896. cp->ctx_align = ctx_blk_size;
  897. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  898. for (i = 0; i < blks; i++) {
  899. cp->ctx_arr[i].ctx =
  900. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  901. &cp->ctx_arr[i].mapping,
  902. GFP_KERNEL);
  903. if (cp->ctx_arr[i].ctx == NULL)
  904. return -ENOMEM;
  905. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  906. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  907. cnic_free_context(dev);
  908. cp->ctx_blk_size += cp->ctx_align;
  909. i = -1;
  910. continue;
  911. }
  912. }
  913. }
  914. return 0;
  915. }
  916. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  917. {
  918. struct cnic_local *cp = dev->cnic_priv;
  919. struct cnic_eth_dev *ethdev = cp->ethdev;
  920. u32 start_cid = ethdev->starting_cid;
  921. int i, j, n, ret, pages;
  922. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  923. cp->iro_arr = ethdev->iro_arr;
  924. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  925. cp->iscsi_start_cid = start_cid;
  926. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  927. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  928. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  929. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  930. if (!cp->fcoe_init_cid)
  931. cp->fcoe_init_cid = 0x10;
  932. }
  933. if (start_cid < BNX2X_ISCSI_START_CID) {
  934. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  935. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  936. cp->fcoe_start_cid += delta;
  937. cp->max_cid_space += delta;
  938. }
  939. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  940. GFP_KERNEL);
  941. if (!cp->iscsi_tbl)
  942. goto error;
  943. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  944. cp->max_cid_space, GFP_KERNEL);
  945. if (!cp->ctx_tbl)
  946. goto error;
  947. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  948. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  949. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  950. }
  951. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  952. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  953. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  954. PAGE_SIZE;
  955. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  956. if (ret)
  957. return -ENOMEM;
  958. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  959. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  960. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  961. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  962. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  963. off;
  964. if ((i % n) == (n - 1))
  965. j++;
  966. }
  967. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  968. if (ret)
  969. goto error;
  970. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  971. ret = cnic_alloc_kcq(dev, &cp->kcq2);
  972. if (ret)
  973. goto error;
  974. }
  975. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  976. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  977. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  978. if (ret)
  979. goto error;
  980. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  981. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  982. if (ret)
  983. goto error;
  984. ret = cnic_alloc_bnx2x_context(dev);
  985. if (ret)
  986. goto error;
  987. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  988. cp->l2_rx_ring_size = 15;
  989. ret = cnic_alloc_uio_rings(dev, 4);
  990. if (ret)
  991. goto error;
  992. ret = cnic_init_uio(dev);
  993. if (ret)
  994. goto error;
  995. return 0;
  996. error:
  997. cnic_free_resc(dev);
  998. return -ENOMEM;
  999. }
  1000. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1001. {
  1002. return cp->max_kwq_idx -
  1003. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1004. }
  1005. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1006. u32 num_wqes)
  1007. {
  1008. struct cnic_local *cp = dev->cnic_priv;
  1009. struct kwqe *prod_qe;
  1010. u16 prod, sw_prod, i;
  1011. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1012. return -EAGAIN; /* bnx2 is down */
  1013. spin_lock_bh(&cp->cnic_ulp_lock);
  1014. if (num_wqes > cnic_kwq_avail(cp) &&
  1015. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1016. spin_unlock_bh(&cp->cnic_ulp_lock);
  1017. return -EAGAIN;
  1018. }
  1019. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1020. prod = cp->kwq_prod_idx;
  1021. sw_prod = prod & MAX_KWQ_IDX;
  1022. for (i = 0; i < num_wqes; i++) {
  1023. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1024. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1025. prod++;
  1026. sw_prod = prod & MAX_KWQ_IDX;
  1027. }
  1028. cp->kwq_prod_idx = prod;
  1029. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1030. spin_unlock_bh(&cp->cnic_ulp_lock);
  1031. return 0;
  1032. }
  1033. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1034. union l5cm_specific_data *l5_data)
  1035. {
  1036. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1037. dma_addr_t map;
  1038. map = ctx->kwqe_data_mapping;
  1039. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1040. l5_data->phy_address.hi = (u64) map >> 32;
  1041. return ctx->kwqe_data;
  1042. }
  1043. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1044. u32 type, union l5cm_specific_data *l5_data)
  1045. {
  1046. struct cnic_local *cp = dev->cnic_priv;
  1047. struct l5cm_spe kwqe;
  1048. struct kwqe_16 *kwq[1];
  1049. int ret;
  1050. kwqe.hdr.conn_and_cmd_data =
  1051. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1052. BNX2X_HW_CID(cp, cid)));
  1053. kwqe.hdr.type = cpu_to_le16(type);
  1054. kwqe.hdr.reserved1 = 0;
  1055. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1056. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1057. kwq[0] = (struct kwqe_16 *) &kwqe;
  1058. spin_lock_bh(&cp->cnic_ulp_lock);
  1059. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1060. spin_unlock_bh(&cp->cnic_ulp_lock);
  1061. if (ret == 1)
  1062. return 0;
  1063. return -EBUSY;
  1064. }
  1065. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1066. struct kcqe *cqes[], u32 num_cqes)
  1067. {
  1068. struct cnic_local *cp = dev->cnic_priv;
  1069. struct cnic_ulp_ops *ulp_ops;
  1070. rcu_read_lock();
  1071. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1072. if (likely(ulp_ops)) {
  1073. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1074. cqes, num_cqes);
  1075. }
  1076. rcu_read_unlock();
  1077. }
  1078. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1079. {
  1080. struct cnic_local *cp = dev->cnic_priv;
  1081. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1082. int hq_bds, pages;
  1083. u32 pfid = cp->pfid;
  1084. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1085. cp->num_ccells = req1->num_ccells_per_conn;
  1086. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1087. cp->num_iscsi_tasks;
  1088. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1089. BNX2X_ISCSI_R2TQE_SIZE;
  1090. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1091. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1092. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1093. cp->num_cqs = req1->num_cqs;
  1094. if (!dev->max_iscsi_conn)
  1095. return 0;
  1096. /* init Tstorm RAM */
  1097. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1098. req1->rq_num_wqes);
  1099. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1100. PAGE_SIZE);
  1101. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1102. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1103. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1104. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1105. req1->num_tasks_per_conn);
  1106. /* init Ustorm RAM */
  1107. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1108. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1109. req1->rq_buffer_size);
  1110. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1111. PAGE_SIZE);
  1112. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1113. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1114. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1115. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1116. req1->num_tasks_per_conn);
  1117. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1118. req1->rq_num_wqes);
  1119. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1120. req1->cq_num_wqes);
  1121. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1122. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1123. /* init Xstorm RAM */
  1124. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1125. PAGE_SIZE);
  1126. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1127. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1128. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1129. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1130. req1->num_tasks_per_conn);
  1131. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1132. hq_bds);
  1133. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1134. req1->num_tasks_per_conn);
  1135. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1136. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1137. /* init Cstorm RAM */
  1138. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1139. PAGE_SIZE);
  1140. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1141. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1142. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1143. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1144. req1->num_tasks_per_conn);
  1145. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1146. req1->cq_num_wqes);
  1147. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1148. hq_bds);
  1149. return 0;
  1150. }
  1151. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1152. {
  1153. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1154. struct cnic_local *cp = dev->cnic_priv;
  1155. u32 pfid = cp->pfid;
  1156. struct iscsi_kcqe kcqe;
  1157. struct kcqe *cqes[1];
  1158. memset(&kcqe, 0, sizeof(kcqe));
  1159. if (!dev->max_iscsi_conn) {
  1160. kcqe.completion_status =
  1161. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1162. goto done;
  1163. }
  1164. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1165. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1166. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1167. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1168. req2->error_bit_map[1]);
  1169. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1170. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1171. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1172. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1173. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1174. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1175. req2->error_bit_map[1]);
  1176. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1177. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1178. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1179. done:
  1180. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1181. cqes[0] = (struct kcqe *) &kcqe;
  1182. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1183. return 0;
  1184. }
  1185. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1186. {
  1187. struct cnic_local *cp = dev->cnic_priv;
  1188. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1189. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1190. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1191. cnic_free_dma(dev, &iscsi->hq_info);
  1192. cnic_free_dma(dev, &iscsi->r2tq_info);
  1193. cnic_free_dma(dev, &iscsi->task_array_info);
  1194. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1195. } else {
  1196. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1197. }
  1198. ctx->cid = 0;
  1199. }
  1200. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1201. {
  1202. u32 cid;
  1203. int ret, pages;
  1204. struct cnic_local *cp = dev->cnic_priv;
  1205. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1206. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1207. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1208. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1209. if (cid == -1) {
  1210. ret = -ENOMEM;
  1211. goto error;
  1212. }
  1213. ctx->cid = cid;
  1214. return 0;
  1215. }
  1216. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1217. if (cid == -1) {
  1218. ret = -ENOMEM;
  1219. goto error;
  1220. }
  1221. ctx->cid = cid;
  1222. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1223. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1224. if (ret)
  1225. goto error;
  1226. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1227. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1228. if (ret)
  1229. goto error;
  1230. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1231. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1232. if (ret)
  1233. goto error;
  1234. return 0;
  1235. error:
  1236. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1237. return ret;
  1238. }
  1239. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1240. struct regpair *ctx_addr)
  1241. {
  1242. struct cnic_local *cp = dev->cnic_priv;
  1243. struct cnic_eth_dev *ethdev = cp->ethdev;
  1244. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1245. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1246. unsigned long align_off = 0;
  1247. dma_addr_t ctx_map;
  1248. void *ctx;
  1249. if (cp->ctx_align) {
  1250. unsigned long mask = cp->ctx_align - 1;
  1251. if (cp->ctx_arr[blk].mapping & mask)
  1252. align_off = cp->ctx_align -
  1253. (cp->ctx_arr[blk].mapping & mask);
  1254. }
  1255. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1256. (off * BNX2X_CONTEXT_MEM_SIZE);
  1257. ctx = cp->ctx_arr[blk].ctx + align_off +
  1258. (off * BNX2X_CONTEXT_MEM_SIZE);
  1259. if (init)
  1260. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1261. ctx_addr->lo = ctx_map & 0xffffffff;
  1262. ctx_addr->hi = (u64) ctx_map >> 32;
  1263. return ctx;
  1264. }
  1265. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1266. u32 num)
  1267. {
  1268. struct cnic_local *cp = dev->cnic_priv;
  1269. struct iscsi_kwqe_conn_offload1 *req1 =
  1270. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1271. struct iscsi_kwqe_conn_offload2 *req2 =
  1272. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1273. struct iscsi_kwqe_conn_offload3 *req3;
  1274. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1275. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1276. u32 cid = ctx->cid;
  1277. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1278. struct iscsi_context *ictx;
  1279. struct regpair context_addr;
  1280. int i, j, n = 2, n_max;
  1281. ctx->ctx_flags = 0;
  1282. if (!req2->num_additional_wqes)
  1283. return -EINVAL;
  1284. n_max = req2->num_additional_wqes + 2;
  1285. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1286. if (ictx == NULL)
  1287. return -ENOMEM;
  1288. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1289. ictx->xstorm_ag_context.hq_prod = 1;
  1290. ictx->xstorm_st_context.iscsi.first_burst_length =
  1291. ISCSI_DEF_FIRST_BURST_LEN;
  1292. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1293. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1294. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1295. req1->sq_page_table_addr_lo;
  1296. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1297. req1->sq_page_table_addr_hi;
  1298. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1299. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1300. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1301. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1302. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1303. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1304. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1305. iscsi->hq_info.pgtbl[0];
  1306. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1307. iscsi->hq_info.pgtbl[1];
  1308. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1309. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1310. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1311. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1312. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1313. iscsi->r2tq_info.pgtbl[0];
  1314. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1315. iscsi->r2tq_info.pgtbl[1];
  1316. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1317. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1318. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1319. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1320. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1321. BNX2X_ISCSI_PBL_NOT_CACHED;
  1322. ictx->xstorm_st_context.iscsi.flags.flags |=
  1323. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1324. ictx->xstorm_st_context.iscsi.flags.flags |=
  1325. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1326. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1327. /* TSTORM requires the base address of RQ DB & not PTE */
  1328. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1329. req2->rq_page_table_addr_lo & PAGE_MASK;
  1330. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1331. req2->rq_page_table_addr_hi;
  1332. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1333. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1334. ictx->tstorm_st_context.tcp.flags2 |=
  1335. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1336. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1337. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1338. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1339. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1340. req2->rq_page_table_addr_lo;
  1341. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1342. req2->rq_page_table_addr_hi;
  1343. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1344. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1345. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1346. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1347. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1348. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1349. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1350. iscsi->r2tq_info.pgtbl[0];
  1351. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1352. iscsi->r2tq_info.pgtbl[1];
  1353. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1354. req1->cq_page_table_addr_lo;
  1355. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1356. req1->cq_page_table_addr_hi;
  1357. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1358. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1359. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1360. ictx->ustorm_st_context.task_pbe_cache_index =
  1361. BNX2X_ISCSI_PBL_NOT_CACHED;
  1362. ictx->ustorm_st_context.task_pdu_cache_index =
  1363. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1364. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1365. if (j == 3) {
  1366. if (n >= n_max)
  1367. break;
  1368. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1369. j = 0;
  1370. }
  1371. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1372. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1373. req3->qp_first_pte[j].hi;
  1374. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1375. req3->qp_first_pte[j].lo;
  1376. }
  1377. ictx->ustorm_st_context.task_pbl_base.lo =
  1378. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1379. ictx->ustorm_st_context.task_pbl_base.hi =
  1380. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1381. ictx->ustorm_st_context.tce_phy_addr.lo =
  1382. iscsi->task_array_info.pgtbl[0];
  1383. ictx->ustorm_st_context.tce_phy_addr.hi =
  1384. iscsi->task_array_info.pgtbl[1];
  1385. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1386. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1387. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1388. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1389. ISCSI_DEF_MAX_BURST_LEN;
  1390. ictx->ustorm_st_context.negotiated_rx |=
  1391. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1392. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1393. ictx->cstorm_st_context.hq_pbl_base.lo =
  1394. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1395. ictx->cstorm_st_context.hq_pbl_base.hi =
  1396. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1397. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1398. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1399. ictx->cstorm_st_context.task_pbl_base.lo =
  1400. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1401. ictx->cstorm_st_context.task_pbl_base.hi =
  1402. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1403. /* CSTORM and USTORM initialization is different, CSTORM requires
  1404. * CQ DB base & not PTE addr */
  1405. ictx->cstorm_st_context.cq_db_base.lo =
  1406. req1->cq_page_table_addr_lo & PAGE_MASK;
  1407. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1408. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1409. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1410. for (i = 0; i < cp->num_cqs; i++) {
  1411. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1412. ISCSI_INITIAL_SN;
  1413. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1414. ISCSI_INITIAL_SN;
  1415. }
  1416. ictx->xstorm_ag_context.cdu_reserved =
  1417. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1418. ISCSI_CONNECTION_TYPE);
  1419. ictx->ustorm_ag_context.cdu_usage =
  1420. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1421. ISCSI_CONNECTION_TYPE);
  1422. return 0;
  1423. }
  1424. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1425. u32 num, int *work)
  1426. {
  1427. struct iscsi_kwqe_conn_offload1 *req1;
  1428. struct iscsi_kwqe_conn_offload2 *req2;
  1429. struct cnic_local *cp = dev->cnic_priv;
  1430. struct cnic_context *ctx;
  1431. struct iscsi_kcqe kcqe;
  1432. struct kcqe *cqes[1];
  1433. u32 l5_cid;
  1434. int ret = 0;
  1435. if (num < 2) {
  1436. *work = num;
  1437. return -EINVAL;
  1438. }
  1439. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1440. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1441. if ((num - 2) < req2->num_additional_wqes) {
  1442. *work = num;
  1443. return -EINVAL;
  1444. }
  1445. *work = 2 + req2->num_additional_wqes;
  1446. l5_cid = req1->iscsi_conn_id;
  1447. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1448. return -EINVAL;
  1449. memset(&kcqe, 0, sizeof(kcqe));
  1450. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1451. kcqe.iscsi_conn_id = l5_cid;
  1452. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1453. ctx = &cp->ctx_tbl[l5_cid];
  1454. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1455. kcqe.completion_status =
  1456. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1457. goto done;
  1458. }
  1459. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1460. atomic_dec(&cp->iscsi_conn);
  1461. goto done;
  1462. }
  1463. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1464. if (ret) {
  1465. atomic_dec(&cp->iscsi_conn);
  1466. ret = 0;
  1467. goto done;
  1468. }
  1469. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1470. if (ret < 0) {
  1471. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1472. atomic_dec(&cp->iscsi_conn);
  1473. goto done;
  1474. }
  1475. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1476. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1477. done:
  1478. cqes[0] = (struct kcqe *) &kcqe;
  1479. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1480. return ret;
  1481. }
  1482. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1483. {
  1484. struct cnic_local *cp = dev->cnic_priv;
  1485. struct iscsi_kwqe_conn_update *req =
  1486. (struct iscsi_kwqe_conn_update *) kwqe;
  1487. void *data;
  1488. union l5cm_specific_data l5_data;
  1489. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1490. int ret;
  1491. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1492. return -EINVAL;
  1493. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1494. if (!data)
  1495. return -ENOMEM;
  1496. memcpy(data, kwqe, sizeof(struct kwqe));
  1497. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1498. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1499. return ret;
  1500. }
  1501. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1502. {
  1503. struct cnic_local *cp = dev->cnic_priv;
  1504. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1505. union l5cm_specific_data l5_data;
  1506. int ret;
  1507. u32 hw_cid, type;
  1508. init_waitqueue_head(&ctx->waitq);
  1509. ctx->wait_cond = 0;
  1510. memset(&l5_data, 0, sizeof(l5_data));
  1511. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1512. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1513. & SPE_HDR_CONN_TYPE;
  1514. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1515. SPE_HDR_FUNCTION_ID);
  1516. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1517. hw_cid, type, &l5_data);
  1518. if (ret == 0)
  1519. wait_event(ctx->waitq, ctx->wait_cond);
  1520. return ret;
  1521. }
  1522. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1523. {
  1524. struct cnic_local *cp = dev->cnic_priv;
  1525. struct iscsi_kwqe_conn_destroy *req =
  1526. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1527. u32 l5_cid = req->reserved0;
  1528. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1529. int ret = 0;
  1530. struct iscsi_kcqe kcqe;
  1531. struct kcqe *cqes[1];
  1532. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1533. goto skip_cfc_delete;
  1534. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1535. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1536. if (delta > (2 * HZ))
  1537. delta = 0;
  1538. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1539. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1540. goto destroy_reply;
  1541. }
  1542. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1543. skip_cfc_delete:
  1544. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1545. atomic_dec(&cp->iscsi_conn);
  1546. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1547. destroy_reply:
  1548. memset(&kcqe, 0, sizeof(kcqe));
  1549. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1550. kcqe.iscsi_conn_id = l5_cid;
  1551. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1552. kcqe.iscsi_conn_context_id = req->context_id;
  1553. cqes[0] = (struct kcqe *) &kcqe;
  1554. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1555. return ret;
  1556. }
  1557. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1558. struct l4_kwq_connect_req1 *kwqe1,
  1559. struct l4_kwq_connect_req3 *kwqe3,
  1560. struct l5cm_active_conn_buffer *conn_buf)
  1561. {
  1562. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1563. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1564. &conn_buf->xstorm_conn_buffer;
  1565. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1566. &conn_buf->tstorm_conn_buffer;
  1567. struct regpair context_addr;
  1568. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1569. struct in6_addr src_ip, dst_ip;
  1570. int i;
  1571. u32 *addrp;
  1572. addrp = (u32 *) &conn_addr->local_ip_addr;
  1573. for (i = 0; i < 4; i++, addrp++)
  1574. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1575. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1576. for (i = 0; i < 4; i++, addrp++)
  1577. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1578. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1579. xstorm_buf->context_addr.hi = context_addr.hi;
  1580. xstorm_buf->context_addr.lo = context_addr.lo;
  1581. xstorm_buf->mss = 0xffff;
  1582. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1583. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1584. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1585. xstorm_buf->pseudo_header_checksum =
  1586. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1587. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1588. tstorm_buf->params |=
  1589. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1590. if (kwqe3->ka_timeout) {
  1591. tstorm_buf->ka_enable = 1;
  1592. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1593. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1594. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1595. }
  1596. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1597. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1598. tstorm_buf->max_rt_time = 0xffffffff;
  1599. }
  1600. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1601. {
  1602. struct cnic_local *cp = dev->cnic_priv;
  1603. u32 pfid = cp->pfid;
  1604. u8 *mac = dev->mac_addr;
  1605. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1606. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1607. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1608. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1609. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1610. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1611. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1612. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1613. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1614. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1615. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1616. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1617. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1618. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1619. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1620. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1621. mac[4]);
  1622. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1623. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1624. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1625. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1626. mac[2]);
  1627. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1628. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1629. mac[1]);
  1630. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1631. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1632. mac[0]);
  1633. }
  1634. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1635. {
  1636. struct cnic_local *cp = dev->cnic_priv;
  1637. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1638. u16 tstorm_flags = 0;
  1639. if (tcp_ts) {
  1640. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1641. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1642. }
  1643. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1644. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1645. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1646. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1647. }
  1648. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1649. u32 num, int *work)
  1650. {
  1651. struct cnic_local *cp = dev->cnic_priv;
  1652. struct l4_kwq_connect_req1 *kwqe1 =
  1653. (struct l4_kwq_connect_req1 *) wqes[0];
  1654. struct l4_kwq_connect_req3 *kwqe3;
  1655. struct l5cm_active_conn_buffer *conn_buf;
  1656. struct l5cm_conn_addr_params *conn_addr;
  1657. union l5cm_specific_data l5_data;
  1658. u32 l5_cid = kwqe1->pg_cid;
  1659. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1660. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1661. int ret;
  1662. if (num < 2) {
  1663. *work = num;
  1664. return -EINVAL;
  1665. }
  1666. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1667. *work = 3;
  1668. else
  1669. *work = 2;
  1670. if (num < *work) {
  1671. *work = num;
  1672. return -EINVAL;
  1673. }
  1674. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1675. netdev_err(dev->netdev, "conn_buf size too big\n");
  1676. return -ENOMEM;
  1677. }
  1678. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1679. if (!conn_buf)
  1680. return -ENOMEM;
  1681. memset(conn_buf, 0, sizeof(*conn_buf));
  1682. conn_addr = &conn_buf->conn_addr_buf;
  1683. conn_addr->remote_addr_0 = csk->ha[0];
  1684. conn_addr->remote_addr_1 = csk->ha[1];
  1685. conn_addr->remote_addr_2 = csk->ha[2];
  1686. conn_addr->remote_addr_3 = csk->ha[3];
  1687. conn_addr->remote_addr_4 = csk->ha[4];
  1688. conn_addr->remote_addr_5 = csk->ha[5];
  1689. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1690. struct l4_kwq_connect_req2 *kwqe2 =
  1691. (struct l4_kwq_connect_req2 *) wqes[1];
  1692. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1693. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1694. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1695. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1696. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1697. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1698. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1699. }
  1700. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1701. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1702. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1703. conn_addr->local_tcp_port = kwqe1->src_port;
  1704. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1705. conn_addr->pmtu = kwqe3->pmtu;
  1706. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1707. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1708. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1709. cnic_bnx2x_set_tcp_timestamp(dev,
  1710. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1711. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1712. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1713. if (!ret)
  1714. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1715. return ret;
  1716. }
  1717. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1718. {
  1719. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1720. union l5cm_specific_data l5_data;
  1721. int ret;
  1722. memset(&l5_data, 0, sizeof(l5_data));
  1723. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1724. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1725. return ret;
  1726. }
  1727. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1728. {
  1729. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1730. union l5cm_specific_data l5_data;
  1731. int ret;
  1732. memset(&l5_data, 0, sizeof(l5_data));
  1733. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1734. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1735. return ret;
  1736. }
  1737. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1738. {
  1739. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1740. struct l4_kcq kcqe;
  1741. struct kcqe *cqes[1];
  1742. memset(&kcqe, 0, sizeof(kcqe));
  1743. kcqe.pg_host_opaque = req->host_opaque;
  1744. kcqe.pg_cid = req->host_opaque;
  1745. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1746. cqes[0] = (struct kcqe *) &kcqe;
  1747. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1748. return 0;
  1749. }
  1750. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1751. {
  1752. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1753. struct l4_kcq kcqe;
  1754. struct kcqe *cqes[1];
  1755. memset(&kcqe, 0, sizeof(kcqe));
  1756. kcqe.pg_host_opaque = req->pg_host_opaque;
  1757. kcqe.pg_cid = req->pg_cid;
  1758. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1759. cqes[0] = (struct kcqe *) &kcqe;
  1760. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1761. return 0;
  1762. }
  1763. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1764. {
  1765. struct fcoe_kwqe_stat *req;
  1766. struct fcoe_stat_ramrod_params *fcoe_stat;
  1767. union l5cm_specific_data l5_data;
  1768. struct cnic_local *cp = dev->cnic_priv;
  1769. int ret;
  1770. u32 cid;
  1771. req = (struct fcoe_kwqe_stat *) kwqe;
  1772. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1773. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1774. if (!fcoe_stat)
  1775. return -ENOMEM;
  1776. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1777. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1778. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
  1779. FCOE_CONNECTION_TYPE, &l5_data);
  1780. return ret;
  1781. }
  1782. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1783. u32 num, int *work)
  1784. {
  1785. int ret;
  1786. struct cnic_local *cp = dev->cnic_priv;
  1787. u32 cid;
  1788. struct fcoe_init_ramrod_params *fcoe_init;
  1789. struct fcoe_kwqe_init1 *req1;
  1790. struct fcoe_kwqe_init2 *req2;
  1791. struct fcoe_kwqe_init3 *req3;
  1792. union l5cm_specific_data l5_data;
  1793. if (num < 3) {
  1794. *work = num;
  1795. return -EINVAL;
  1796. }
  1797. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1798. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1799. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1800. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1801. *work = 1;
  1802. return -EINVAL;
  1803. }
  1804. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1805. *work = 2;
  1806. return -EINVAL;
  1807. }
  1808. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1809. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1810. return -ENOMEM;
  1811. }
  1812. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1813. if (!fcoe_init)
  1814. return -ENOMEM;
  1815. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1816. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1817. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1818. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1819. fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
  1820. fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
  1821. fcoe_init->eq_next_page_addr.lo =
  1822. cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
  1823. fcoe_init->eq_next_page_addr.hi =
  1824. (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
  1825. fcoe_init->sb_num = cp->status_blk_num;
  1826. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1827. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1828. cp->kcq2.sw_prod_idx = 0;
  1829. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1830. printk(KERN_ERR "bdbg: submitting INIT RAMROD \n");
  1831. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
  1832. FCOE_CONNECTION_TYPE, &l5_data);
  1833. *work = 3;
  1834. return ret;
  1835. }
  1836. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1837. u32 num, int *work)
  1838. {
  1839. int ret = 0;
  1840. u32 cid = -1, l5_cid;
  1841. struct cnic_local *cp = dev->cnic_priv;
  1842. struct fcoe_kwqe_conn_offload1 *req1;
  1843. struct fcoe_kwqe_conn_offload2 *req2;
  1844. struct fcoe_kwqe_conn_offload3 *req3;
  1845. struct fcoe_kwqe_conn_offload4 *req4;
  1846. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1847. struct cnic_context *ctx;
  1848. struct fcoe_context *fctx;
  1849. struct regpair ctx_addr;
  1850. union l5cm_specific_data l5_data;
  1851. struct fcoe_kcqe kcqe;
  1852. struct kcqe *cqes[1];
  1853. if (num < 4) {
  1854. *work = num;
  1855. return -EINVAL;
  1856. }
  1857. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1858. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1859. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1860. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1861. *work = 4;
  1862. l5_cid = req1->fcoe_conn_id;
  1863. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1864. goto err_reply;
  1865. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1866. ctx = &cp->ctx_tbl[l5_cid];
  1867. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1868. goto err_reply;
  1869. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1870. if (ret) {
  1871. ret = 0;
  1872. goto err_reply;
  1873. }
  1874. cid = ctx->cid;
  1875. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1876. if (fctx) {
  1877. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1878. u32 val;
  1879. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1880. FCOE_CONNECTION_TYPE);
  1881. fctx->xstorm_ag_context.cdu_reserved = val;
  1882. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1883. FCOE_CONNECTION_TYPE);
  1884. fctx->ustorm_ag_context.cdu_usage = val;
  1885. }
  1886. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1887. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1888. goto err_reply;
  1889. }
  1890. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1891. if (!fcoe_offload)
  1892. goto err_reply;
  1893. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1894. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1895. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1896. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1897. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1898. cid = BNX2X_HW_CID(cp, cid);
  1899. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1900. FCOE_CONNECTION_TYPE, &l5_data);
  1901. if (!ret)
  1902. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1903. return ret;
  1904. err_reply:
  1905. if (cid != -1)
  1906. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1907. memset(&kcqe, 0, sizeof(kcqe));
  1908. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1909. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1910. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1911. cqes[0] = (struct kcqe *) &kcqe;
  1912. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1913. return ret;
  1914. }
  1915. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1916. {
  1917. struct fcoe_kwqe_conn_enable_disable *req;
  1918. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1919. union l5cm_specific_data l5_data;
  1920. int ret;
  1921. u32 cid, l5_cid;
  1922. struct cnic_local *cp = dev->cnic_priv;
  1923. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1924. cid = req->context_id;
  1925. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1926. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1927. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1928. return -ENOMEM;
  1929. }
  1930. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1931. if (!fcoe_enable)
  1932. return -ENOMEM;
  1933. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1934. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1935. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1936. FCOE_CONNECTION_TYPE, &l5_data);
  1937. return ret;
  1938. }
  1939. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1940. {
  1941. struct fcoe_kwqe_conn_enable_disable *req;
  1942. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1943. union l5cm_specific_data l5_data;
  1944. int ret;
  1945. u32 cid, l5_cid;
  1946. struct cnic_local *cp = dev->cnic_priv;
  1947. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1948. cid = req->context_id;
  1949. l5_cid = req->conn_id;
  1950. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1951. return -EINVAL;
  1952. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1953. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1954. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1955. return -ENOMEM;
  1956. }
  1957. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1958. if (!fcoe_disable)
  1959. return -ENOMEM;
  1960. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1961. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  1962. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  1963. FCOE_CONNECTION_TYPE, &l5_data);
  1964. return ret;
  1965. }
  1966. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1967. {
  1968. struct fcoe_kwqe_conn_destroy *req;
  1969. union l5cm_specific_data l5_data;
  1970. int ret;
  1971. u32 cid, l5_cid;
  1972. struct cnic_local *cp = dev->cnic_priv;
  1973. struct cnic_context *ctx;
  1974. struct fcoe_kcqe kcqe;
  1975. struct kcqe *cqes[1];
  1976. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  1977. cid = req->context_id;
  1978. l5_cid = req->conn_id;
  1979. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1980. return -EINVAL;
  1981. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1982. ctx = &cp->ctx_tbl[l5_cid];
  1983. init_waitqueue_head(&ctx->waitq);
  1984. ctx->wait_cond = 0;
  1985. memset(&l5_data, 0, sizeof(l5_data));
  1986. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  1987. FCOE_CONNECTION_TYPE, &l5_data);
  1988. if (ret == 0) {
  1989. wait_event(ctx->waitq, ctx->wait_cond);
  1990. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1991. queue_delayed_work(cnic_wq, &cp->delete_task,
  1992. msecs_to_jiffies(2000));
  1993. }
  1994. memset(&kcqe, 0, sizeof(kcqe));
  1995. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  1996. kcqe.fcoe_conn_id = req->conn_id;
  1997. kcqe.fcoe_conn_context_id = cid;
  1998. cqes[0] = (struct kcqe *) &kcqe;
  1999. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2000. return ret;
  2001. }
  2002. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2003. {
  2004. struct fcoe_kwqe_destroy *req;
  2005. union l5cm_specific_data l5_data;
  2006. struct cnic_local *cp = dev->cnic_priv;
  2007. int ret;
  2008. u32 cid;
  2009. req = (struct fcoe_kwqe_destroy *) kwqe;
  2010. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2011. memset(&l5_data, 0, sizeof(l5_data));
  2012. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
  2013. FCOE_CONNECTION_TYPE, &l5_data);
  2014. return ret;
  2015. }
  2016. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2017. struct kwqe *wqes[], u32 num_wqes)
  2018. {
  2019. int i, work, ret;
  2020. u32 opcode;
  2021. struct kwqe *kwqe;
  2022. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2023. return -EAGAIN; /* bnx2 is down */
  2024. for (i = 0; i < num_wqes; ) {
  2025. kwqe = wqes[i];
  2026. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2027. work = 1;
  2028. switch (opcode) {
  2029. case ISCSI_KWQE_OPCODE_INIT1:
  2030. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2031. break;
  2032. case ISCSI_KWQE_OPCODE_INIT2:
  2033. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2034. break;
  2035. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2036. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2037. num_wqes - i, &work);
  2038. break;
  2039. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2040. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2041. break;
  2042. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2043. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2044. break;
  2045. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2046. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2047. &work);
  2048. break;
  2049. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2050. ret = cnic_bnx2x_close(dev, kwqe);
  2051. break;
  2052. case L4_KWQE_OPCODE_VALUE_RESET:
  2053. ret = cnic_bnx2x_reset(dev, kwqe);
  2054. break;
  2055. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2056. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2057. break;
  2058. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2059. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2060. break;
  2061. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2062. ret = 0;
  2063. break;
  2064. default:
  2065. ret = 0;
  2066. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2067. opcode);
  2068. break;
  2069. }
  2070. if (ret < 0)
  2071. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2072. opcode);
  2073. i += work;
  2074. }
  2075. return 0;
  2076. }
  2077. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2078. struct kwqe *wqes[], u32 num_wqes)
  2079. {
  2080. struct cnic_local *cp = dev->cnic_priv;
  2081. int i, work, ret;
  2082. u32 opcode;
  2083. struct kwqe *kwqe;
  2084. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2085. return -EAGAIN; /* bnx2 is down */
  2086. if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
  2087. return -EINVAL;
  2088. for (i = 0; i < num_wqes; ) {
  2089. kwqe = wqes[i];
  2090. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2091. work = 1;
  2092. switch (opcode) {
  2093. case FCOE_KWQE_OPCODE_INIT1:
  2094. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2095. num_wqes - i, &work);
  2096. break;
  2097. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2098. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2099. num_wqes - i, &work);
  2100. break;
  2101. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2102. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2103. break;
  2104. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2105. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2106. break;
  2107. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2108. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2109. break;
  2110. case FCOE_KWQE_OPCODE_DESTROY:
  2111. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2112. break;
  2113. case FCOE_KWQE_OPCODE_STAT:
  2114. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2115. break;
  2116. default:
  2117. ret = 0;
  2118. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2119. opcode);
  2120. break;
  2121. }
  2122. if (ret < 0)
  2123. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2124. opcode);
  2125. i += work;
  2126. }
  2127. return 0;
  2128. }
  2129. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2130. u32 num_wqes)
  2131. {
  2132. int ret = -EINVAL;
  2133. u32 layer_code;
  2134. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2135. return -EAGAIN; /* bnx2x is down */
  2136. if (!num_wqes)
  2137. return 0;
  2138. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2139. switch (layer_code) {
  2140. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2141. case KWQE_FLAGS_LAYER_MASK_L4:
  2142. case KWQE_FLAGS_LAYER_MASK_L2:
  2143. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2144. break;
  2145. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2146. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2147. break;
  2148. }
  2149. return ret;
  2150. }
  2151. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2152. {
  2153. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2154. return KCQE_FLAGS_LAYER_MASK_L4;
  2155. return opflag & KCQE_FLAGS_LAYER_MASK;
  2156. }
  2157. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2158. {
  2159. struct cnic_local *cp = dev->cnic_priv;
  2160. int i, j, comp = 0;
  2161. i = 0;
  2162. j = 1;
  2163. while (num_cqes) {
  2164. struct cnic_ulp_ops *ulp_ops;
  2165. int ulp_type;
  2166. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2167. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2168. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2169. comp++;
  2170. while (j < num_cqes) {
  2171. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2172. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2173. break;
  2174. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2175. comp++;
  2176. j++;
  2177. }
  2178. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2179. ulp_type = CNIC_ULP_RDMA;
  2180. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2181. ulp_type = CNIC_ULP_ISCSI;
  2182. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2183. ulp_type = CNIC_ULP_FCOE;
  2184. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2185. ulp_type = CNIC_ULP_L4;
  2186. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2187. goto end;
  2188. else {
  2189. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2190. kcqe_op_flag);
  2191. goto end;
  2192. }
  2193. rcu_read_lock();
  2194. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2195. if (likely(ulp_ops)) {
  2196. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2197. cp->completed_kcq + i, j);
  2198. }
  2199. rcu_read_unlock();
  2200. end:
  2201. num_cqes -= j;
  2202. i += j;
  2203. j = 1;
  2204. }
  2205. if (unlikely(comp))
  2206. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2207. }
  2208. static u16 cnic_bnx2_next_idx(u16 idx)
  2209. {
  2210. return idx + 1;
  2211. }
  2212. static u16 cnic_bnx2_hw_idx(u16 idx)
  2213. {
  2214. return idx;
  2215. }
  2216. static u16 cnic_bnx2x_next_idx(u16 idx)
  2217. {
  2218. idx++;
  2219. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2220. idx++;
  2221. return idx;
  2222. }
  2223. static u16 cnic_bnx2x_hw_idx(u16 idx)
  2224. {
  2225. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2226. idx++;
  2227. return idx;
  2228. }
  2229. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2230. {
  2231. struct cnic_local *cp = dev->cnic_priv;
  2232. u16 i, ri, hw_prod, last;
  2233. struct kcqe *kcqe;
  2234. int kcqe_cnt = 0, last_cnt = 0;
  2235. i = ri = last = info->sw_prod_idx;
  2236. ri &= MAX_KCQ_IDX;
  2237. hw_prod = *info->hw_prod_idx_ptr;
  2238. hw_prod = cp->hw_idx(hw_prod);
  2239. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2240. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2241. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2242. i = cp->next_idx(i);
  2243. ri = i & MAX_KCQ_IDX;
  2244. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2245. last_cnt = kcqe_cnt;
  2246. last = i;
  2247. }
  2248. }
  2249. info->sw_prod_idx = last;
  2250. return last_cnt;
  2251. }
  2252. static int cnic_l2_completion(struct cnic_local *cp)
  2253. {
  2254. u16 hw_cons, sw_cons;
  2255. struct cnic_uio_dev *udev = cp->udev;
  2256. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2257. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2258. u32 cmd;
  2259. int comp = 0;
  2260. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2261. return 0;
  2262. hw_cons = *cp->rx_cons_ptr;
  2263. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2264. hw_cons++;
  2265. sw_cons = cp->rx_cons;
  2266. while (sw_cons != hw_cons) {
  2267. u8 cqe_fp_flags;
  2268. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2269. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2270. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2271. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2272. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2273. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2274. cmd == RAMROD_CMD_ID_ETH_HALT)
  2275. comp++;
  2276. }
  2277. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2278. }
  2279. return comp;
  2280. }
  2281. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2282. {
  2283. u16 rx_cons, tx_cons;
  2284. int comp = 0;
  2285. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2286. return;
  2287. rx_cons = *cp->rx_cons_ptr;
  2288. tx_cons = *cp->tx_cons_ptr;
  2289. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2290. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2291. comp = cnic_l2_completion(cp);
  2292. cp->tx_cons = tx_cons;
  2293. cp->rx_cons = rx_cons;
  2294. if (cp->udev)
  2295. uio_event_notify(&cp->udev->cnic_uinfo);
  2296. }
  2297. if (comp)
  2298. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2299. }
  2300. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2301. {
  2302. struct cnic_local *cp = dev->cnic_priv;
  2303. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2304. int kcqe_cnt;
  2305. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2306. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2307. service_kcqes(dev, kcqe_cnt);
  2308. /* Tell compiler that status_blk fields can change. */
  2309. barrier();
  2310. if (status_idx != *cp->kcq1.status_idx_ptr) {
  2311. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2312. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2313. } else
  2314. break;
  2315. }
  2316. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2317. cnic_chk_pkt_rings(cp);
  2318. return status_idx;
  2319. }
  2320. static int cnic_service_bnx2(void *data, void *status_blk)
  2321. {
  2322. struct cnic_dev *dev = data;
  2323. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2324. struct status_block *sblk = status_blk;
  2325. return sblk->status_idx;
  2326. }
  2327. return cnic_service_bnx2_queues(dev);
  2328. }
  2329. static void cnic_service_bnx2_msix(unsigned long data)
  2330. {
  2331. struct cnic_dev *dev = (struct cnic_dev *) data;
  2332. struct cnic_local *cp = dev->cnic_priv;
  2333. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2334. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2335. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2336. }
  2337. static void cnic_doirq(struct cnic_dev *dev)
  2338. {
  2339. struct cnic_local *cp = dev->cnic_priv;
  2340. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2341. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2342. prefetch(cp->status_blk.gen);
  2343. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2344. tasklet_schedule(&cp->cnic_irq_task);
  2345. }
  2346. }
  2347. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2348. {
  2349. struct cnic_dev *dev = dev_instance;
  2350. struct cnic_local *cp = dev->cnic_priv;
  2351. if (cp->ack_int)
  2352. cp->ack_int(dev);
  2353. cnic_doirq(dev);
  2354. return IRQ_HANDLED;
  2355. }
  2356. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2357. u16 index, u8 op, u8 update)
  2358. {
  2359. struct cnic_local *cp = dev->cnic_priv;
  2360. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2361. COMMAND_REG_INT_ACK);
  2362. struct igu_ack_register igu_ack;
  2363. igu_ack.status_block_index = index;
  2364. igu_ack.sb_id_and_flags =
  2365. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2366. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2367. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2368. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2369. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2370. }
  2371. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2372. u16 index, u8 op, u8 update)
  2373. {
  2374. struct igu_regular cmd_data;
  2375. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2376. cmd_data.sb_id_and_flags =
  2377. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2378. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2379. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2380. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2381. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2382. }
  2383. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2384. {
  2385. struct cnic_local *cp = dev->cnic_priv;
  2386. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2387. IGU_INT_DISABLE, 0);
  2388. }
  2389. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2390. {
  2391. struct cnic_local *cp = dev->cnic_priv;
  2392. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2393. IGU_INT_DISABLE, 0);
  2394. }
  2395. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2396. {
  2397. u32 last_status = *info->status_idx_ptr;
  2398. int kcqe_cnt;
  2399. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2400. service_kcqes(dev, kcqe_cnt);
  2401. /* Tell compiler that sblk fields can change. */
  2402. barrier();
  2403. if (last_status == *info->status_idx_ptr)
  2404. break;
  2405. last_status = *info->status_idx_ptr;
  2406. }
  2407. return last_status;
  2408. }
  2409. static void cnic_service_bnx2x_bh(unsigned long data)
  2410. {
  2411. struct cnic_dev *dev = (struct cnic_dev *) data;
  2412. struct cnic_local *cp = dev->cnic_priv;
  2413. u32 status_idx;
  2414. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2415. return;
  2416. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2417. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2418. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  2419. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2420. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2421. MAX_KCQ_IDX);
  2422. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2423. status_idx, IGU_INT_ENABLE, 1);
  2424. } else {
  2425. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2426. status_idx, IGU_INT_ENABLE, 1);
  2427. }
  2428. }
  2429. static int cnic_service_bnx2x(void *data, void *status_blk)
  2430. {
  2431. struct cnic_dev *dev = data;
  2432. struct cnic_local *cp = dev->cnic_priv;
  2433. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2434. cnic_doirq(dev);
  2435. cnic_chk_pkt_rings(cp);
  2436. return 0;
  2437. }
  2438. static void cnic_ulp_stop(struct cnic_dev *dev)
  2439. {
  2440. struct cnic_local *cp = dev->cnic_priv;
  2441. int if_type;
  2442. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2443. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2444. struct cnic_ulp_ops *ulp_ops;
  2445. mutex_lock(&cnic_lock);
  2446. ulp_ops = cp->ulp_ops[if_type];
  2447. if (!ulp_ops) {
  2448. mutex_unlock(&cnic_lock);
  2449. continue;
  2450. }
  2451. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2452. mutex_unlock(&cnic_lock);
  2453. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2454. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2455. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2456. }
  2457. }
  2458. static void cnic_ulp_start(struct cnic_dev *dev)
  2459. {
  2460. struct cnic_local *cp = dev->cnic_priv;
  2461. int if_type;
  2462. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2463. struct cnic_ulp_ops *ulp_ops;
  2464. mutex_lock(&cnic_lock);
  2465. ulp_ops = cp->ulp_ops[if_type];
  2466. if (!ulp_ops || !ulp_ops->cnic_start) {
  2467. mutex_unlock(&cnic_lock);
  2468. continue;
  2469. }
  2470. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2471. mutex_unlock(&cnic_lock);
  2472. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2473. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2474. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2475. }
  2476. }
  2477. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2478. {
  2479. struct cnic_dev *dev = data;
  2480. switch (info->cmd) {
  2481. case CNIC_CTL_STOP_CMD:
  2482. cnic_hold(dev);
  2483. cnic_ulp_stop(dev);
  2484. cnic_stop_hw(dev);
  2485. cnic_put(dev);
  2486. break;
  2487. case CNIC_CTL_START_CMD:
  2488. cnic_hold(dev);
  2489. if (!cnic_start_hw(dev))
  2490. cnic_ulp_start(dev);
  2491. cnic_put(dev);
  2492. break;
  2493. case CNIC_CTL_COMPLETION_CMD: {
  2494. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2495. u32 l5_cid;
  2496. struct cnic_local *cp = dev->cnic_priv;
  2497. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2498. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2499. ctx->wait_cond = 1;
  2500. wake_up(&ctx->waitq);
  2501. }
  2502. break;
  2503. }
  2504. default:
  2505. return -EINVAL;
  2506. }
  2507. return 0;
  2508. }
  2509. static void cnic_ulp_init(struct cnic_dev *dev)
  2510. {
  2511. int i;
  2512. struct cnic_local *cp = dev->cnic_priv;
  2513. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2514. struct cnic_ulp_ops *ulp_ops;
  2515. mutex_lock(&cnic_lock);
  2516. ulp_ops = cnic_ulp_tbl[i];
  2517. if (!ulp_ops || !ulp_ops->cnic_init) {
  2518. mutex_unlock(&cnic_lock);
  2519. continue;
  2520. }
  2521. ulp_get(ulp_ops);
  2522. mutex_unlock(&cnic_lock);
  2523. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2524. ulp_ops->cnic_init(dev);
  2525. ulp_put(ulp_ops);
  2526. }
  2527. }
  2528. static void cnic_ulp_exit(struct cnic_dev *dev)
  2529. {
  2530. int i;
  2531. struct cnic_local *cp = dev->cnic_priv;
  2532. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2533. struct cnic_ulp_ops *ulp_ops;
  2534. mutex_lock(&cnic_lock);
  2535. ulp_ops = cnic_ulp_tbl[i];
  2536. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2537. mutex_unlock(&cnic_lock);
  2538. continue;
  2539. }
  2540. ulp_get(ulp_ops);
  2541. mutex_unlock(&cnic_lock);
  2542. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2543. ulp_ops->cnic_exit(dev);
  2544. ulp_put(ulp_ops);
  2545. }
  2546. }
  2547. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2548. {
  2549. struct cnic_dev *dev = csk->dev;
  2550. struct l4_kwq_offload_pg *l4kwqe;
  2551. struct kwqe *wqes[1];
  2552. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2553. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2554. wqes[0] = (struct kwqe *) l4kwqe;
  2555. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2556. l4kwqe->flags =
  2557. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2558. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2559. l4kwqe->da0 = csk->ha[0];
  2560. l4kwqe->da1 = csk->ha[1];
  2561. l4kwqe->da2 = csk->ha[2];
  2562. l4kwqe->da3 = csk->ha[3];
  2563. l4kwqe->da4 = csk->ha[4];
  2564. l4kwqe->da5 = csk->ha[5];
  2565. l4kwqe->sa0 = dev->mac_addr[0];
  2566. l4kwqe->sa1 = dev->mac_addr[1];
  2567. l4kwqe->sa2 = dev->mac_addr[2];
  2568. l4kwqe->sa3 = dev->mac_addr[3];
  2569. l4kwqe->sa4 = dev->mac_addr[4];
  2570. l4kwqe->sa5 = dev->mac_addr[5];
  2571. l4kwqe->etype = ETH_P_IP;
  2572. l4kwqe->ipid_start = DEF_IPID_START;
  2573. l4kwqe->host_opaque = csk->l5_cid;
  2574. if (csk->vlan_id) {
  2575. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2576. l4kwqe->vlan_tag = csk->vlan_id;
  2577. l4kwqe->l2hdr_nbytes += 4;
  2578. }
  2579. return dev->submit_kwqes(dev, wqes, 1);
  2580. }
  2581. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2582. {
  2583. struct cnic_dev *dev = csk->dev;
  2584. struct l4_kwq_update_pg *l4kwqe;
  2585. struct kwqe *wqes[1];
  2586. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2587. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2588. wqes[0] = (struct kwqe *) l4kwqe;
  2589. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2590. l4kwqe->flags =
  2591. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2592. l4kwqe->pg_cid = csk->pg_cid;
  2593. l4kwqe->da0 = csk->ha[0];
  2594. l4kwqe->da1 = csk->ha[1];
  2595. l4kwqe->da2 = csk->ha[2];
  2596. l4kwqe->da3 = csk->ha[3];
  2597. l4kwqe->da4 = csk->ha[4];
  2598. l4kwqe->da5 = csk->ha[5];
  2599. l4kwqe->pg_host_opaque = csk->l5_cid;
  2600. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2601. return dev->submit_kwqes(dev, wqes, 1);
  2602. }
  2603. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2604. {
  2605. struct cnic_dev *dev = csk->dev;
  2606. struct l4_kwq_upload *l4kwqe;
  2607. struct kwqe *wqes[1];
  2608. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2609. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2610. wqes[0] = (struct kwqe *) l4kwqe;
  2611. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2612. l4kwqe->flags =
  2613. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2614. l4kwqe->cid = csk->pg_cid;
  2615. return dev->submit_kwqes(dev, wqes, 1);
  2616. }
  2617. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2618. {
  2619. struct cnic_dev *dev = csk->dev;
  2620. struct l4_kwq_connect_req1 *l4kwqe1;
  2621. struct l4_kwq_connect_req2 *l4kwqe2;
  2622. struct l4_kwq_connect_req3 *l4kwqe3;
  2623. struct kwqe *wqes[3];
  2624. u8 tcp_flags = 0;
  2625. int num_wqes = 2;
  2626. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2627. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2628. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2629. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2630. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2631. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2632. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2633. l4kwqe3->flags =
  2634. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2635. l4kwqe3->ka_timeout = csk->ka_timeout;
  2636. l4kwqe3->ka_interval = csk->ka_interval;
  2637. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2638. l4kwqe3->tos = csk->tos;
  2639. l4kwqe3->ttl = csk->ttl;
  2640. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2641. l4kwqe3->pmtu = csk->mtu;
  2642. l4kwqe3->rcv_buf = csk->rcv_buf;
  2643. l4kwqe3->snd_buf = csk->snd_buf;
  2644. l4kwqe3->seed = csk->seed;
  2645. wqes[0] = (struct kwqe *) l4kwqe1;
  2646. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2647. wqes[1] = (struct kwqe *) l4kwqe2;
  2648. wqes[2] = (struct kwqe *) l4kwqe3;
  2649. num_wqes = 3;
  2650. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2651. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2652. l4kwqe2->flags =
  2653. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2654. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2655. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2656. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2657. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2658. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2659. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2660. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2661. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2662. sizeof(struct tcphdr);
  2663. } else {
  2664. wqes[1] = (struct kwqe *) l4kwqe3;
  2665. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2666. sizeof(struct tcphdr);
  2667. }
  2668. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2669. l4kwqe1->flags =
  2670. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2671. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2672. l4kwqe1->cid = csk->cid;
  2673. l4kwqe1->pg_cid = csk->pg_cid;
  2674. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2675. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2676. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2677. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2678. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2679. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2680. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2681. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2682. if (csk->tcp_flags & SK_TCP_NAGLE)
  2683. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2684. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2685. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2686. if (csk->tcp_flags & SK_TCP_SACK)
  2687. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2688. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2689. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2690. l4kwqe1->tcp_flags = tcp_flags;
  2691. return dev->submit_kwqes(dev, wqes, num_wqes);
  2692. }
  2693. static int cnic_cm_close_req(struct cnic_sock *csk)
  2694. {
  2695. struct cnic_dev *dev = csk->dev;
  2696. struct l4_kwq_close_req *l4kwqe;
  2697. struct kwqe *wqes[1];
  2698. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2699. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2700. wqes[0] = (struct kwqe *) l4kwqe;
  2701. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2702. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2703. l4kwqe->cid = csk->cid;
  2704. return dev->submit_kwqes(dev, wqes, 1);
  2705. }
  2706. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2707. {
  2708. struct cnic_dev *dev = csk->dev;
  2709. struct l4_kwq_reset_req *l4kwqe;
  2710. struct kwqe *wqes[1];
  2711. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2712. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2713. wqes[0] = (struct kwqe *) l4kwqe;
  2714. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2715. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2716. l4kwqe->cid = csk->cid;
  2717. return dev->submit_kwqes(dev, wqes, 1);
  2718. }
  2719. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2720. u32 l5_cid, struct cnic_sock **csk, void *context)
  2721. {
  2722. struct cnic_local *cp = dev->cnic_priv;
  2723. struct cnic_sock *csk1;
  2724. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2725. return -EINVAL;
  2726. if (cp->ctx_tbl) {
  2727. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2728. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2729. return -EAGAIN;
  2730. }
  2731. csk1 = &cp->csk_tbl[l5_cid];
  2732. if (atomic_read(&csk1->ref_count))
  2733. return -EAGAIN;
  2734. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2735. return -EBUSY;
  2736. csk1->dev = dev;
  2737. csk1->cid = cid;
  2738. csk1->l5_cid = l5_cid;
  2739. csk1->ulp_type = ulp_type;
  2740. csk1->context = context;
  2741. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2742. csk1->ka_interval = DEF_KA_INTERVAL;
  2743. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2744. csk1->tos = DEF_TOS;
  2745. csk1->ttl = DEF_TTL;
  2746. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2747. csk1->rcv_buf = DEF_RCV_BUF;
  2748. csk1->snd_buf = DEF_SND_BUF;
  2749. csk1->seed = DEF_SEED;
  2750. *csk = csk1;
  2751. return 0;
  2752. }
  2753. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2754. {
  2755. if (csk->src_port) {
  2756. struct cnic_dev *dev = csk->dev;
  2757. struct cnic_local *cp = dev->cnic_priv;
  2758. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2759. csk->src_port = 0;
  2760. }
  2761. }
  2762. static void cnic_close_conn(struct cnic_sock *csk)
  2763. {
  2764. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2765. cnic_cm_upload_pg(csk);
  2766. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2767. }
  2768. cnic_cm_cleanup(csk);
  2769. }
  2770. static int cnic_cm_destroy(struct cnic_sock *csk)
  2771. {
  2772. if (!cnic_in_use(csk))
  2773. return -EINVAL;
  2774. csk_hold(csk);
  2775. clear_bit(SK_F_INUSE, &csk->flags);
  2776. smp_mb__after_clear_bit();
  2777. while (atomic_read(&csk->ref_count) != 1)
  2778. msleep(1);
  2779. cnic_cm_cleanup(csk);
  2780. csk->flags = 0;
  2781. csk_put(csk);
  2782. return 0;
  2783. }
  2784. static inline u16 cnic_get_vlan(struct net_device *dev,
  2785. struct net_device **vlan_dev)
  2786. {
  2787. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2788. *vlan_dev = vlan_dev_real_dev(dev);
  2789. return vlan_dev_vlan_id(dev);
  2790. }
  2791. *vlan_dev = dev;
  2792. return 0;
  2793. }
  2794. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2795. struct dst_entry **dst)
  2796. {
  2797. #if defined(CONFIG_INET)
  2798. struct flowi fl;
  2799. int err;
  2800. struct rtable *rt;
  2801. memset(&fl, 0, sizeof(fl));
  2802. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2803. err = ip_route_output_key(&init_net, &rt, &fl);
  2804. if (!err)
  2805. *dst = &rt->dst;
  2806. return err;
  2807. #else
  2808. return -ENETUNREACH;
  2809. #endif
  2810. }
  2811. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2812. struct dst_entry **dst)
  2813. {
  2814. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2815. struct flowi fl;
  2816. memset(&fl, 0, sizeof(fl));
  2817. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2818. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2819. fl.oif = dst_addr->sin6_scope_id;
  2820. *dst = ip6_route_output(&init_net, NULL, &fl);
  2821. if (*dst)
  2822. return 0;
  2823. #endif
  2824. return -ENETUNREACH;
  2825. }
  2826. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2827. int ulp_type)
  2828. {
  2829. struct cnic_dev *dev = NULL;
  2830. struct dst_entry *dst;
  2831. struct net_device *netdev = NULL;
  2832. int err = -ENETUNREACH;
  2833. if (dst_addr->sin_family == AF_INET)
  2834. err = cnic_get_v4_route(dst_addr, &dst);
  2835. else if (dst_addr->sin_family == AF_INET6) {
  2836. struct sockaddr_in6 *dst_addr6 =
  2837. (struct sockaddr_in6 *) dst_addr;
  2838. err = cnic_get_v6_route(dst_addr6, &dst);
  2839. } else
  2840. return NULL;
  2841. if (err)
  2842. return NULL;
  2843. if (!dst->dev)
  2844. goto done;
  2845. cnic_get_vlan(dst->dev, &netdev);
  2846. dev = cnic_from_netdev(netdev);
  2847. done:
  2848. dst_release(dst);
  2849. if (dev)
  2850. cnic_put(dev);
  2851. return dev;
  2852. }
  2853. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2854. {
  2855. struct cnic_dev *dev = csk->dev;
  2856. struct cnic_local *cp = dev->cnic_priv;
  2857. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2858. }
  2859. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2860. {
  2861. struct cnic_dev *dev = csk->dev;
  2862. struct cnic_local *cp = dev->cnic_priv;
  2863. int is_v6, rc = 0;
  2864. struct dst_entry *dst = NULL;
  2865. struct net_device *realdev;
  2866. __be16 local_port;
  2867. u32 port_id;
  2868. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2869. saddr->remote.v6.sin6_family == AF_INET6)
  2870. is_v6 = 1;
  2871. else if (saddr->local.v4.sin_family == AF_INET &&
  2872. saddr->remote.v4.sin_family == AF_INET)
  2873. is_v6 = 0;
  2874. else
  2875. return -EINVAL;
  2876. clear_bit(SK_F_IPV6, &csk->flags);
  2877. if (is_v6) {
  2878. set_bit(SK_F_IPV6, &csk->flags);
  2879. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2880. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2881. sizeof(struct in6_addr));
  2882. csk->dst_port = saddr->remote.v6.sin6_port;
  2883. local_port = saddr->local.v6.sin6_port;
  2884. } else {
  2885. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2886. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2887. csk->dst_port = saddr->remote.v4.sin_port;
  2888. local_port = saddr->local.v4.sin_port;
  2889. }
  2890. csk->vlan_id = 0;
  2891. csk->mtu = dev->netdev->mtu;
  2892. if (dst && dst->dev) {
  2893. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2894. if (realdev == dev->netdev) {
  2895. csk->vlan_id = vlan;
  2896. csk->mtu = dst_mtu(dst);
  2897. }
  2898. }
  2899. port_id = be16_to_cpu(local_port);
  2900. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2901. port_id < CNIC_LOCAL_PORT_MAX) {
  2902. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2903. port_id = 0;
  2904. } else
  2905. port_id = 0;
  2906. if (!port_id) {
  2907. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2908. if (port_id == -1) {
  2909. rc = -ENOMEM;
  2910. goto err_out;
  2911. }
  2912. local_port = cpu_to_be16(port_id);
  2913. }
  2914. csk->src_port = local_port;
  2915. err_out:
  2916. dst_release(dst);
  2917. return rc;
  2918. }
  2919. static void cnic_init_csk_state(struct cnic_sock *csk)
  2920. {
  2921. csk->state = 0;
  2922. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2923. clear_bit(SK_F_CLOSING, &csk->flags);
  2924. }
  2925. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2926. {
  2927. int err = 0;
  2928. if (!cnic_in_use(csk))
  2929. return -EINVAL;
  2930. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2931. return -EINVAL;
  2932. cnic_init_csk_state(csk);
  2933. err = cnic_get_route(csk, saddr);
  2934. if (err)
  2935. goto err_out;
  2936. err = cnic_resolve_addr(csk, saddr);
  2937. if (!err)
  2938. return 0;
  2939. err_out:
  2940. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2941. return err;
  2942. }
  2943. static int cnic_cm_abort(struct cnic_sock *csk)
  2944. {
  2945. struct cnic_local *cp = csk->dev->cnic_priv;
  2946. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2947. if (!cnic_in_use(csk))
  2948. return -EINVAL;
  2949. if (cnic_abort_prep(csk))
  2950. return cnic_cm_abort_req(csk);
  2951. /* Getting here means that we haven't started connect, or
  2952. * connect was not successful.
  2953. */
  2954. cp->close_conn(csk, opcode);
  2955. if (csk->state != opcode)
  2956. return -EALREADY;
  2957. return 0;
  2958. }
  2959. static int cnic_cm_close(struct cnic_sock *csk)
  2960. {
  2961. if (!cnic_in_use(csk))
  2962. return -EINVAL;
  2963. if (cnic_close_prep(csk)) {
  2964. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2965. return cnic_cm_close_req(csk);
  2966. } else {
  2967. return -EALREADY;
  2968. }
  2969. return 0;
  2970. }
  2971. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2972. u8 opcode)
  2973. {
  2974. struct cnic_ulp_ops *ulp_ops;
  2975. int ulp_type = csk->ulp_type;
  2976. rcu_read_lock();
  2977. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2978. if (ulp_ops) {
  2979. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2980. ulp_ops->cm_connect_complete(csk);
  2981. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2982. ulp_ops->cm_close_complete(csk);
  2983. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2984. ulp_ops->cm_remote_abort(csk);
  2985. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2986. ulp_ops->cm_abort_complete(csk);
  2987. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2988. ulp_ops->cm_remote_close(csk);
  2989. }
  2990. rcu_read_unlock();
  2991. }
  2992. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2993. {
  2994. if (cnic_offld_prep(csk)) {
  2995. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2996. cnic_cm_update_pg(csk);
  2997. else
  2998. cnic_cm_offload_pg(csk);
  2999. }
  3000. return 0;
  3001. }
  3002. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3003. {
  3004. struct cnic_local *cp = dev->cnic_priv;
  3005. u32 l5_cid = kcqe->pg_host_opaque;
  3006. u8 opcode = kcqe->op_code;
  3007. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3008. csk_hold(csk);
  3009. if (!cnic_in_use(csk))
  3010. goto done;
  3011. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3012. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3013. goto done;
  3014. }
  3015. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3016. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3017. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3018. cnic_cm_upcall(cp, csk,
  3019. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3020. goto done;
  3021. }
  3022. csk->pg_cid = kcqe->pg_cid;
  3023. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3024. cnic_cm_conn_req(csk);
  3025. done:
  3026. csk_put(csk);
  3027. }
  3028. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3029. {
  3030. struct cnic_local *cp = dev->cnic_priv;
  3031. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3032. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3033. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3034. ctx->timestamp = jiffies;
  3035. ctx->wait_cond = 1;
  3036. wake_up(&ctx->waitq);
  3037. }
  3038. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3039. {
  3040. struct cnic_local *cp = dev->cnic_priv;
  3041. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3042. u8 opcode = l4kcqe->op_code;
  3043. u32 l5_cid;
  3044. struct cnic_sock *csk;
  3045. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3046. cnic_process_fcoe_term_conn(dev, kcqe);
  3047. return;
  3048. }
  3049. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3050. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3051. cnic_cm_process_offld_pg(dev, l4kcqe);
  3052. return;
  3053. }
  3054. l5_cid = l4kcqe->conn_id;
  3055. if (opcode & 0x80)
  3056. l5_cid = l4kcqe->cid;
  3057. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3058. return;
  3059. csk = &cp->csk_tbl[l5_cid];
  3060. csk_hold(csk);
  3061. if (!cnic_in_use(csk)) {
  3062. csk_put(csk);
  3063. return;
  3064. }
  3065. switch (opcode) {
  3066. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3067. if (l4kcqe->status != 0) {
  3068. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3069. cnic_cm_upcall(cp, csk,
  3070. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3071. }
  3072. break;
  3073. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3074. if (l4kcqe->status == 0)
  3075. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3076. smp_mb__before_clear_bit();
  3077. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3078. cnic_cm_upcall(cp, csk, opcode);
  3079. break;
  3080. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3081. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3082. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3083. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3084. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3085. cp->close_conn(csk, opcode);
  3086. break;
  3087. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3088. cnic_cm_upcall(cp, csk, opcode);
  3089. break;
  3090. }
  3091. csk_put(csk);
  3092. }
  3093. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3094. {
  3095. struct cnic_dev *dev = data;
  3096. int i;
  3097. for (i = 0; i < num; i++)
  3098. cnic_cm_process_kcqe(dev, kcqe[i]);
  3099. }
  3100. static struct cnic_ulp_ops cm_ulp_ops = {
  3101. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3102. };
  3103. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3104. {
  3105. struct cnic_local *cp = dev->cnic_priv;
  3106. kfree(cp->csk_tbl);
  3107. cp->csk_tbl = NULL;
  3108. cnic_free_id_tbl(&cp->csk_port_tbl);
  3109. }
  3110. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3111. {
  3112. struct cnic_local *cp = dev->cnic_priv;
  3113. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3114. GFP_KERNEL);
  3115. if (!cp->csk_tbl)
  3116. return -ENOMEM;
  3117. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3118. CNIC_LOCAL_PORT_MIN)) {
  3119. cnic_cm_free_mem(dev);
  3120. return -ENOMEM;
  3121. }
  3122. return 0;
  3123. }
  3124. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3125. {
  3126. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3127. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3128. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3129. csk->state = opcode;
  3130. }
  3131. /* 1. If event opcode matches the expected event in csk->state
  3132. * 2. If the expected event is CLOSE_COMP, we accept any event
  3133. * 3. If the expected event is 0, meaning the connection was never
  3134. * never established, we accept the opcode from cm_abort.
  3135. */
  3136. if (opcode == csk->state || csk->state == 0 ||
  3137. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  3138. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3139. if (csk->state == 0)
  3140. csk->state = opcode;
  3141. return 1;
  3142. }
  3143. }
  3144. return 0;
  3145. }
  3146. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3147. {
  3148. struct cnic_dev *dev = csk->dev;
  3149. struct cnic_local *cp = dev->cnic_priv;
  3150. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3151. cnic_cm_upcall(cp, csk, opcode);
  3152. return;
  3153. }
  3154. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3155. cnic_close_conn(csk);
  3156. csk->state = opcode;
  3157. cnic_cm_upcall(cp, csk, opcode);
  3158. }
  3159. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3160. {
  3161. }
  3162. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3163. {
  3164. u32 seed;
  3165. get_random_bytes(&seed, 4);
  3166. cnic_ctx_wr(dev, 45, 0, seed);
  3167. return 0;
  3168. }
  3169. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3170. {
  3171. struct cnic_dev *dev = csk->dev;
  3172. struct cnic_local *cp = dev->cnic_priv;
  3173. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3174. union l5cm_specific_data l5_data;
  3175. u32 cmd = 0;
  3176. int close_complete = 0;
  3177. switch (opcode) {
  3178. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3179. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3180. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3181. if (cnic_ready_to_close(csk, opcode)) {
  3182. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3183. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3184. else
  3185. close_complete = 1;
  3186. }
  3187. break;
  3188. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3189. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3190. break;
  3191. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3192. close_complete = 1;
  3193. break;
  3194. }
  3195. if (cmd) {
  3196. memset(&l5_data, 0, sizeof(l5_data));
  3197. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3198. &l5_data);
  3199. } else if (close_complete) {
  3200. ctx->timestamp = jiffies;
  3201. cnic_close_conn(csk);
  3202. cnic_cm_upcall(cp, csk, csk->state);
  3203. }
  3204. }
  3205. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3206. {
  3207. struct cnic_local *cp = dev->cnic_priv;
  3208. int i;
  3209. if (!cp->ctx_tbl)
  3210. return;
  3211. if (!netif_running(dev->netdev))
  3212. return;
  3213. for (i = 0; i < cp->max_cid_space; i++) {
  3214. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3215. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3216. msleep(10);
  3217. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3218. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3219. ctx->cid);
  3220. }
  3221. cancel_delayed_work(&cp->delete_task);
  3222. flush_workqueue(cnic_wq);
  3223. if (atomic_read(&cp->iscsi_conn) != 0)
  3224. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3225. atomic_read(&cp->iscsi_conn));
  3226. }
  3227. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3228. {
  3229. struct cnic_local *cp = dev->cnic_priv;
  3230. u32 pfid = cp->pfid;
  3231. u32 port = CNIC_PORT(cp);
  3232. cnic_init_bnx2x_mac(dev);
  3233. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3234. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3235. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3236. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3237. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3238. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3239. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3240. DEF_MAX_DA_COUNT);
  3241. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3242. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3243. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3244. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3245. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3246. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3247. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3248. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3249. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3250. DEF_MAX_CWND);
  3251. return 0;
  3252. }
  3253. static void cnic_delete_task(struct work_struct *work)
  3254. {
  3255. struct cnic_local *cp;
  3256. struct cnic_dev *dev;
  3257. u32 i;
  3258. int need_resched = 0;
  3259. cp = container_of(work, struct cnic_local, delete_task.work);
  3260. dev = cp->dev;
  3261. for (i = 0; i < cp->max_cid_space; i++) {
  3262. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3263. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3264. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3265. continue;
  3266. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3267. need_resched = 1;
  3268. continue;
  3269. }
  3270. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3271. continue;
  3272. cnic_bnx2x_destroy_ramrod(dev, i);
  3273. cnic_free_bnx2x_conn_resc(dev, i);
  3274. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3275. atomic_dec(&cp->iscsi_conn);
  3276. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3277. }
  3278. if (need_resched)
  3279. queue_delayed_work(cnic_wq, &cp->delete_task,
  3280. msecs_to_jiffies(10));
  3281. }
  3282. static int cnic_cm_open(struct cnic_dev *dev)
  3283. {
  3284. struct cnic_local *cp = dev->cnic_priv;
  3285. int err;
  3286. err = cnic_cm_alloc_mem(dev);
  3287. if (err)
  3288. return err;
  3289. err = cp->start_cm(dev);
  3290. if (err)
  3291. goto err_out;
  3292. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3293. dev->cm_create = cnic_cm_create;
  3294. dev->cm_destroy = cnic_cm_destroy;
  3295. dev->cm_connect = cnic_cm_connect;
  3296. dev->cm_abort = cnic_cm_abort;
  3297. dev->cm_close = cnic_cm_close;
  3298. dev->cm_select_dev = cnic_cm_select_dev;
  3299. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3300. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3301. return 0;
  3302. err_out:
  3303. cnic_cm_free_mem(dev);
  3304. return err;
  3305. }
  3306. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3307. {
  3308. struct cnic_local *cp = dev->cnic_priv;
  3309. int i;
  3310. cp->stop_cm(dev);
  3311. if (!cp->csk_tbl)
  3312. return 0;
  3313. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3314. struct cnic_sock *csk = &cp->csk_tbl[i];
  3315. clear_bit(SK_F_INUSE, &csk->flags);
  3316. cnic_cm_cleanup(csk);
  3317. }
  3318. cnic_cm_free_mem(dev);
  3319. return 0;
  3320. }
  3321. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3322. {
  3323. u32 cid_addr;
  3324. int i;
  3325. cid_addr = GET_CID_ADDR(cid);
  3326. for (i = 0; i < CTX_SIZE; i += 4)
  3327. cnic_ctx_wr(dev, cid_addr, i, 0);
  3328. }
  3329. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3330. {
  3331. struct cnic_local *cp = dev->cnic_priv;
  3332. int ret = 0, i;
  3333. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3334. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3335. return 0;
  3336. for (i = 0; i < cp->ctx_blks; i++) {
  3337. int j;
  3338. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3339. u32 val;
  3340. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3341. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3342. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3343. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3344. (u64) cp->ctx_arr[i].mapping >> 32);
  3345. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3346. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3347. for (j = 0; j < 10; j++) {
  3348. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3349. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3350. break;
  3351. udelay(5);
  3352. }
  3353. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3354. ret = -EBUSY;
  3355. break;
  3356. }
  3357. }
  3358. return ret;
  3359. }
  3360. static void cnic_free_irq(struct cnic_dev *dev)
  3361. {
  3362. struct cnic_local *cp = dev->cnic_priv;
  3363. struct cnic_eth_dev *ethdev = cp->ethdev;
  3364. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3365. cp->disable_int_sync(dev);
  3366. tasklet_kill(&cp->cnic_irq_task);
  3367. free_irq(ethdev->irq_arr[0].vector, dev);
  3368. }
  3369. }
  3370. static int cnic_request_irq(struct cnic_dev *dev)
  3371. {
  3372. struct cnic_local *cp = dev->cnic_priv;
  3373. struct cnic_eth_dev *ethdev = cp->ethdev;
  3374. int err;
  3375. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3376. if (err)
  3377. tasklet_disable(&cp->cnic_irq_task);
  3378. return err;
  3379. }
  3380. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3381. {
  3382. struct cnic_local *cp = dev->cnic_priv;
  3383. struct cnic_eth_dev *ethdev = cp->ethdev;
  3384. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3385. int err, i = 0;
  3386. int sblk_num = cp->status_blk_num;
  3387. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3388. BNX2_HC_SB_CONFIG_1;
  3389. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3390. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3391. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3392. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3393. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3394. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3395. (unsigned long) dev);
  3396. err = cnic_request_irq(dev);
  3397. if (err)
  3398. return err;
  3399. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3400. i < 10) {
  3401. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3402. 1 << (11 + sblk_num));
  3403. udelay(10);
  3404. i++;
  3405. barrier();
  3406. }
  3407. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3408. cnic_free_irq(dev);
  3409. goto failed;
  3410. }
  3411. } else {
  3412. struct status_block *sblk = cp->status_blk.gen;
  3413. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3414. int i = 0;
  3415. while (sblk->status_completion_producer_index && i < 10) {
  3416. CNIC_WR(dev, BNX2_HC_COMMAND,
  3417. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3418. udelay(10);
  3419. i++;
  3420. barrier();
  3421. }
  3422. if (sblk->status_completion_producer_index)
  3423. goto failed;
  3424. }
  3425. return 0;
  3426. failed:
  3427. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3428. return -EBUSY;
  3429. }
  3430. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3431. {
  3432. struct cnic_local *cp = dev->cnic_priv;
  3433. struct cnic_eth_dev *ethdev = cp->ethdev;
  3434. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3435. return;
  3436. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3437. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3438. }
  3439. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3440. {
  3441. struct cnic_local *cp = dev->cnic_priv;
  3442. struct cnic_eth_dev *ethdev = cp->ethdev;
  3443. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3444. return;
  3445. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3446. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3447. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3448. synchronize_irq(ethdev->irq_arr[0].vector);
  3449. }
  3450. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3451. {
  3452. struct cnic_local *cp = dev->cnic_priv;
  3453. struct cnic_eth_dev *ethdev = cp->ethdev;
  3454. struct cnic_uio_dev *udev = cp->udev;
  3455. u32 cid_addr, tx_cid, sb_id;
  3456. u32 val, offset0, offset1, offset2, offset3;
  3457. int i;
  3458. struct tx_bd *txbd;
  3459. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3460. struct status_block *s_blk = cp->status_blk.gen;
  3461. sb_id = cp->status_blk_num;
  3462. tx_cid = 20;
  3463. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3464. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3465. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3466. tx_cid = TX_TSS_CID + sb_id - 1;
  3467. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3468. (TX_TSS_CID << 7));
  3469. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3470. }
  3471. cp->tx_cons = *cp->tx_cons_ptr;
  3472. cid_addr = GET_CID_ADDR(tx_cid);
  3473. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3474. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3475. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3476. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3477. offset0 = BNX2_L2CTX_TYPE_XI;
  3478. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3479. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3480. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3481. } else {
  3482. cnic_init_context(dev, tx_cid);
  3483. cnic_init_context(dev, tx_cid + 1);
  3484. offset0 = BNX2_L2CTX_TYPE;
  3485. offset1 = BNX2_L2CTX_CMD_TYPE;
  3486. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3487. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3488. }
  3489. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3490. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3491. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3492. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3493. txbd = (struct tx_bd *) udev->l2_ring;
  3494. buf_map = udev->l2_buf_map;
  3495. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3496. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3497. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3498. }
  3499. val = (u64) ring_map >> 32;
  3500. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3501. txbd->tx_bd_haddr_hi = val;
  3502. val = (u64) ring_map & 0xffffffff;
  3503. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3504. txbd->tx_bd_haddr_lo = val;
  3505. }
  3506. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3507. {
  3508. struct cnic_local *cp = dev->cnic_priv;
  3509. struct cnic_eth_dev *ethdev = cp->ethdev;
  3510. struct cnic_uio_dev *udev = cp->udev;
  3511. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3512. int i;
  3513. struct rx_bd *rxbd;
  3514. struct status_block *s_blk = cp->status_blk.gen;
  3515. dma_addr_t ring_map = udev->l2_ring_map;
  3516. sb_id = cp->status_blk_num;
  3517. cnic_init_context(dev, 2);
  3518. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3519. coal_reg = BNX2_HC_COMMAND;
  3520. coal_val = CNIC_RD(dev, coal_reg);
  3521. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3522. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3523. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3524. coal_reg = BNX2_HC_COALESCE_NOW;
  3525. coal_val = 1 << (11 + sb_id);
  3526. }
  3527. i = 0;
  3528. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3529. CNIC_WR(dev, coal_reg, coal_val);
  3530. udelay(10);
  3531. i++;
  3532. barrier();
  3533. }
  3534. cp->rx_cons = *cp->rx_cons_ptr;
  3535. cid_addr = GET_CID_ADDR(2);
  3536. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3537. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3538. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3539. if (sb_id == 0)
  3540. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3541. else
  3542. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3543. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3544. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3545. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3546. dma_addr_t buf_map;
  3547. int n = (i % cp->l2_rx_ring_size) + 1;
  3548. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3549. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3550. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3551. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3552. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3553. }
  3554. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3555. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3556. rxbd->rx_bd_haddr_hi = val;
  3557. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3558. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3559. rxbd->rx_bd_haddr_lo = val;
  3560. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3561. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3562. }
  3563. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3564. {
  3565. struct kwqe *wqes[1], l2kwqe;
  3566. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3567. wqes[0] = &l2kwqe;
  3568. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3569. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3570. KWQE_OPCODE_SHIFT) | 2;
  3571. dev->submit_kwqes(dev, wqes, 1);
  3572. }
  3573. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3574. {
  3575. struct cnic_local *cp = dev->cnic_priv;
  3576. u32 val;
  3577. val = cp->func << 2;
  3578. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3579. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3580. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3581. dev->mac_addr[0] = (u8) (val >> 8);
  3582. dev->mac_addr[1] = (u8) val;
  3583. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3584. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3585. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3586. dev->mac_addr[2] = (u8) (val >> 24);
  3587. dev->mac_addr[3] = (u8) (val >> 16);
  3588. dev->mac_addr[4] = (u8) (val >> 8);
  3589. dev->mac_addr[5] = (u8) val;
  3590. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3591. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3592. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3593. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3594. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3595. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3596. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3597. }
  3598. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3599. {
  3600. struct cnic_local *cp = dev->cnic_priv;
  3601. struct cnic_eth_dev *ethdev = cp->ethdev;
  3602. struct status_block *sblk = cp->status_blk.gen;
  3603. u32 val, kcq_cid_addr, kwq_cid_addr;
  3604. int err;
  3605. cnic_set_bnx2_mac(dev);
  3606. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3607. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3608. if (BCM_PAGE_BITS > 12)
  3609. val |= (12 - 8) << 4;
  3610. else
  3611. val |= (BCM_PAGE_BITS - 8) << 4;
  3612. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3613. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3614. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3615. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3616. err = cnic_setup_5709_context(dev, 1);
  3617. if (err)
  3618. return err;
  3619. cnic_init_context(dev, KWQ_CID);
  3620. cnic_init_context(dev, KCQ_CID);
  3621. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3622. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3623. cp->max_kwq_idx = MAX_KWQ_IDX;
  3624. cp->kwq_prod_idx = 0;
  3625. cp->kwq_con_idx = 0;
  3626. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3627. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3628. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3629. else
  3630. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3631. /* Initialize the kernel work queue context. */
  3632. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3633. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3634. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3635. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3636. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3637. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3638. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3639. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3640. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3641. val = (u32) cp->kwq_info.pgtbl_map;
  3642. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3643. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3644. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3645. cp->kcq1.sw_prod_idx = 0;
  3646. cp->kcq1.hw_prod_idx_ptr =
  3647. (u16 *) &sblk->status_completion_producer_index;
  3648. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3649. /* Initialize the kernel complete queue context. */
  3650. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3651. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3652. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3653. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3654. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3655. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3656. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3657. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3658. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3659. val = (u32) cp->kcq1.dma.pgtbl_map;
  3660. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3661. cp->int_num = 0;
  3662. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3663. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3664. u32 sb_id = cp->status_blk_num;
  3665. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3666. cp->kcq1.hw_prod_idx_ptr =
  3667. (u16 *) &msblk->status_completion_producer_index;
  3668. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3669. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3670. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3671. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3672. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3673. }
  3674. /* Enable Commnad Scheduler notification when we write to the
  3675. * host producer index of the kernel contexts. */
  3676. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3677. /* Enable Command Scheduler notification when we write to either
  3678. * the Send Queue or Receive Queue producer indexes of the kernel
  3679. * bypass contexts. */
  3680. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3681. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3682. /* Notify COM when the driver post an application buffer. */
  3683. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3684. /* Set the CP and COM doorbells. These two processors polls the
  3685. * doorbell for a non zero value before running. This must be done
  3686. * after setting up the kernel queue contexts. */
  3687. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3688. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3689. cnic_init_bnx2_tx_ring(dev);
  3690. cnic_init_bnx2_rx_ring(dev);
  3691. err = cnic_init_bnx2_irq(dev);
  3692. if (err) {
  3693. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3694. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3695. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3696. return err;
  3697. }
  3698. return 0;
  3699. }
  3700. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3701. {
  3702. struct cnic_local *cp = dev->cnic_priv;
  3703. struct cnic_eth_dev *ethdev = cp->ethdev;
  3704. u32 start_offset = ethdev->ctx_tbl_offset;
  3705. int i;
  3706. for (i = 0; i < cp->ctx_blks; i++) {
  3707. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3708. dma_addr_t map = ctx->mapping;
  3709. if (cp->ctx_align) {
  3710. unsigned long mask = cp->ctx_align - 1;
  3711. map = (map + mask) & ~mask;
  3712. }
  3713. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3714. }
  3715. }
  3716. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3717. {
  3718. struct cnic_local *cp = dev->cnic_priv;
  3719. struct cnic_eth_dev *ethdev = cp->ethdev;
  3720. int err = 0;
  3721. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3722. (unsigned long) dev);
  3723. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3724. err = cnic_request_irq(dev);
  3725. return err;
  3726. }
  3727. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3728. u16 sb_id, u8 sb_index,
  3729. u8 disable)
  3730. {
  3731. u32 addr = BAR_CSTRORM_INTMEM +
  3732. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3733. offsetof(struct hc_status_block_data_e1x, index_data) +
  3734. sizeof(struct hc_index_data)*sb_index +
  3735. offsetof(struct hc_index_data, flags);
  3736. u16 flags = CNIC_RD16(dev, addr);
  3737. /* clear and set */
  3738. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3739. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3740. HC_INDEX_DATA_HC_ENABLED);
  3741. CNIC_WR16(dev, addr, flags);
  3742. }
  3743. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3744. {
  3745. struct cnic_local *cp = dev->cnic_priv;
  3746. u8 sb_id = cp->status_blk_num;
  3747. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3748. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3749. offsetof(struct hc_status_block_data_e1x, index_data) +
  3750. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3751. offsetof(struct hc_index_data, timeout), 64 / 12);
  3752. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3753. }
  3754. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3755. {
  3756. }
  3757. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3758. struct client_init_ramrod_data *data)
  3759. {
  3760. struct cnic_local *cp = dev->cnic_priv;
  3761. struct cnic_uio_dev *udev = cp->udev;
  3762. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3763. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3764. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3765. int port = CNIC_PORT(cp);
  3766. int i;
  3767. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3768. u32 val;
  3769. memset(txbd, 0, BCM_PAGE_SIZE);
  3770. buf_map = udev->l2_buf_map;
  3771. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3772. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3773. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3774. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3775. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3776. reg_bd->addr_hi = start_bd->addr_hi;
  3777. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3778. start_bd->nbytes = cpu_to_le16(0x10);
  3779. start_bd->nbd = cpu_to_le16(3);
  3780. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3781. start_bd->general_data = (UNICAST_ADDRESS <<
  3782. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3783. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3784. }
  3785. val = (u64) ring_map >> 32;
  3786. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3787. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3788. val = (u64) ring_map & 0xffffffff;
  3789. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3790. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3791. /* Other ramrod params */
  3792. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3793. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3794. /* reset xstorm per client statistics */
  3795. if (cli < MAX_STAT_COUNTER_ID) {
  3796. val = BAR_XSTRORM_INTMEM +
  3797. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3798. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3799. CNIC_WR(dev, val + i * 4, 0);
  3800. }
  3801. cp->tx_cons_ptr =
  3802. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3803. }
  3804. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3805. struct client_init_ramrod_data *data)
  3806. {
  3807. struct cnic_local *cp = dev->cnic_priv;
  3808. struct cnic_uio_dev *udev = cp->udev;
  3809. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3810. BCM_PAGE_SIZE);
  3811. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3812. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3813. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3814. int i;
  3815. int port = CNIC_PORT(cp);
  3816. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3817. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3818. u32 val;
  3819. dma_addr_t ring_map = udev->l2_ring_map;
  3820. /* General data */
  3821. data->general.client_id = cli;
  3822. data->general.statistics_en_flg = 1;
  3823. data->general.statistics_counter_id = cli;
  3824. data->general.activate_flg = 1;
  3825. data->general.sp_client_id = cli;
  3826. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3827. dma_addr_t buf_map;
  3828. int n = (i % cp->l2_rx_ring_size) + 1;
  3829. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3830. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3831. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3832. }
  3833. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3834. rxbd->addr_hi = cpu_to_le32(val);
  3835. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3836. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3837. rxbd->addr_lo = cpu_to_le32(val);
  3838. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3839. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3840. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3841. rxcqe->addr_hi = cpu_to_le32(val);
  3842. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3843. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3844. rxcqe->addr_lo = cpu_to_le32(val);
  3845. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3846. /* Other ramrod params */
  3847. data->rx.client_qzone_id = cl_qzone_id;
  3848. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3849. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3850. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3851. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3852. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3853. data->rx.outer_vlan_removal_enable_flg = 1;
  3854. /* reset tstorm and ustorm per client statistics */
  3855. if (cli < MAX_STAT_COUNTER_ID) {
  3856. val = BAR_TSTRORM_INTMEM +
  3857. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3858. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3859. CNIC_WR(dev, val + i * 4, 0);
  3860. val = BAR_USTRORM_INTMEM +
  3861. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3862. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3863. CNIC_WR(dev, val + i * 4, 0);
  3864. }
  3865. cp->rx_cons_ptr =
  3866. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3867. cp->rx_cons = *cp->rx_cons_ptr;
  3868. }
  3869. static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
  3870. u32 lower_addr)
  3871. {
  3872. u32 val;
  3873. u8 mac[6];
  3874. val = CNIC_RD(dev, upper_addr);
  3875. mac[0] = (u8) (val >> 8);
  3876. mac[1] = (u8) val;
  3877. val = CNIC_RD(dev, lower_addr);
  3878. mac[2] = (u8) (val >> 24);
  3879. mac[3] = (u8) (val >> 16);
  3880. mac[4] = (u8) (val >> 8);
  3881. mac[5] = (u8) val;
  3882. if (is_valid_ether_addr(mac)) {
  3883. memcpy(dev->mac_addr, mac, 6);
  3884. return 0;
  3885. } else {
  3886. return -EINVAL;
  3887. }
  3888. }
  3889. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3890. {
  3891. struct cnic_local *cp = dev->cnic_priv;
  3892. u32 base, base2, addr, addr1, val;
  3893. int port = CNIC_PORT(cp);
  3894. dev->max_iscsi_conn = 0;
  3895. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3896. if (base == 0)
  3897. return;
  3898. base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
  3899. MISC_REG_GENERIC_CR_0));
  3900. addr = BNX2X_SHMEM_ADDR(base,
  3901. dev_info.port_hw_config[port].iscsi_mac_upper);
  3902. addr1 = BNX2X_SHMEM_ADDR(base,
  3903. dev_info.port_hw_config[port].iscsi_mac_lower);
  3904. cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
  3905. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3906. val = CNIC_RD(dev, addr);
  3907. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3908. u16 val16;
  3909. addr = BNX2X_SHMEM_ADDR(base,
  3910. drv_lic_key[port].max_iscsi_init_conn);
  3911. val16 = CNIC_RD16(dev, addr);
  3912. if (val16)
  3913. val16 ^= 0x1e1e;
  3914. dev->max_iscsi_conn = val16;
  3915. }
  3916. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  3917. dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  3918. if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3919. int func = CNIC_FUNC(cp);
  3920. u32 mf_cfg_addr;
  3921. if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
  3922. mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
  3923. mf_cfg_addr));
  3924. else
  3925. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3926. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3927. /* Must determine if the MF is SD vs SI mode */
  3928. addr = BNX2X_SHMEM_ADDR(base,
  3929. dev_info.shared_feature_config.config);
  3930. val = CNIC_RD(dev, addr);
  3931. if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
  3932. SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
  3933. int rc;
  3934. /* MULTI_FUNCTION_SI mode */
  3935. addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3936. func_ext_config[func].func_cfg);
  3937. val = CNIC_RD(dev, addr);
  3938. if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
  3939. dev->max_iscsi_conn = 0;
  3940. if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
  3941. dev->max_fcoe_conn = 0;
  3942. addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3943. func_ext_config[func].
  3944. iscsi_mac_addr_upper);
  3945. addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3946. func_ext_config[func].
  3947. iscsi_mac_addr_lower);
  3948. rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
  3949. addr1);
  3950. if (rc && func > 1)
  3951. dev->max_iscsi_conn = 0;
  3952. return;
  3953. }
  3954. }
  3955. addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
  3956. func_mf_config[func].e1hov_tag);
  3957. val = CNIC_RD(dev, addr);
  3958. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3959. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3960. dev->max_fcoe_conn = 0;
  3961. dev->max_iscsi_conn = 0;
  3962. }
  3963. }
  3964. if (!is_valid_ether_addr(dev->mac_addr))
  3965. dev->max_iscsi_conn = 0;
  3966. }
  3967. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3968. {
  3969. struct cnic_local *cp = dev->cnic_priv;
  3970. u32 pfid = cp->pfid;
  3971. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3972. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3973. cp->kcq1.sw_prod_idx = 0;
  3974. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3975. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3976. cp->kcq1.hw_prod_idx_ptr =
  3977. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3978. cp->kcq1.status_idx_ptr =
  3979. &sb->sb.running_index[SM_RX_ID];
  3980. } else {
  3981. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3982. cp->kcq1.hw_prod_idx_ptr =
  3983. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3984. cp->kcq1.status_idx_ptr =
  3985. &sb->sb.running_index[SM_RX_ID];
  3986. }
  3987. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3988. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3989. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3990. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3991. cp->kcq2.sw_prod_idx = 0;
  3992. cp->kcq2.hw_prod_idx_ptr =
  3993. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3994. cp->kcq2.status_idx_ptr =
  3995. &sb->sb.running_index[SM_RX_ID];
  3996. }
  3997. }
  3998. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3999. {
  4000. struct cnic_local *cp = dev->cnic_priv;
  4001. struct cnic_eth_dev *ethdev = cp->ethdev;
  4002. int func = CNIC_FUNC(cp), ret, i;
  4003. u32 pfid;
  4004. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  4005. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4006. if (!(val & 1))
  4007. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4008. else
  4009. val = (val >> 1) & 1;
  4010. if (val)
  4011. cp->pfid = func >> 1;
  4012. else
  4013. cp->pfid = func & 0x6;
  4014. } else {
  4015. cp->pfid = func;
  4016. }
  4017. pfid = cp->pfid;
  4018. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4019. cp->iscsi_start_cid);
  4020. if (ret)
  4021. return -ENOMEM;
  4022. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  4023. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  4024. BNX2X_FCOE_NUM_CONNECTIONS,
  4025. cp->fcoe_start_cid);
  4026. if (ret)
  4027. return -ENOMEM;
  4028. }
  4029. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4030. cnic_init_bnx2x_kcq(dev);
  4031. cnic_get_bnx2x_iscsi_info(dev);
  4032. /* Only 1 EQ */
  4033. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4034. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4035. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4036. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4037. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4038. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4039. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4040. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4041. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4042. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4043. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4044. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4045. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4046. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4047. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4048. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4049. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4050. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4051. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4052. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4053. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4054. HC_INDEX_ISCSI_EQ_CONS);
  4055. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  4056. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4057. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  4058. cp->conn_buf_info.pgtbl[2 * i]);
  4059. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4060. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  4061. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  4062. }
  4063. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4064. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4065. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4066. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4067. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4068. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4069. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4070. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4071. cnic_setup_bnx2x_context(dev);
  4072. ret = cnic_init_bnx2x_irq(dev);
  4073. if (ret)
  4074. return ret;
  4075. return 0;
  4076. }
  4077. static void cnic_init_rings(struct cnic_dev *dev)
  4078. {
  4079. struct cnic_local *cp = dev->cnic_priv;
  4080. struct cnic_uio_dev *udev = cp->udev;
  4081. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4082. return;
  4083. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4084. cnic_init_bnx2_tx_ring(dev);
  4085. cnic_init_bnx2_rx_ring(dev);
  4086. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4087. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4088. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4089. u32 cid = cp->ethdev->iscsi_l2_cid;
  4090. u32 cl_qzone_id, type;
  4091. struct client_init_ramrod_data *data;
  4092. union l5cm_specific_data l5_data;
  4093. struct ustorm_eth_rx_producers rx_prods = {0};
  4094. u32 off, i;
  4095. rx_prods.bd_prod = 0;
  4096. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4097. barrier();
  4098. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4099. off = BAR_USTRORM_INTMEM +
  4100. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  4101. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4102. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4103. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4104. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4105. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4106. data = udev->l2_buf;
  4107. memset(data, 0, sizeof(*data));
  4108. cnic_init_bnx2x_tx_ring(dev, data);
  4109. cnic_init_bnx2x_rx_ring(dev, data);
  4110. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4111. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4112. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  4113. & SPE_HDR_CONN_TYPE;
  4114. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  4115. SPE_HDR_FUNCTION_ID);
  4116. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4117. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4118. cid, type, &l5_data);
  4119. i = 0;
  4120. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4121. ++i < 10)
  4122. msleep(1);
  4123. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4124. netdev_err(dev->netdev,
  4125. "iSCSI CLIENT_SETUP did not complete\n");
  4126. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4127. cnic_ring_ctl(dev, cid, cli, 1);
  4128. }
  4129. }
  4130. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4131. {
  4132. struct cnic_local *cp = dev->cnic_priv;
  4133. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4134. return;
  4135. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4136. cnic_shutdown_bnx2_rx_ring(dev);
  4137. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4138. struct cnic_local *cp = dev->cnic_priv;
  4139. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4140. u32 cid = cp->ethdev->iscsi_l2_cid;
  4141. union l5cm_specific_data l5_data;
  4142. int i;
  4143. u32 type;
  4144. cnic_ring_ctl(dev, cid, cli, 0);
  4145. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4146. l5_data.phy_address.lo = cli;
  4147. l5_data.phy_address.hi = 0;
  4148. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4149. cid, ETH_CONNECTION_TYPE, &l5_data);
  4150. i = 0;
  4151. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4152. ++i < 10)
  4153. msleep(1);
  4154. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4155. netdev_err(dev->netdev,
  4156. "iSCSI CLIENT_HALT did not complete\n");
  4157. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4158. memset(&l5_data, 0, sizeof(l5_data));
  4159. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  4160. & SPE_HDR_CONN_TYPE;
  4161. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  4162. SPE_HDR_FUNCTION_ID);
  4163. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4164. cid, type, &l5_data);
  4165. msleep(10);
  4166. }
  4167. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4168. }
  4169. static int cnic_register_netdev(struct cnic_dev *dev)
  4170. {
  4171. struct cnic_local *cp = dev->cnic_priv;
  4172. struct cnic_eth_dev *ethdev = cp->ethdev;
  4173. int err;
  4174. if (!ethdev)
  4175. return -ENODEV;
  4176. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4177. return 0;
  4178. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4179. if (err)
  4180. netdev_err(dev->netdev, "register_cnic failed\n");
  4181. return err;
  4182. }
  4183. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4184. {
  4185. struct cnic_local *cp = dev->cnic_priv;
  4186. struct cnic_eth_dev *ethdev = cp->ethdev;
  4187. if (!ethdev)
  4188. return;
  4189. ethdev->drv_unregister_cnic(dev->netdev);
  4190. }
  4191. static int cnic_start_hw(struct cnic_dev *dev)
  4192. {
  4193. struct cnic_local *cp = dev->cnic_priv;
  4194. struct cnic_eth_dev *ethdev = cp->ethdev;
  4195. int err;
  4196. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4197. return -EALREADY;
  4198. dev->regview = ethdev->io_base;
  4199. pci_dev_get(dev->pcidev);
  4200. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4201. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4202. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4203. err = cp->alloc_resc(dev);
  4204. if (err) {
  4205. netdev_err(dev->netdev, "allocate resource failure\n");
  4206. goto err1;
  4207. }
  4208. err = cp->start_hw(dev);
  4209. if (err)
  4210. goto err1;
  4211. err = cnic_cm_open(dev);
  4212. if (err)
  4213. goto err1;
  4214. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4215. cp->enable_int(dev);
  4216. return 0;
  4217. err1:
  4218. cp->free_resc(dev);
  4219. pci_dev_put(dev->pcidev);
  4220. return err;
  4221. }
  4222. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4223. {
  4224. cnic_disable_bnx2_int_sync(dev);
  4225. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4226. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4227. cnic_init_context(dev, KWQ_CID);
  4228. cnic_init_context(dev, KCQ_CID);
  4229. cnic_setup_5709_context(dev, 0);
  4230. cnic_free_irq(dev);
  4231. cnic_free_resc(dev);
  4232. }
  4233. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4234. {
  4235. struct cnic_local *cp = dev->cnic_priv;
  4236. cnic_free_irq(dev);
  4237. *cp->kcq1.hw_prod_idx_ptr = 0;
  4238. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4239. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4240. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4241. cnic_free_resc(dev);
  4242. }
  4243. static void cnic_stop_hw(struct cnic_dev *dev)
  4244. {
  4245. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4246. struct cnic_local *cp = dev->cnic_priv;
  4247. int i = 0;
  4248. /* Need to wait for the ring shutdown event to complete
  4249. * before clearing the CNIC_UP flag.
  4250. */
  4251. while (cp->udev->uio_dev != -1 && i < 15) {
  4252. msleep(100);
  4253. i++;
  4254. }
  4255. cnic_shutdown_rings(dev);
  4256. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4257. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4258. synchronize_rcu();
  4259. cnic_cm_shutdown(dev);
  4260. cp->stop_hw(dev);
  4261. pci_dev_put(dev->pcidev);
  4262. }
  4263. }
  4264. static void cnic_free_dev(struct cnic_dev *dev)
  4265. {
  4266. int i = 0;
  4267. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4268. msleep(100);
  4269. i++;
  4270. }
  4271. if (atomic_read(&dev->ref_count) != 0)
  4272. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4273. netdev_info(dev->netdev, "Removed CNIC device\n");
  4274. dev_put(dev->netdev);
  4275. kfree(dev);
  4276. }
  4277. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4278. struct pci_dev *pdev)
  4279. {
  4280. struct cnic_dev *cdev;
  4281. struct cnic_local *cp;
  4282. int alloc_size;
  4283. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4284. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4285. if (cdev == NULL) {
  4286. netdev_err(dev, "allocate dev struct failure\n");
  4287. return NULL;
  4288. }
  4289. cdev->netdev = dev;
  4290. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4291. cdev->register_device = cnic_register_device;
  4292. cdev->unregister_device = cnic_unregister_device;
  4293. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4294. cp = cdev->cnic_priv;
  4295. cp->dev = cdev;
  4296. cp->l2_single_buf_size = 0x400;
  4297. cp->l2_rx_ring_size = 3;
  4298. spin_lock_init(&cp->cnic_ulp_lock);
  4299. netdev_info(dev, "Added CNIC device\n");
  4300. return cdev;
  4301. }
  4302. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4303. {
  4304. struct pci_dev *pdev;
  4305. struct cnic_dev *cdev;
  4306. struct cnic_local *cp;
  4307. struct cnic_eth_dev *ethdev = NULL;
  4308. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4309. probe = symbol_get(bnx2_cnic_probe);
  4310. if (probe) {
  4311. ethdev = (*probe)(dev);
  4312. symbol_put(bnx2_cnic_probe);
  4313. }
  4314. if (!ethdev)
  4315. return NULL;
  4316. pdev = ethdev->pdev;
  4317. if (!pdev)
  4318. return NULL;
  4319. dev_hold(dev);
  4320. pci_dev_get(pdev);
  4321. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4322. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  4323. u8 rev;
  4324. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  4325. if (rev < 0x10) {
  4326. pci_dev_put(pdev);
  4327. goto cnic_err;
  4328. }
  4329. }
  4330. pci_dev_put(pdev);
  4331. cdev = cnic_alloc_dev(dev, pdev);
  4332. if (cdev == NULL)
  4333. goto cnic_err;
  4334. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4335. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4336. cp = cdev->cnic_priv;
  4337. cp->ethdev = ethdev;
  4338. cdev->pcidev = pdev;
  4339. cp->chip_id = ethdev->chip_id;
  4340. cp->cnic_ops = &cnic_bnx2_ops;
  4341. cp->start_hw = cnic_start_bnx2_hw;
  4342. cp->stop_hw = cnic_stop_bnx2_hw;
  4343. cp->setup_pgtbl = cnic_setup_page_tbl;
  4344. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4345. cp->free_resc = cnic_free_resc;
  4346. cp->start_cm = cnic_cm_init_bnx2_hw;
  4347. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4348. cp->enable_int = cnic_enable_bnx2_int;
  4349. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4350. cp->close_conn = cnic_close_bnx2_conn;
  4351. cp->next_idx = cnic_bnx2_next_idx;
  4352. cp->hw_idx = cnic_bnx2_hw_idx;
  4353. return cdev;
  4354. cnic_err:
  4355. dev_put(dev);
  4356. return NULL;
  4357. }
  4358. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4359. {
  4360. struct pci_dev *pdev;
  4361. struct cnic_dev *cdev;
  4362. struct cnic_local *cp;
  4363. struct cnic_eth_dev *ethdev = NULL;
  4364. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4365. probe = symbol_get(bnx2x_cnic_probe);
  4366. if (probe) {
  4367. ethdev = (*probe)(dev);
  4368. symbol_put(bnx2x_cnic_probe);
  4369. }
  4370. if (!ethdev)
  4371. return NULL;
  4372. pdev = ethdev->pdev;
  4373. if (!pdev)
  4374. return NULL;
  4375. dev_hold(dev);
  4376. cdev = cnic_alloc_dev(dev, pdev);
  4377. if (cdev == NULL) {
  4378. dev_put(dev);
  4379. return NULL;
  4380. }
  4381. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4382. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4383. cp = cdev->cnic_priv;
  4384. cp->ethdev = ethdev;
  4385. cdev->pcidev = pdev;
  4386. cp->chip_id = ethdev->chip_id;
  4387. cp->cnic_ops = &cnic_bnx2x_ops;
  4388. cp->start_hw = cnic_start_bnx2x_hw;
  4389. cp->stop_hw = cnic_stop_bnx2x_hw;
  4390. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4391. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4392. cp->free_resc = cnic_free_resc;
  4393. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4394. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4395. cp->enable_int = cnic_enable_bnx2x_int;
  4396. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4397. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  4398. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4399. else
  4400. cp->ack_int = cnic_ack_bnx2x_msix;
  4401. cp->close_conn = cnic_close_bnx2x_conn;
  4402. cp->next_idx = cnic_bnx2x_next_idx;
  4403. cp->hw_idx = cnic_bnx2x_hw_idx;
  4404. return cdev;
  4405. }
  4406. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4407. {
  4408. struct ethtool_drvinfo drvinfo;
  4409. struct cnic_dev *cdev = NULL;
  4410. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4411. memset(&drvinfo, 0, sizeof(drvinfo));
  4412. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4413. if (!strcmp(drvinfo.driver, "bnx2"))
  4414. cdev = init_bnx2_cnic(dev);
  4415. if (!strcmp(drvinfo.driver, "bnx2x"))
  4416. cdev = init_bnx2x_cnic(dev);
  4417. if (cdev) {
  4418. write_lock(&cnic_dev_lock);
  4419. list_add(&cdev->list, &cnic_dev_list);
  4420. write_unlock(&cnic_dev_lock);
  4421. }
  4422. }
  4423. return cdev;
  4424. }
  4425. /**
  4426. * netdev event handler
  4427. */
  4428. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4429. void *ptr)
  4430. {
  4431. struct net_device *netdev = ptr;
  4432. struct cnic_dev *dev;
  4433. int if_type;
  4434. int new_dev = 0;
  4435. dev = cnic_from_netdev(netdev);
  4436. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  4437. /* Check for the hot-plug device */
  4438. dev = is_cnic_dev(netdev);
  4439. if (dev) {
  4440. new_dev = 1;
  4441. cnic_hold(dev);
  4442. }
  4443. }
  4444. if (dev) {
  4445. struct cnic_local *cp = dev->cnic_priv;
  4446. if (new_dev)
  4447. cnic_ulp_init(dev);
  4448. else if (event == NETDEV_UNREGISTER)
  4449. cnic_ulp_exit(dev);
  4450. if (event == NETDEV_UP) {
  4451. if (cnic_register_netdev(dev) != 0) {
  4452. cnic_put(dev);
  4453. goto done;
  4454. }
  4455. if (!cnic_start_hw(dev))
  4456. cnic_ulp_start(dev);
  4457. }
  4458. rcu_read_lock();
  4459. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4460. struct cnic_ulp_ops *ulp_ops;
  4461. void *ctx;
  4462. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4463. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4464. continue;
  4465. ctx = cp->ulp_handle[if_type];
  4466. ulp_ops->indicate_netevent(ctx, event);
  4467. }
  4468. rcu_read_unlock();
  4469. if (event == NETDEV_GOING_DOWN) {
  4470. cnic_ulp_stop(dev);
  4471. cnic_stop_hw(dev);
  4472. cnic_unregister_netdev(dev);
  4473. } else if (event == NETDEV_UNREGISTER) {
  4474. write_lock(&cnic_dev_lock);
  4475. list_del_init(&dev->list);
  4476. write_unlock(&cnic_dev_lock);
  4477. cnic_put(dev);
  4478. cnic_free_dev(dev);
  4479. goto done;
  4480. }
  4481. cnic_put(dev);
  4482. }
  4483. done:
  4484. return NOTIFY_DONE;
  4485. }
  4486. static struct notifier_block cnic_netdev_notifier = {
  4487. .notifier_call = cnic_netdev_event
  4488. };
  4489. static void cnic_release(void)
  4490. {
  4491. struct cnic_dev *dev;
  4492. struct cnic_uio_dev *udev;
  4493. while (!list_empty(&cnic_dev_list)) {
  4494. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4495. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4496. cnic_ulp_stop(dev);
  4497. cnic_stop_hw(dev);
  4498. }
  4499. cnic_ulp_exit(dev);
  4500. cnic_unregister_netdev(dev);
  4501. list_del_init(&dev->list);
  4502. cnic_free_dev(dev);
  4503. }
  4504. while (!list_empty(&cnic_udev_list)) {
  4505. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4506. list);
  4507. cnic_free_uio(udev);
  4508. }
  4509. }
  4510. static int __init cnic_init(void)
  4511. {
  4512. int rc = 0;
  4513. pr_info("%s", version);
  4514. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4515. if (rc) {
  4516. cnic_release();
  4517. return rc;
  4518. }
  4519. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4520. if (!cnic_wq) {
  4521. cnic_release();
  4522. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4523. return -ENOMEM;
  4524. }
  4525. return 0;
  4526. }
  4527. static void __exit cnic_exit(void)
  4528. {
  4529. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4530. cnic_release();
  4531. destroy_workqueue(cnic_wq);
  4532. }
  4533. module_init(cnic_init);
  4534. module_exit(cnic_exit);