clkt34xx_dpll3m2.c 3.1 KB

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  1. /*
  2. * OMAP34xx M2 divider clock code
  3. *
  4. * Copyright (C) 2007-2008 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2010 Nokia Corporation
  6. *
  7. * Paul Walmsley
  8. * Jouni Högander
  9. *
  10. * Parts of this code are based on code written by
  11. * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License version 2 as
  15. * published by the Free Software Foundation.
  16. */
  17. #undef DEBUG
  18. #include <linux/kernel.h>
  19. #include <linux/errno.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include "clock.h"
  23. #include "clock3xxx.h"
  24. #include "clock34xx.h"
  25. #include "sdrc.h"
  26. #include "sram.h"
  27. #define CYCLES_PER_MHZ 1000000
  28. /*
  29. * CORE DPLL (DPLL3) M2 divider rate programming functions
  30. *
  31. * These call into SRAM code to do the actual CM writes, since the SDRAM
  32. * is clocked from DPLL3.
  33. */
  34. /**
  35. * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
  36. * @clk: struct clk * of DPLL to set
  37. * @rate: rounded target rate
  38. *
  39. * Program the DPLL M2 divider with the rounded target rate. Returns
  40. * -EINVAL upon error, or 0 upon success.
  41. */
  42. int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
  43. {
  44. u32 new_div = 0;
  45. u32 unlock_dll = 0;
  46. u32 c;
  47. unsigned long validrate, sdrcrate, _mpurate;
  48. struct omap_sdrc_params *sdrc_cs0;
  49. struct omap_sdrc_params *sdrc_cs1;
  50. int ret;
  51. unsigned long clkrate;
  52. if (!clk || !rate)
  53. return -EINVAL;
  54. validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
  55. if (validrate != rate)
  56. return -EINVAL;
  57. sdrcrate = __clk_get_rate(sdrc_ick_p);
  58. clkrate = __clk_get_rate(clk);
  59. if (rate > clkrate)
  60. sdrcrate <<= ((rate / clkrate) >> 1);
  61. else
  62. sdrcrate >>= ((clkrate / rate) >> 1);
  63. ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
  64. if (ret)
  65. return -EINVAL;
  66. if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
  67. pr_debug("clock: will unlock SDRC DLL\n");
  68. unlock_dll = 1;
  69. }
  70. /*
  71. * XXX This only needs to be done when the CPU frequency changes
  72. */
  73. _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
  74. c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
  75. c += 1; /* for safety */
  76. c *= SDRC_MPURATE_LOOPS;
  77. c >>= SDRC_MPURATE_SCALE;
  78. if (c == 0)
  79. c = 1;
  80. pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
  81. clkrate, validrate);
  82. pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  83. sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  84. sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
  85. if (sdrc_cs1)
  86. pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  87. sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
  88. sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
  89. if (sdrc_cs1)
  90. omap3_configure_core_dpll(
  91. new_div, unlock_dll, c, rate > clkrate,
  92. sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  93. sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
  94. sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
  95. sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
  96. else
  97. omap3_configure_core_dpll(
  98. new_div, unlock_dll, c, rate > clkrate,
  99. sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  100. sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
  101. 0, 0, 0, 0);
  102. clk->rate = rate;
  103. return 0;
  104. }