fimc-capture.c 49 KB

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  1. /*
  2. * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver
  3. *
  4. * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/errno.h>
  15. #include <linux/bug.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/list.h>
  20. #include <linux/slab.h>
  21. #include <linux/videodev2.h>
  22. #include <media/v4l2-device.h>
  23. #include <media/v4l2-ioctl.h>
  24. #include <media/v4l2-mem2mem.h>
  25. #include <media/videobuf2-core.h>
  26. #include <media/videobuf2-dma-contig.h>
  27. #include "common.h"
  28. #include "fimc-core.h"
  29. #include "fimc-reg.h"
  30. #include "media-dev.h"
  31. static int fimc_capture_hw_init(struct fimc_dev *fimc)
  32. {
  33. struct fimc_source_info *si = &fimc->vid_cap.source_config;
  34. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  35. int ret;
  36. unsigned long flags;
  37. if (ctx == NULL || ctx->s_frame.fmt == NULL)
  38. return -EINVAL;
  39. if (si->fimc_bus_type == FIMC_BUS_TYPE_ISP_WRITEBACK) {
  40. ret = fimc_hw_camblk_cfg_writeback(fimc);
  41. if (ret < 0)
  42. return ret;
  43. }
  44. spin_lock_irqsave(&fimc->slock, flags);
  45. fimc_prepare_dma_offset(ctx, &ctx->d_frame);
  46. fimc_set_yuv_order(ctx);
  47. fimc_hw_set_camera_polarity(fimc, si);
  48. fimc_hw_set_camera_type(fimc, si);
  49. fimc_hw_set_camera_source(fimc, si);
  50. fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
  51. ret = fimc_set_scaler_info(ctx);
  52. if (!ret) {
  53. fimc_hw_set_input_path(ctx);
  54. fimc_hw_set_prescaler(ctx);
  55. fimc_hw_set_mainscaler(ctx);
  56. fimc_hw_set_target_format(ctx);
  57. fimc_hw_set_rotation(ctx);
  58. fimc_hw_set_effect(ctx);
  59. fimc_hw_set_output_path(ctx);
  60. fimc_hw_set_out_dma(ctx);
  61. if (fimc->drv_data->alpha_color)
  62. fimc_hw_set_rgb_alpha(ctx);
  63. clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
  64. }
  65. spin_unlock_irqrestore(&fimc->slock, flags);
  66. return ret;
  67. }
  68. /*
  69. * Reinitialize the driver so it is ready to start the streaming again.
  70. * Set fimc->state to indicate stream off and the hardware shut down state.
  71. * If not suspending (@suspend is false), return any buffers to videobuf2.
  72. * Otherwise put any owned buffers onto the pending buffers queue, so they
  73. * can be re-spun when the device is being resumed. Also perform FIMC
  74. * software reset and disable streaming on the whole pipeline if required.
  75. */
  76. static int fimc_capture_state_cleanup(struct fimc_dev *fimc, bool suspend)
  77. {
  78. struct fimc_vid_cap *cap = &fimc->vid_cap;
  79. struct fimc_vid_buffer *buf;
  80. unsigned long flags;
  81. bool streaming;
  82. spin_lock_irqsave(&fimc->slock, flags);
  83. streaming = fimc->state & (1 << ST_CAPT_ISP_STREAM);
  84. fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_SHUT |
  85. 1 << ST_CAPT_STREAM | 1 << ST_CAPT_ISP_STREAM);
  86. if (suspend)
  87. fimc->state |= (1 << ST_CAPT_SUSPENDED);
  88. else
  89. fimc->state &= ~(1 << ST_CAPT_PEND | 1 << ST_CAPT_SUSPENDED);
  90. /* Release unused buffers */
  91. while (!suspend && !list_empty(&cap->pending_buf_q)) {
  92. buf = fimc_pending_queue_pop(cap);
  93. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  94. }
  95. /* If suspending put unused buffers onto pending queue */
  96. while (!list_empty(&cap->active_buf_q)) {
  97. buf = fimc_active_queue_pop(cap);
  98. if (suspend)
  99. fimc_pending_queue_add(cap, buf);
  100. else
  101. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  102. }
  103. fimc_hw_reset(fimc);
  104. cap->buf_index = 0;
  105. spin_unlock_irqrestore(&fimc->slock, flags);
  106. if (streaming)
  107. return fimc_pipeline_call(fimc, set_stream,
  108. &fimc->pipeline, 0);
  109. else
  110. return 0;
  111. }
  112. static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend)
  113. {
  114. unsigned long flags;
  115. if (!fimc_capture_active(fimc))
  116. return 0;
  117. spin_lock_irqsave(&fimc->slock, flags);
  118. set_bit(ST_CAPT_SHUT, &fimc->state);
  119. fimc_deactivate_capture(fimc);
  120. spin_unlock_irqrestore(&fimc->slock, flags);
  121. wait_event_timeout(fimc->irq_queue,
  122. !test_bit(ST_CAPT_SHUT, &fimc->state),
  123. (2*HZ/10)); /* 200 ms */
  124. return fimc_capture_state_cleanup(fimc, suspend);
  125. }
  126. /**
  127. * fimc_capture_config_update - apply the camera interface configuration
  128. *
  129. * To be called from within the interrupt handler with fimc.slock
  130. * spinlock held. It updates the camera pixel crop, rotation and
  131. * image flip in H/W.
  132. */
  133. static int fimc_capture_config_update(struct fimc_ctx *ctx)
  134. {
  135. struct fimc_dev *fimc = ctx->fimc_dev;
  136. int ret;
  137. fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
  138. ret = fimc_set_scaler_info(ctx);
  139. if (ret)
  140. return ret;
  141. fimc_hw_set_prescaler(ctx);
  142. fimc_hw_set_mainscaler(ctx);
  143. fimc_hw_set_target_format(ctx);
  144. fimc_hw_set_rotation(ctx);
  145. fimc_hw_set_effect(ctx);
  146. fimc_prepare_dma_offset(ctx, &ctx->d_frame);
  147. fimc_hw_set_out_dma(ctx);
  148. if (fimc->drv_data->alpha_color)
  149. fimc_hw_set_rgb_alpha(ctx);
  150. clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
  151. return ret;
  152. }
  153. void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
  154. {
  155. struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS];
  156. struct fimc_vid_cap *cap = &fimc->vid_cap;
  157. struct fimc_frame *f = &cap->ctx->d_frame;
  158. struct fimc_vid_buffer *v_buf;
  159. struct timeval *tv;
  160. struct timespec ts;
  161. if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
  162. wake_up(&fimc->irq_queue);
  163. goto done;
  164. }
  165. if (!list_empty(&cap->active_buf_q) &&
  166. test_bit(ST_CAPT_RUN, &fimc->state) && deq_buf) {
  167. ktime_get_real_ts(&ts);
  168. v_buf = fimc_active_queue_pop(cap);
  169. tv = &v_buf->vb.v4l2_buf.timestamp;
  170. tv->tv_sec = ts.tv_sec;
  171. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  172. v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
  173. vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
  174. }
  175. if (!list_empty(&cap->pending_buf_q)) {
  176. v_buf = fimc_pending_queue_pop(cap);
  177. fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
  178. v_buf->index = cap->buf_index;
  179. /* Move the buffer to the capture active queue */
  180. fimc_active_queue_add(cap, v_buf);
  181. dbg("next frame: %d, done frame: %d",
  182. fimc_hw_get_frame_index(fimc), v_buf->index);
  183. if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
  184. cap->buf_index = 0;
  185. }
  186. /*
  187. * Set up a buffer at MIPI-CSIS if current image format
  188. * requires the frame embedded data capture.
  189. */
  190. if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) {
  191. unsigned int plane = ffs(f->fmt->mdataplanes) - 1;
  192. unsigned int size = f->payload[plane];
  193. s32 index = fimc_hw_get_frame_index(fimc);
  194. void *vaddr;
  195. list_for_each_entry(v_buf, &cap->active_buf_q, list) {
  196. if (v_buf->index != index)
  197. continue;
  198. vaddr = vb2_plane_vaddr(&v_buf->vb, plane);
  199. v4l2_subdev_call(csis, video, s_rx_buffer,
  200. vaddr, &size);
  201. break;
  202. }
  203. }
  204. if (cap->active_buf_cnt == 0) {
  205. if (deq_buf)
  206. clear_bit(ST_CAPT_RUN, &fimc->state);
  207. if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
  208. cap->buf_index = 0;
  209. } else {
  210. set_bit(ST_CAPT_RUN, &fimc->state);
  211. }
  212. if (test_bit(ST_CAPT_APPLY_CFG, &fimc->state))
  213. fimc_capture_config_update(cap->ctx);
  214. done:
  215. if (cap->active_buf_cnt == 1) {
  216. fimc_deactivate_capture(fimc);
  217. clear_bit(ST_CAPT_STREAM, &fimc->state);
  218. }
  219. dbg("frame: %d, active_buf_cnt: %d",
  220. fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
  221. }
  222. static int start_streaming(struct vb2_queue *q, unsigned int count)
  223. {
  224. struct fimc_ctx *ctx = q->drv_priv;
  225. struct fimc_dev *fimc = ctx->fimc_dev;
  226. struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
  227. int min_bufs;
  228. int ret;
  229. vid_cap->frame_count = 0;
  230. ret = fimc_capture_hw_init(fimc);
  231. if (ret) {
  232. fimc_capture_state_cleanup(fimc, false);
  233. return ret;
  234. }
  235. set_bit(ST_CAPT_PEND, &fimc->state);
  236. min_bufs = fimc->vid_cap.reqbufs_count > 1 ? 2 : 1;
  237. if (vid_cap->active_buf_cnt >= min_bufs &&
  238. !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
  239. fimc_activate_capture(ctx);
  240. if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
  241. return fimc_pipeline_call(fimc, set_stream,
  242. &fimc->pipeline, 1);
  243. }
  244. return 0;
  245. }
  246. static int stop_streaming(struct vb2_queue *q)
  247. {
  248. struct fimc_ctx *ctx = q->drv_priv;
  249. struct fimc_dev *fimc = ctx->fimc_dev;
  250. if (!fimc_capture_active(fimc))
  251. return -EINVAL;
  252. return fimc_stop_capture(fimc, false);
  253. }
  254. int fimc_capture_suspend(struct fimc_dev *fimc)
  255. {
  256. bool suspend = fimc_capture_busy(fimc);
  257. int ret = fimc_stop_capture(fimc, suspend);
  258. if (ret)
  259. return ret;
  260. return fimc_pipeline_call(fimc, close, &fimc->pipeline);
  261. }
  262. static void buffer_queue(struct vb2_buffer *vb);
  263. int fimc_capture_resume(struct fimc_dev *fimc)
  264. {
  265. struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
  266. struct exynos_video_entity *ve = &vid_cap->ve;
  267. struct fimc_vid_buffer *buf;
  268. int i;
  269. if (!test_and_clear_bit(ST_CAPT_SUSPENDED, &fimc->state))
  270. return 0;
  271. INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
  272. vid_cap->buf_index = 0;
  273. fimc_pipeline_call(fimc, open, &fimc->pipeline,
  274. &ve->vdev.entity, false);
  275. fimc_capture_hw_init(fimc);
  276. clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
  277. for (i = 0; i < vid_cap->reqbufs_count; i++) {
  278. if (list_empty(&vid_cap->pending_buf_q))
  279. break;
  280. buf = fimc_pending_queue_pop(vid_cap);
  281. buffer_queue(&buf->vb);
  282. }
  283. return 0;
  284. }
  285. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  286. unsigned int *num_buffers, unsigned int *num_planes,
  287. unsigned int sizes[], void *allocators[])
  288. {
  289. const struct v4l2_pix_format_mplane *pixm = NULL;
  290. struct fimc_ctx *ctx = vq->drv_priv;
  291. struct fimc_frame *frame = &ctx->d_frame;
  292. struct fimc_fmt *fmt = frame->fmt;
  293. unsigned long wh;
  294. int i;
  295. if (pfmt) {
  296. pixm = &pfmt->fmt.pix_mp;
  297. fmt = fimc_find_format(&pixm->pixelformat, NULL,
  298. FMT_FLAGS_CAM | FMT_FLAGS_M2M, -1);
  299. wh = pixm->width * pixm->height;
  300. } else {
  301. wh = frame->f_width * frame->f_height;
  302. }
  303. if (fmt == NULL)
  304. return -EINVAL;
  305. *num_planes = fmt->memplanes;
  306. for (i = 0; i < fmt->memplanes; i++) {
  307. unsigned int size = (wh * fmt->depth[i]) / 8;
  308. if (pixm)
  309. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  310. else if (fimc_fmt_is_user_defined(fmt->color))
  311. sizes[i] = frame->payload[i];
  312. else
  313. sizes[i] = max_t(u32, size, frame->payload[i]);
  314. allocators[i] = ctx->fimc_dev->alloc_ctx;
  315. }
  316. return 0;
  317. }
  318. static int buffer_prepare(struct vb2_buffer *vb)
  319. {
  320. struct vb2_queue *vq = vb->vb2_queue;
  321. struct fimc_ctx *ctx = vq->drv_priv;
  322. int i;
  323. if (ctx->d_frame.fmt == NULL)
  324. return -EINVAL;
  325. for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) {
  326. unsigned long size = ctx->d_frame.payload[i];
  327. if (vb2_plane_size(vb, i) < size) {
  328. v4l2_err(&ctx->fimc_dev->vid_cap.ve.vdev,
  329. "User buffer too small (%ld < %ld)\n",
  330. vb2_plane_size(vb, i), size);
  331. return -EINVAL;
  332. }
  333. vb2_set_plane_payload(vb, i, size);
  334. }
  335. return 0;
  336. }
  337. static void buffer_queue(struct vb2_buffer *vb)
  338. {
  339. struct fimc_vid_buffer *buf
  340. = container_of(vb, struct fimc_vid_buffer, vb);
  341. struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  342. struct fimc_dev *fimc = ctx->fimc_dev;
  343. struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
  344. struct exynos_video_entity *ve = &vid_cap->ve;
  345. unsigned long flags;
  346. int min_bufs;
  347. spin_lock_irqsave(&fimc->slock, flags);
  348. fimc_prepare_addr(ctx, &buf->vb, &ctx->d_frame, &buf->paddr);
  349. if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) &&
  350. !test_bit(ST_CAPT_STREAM, &fimc->state) &&
  351. vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) {
  352. /* Setup the buffer directly for processing. */
  353. int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
  354. vid_cap->buf_index;
  355. fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
  356. buf->index = vid_cap->buf_index;
  357. fimc_active_queue_add(vid_cap, buf);
  358. if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS)
  359. vid_cap->buf_index = 0;
  360. } else {
  361. fimc_pending_queue_add(vid_cap, buf);
  362. }
  363. min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1;
  364. if (vb2_is_streaming(&vid_cap->vbq) &&
  365. vid_cap->active_buf_cnt >= min_bufs &&
  366. !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
  367. int ret;
  368. fimc_activate_capture(ctx);
  369. spin_unlock_irqrestore(&fimc->slock, flags);
  370. if (test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
  371. return;
  372. ret = fimc_pipeline_call(fimc, set_stream, &fimc->pipeline, 1);
  373. if (ret < 0)
  374. v4l2_err(&ve->vdev, "stream on failed: %d\n", ret);
  375. return;
  376. }
  377. spin_unlock_irqrestore(&fimc->slock, flags);
  378. }
  379. static struct vb2_ops fimc_capture_qops = {
  380. .queue_setup = queue_setup,
  381. .buf_prepare = buffer_prepare,
  382. .buf_queue = buffer_queue,
  383. .wait_prepare = vb2_ops_wait_prepare,
  384. .wait_finish = vb2_ops_wait_finish,
  385. .start_streaming = start_streaming,
  386. .stop_streaming = stop_streaming,
  387. };
  388. static int fimc_capture_set_default_format(struct fimc_dev *fimc);
  389. static int fimc_capture_open(struct file *file)
  390. {
  391. struct fimc_dev *fimc = video_drvdata(file);
  392. struct fimc_vid_cap *vc = &fimc->vid_cap;
  393. struct exynos_video_entity *ve = &vc->ve;
  394. int ret = -EBUSY;
  395. dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
  396. mutex_lock(&fimc->lock);
  397. if (fimc_m2m_active(fimc))
  398. goto unlock;
  399. set_bit(ST_CAPT_BUSY, &fimc->state);
  400. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  401. if (ret < 0)
  402. goto unlock;
  403. ret = v4l2_fh_open(file);
  404. if (ret) {
  405. pm_runtime_put(&fimc->pdev->dev);
  406. goto unlock;
  407. }
  408. if (v4l2_fh_is_singular_file(file)) {
  409. fimc_md_graph_lock(ve);
  410. ret = fimc_pipeline_call(fimc, open, &fimc->pipeline,
  411. &fimc->vid_cap.ve.vdev.entity, true);
  412. if (ret == 0)
  413. ret = fimc_capture_set_default_format(fimc);
  414. if (ret == 0 && vc->user_subdev_api && vc->inh_sensor_ctrls) {
  415. /*
  416. * Recreate controls of the the video node to drop
  417. * any controls inherited from the sensor subdev.
  418. */
  419. fimc_ctrls_delete(vc->ctx);
  420. ret = fimc_ctrls_create(vc->ctx);
  421. if (ret == 0)
  422. vc->inh_sensor_ctrls = false;
  423. }
  424. if (ret == 0)
  425. ve->vdev.entity.use_count++;
  426. fimc_md_graph_unlock(ve);
  427. if (ret < 0) {
  428. clear_bit(ST_CAPT_BUSY, &fimc->state);
  429. pm_runtime_put_sync(&fimc->pdev->dev);
  430. v4l2_fh_release(file);
  431. }
  432. }
  433. unlock:
  434. mutex_unlock(&fimc->lock);
  435. return ret;
  436. }
  437. static int fimc_capture_release(struct file *file)
  438. {
  439. struct fimc_dev *fimc = video_drvdata(file);
  440. struct fimc_vid_cap *vc = &fimc->vid_cap;
  441. bool close = v4l2_fh_is_singular_file(file);
  442. int ret;
  443. dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
  444. mutex_lock(&fimc->lock);
  445. if (close && vc->streaming) {
  446. media_entity_pipeline_stop(&vc->ve.vdev.entity);
  447. vc->streaming = false;
  448. }
  449. ret = vb2_fop_release(file);
  450. if (close) {
  451. clear_bit(ST_CAPT_BUSY, &fimc->state);
  452. fimc_stop_capture(fimc, false);
  453. fimc_pipeline_call(fimc, close, &fimc->pipeline);
  454. clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
  455. fimc_md_graph_lock(&vc->ve);
  456. vc->ve.vdev.entity.use_count--;
  457. fimc_md_graph_unlock(&vc->ve);
  458. }
  459. pm_runtime_put(&fimc->pdev->dev);
  460. mutex_unlock(&fimc->lock);
  461. return ret;
  462. }
  463. static const struct v4l2_file_operations fimc_capture_fops = {
  464. .owner = THIS_MODULE,
  465. .open = fimc_capture_open,
  466. .release = fimc_capture_release,
  467. .poll = vb2_fop_poll,
  468. .unlocked_ioctl = video_ioctl2,
  469. .mmap = vb2_fop_mmap,
  470. };
  471. /*
  472. * Format and crop negotiation helpers
  473. */
  474. static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx,
  475. u32 *width, u32 *height,
  476. u32 *code, u32 *fourcc, int pad)
  477. {
  478. bool rotation = ctx->rotation == 90 || ctx->rotation == 270;
  479. struct fimc_dev *fimc = ctx->fimc_dev;
  480. const struct fimc_variant *var = fimc->variant;
  481. const struct fimc_pix_limit *pl = var->pix_limit;
  482. struct fimc_frame *dst = &ctx->d_frame;
  483. u32 depth, min_w, max_w, min_h, align_h = 3;
  484. u32 mask = FMT_FLAGS_CAM;
  485. struct fimc_fmt *ffmt;
  486. /* Conversion from/to JPEG or User Defined format is not supported */
  487. if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE &&
  488. fimc_fmt_is_user_defined(ctx->s_frame.fmt->color))
  489. *code = ctx->s_frame.fmt->mbus_code;
  490. if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad == FIMC_SD_PAD_SOURCE)
  491. mask |= FMT_FLAGS_M2M;
  492. if (pad == FIMC_SD_PAD_SINK_FIFO)
  493. mask = FMT_FLAGS_WRITEBACK;
  494. ffmt = fimc_find_format(fourcc, code, mask, 0);
  495. if (WARN_ON(!ffmt))
  496. return NULL;
  497. if (code)
  498. *code = ffmt->mbus_code;
  499. if (fourcc)
  500. *fourcc = ffmt->fourcc;
  501. if (pad != FIMC_SD_PAD_SOURCE) {
  502. max_w = fimc_fmt_is_user_defined(ffmt->color) ?
  503. pl->scaler_dis_w : pl->scaler_en_w;
  504. /* Apply the camera input interface pixel constraints */
  505. v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4,
  506. height, max_t(u32, *height, 32),
  507. FIMC_CAMIF_MAX_HEIGHT,
  508. fimc_fmt_is_user_defined(ffmt->color) ?
  509. 3 : 1,
  510. 0);
  511. return ffmt;
  512. }
  513. /* Can't scale or crop in transparent (JPEG) transfer mode */
  514. if (fimc_fmt_is_user_defined(ffmt->color)) {
  515. *width = ctx->s_frame.f_width;
  516. *height = ctx->s_frame.f_height;
  517. return ffmt;
  518. }
  519. /* Apply the scaler and the output DMA constraints */
  520. max_w = rotation ? pl->out_rot_en_w : pl->out_rot_dis_w;
  521. if (ctx->state & FIMC_COMPOSE) {
  522. min_w = dst->offs_h + dst->width;
  523. min_h = dst->offs_v + dst->height;
  524. } else {
  525. min_w = var->min_out_pixsize;
  526. min_h = var->min_out_pixsize;
  527. }
  528. if (var->min_vsize_align == 1 && !rotation)
  529. align_h = fimc_fmt_is_rgb(ffmt->color) ? 0 : 1;
  530. depth = fimc_get_format_depth(ffmt);
  531. v4l_bound_align_image(width, min_w, max_w,
  532. ffs(var->min_out_pixsize) - 1,
  533. height, min_h, FIMC_CAMIF_MAX_HEIGHT,
  534. align_h,
  535. 64/(ALIGN(depth, 8)));
  536. dbg("pad%d: code: 0x%x, %dx%d. dst fmt: %dx%d",
  537. pad, code ? *code : 0, *width, *height,
  538. dst->f_width, dst->f_height);
  539. return ffmt;
  540. }
  541. static void fimc_capture_try_selection(struct fimc_ctx *ctx,
  542. struct v4l2_rect *r,
  543. int target)
  544. {
  545. bool rotate = ctx->rotation == 90 || ctx->rotation == 270;
  546. struct fimc_dev *fimc = ctx->fimc_dev;
  547. const struct fimc_variant *var = fimc->variant;
  548. const struct fimc_pix_limit *pl = var->pix_limit;
  549. struct fimc_frame *sink = &ctx->s_frame;
  550. u32 max_w, max_h, min_w = 0, min_h = 0, min_sz;
  551. u32 align_sz = 0, align_h = 4;
  552. u32 max_sc_h, max_sc_v;
  553. /* In JPEG transparent transfer mode cropping is not supported */
  554. if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) {
  555. r->width = sink->f_width;
  556. r->height = sink->f_height;
  557. r->left = r->top = 0;
  558. return;
  559. }
  560. if (target == V4L2_SEL_TGT_COMPOSE) {
  561. if (ctx->rotation != 90 && ctx->rotation != 270)
  562. align_h = 1;
  563. max_sc_h = min(SCALER_MAX_HRATIO, 1 << (ffs(sink->width) - 3));
  564. max_sc_v = min(SCALER_MAX_VRATIO, 1 << (ffs(sink->height) - 1));
  565. min_sz = var->min_out_pixsize;
  566. } else {
  567. u32 depth = fimc_get_format_depth(sink->fmt);
  568. align_sz = 64/ALIGN(depth, 8);
  569. min_sz = var->min_inp_pixsize;
  570. min_w = min_h = min_sz;
  571. max_sc_h = max_sc_v = 1;
  572. }
  573. /*
  574. * For the compose rectangle the following constraints must be met:
  575. * - it must fit in the sink pad format rectangle (f_width/f_height);
  576. * - maximum downscaling ratio is 64;
  577. * - maximum crop size depends if the rotator is used or not;
  578. * - the sink pad format width/height must be 4 multiple of the
  579. * prescaler ratios determined by sink pad size and source pad crop,
  580. * the prescaler ratio is returned by fimc_get_scaler_factor().
  581. */
  582. max_w = min_t(u32,
  583. rotate ? pl->out_rot_en_w : pl->out_rot_dis_w,
  584. rotate ? sink->f_height : sink->f_width);
  585. max_h = min_t(u32, FIMC_CAMIF_MAX_HEIGHT, sink->f_height);
  586. if (target == V4L2_SEL_TGT_COMPOSE) {
  587. min_w = min_t(u32, max_w, sink->f_width / max_sc_h);
  588. min_h = min_t(u32, max_h, sink->f_height / max_sc_v);
  589. if (rotate) {
  590. swap(max_sc_h, max_sc_v);
  591. swap(min_w, min_h);
  592. }
  593. }
  594. v4l_bound_align_image(&r->width, min_w, max_w, ffs(min_sz) - 1,
  595. &r->height, min_h, max_h, align_h,
  596. align_sz);
  597. /* Adjust left/top if crop/compose rectangle is out of bounds */
  598. r->left = clamp_t(u32, r->left, 0, sink->f_width - r->width);
  599. r->top = clamp_t(u32, r->top, 0, sink->f_height - r->height);
  600. r->left = round_down(r->left, var->hor_offs_align);
  601. dbg("target %#x: (%d,%d)/%dx%d, sink fmt: %dx%d",
  602. target, r->left, r->top, r->width, r->height,
  603. sink->f_width, sink->f_height);
  604. }
  605. /*
  606. * The video node ioctl operations
  607. */
  608. static int fimc_cap_querycap(struct file *file, void *priv,
  609. struct v4l2_capability *cap)
  610. {
  611. struct fimc_dev *fimc = video_drvdata(file);
  612. __fimc_vidioc_querycap(&fimc->pdev->dev, cap, V4L2_CAP_STREAMING |
  613. V4L2_CAP_VIDEO_CAPTURE_MPLANE);
  614. return 0;
  615. }
  616. static int fimc_cap_enum_fmt_mplane(struct file *file, void *priv,
  617. struct v4l2_fmtdesc *f)
  618. {
  619. struct fimc_fmt *fmt;
  620. fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM | FMT_FLAGS_M2M,
  621. f->index);
  622. if (!fmt)
  623. return -EINVAL;
  624. strncpy(f->description, fmt->name, sizeof(f->description) - 1);
  625. f->pixelformat = fmt->fourcc;
  626. if (fmt->fourcc == V4L2_MBUS_FMT_JPEG_1X8)
  627. f->flags |= V4L2_FMT_FLAG_COMPRESSED;
  628. return 0;
  629. }
  630. static struct media_entity *fimc_pipeline_get_head(struct media_entity *me)
  631. {
  632. struct media_pad *pad = &me->pads[0];
  633. while (!(pad->flags & MEDIA_PAD_FL_SOURCE)) {
  634. pad = media_entity_remote_pad(pad);
  635. if (!pad)
  636. break;
  637. me = pad->entity;
  638. pad = &me->pads[0];
  639. }
  640. return me;
  641. }
  642. /**
  643. * fimc_pipeline_try_format - negotiate and/or set formats at pipeline
  644. * elements
  645. * @ctx: FIMC capture context
  646. * @tfmt: media bus format to try/set on subdevs
  647. * @fmt_id: fimc pixel format id corresponding to returned @tfmt (output)
  648. * @set: true to set format on subdevs, false to try only
  649. */
  650. static int fimc_pipeline_try_format(struct fimc_ctx *ctx,
  651. struct v4l2_mbus_framefmt *tfmt,
  652. struct fimc_fmt **fmt_id,
  653. bool set)
  654. {
  655. struct fimc_dev *fimc = ctx->fimc_dev;
  656. struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
  657. struct v4l2_subdev_format sfmt;
  658. struct v4l2_mbus_framefmt *mf = &sfmt.format;
  659. struct media_entity *me;
  660. struct fimc_fmt *ffmt;
  661. struct media_pad *pad;
  662. int ret, i = 1;
  663. u32 fcc;
  664. if (WARN_ON(!sd || !tfmt))
  665. return -EINVAL;
  666. memset(&sfmt, 0, sizeof(sfmt));
  667. sfmt.format = *tfmt;
  668. sfmt.which = set ? V4L2_SUBDEV_FORMAT_ACTIVE : V4L2_SUBDEV_FORMAT_TRY;
  669. me = fimc_pipeline_get_head(&sd->entity);
  670. while (1) {
  671. ffmt = fimc_find_format(NULL, mf->code != 0 ? &mf->code : NULL,
  672. FMT_FLAGS_CAM, i++);
  673. if (ffmt == NULL) {
  674. /*
  675. * Notify user-space if common pixel code for
  676. * host and sensor does not exist.
  677. */
  678. return -EINVAL;
  679. }
  680. mf->code = tfmt->code = ffmt->mbus_code;
  681. /* set format on all pipeline subdevs */
  682. while (me != &fimc->vid_cap.subdev.entity) {
  683. sd = media_entity_to_v4l2_subdev(me);
  684. sfmt.pad = 0;
  685. ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &sfmt);
  686. if (ret)
  687. return ret;
  688. if (me->pads[0].flags & MEDIA_PAD_FL_SINK) {
  689. sfmt.pad = me->num_pads - 1;
  690. mf->code = tfmt->code;
  691. ret = v4l2_subdev_call(sd, pad, set_fmt, NULL,
  692. &sfmt);
  693. if (ret)
  694. return ret;
  695. }
  696. pad = media_entity_remote_pad(&me->pads[sfmt.pad]);
  697. if (!pad)
  698. return -EINVAL;
  699. me = pad->entity;
  700. }
  701. if (mf->code != tfmt->code)
  702. continue;
  703. fcc = ffmt->fourcc;
  704. tfmt->width = mf->width;
  705. tfmt->height = mf->height;
  706. ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height,
  707. NULL, &fcc, FIMC_SD_PAD_SINK_CAM);
  708. ffmt = fimc_capture_try_format(ctx, &tfmt->width, &tfmt->height,
  709. NULL, &fcc, FIMC_SD_PAD_SOURCE);
  710. if (ffmt && ffmt->mbus_code)
  711. mf->code = ffmt->mbus_code;
  712. if (mf->width != tfmt->width || mf->height != tfmt->height)
  713. continue;
  714. tfmt->code = mf->code;
  715. break;
  716. }
  717. if (fmt_id && ffmt)
  718. *fmt_id = ffmt;
  719. *tfmt = *mf;
  720. return 0;
  721. }
  722. /**
  723. * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters
  724. * @sensor: pointer to the sensor subdev
  725. * @plane_fmt: provides plane sizes corresponding to the frame layout entries
  726. * @try: true to set the frame parameters, false to query only
  727. *
  728. * This function is used by this driver only for compressed/blob data formats.
  729. */
  730. static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor,
  731. struct v4l2_plane_pix_format *plane_fmt,
  732. unsigned int num_planes, bool try)
  733. {
  734. struct v4l2_mbus_frame_desc fd;
  735. int i, ret;
  736. int pad;
  737. for (i = 0; i < num_planes; i++)
  738. fd.entry[i].length = plane_fmt[i].sizeimage;
  739. pad = sensor->entity.num_pads - 1;
  740. if (try)
  741. ret = v4l2_subdev_call(sensor, pad, set_frame_desc, pad, &fd);
  742. else
  743. ret = v4l2_subdev_call(sensor, pad, get_frame_desc, pad, &fd);
  744. if (ret < 0)
  745. return ret;
  746. if (num_planes != fd.num_entries)
  747. return -EINVAL;
  748. for (i = 0; i < num_planes; i++)
  749. plane_fmt[i].sizeimage = fd.entry[i].length;
  750. if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) {
  751. v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n",
  752. fd.entry[0].length);
  753. return -EINVAL;
  754. }
  755. return 0;
  756. }
  757. static int fimc_cap_g_fmt_mplane(struct file *file, void *fh,
  758. struct v4l2_format *f)
  759. {
  760. struct fimc_dev *fimc = video_drvdata(file);
  761. __fimc_get_format(&fimc->vid_cap.ctx->d_frame, f);
  762. return 0;
  763. }
  764. static int fimc_cap_try_fmt_mplane(struct file *file, void *fh,
  765. struct v4l2_format *f)
  766. {
  767. struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
  768. struct fimc_dev *fimc = video_drvdata(file);
  769. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  770. struct exynos_video_entity *ve = &fimc->vid_cap.ve;
  771. struct v4l2_mbus_framefmt mf;
  772. struct fimc_fmt *ffmt = NULL;
  773. int ret = 0;
  774. if (fimc_jpeg_fourcc(pix->pixelformat)) {
  775. fimc_capture_try_format(ctx, &pix->width, &pix->height,
  776. NULL, &pix->pixelformat,
  777. FIMC_SD_PAD_SINK_CAM);
  778. ctx->s_frame.f_width = pix->width;
  779. ctx->s_frame.f_height = pix->height;
  780. }
  781. ffmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
  782. NULL, &pix->pixelformat,
  783. FIMC_SD_PAD_SOURCE);
  784. if (!ffmt)
  785. return -EINVAL;
  786. if (!fimc->vid_cap.user_subdev_api) {
  787. mf.width = pix->width;
  788. mf.height = pix->height;
  789. mf.code = ffmt->mbus_code;
  790. fimc_md_graph_lock(ve);
  791. fimc_pipeline_try_format(ctx, &mf, &ffmt, false);
  792. fimc_md_graph_unlock(ve);
  793. pix->width = mf.width;
  794. pix->height = mf.height;
  795. if (ffmt)
  796. pix->pixelformat = ffmt->fourcc;
  797. }
  798. fimc_adjust_mplane_format(ffmt, pix->width, pix->height, pix);
  799. if (ffmt->flags & FMT_FLAGS_COMPRESSED)
  800. fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
  801. pix->plane_fmt, ffmt->memplanes, true);
  802. return ret;
  803. }
  804. static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx,
  805. enum fimc_color_fmt color)
  806. {
  807. bool jpeg = fimc_fmt_is_user_defined(color);
  808. ctx->scaler.enabled = !jpeg;
  809. fimc_ctrls_activate(ctx, !jpeg);
  810. if (jpeg)
  811. set_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
  812. else
  813. clear_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
  814. }
  815. static int __fimc_capture_set_format(struct fimc_dev *fimc,
  816. struct v4l2_format *f)
  817. {
  818. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  819. struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
  820. struct v4l2_mbus_framefmt *mf = &fimc->vid_cap.ci_fmt;
  821. struct fimc_frame *ff = &ctx->d_frame;
  822. struct fimc_fmt *s_fmt = NULL;
  823. int ret, i;
  824. if (vb2_is_busy(&fimc->vid_cap.vbq))
  825. return -EBUSY;
  826. /* Pre-configure format at camera interface input, for JPEG only */
  827. if (fimc_jpeg_fourcc(pix->pixelformat)) {
  828. fimc_capture_try_format(ctx, &pix->width, &pix->height,
  829. NULL, &pix->pixelformat,
  830. FIMC_SD_PAD_SINK_CAM);
  831. ctx->s_frame.f_width = pix->width;
  832. ctx->s_frame.f_height = pix->height;
  833. }
  834. /* Try the format at the scaler and the DMA output */
  835. ff->fmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
  836. NULL, &pix->pixelformat,
  837. FIMC_SD_PAD_SOURCE);
  838. if (!ff->fmt)
  839. return -EINVAL;
  840. /* Update RGB Alpha control state and value range */
  841. fimc_alpha_ctrl_update(ctx);
  842. /* Try to match format at the host and the sensor */
  843. if (!fimc->vid_cap.user_subdev_api) {
  844. mf->code = ff->fmt->mbus_code;
  845. mf->width = pix->width;
  846. mf->height = pix->height;
  847. ret = fimc_pipeline_try_format(ctx, mf, &s_fmt, true);
  848. if (ret)
  849. return ret;
  850. pix->width = mf->width;
  851. pix->height = mf->height;
  852. }
  853. fimc_adjust_mplane_format(ff->fmt, pix->width, pix->height, pix);
  854. if (ff->fmt->flags & FMT_FLAGS_COMPRESSED) {
  855. ret = fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
  856. pix->plane_fmt, ff->fmt->memplanes,
  857. true);
  858. if (ret < 0)
  859. return ret;
  860. }
  861. for (i = 0; i < ff->fmt->memplanes; i++) {
  862. ff->bytesperline[i] = pix->plane_fmt[i].bytesperline;
  863. ff->payload[i] = pix->plane_fmt[i].sizeimage;
  864. }
  865. set_frame_bounds(ff, pix->width, pix->height);
  866. /* Reset the composition rectangle if not yet configured */
  867. if (!(ctx->state & FIMC_COMPOSE))
  868. set_frame_crop(ff, 0, 0, pix->width, pix->height);
  869. fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color);
  870. /* Reset cropping and set format at the camera interface input */
  871. if (!fimc->vid_cap.user_subdev_api) {
  872. ctx->s_frame.fmt = s_fmt;
  873. set_frame_bounds(&ctx->s_frame, pix->width, pix->height);
  874. set_frame_crop(&ctx->s_frame, 0, 0, pix->width, pix->height);
  875. }
  876. return ret;
  877. }
  878. static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
  879. struct v4l2_format *f)
  880. {
  881. struct fimc_dev *fimc = video_drvdata(file);
  882. int ret;
  883. fimc_md_graph_lock(&fimc->vid_cap.ve);
  884. /*
  885. * The graph is walked within __fimc_capture_set_format() to set
  886. * the format at subdevs thus the graph mutex needs to be held at
  887. * this point.
  888. */
  889. ret = __fimc_capture_set_format(fimc, f);
  890. fimc_md_graph_unlock(&fimc->vid_cap.ve);
  891. return ret;
  892. }
  893. static int fimc_cap_enum_input(struct file *file, void *priv,
  894. struct v4l2_input *i)
  895. {
  896. struct fimc_dev *fimc = video_drvdata(file);
  897. struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
  898. if (i->index != 0)
  899. return -EINVAL;
  900. i->type = V4L2_INPUT_TYPE_CAMERA;
  901. if (sd)
  902. strlcpy(i->name, sd->name, sizeof(i->name));
  903. return 0;
  904. }
  905. static int fimc_cap_s_input(struct file *file, void *priv, unsigned int i)
  906. {
  907. return i == 0 ? i : -EINVAL;
  908. }
  909. static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i)
  910. {
  911. *i = 0;
  912. return 0;
  913. }
  914. /**
  915. * fimc_pipeline_validate - check for formats inconsistencies
  916. * between source and sink pad of each link
  917. *
  918. * Return 0 if all formats match or -EPIPE otherwise.
  919. */
  920. static int fimc_pipeline_validate(struct fimc_dev *fimc)
  921. {
  922. struct v4l2_subdev_format sink_fmt, src_fmt;
  923. struct fimc_vid_cap *vc = &fimc->vid_cap;
  924. struct v4l2_subdev *sd = &vc->subdev;
  925. struct media_pad *sink_pad, *src_pad;
  926. int i, ret;
  927. while (1) {
  928. /*
  929. * Find current entity sink pad and any remote sink pad linked
  930. * to it. We stop if there is no sink pad in current entity or
  931. * it is not linked to any other remote entity.
  932. */
  933. src_pad = NULL;
  934. for (i = 0; i < sd->entity.num_pads; i++) {
  935. struct media_pad *p = &sd->entity.pads[i];
  936. if (p->flags & MEDIA_PAD_FL_SINK) {
  937. sink_pad = p;
  938. src_pad = media_entity_remote_pad(sink_pad);
  939. if (src_pad)
  940. break;
  941. }
  942. }
  943. if (src_pad == NULL ||
  944. media_entity_type(src_pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  945. break;
  946. /* Don't call FIMC subdev operation to avoid nested locking */
  947. if (sd == &vc->subdev) {
  948. struct fimc_frame *ff = &vc->ctx->s_frame;
  949. sink_fmt.format.width = ff->f_width;
  950. sink_fmt.format.height = ff->f_height;
  951. sink_fmt.format.code = ff->fmt ? ff->fmt->mbus_code : 0;
  952. } else {
  953. sink_fmt.pad = sink_pad->index;
  954. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  955. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt);
  956. if (ret < 0 && ret != -ENOIOCTLCMD)
  957. return -EPIPE;
  958. }
  959. /* Retrieve format at the source pad */
  960. sd = media_entity_to_v4l2_subdev(src_pad->entity);
  961. src_fmt.pad = src_pad->index;
  962. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  963. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  964. if (ret < 0 && ret != -ENOIOCTLCMD)
  965. return -EPIPE;
  966. if (src_fmt.format.width != sink_fmt.format.width ||
  967. src_fmt.format.height != sink_fmt.format.height ||
  968. src_fmt.format.code != sink_fmt.format.code)
  969. return -EPIPE;
  970. if (sd == fimc->pipeline.subdevs[IDX_SENSOR] &&
  971. fimc_user_defined_mbus_fmt(src_fmt.format.code)) {
  972. struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES];
  973. struct fimc_frame *frame = &vc->ctx->d_frame;
  974. unsigned int i;
  975. ret = fimc_get_sensor_frame_desc(sd, plane_fmt,
  976. frame->fmt->memplanes,
  977. false);
  978. if (ret < 0)
  979. return -EPIPE;
  980. for (i = 0; i < frame->fmt->memplanes; i++)
  981. if (frame->payload[i] < plane_fmt[i].sizeimage)
  982. return -EPIPE;
  983. }
  984. }
  985. return 0;
  986. }
  987. static int fimc_cap_streamon(struct file *file, void *priv,
  988. enum v4l2_buf_type type)
  989. {
  990. struct fimc_dev *fimc = video_drvdata(file);
  991. struct fimc_pipeline *p = &fimc->pipeline;
  992. struct fimc_vid_cap *vc = &fimc->vid_cap;
  993. struct media_entity *entity = &vc->ve.vdev.entity;
  994. struct fimc_source_info *si = NULL;
  995. struct v4l2_subdev *sd;
  996. int ret;
  997. if (fimc_capture_active(fimc))
  998. return -EBUSY;
  999. ret = media_entity_pipeline_start(entity, p->m_pipeline);
  1000. if (ret < 0)
  1001. return ret;
  1002. sd = p->subdevs[IDX_SENSOR];
  1003. if (sd)
  1004. si = v4l2_get_subdev_hostdata(sd);
  1005. if (si == NULL) {
  1006. ret = -EPIPE;
  1007. goto err_p_stop;
  1008. }
  1009. /*
  1010. * Save configuration data related to currently attached image
  1011. * sensor or other data source, e.g. FIMC-IS.
  1012. */
  1013. vc->source_config = *si;
  1014. if (vc->input == GRP_ID_FIMC_IS)
  1015. vc->source_config.fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK;
  1016. if (vc->user_subdev_api) {
  1017. ret = fimc_pipeline_validate(fimc);
  1018. if (ret < 0)
  1019. goto err_p_stop;
  1020. }
  1021. ret = vb2_ioctl_streamon(file, priv, type);
  1022. if (!ret) {
  1023. vc->streaming = true;
  1024. return ret;
  1025. }
  1026. err_p_stop:
  1027. media_entity_pipeline_stop(entity);
  1028. return ret;
  1029. }
  1030. static int fimc_cap_streamoff(struct file *file, void *priv,
  1031. enum v4l2_buf_type type)
  1032. {
  1033. struct fimc_dev *fimc = video_drvdata(file);
  1034. struct fimc_vid_cap *vc = &fimc->vid_cap;
  1035. int ret;
  1036. ret = vb2_ioctl_streamoff(file, priv, type);
  1037. if (ret < 0)
  1038. return ret;
  1039. media_entity_pipeline_stop(&vc->ve.vdev.entity);
  1040. vc->streaming = false;
  1041. return 0;
  1042. }
  1043. static int fimc_cap_reqbufs(struct file *file, void *priv,
  1044. struct v4l2_requestbuffers *reqbufs)
  1045. {
  1046. struct fimc_dev *fimc = video_drvdata(file);
  1047. int ret;
  1048. ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
  1049. if (!ret)
  1050. fimc->vid_cap.reqbufs_count = reqbufs->count;
  1051. return ret;
  1052. }
  1053. static int fimc_cap_g_selection(struct file *file, void *fh,
  1054. struct v4l2_selection *s)
  1055. {
  1056. struct fimc_dev *fimc = video_drvdata(file);
  1057. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  1058. struct fimc_frame *f = &ctx->s_frame;
  1059. if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  1060. return -EINVAL;
  1061. switch (s->target) {
  1062. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  1063. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  1064. f = &ctx->d_frame;
  1065. case V4L2_SEL_TGT_CROP_BOUNDS:
  1066. case V4L2_SEL_TGT_CROP_DEFAULT:
  1067. s->r.left = 0;
  1068. s->r.top = 0;
  1069. s->r.width = f->o_width;
  1070. s->r.height = f->o_height;
  1071. return 0;
  1072. case V4L2_SEL_TGT_COMPOSE:
  1073. f = &ctx->d_frame;
  1074. case V4L2_SEL_TGT_CROP:
  1075. s->r.left = f->offs_h;
  1076. s->r.top = f->offs_v;
  1077. s->r.width = f->width;
  1078. s->r.height = f->height;
  1079. return 0;
  1080. }
  1081. return -EINVAL;
  1082. }
  1083. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  1084. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  1085. {
  1086. if (a->left < b->left || a->top < b->top)
  1087. return 0;
  1088. if (a->left + a->width > b->left + b->width)
  1089. return 0;
  1090. if (a->top + a->height > b->top + b->height)
  1091. return 0;
  1092. return 1;
  1093. }
  1094. static int fimc_cap_s_selection(struct file *file, void *fh,
  1095. struct v4l2_selection *s)
  1096. {
  1097. struct fimc_dev *fimc = video_drvdata(file);
  1098. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  1099. struct v4l2_rect rect = s->r;
  1100. struct fimc_frame *f;
  1101. unsigned long flags;
  1102. if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  1103. return -EINVAL;
  1104. if (s->target == V4L2_SEL_TGT_COMPOSE)
  1105. f = &ctx->d_frame;
  1106. else if (s->target == V4L2_SEL_TGT_CROP)
  1107. f = &ctx->s_frame;
  1108. else
  1109. return -EINVAL;
  1110. fimc_capture_try_selection(ctx, &rect, s->target);
  1111. if (s->flags & V4L2_SEL_FLAG_LE &&
  1112. !enclosed_rectangle(&rect, &s->r))
  1113. return -ERANGE;
  1114. if (s->flags & V4L2_SEL_FLAG_GE &&
  1115. !enclosed_rectangle(&s->r, &rect))
  1116. return -ERANGE;
  1117. s->r = rect;
  1118. spin_lock_irqsave(&fimc->slock, flags);
  1119. set_frame_crop(f, s->r.left, s->r.top, s->r.width,
  1120. s->r.height);
  1121. spin_unlock_irqrestore(&fimc->slock, flags);
  1122. set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
  1123. return 0;
  1124. }
  1125. static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
  1126. .vidioc_querycap = fimc_cap_querycap,
  1127. .vidioc_enum_fmt_vid_cap_mplane = fimc_cap_enum_fmt_mplane,
  1128. .vidioc_try_fmt_vid_cap_mplane = fimc_cap_try_fmt_mplane,
  1129. .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane,
  1130. .vidioc_g_fmt_vid_cap_mplane = fimc_cap_g_fmt_mplane,
  1131. .vidioc_reqbufs = fimc_cap_reqbufs,
  1132. .vidioc_querybuf = vb2_ioctl_querybuf,
  1133. .vidioc_qbuf = vb2_ioctl_qbuf,
  1134. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  1135. .vidioc_expbuf = vb2_ioctl_expbuf,
  1136. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  1137. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  1138. .vidioc_streamon = fimc_cap_streamon,
  1139. .vidioc_streamoff = fimc_cap_streamoff,
  1140. .vidioc_g_selection = fimc_cap_g_selection,
  1141. .vidioc_s_selection = fimc_cap_s_selection,
  1142. .vidioc_enum_input = fimc_cap_enum_input,
  1143. .vidioc_s_input = fimc_cap_s_input,
  1144. .vidioc_g_input = fimc_cap_g_input,
  1145. };
  1146. /* Capture subdev media entity operations */
  1147. static int fimc_link_setup(struct media_entity *entity,
  1148. const struct media_pad *local,
  1149. const struct media_pad *remote, u32 flags)
  1150. {
  1151. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  1152. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1153. struct fimc_vid_cap *vc = &fimc->vid_cap;
  1154. struct v4l2_subdev *sensor;
  1155. if (media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  1156. return -EINVAL;
  1157. if (WARN_ON(fimc == NULL))
  1158. return 0;
  1159. dbg("%s --> %s, flags: 0x%x. input: 0x%x",
  1160. local->entity->name, remote->entity->name, flags,
  1161. fimc->vid_cap.input);
  1162. if (!(flags & MEDIA_LNK_FL_ENABLED)) {
  1163. fimc->vid_cap.input = 0;
  1164. return 0;
  1165. }
  1166. if (vc->input != 0)
  1167. return -EBUSY;
  1168. vc->input = sd->grp_id;
  1169. if (vc->user_subdev_api || vc->inh_sensor_ctrls)
  1170. return 0;
  1171. /* Inherit V4L2 controls from the image sensor subdev. */
  1172. sensor = fimc_find_remote_sensor(&vc->subdev.entity);
  1173. if (sensor == NULL)
  1174. return 0;
  1175. return v4l2_ctrl_add_handler(&vc->ctx->ctrls.handler,
  1176. sensor->ctrl_handler, NULL);
  1177. }
  1178. static const struct media_entity_operations fimc_sd_media_ops = {
  1179. .link_setup = fimc_link_setup,
  1180. };
  1181. /**
  1182. * fimc_sensor_notify - v4l2_device notification from a sensor subdev
  1183. * @sd: pointer to a subdev generating the notification
  1184. * @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY
  1185. * @arg: pointer to an u32 type integer that stores the frame payload value
  1186. *
  1187. * The End Of Frame notification sent by sensor subdev in its still capture
  1188. * mode. If there is only a single VSYNC generated by the sensor at the
  1189. * beginning of a frame transmission, FIMC does not issue the LastIrq
  1190. * (end of frame) interrupt. And this notification is used to complete the
  1191. * frame capture and returning a buffer to user-space. Subdev drivers should
  1192. * call this notification from their last 'End of frame capture' interrupt.
  1193. */
  1194. void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
  1195. void *arg)
  1196. {
  1197. struct fimc_source_info *si;
  1198. struct fimc_vid_buffer *buf;
  1199. struct fimc_md *fmd;
  1200. struct fimc_dev *fimc;
  1201. unsigned long flags;
  1202. if (sd == NULL)
  1203. return;
  1204. si = v4l2_get_subdev_hostdata(sd);
  1205. fmd = entity_to_fimc_mdev(&sd->entity);
  1206. spin_lock_irqsave(&fmd->slock, flags);
  1207. fimc = si ? source_to_sensor_info(si)->host : NULL;
  1208. if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY &&
  1209. test_bit(ST_CAPT_PEND, &fimc->state)) {
  1210. unsigned long irq_flags;
  1211. spin_lock_irqsave(&fimc->slock, irq_flags);
  1212. if (!list_empty(&fimc->vid_cap.active_buf_q)) {
  1213. buf = list_entry(fimc->vid_cap.active_buf_q.next,
  1214. struct fimc_vid_buffer, list);
  1215. vb2_set_plane_payload(&buf->vb, 0, *((u32 *)arg));
  1216. }
  1217. fimc_capture_irq_handler(fimc, 1);
  1218. fimc_deactivate_capture(fimc);
  1219. spin_unlock_irqrestore(&fimc->slock, irq_flags);
  1220. }
  1221. spin_unlock_irqrestore(&fmd->slock, flags);
  1222. }
  1223. static int fimc_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  1224. struct v4l2_subdev_fh *fh,
  1225. struct v4l2_subdev_mbus_code_enum *code)
  1226. {
  1227. struct fimc_fmt *fmt;
  1228. fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, code->index);
  1229. if (!fmt)
  1230. return -EINVAL;
  1231. code->code = fmt->mbus_code;
  1232. return 0;
  1233. }
  1234. static int fimc_subdev_get_fmt(struct v4l2_subdev *sd,
  1235. struct v4l2_subdev_fh *fh,
  1236. struct v4l2_subdev_format *fmt)
  1237. {
  1238. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1239. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  1240. struct fimc_frame *ff = &ctx->s_frame;
  1241. struct v4l2_mbus_framefmt *mf;
  1242. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1243. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  1244. fmt->format = *mf;
  1245. return 0;
  1246. }
  1247. mf = &fmt->format;
  1248. mutex_lock(&fimc->lock);
  1249. switch (fmt->pad) {
  1250. case FIMC_SD_PAD_SOURCE:
  1251. if (!WARN_ON(ff->fmt == NULL))
  1252. mf->code = ff->fmt->mbus_code;
  1253. /* Sink pads crop rectangle size */
  1254. mf->width = ff->width;
  1255. mf->height = ff->height;
  1256. break;
  1257. case FIMC_SD_PAD_SINK_FIFO:
  1258. *mf = fimc->vid_cap.wb_fmt;
  1259. break;
  1260. case FIMC_SD_PAD_SINK_CAM:
  1261. default:
  1262. *mf = fimc->vid_cap.ci_fmt;
  1263. break;
  1264. }
  1265. mutex_unlock(&fimc->lock);
  1266. mf->colorspace = V4L2_COLORSPACE_JPEG;
  1267. return 0;
  1268. }
  1269. static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
  1270. struct v4l2_subdev_fh *fh,
  1271. struct v4l2_subdev_format *fmt)
  1272. {
  1273. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1274. struct v4l2_mbus_framefmt *mf = &fmt->format;
  1275. struct fimc_vid_cap *vc = &fimc->vid_cap;
  1276. struct fimc_ctx *ctx = vc->ctx;
  1277. struct fimc_frame *ff;
  1278. struct fimc_fmt *ffmt;
  1279. dbg("pad%d: code: 0x%x, %dx%d",
  1280. fmt->pad, mf->code, mf->width, mf->height);
  1281. if (fmt->pad == FIMC_SD_PAD_SOURCE && vb2_is_busy(&vc->vbq))
  1282. return -EBUSY;
  1283. mutex_lock(&fimc->lock);
  1284. ffmt = fimc_capture_try_format(ctx, &mf->width, &mf->height,
  1285. &mf->code, NULL, fmt->pad);
  1286. mutex_unlock(&fimc->lock);
  1287. mf->colorspace = V4L2_COLORSPACE_JPEG;
  1288. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1289. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  1290. *mf = fmt->format;
  1291. return 0;
  1292. }
  1293. /* There must be a bug in the driver if this happens */
  1294. if (WARN_ON(ffmt == NULL))
  1295. return -EINVAL;
  1296. /* Update RGB Alpha control state and value range */
  1297. fimc_alpha_ctrl_update(ctx);
  1298. fimc_capture_mark_jpeg_xfer(ctx, ffmt->color);
  1299. if (fmt->pad == FIMC_SD_PAD_SOURCE) {
  1300. ff = &ctx->d_frame;
  1301. /* Sink pads crop rectangle size */
  1302. mf->width = ctx->s_frame.width;
  1303. mf->height = ctx->s_frame.height;
  1304. } else {
  1305. ff = &ctx->s_frame;
  1306. }
  1307. mutex_lock(&fimc->lock);
  1308. set_frame_bounds(ff, mf->width, mf->height);
  1309. if (fmt->pad == FIMC_SD_PAD_SINK_FIFO)
  1310. vc->wb_fmt = *mf;
  1311. else if (fmt->pad == FIMC_SD_PAD_SINK_CAM)
  1312. vc->ci_fmt = *mf;
  1313. ff->fmt = ffmt;
  1314. /* Reset the crop rectangle if required. */
  1315. if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE)))
  1316. set_frame_crop(ff, 0, 0, mf->width, mf->height);
  1317. if (fmt->pad != FIMC_SD_PAD_SOURCE)
  1318. ctx->state &= ~FIMC_COMPOSE;
  1319. mutex_unlock(&fimc->lock);
  1320. return 0;
  1321. }
  1322. static int fimc_subdev_get_selection(struct v4l2_subdev *sd,
  1323. struct v4l2_subdev_fh *fh,
  1324. struct v4l2_subdev_selection *sel)
  1325. {
  1326. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1327. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  1328. struct fimc_frame *f = &ctx->s_frame;
  1329. struct v4l2_rect *r = &sel->r;
  1330. struct v4l2_rect *try_sel;
  1331. if (sel->pad == FIMC_SD_PAD_SOURCE)
  1332. return -EINVAL;
  1333. mutex_lock(&fimc->lock);
  1334. switch (sel->target) {
  1335. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  1336. f = &ctx->d_frame;
  1337. case V4L2_SEL_TGT_CROP_BOUNDS:
  1338. r->width = f->o_width;
  1339. r->height = f->o_height;
  1340. r->left = 0;
  1341. r->top = 0;
  1342. mutex_unlock(&fimc->lock);
  1343. return 0;
  1344. case V4L2_SEL_TGT_CROP:
  1345. try_sel = v4l2_subdev_get_try_crop(fh, sel->pad);
  1346. break;
  1347. case V4L2_SEL_TGT_COMPOSE:
  1348. try_sel = v4l2_subdev_get_try_compose(fh, sel->pad);
  1349. f = &ctx->d_frame;
  1350. break;
  1351. default:
  1352. mutex_unlock(&fimc->lock);
  1353. return -EINVAL;
  1354. }
  1355. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1356. sel->r = *try_sel;
  1357. } else {
  1358. r->left = f->offs_h;
  1359. r->top = f->offs_v;
  1360. r->width = f->width;
  1361. r->height = f->height;
  1362. }
  1363. dbg("target %#x: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d",
  1364. sel->pad, r->left, r->top, r->width, r->height,
  1365. f->f_width, f->f_height);
  1366. mutex_unlock(&fimc->lock);
  1367. return 0;
  1368. }
  1369. static int fimc_subdev_set_selection(struct v4l2_subdev *sd,
  1370. struct v4l2_subdev_fh *fh,
  1371. struct v4l2_subdev_selection *sel)
  1372. {
  1373. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1374. struct fimc_ctx *ctx = fimc->vid_cap.ctx;
  1375. struct fimc_frame *f = &ctx->s_frame;
  1376. struct v4l2_rect *r = &sel->r;
  1377. struct v4l2_rect *try_sel;
  1378. unsigned long flags;
  1379. if (sel->pad == FIMC_SD_PAD_SOURCE)
  1380. return -EINVAL;
  1381. mutex_lock(&fimc->lock);
  1382. fimc_capture_try_selection(ctx, r, V4L2_SEL_TGT_CROP);
  1383. switch (sel->target) {
  1384. case V4L2_SEL_TGT_CROP:
  1385. try_sel = v4l2_subdev_get_try_crop(fh, sel->pad);
  1386. break;
  1387. case V4L2_SEL_TGT_COMPOSE:
  1388. try_sel = v4l2_subdev_get_try_compose(fh, sel->pad);
  1389. f = &ctx->d_frame;
  1390. break;
  1391. default:
  1392. mutex_unlock(&fimc->lock);
  1393. return -EINVAL;
  1394. }
  1395. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1396. *try_sel = sel->r;
  1397. } else {
  1398. spin_lock_irqsave(&fimc->slock, flags);
  1399. set_frame_crop(f, r->left, r->top, r->width, r->height);
  1400. set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
  1401. if (sel->target == V4L2_SEL_TGT_COMPOSE)
  1402. ctx->state |= FIMC_COMPOSE;
  1403. spin_unlock_irqrestore(&fimc->slock, flags);
  1404. }
  1405. dbg("target %#x: (%d,%d)/%dx%d", sel->target, r->left, r->top,
  1406. r->width, r->height);
  1407. mutex_unlock(&fimc->lock);
  1408. return 0;
  1409. }
  1410. static struct v4l2_subdev_pad_ops fimc_subdev_pad_ops = {
  1411. .enum_mbus_code = fimc_subdev_enum_mbus_code,
  1412. .get_selection = fimc_subdev_get_selection,
  1413. .set_selection = fimc_subdev_set_selection,
  1414. .get_fmt = fimc_subdev_get_fmt,
  1415. .set_fmt = fimc_subdev_set_fmt,
  1416. };
  1417. static struct v4l2_subdev_ops fimc_subdev_ops = {
  1418. .pad = &fimc_subdev_pad_ops,
  1419. };
  1420. /* Set default format at the sensor and host interface */
  1421. static int fimc_capture_set_default_format(struct fimc_dev *fimc)
  1422. {
  1423. struct v4l2_format fmt = {
  1424. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
  1425. .fmt.pix_mp = {
  1426. .width = 640,
  1427. .height = 480,
  1428. .pixelformat = V4L2_PIX_FMT_YUYV,
  1429. .field = V4L2_FIELD_NONE,
  1430. .colorspace = V4L2_COLORSPACE_JPEG,
  1431. },
  1432. };
  1433. return __fimc_capture_set_format(fimc, &fmt);
  1434. }
  1435. /* fimc->lock must be already initialized */
  1436. static int fimc_register_capture_device(struct fimc_dev *fimc,
  1437. struct v4l2_device *v4l2_dev)
  1438. {
  1439. struct video_device *vfd = &fimc->vid_cap.ve.vdev;
  1440. struct vb2_queue *q = &fimc->vid_cap.vbq;
  1441. struct fimc_ctx *ctx;
  1442. struct fimc_vid_cap *vid_cap;
  1443. int ret = -ENOMEM;
  1444. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1445. if (!ctx)
  1446. return -ENOMEM;
  1447. ctx->fimc_dev = fimc;
  1448. ctx->in_path = FIMC_IO_CAMERA;
  1449. ctx->out_path = FIMC_IO_DMA;
  1450. ctx->state = FIMC_CTX_CAP;
  1451. ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0);
  1452. ctx->d_frame.fmt = ctx->s_frame.fmt;
  1453. memset(vfd, 0, sizeof(*vfd));
  1454. snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.capture", fimc->id);
  1455. vfd->fops = &fimc_capture_fops;
  1456. vfd->ioctl_ops = &fimc_capture_ioctl_ops;
  1457. vfd->v4l2_dev = v4l2_dev;
  1458. vfd->minor = -1;
  1459. vfd->release = video_device_release_empty;
  1460. vfd->queue = q;
  1461. vfd->lock = &fimc->lock;
  1462. video_set_drvdata(vfd, fimc);
  1463. vid_cap = &fimc->vid_cap;
  1464. vid_cap->active_buf_cnt = 0;
  1465. vid_cap->reqbufs_count = 0;
  1466. vid_cap->ctx = ctx;
  1467. INIT_LIST_HEAD(&vid_cap->pending_buf_q);
  1468. INIT_LIST_HEAD(&vid_cap->active_buf_q);
  1469. memset(q, 0, sizeof(*q));
  1470. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1471. q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
  1472. q->drv_priv = ctx;
  1473. q->ops = &fimc_capture_qops;
  1474. q->mem_ops = &vb2_dma_contig_memops;
  1475. q->buf_struct_size = sizeof(struct fimc_vid_buffer);
  1476. q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1477. q->lock = &fimc->lock;
  1478. ret = vb2_queue_init(q);
  1479. if (ret)
  1480. goto err_free_ctx;
  1481. vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1482. ret = media_entity_init(&vfd->entity, 1, &vid_cap->vd_pad, 0);
  1483. if (ret)
  1484. goto err_free_ctx;
  1485. ret = fimc_ctrls_create(ctx);
  1486. if (ret)
  1487. goto err_me_cleanup;
  1488. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1489. if (ret)
  1490. goto err_ctrl_free;
  1491. v4l2_info(v4l2_dev, "Registered %s as /dev/%s\n",
  1492. vfd->name, video_device_node_name(vfd));
  1493. vfd->ctrl_handler = &ctx->ctrls.handler;
  1494. return 0;
  1495. err_ctrl_free:
  1496. fimc_ctrls_delete(ctx);
  1497. err_me_cleanup:
  1498. media_entity_cleanup(&vfd->entity);
  1499. err_free_ctx:
  1500. kfree(ctx);
  1501. return ret;
  1502. }
  1503. static int fimc_capture_subdev_registered(struct v4l2_subdev *sd)
  1504. {
  1505. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1506. int ret;
  1507. if (fimc == NULL)
  1508. return -ENXIO;
  1509. ret = fimc_register_m2m_device(fimc, sd->v4l2_dev);
  1510. if (ret)
  1511. return ret;
  1512. fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
  1513. ret = fimc_register_capture_device(fimc, sd->v4l2_dev);
  1514. if (ret) {
  1515. fimc_unregister_m2m_device(fimc);
  1516. fimc->pipeline_ops = NULL;
  1517. }
  1518. return ret;
  1519. }
  1520. static void fimc_capture_subdev_unregistered(struct v4l2_subdev *sd)
  1521. {
  1522. struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
  1523. struct video_device *vdev;
  1524. if (fimc == NULL)
  1525. return;
  1526. fimc_unregister_m2m_device(fimc);
  1527. vdev = &fimc->vid_cap.ve.vdev;
  1528. if (video_is_registered(vdev)) {
  1529. video_unregister_device(vdev);
  1530. media_entity_cleanup(&vdev->entity);
  1531. fimc_ctrls_delete(fimc->vid_cap.ctx);
  1532. fimc->pipeline_ops = NULL;
  1533. }
  1534. kfree(fimc->vid_cap.ctx);
  1535. fimc->vid_cap.ctx = NULL;
  1536. }
  1537. static const struct v4l2_subdev_internal_ops fimc_capture_sd_internal_ops = {
  1538. .registered = fimc_capture_subdev_registered,
  1539. .unregistered = fimc_capture_subdev_unregistered,
  1540. };
  1541. int fimc_initialize_capture_subdev(struct fimc_dev *fimc)
  1542. {
  1543. struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
  1544. int ret;
  1545. v4l2_subdev_init(sd, &fimc_subdev_ops);
  1546. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1547. snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->id);
  1548. fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_CAM].flags = MEDIA_PAD_FL_SINK;
  1549. fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK_FIFO].flags = MEDIA_PAD_FL_SINK;
  1550. fimc->vid_cap.sd_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
  1551. ret = media_entity_init(&sd->entity, FIMC_SD_PADS_NUM,
  1552. fimc->vid_cap.sd_pads, 0);
  1553. if (ret)
  1554. return ret;
  1555. sd->entity.ops = &fimc_sd_media_ops;
  1556. sd->internal_ops = &fimc_capture_sd_internal_ops;
  1557. v4l2_set_subdevdata(sd, fimc);
  1558. return 0;
  1559. }
  1560. void fimc_unregister_capture_subdev(struct fimc_dev *fimc)
  1561. {
  1562. struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
  1563. v4l2_device_unregister_subdev(sd);
  1564. media_entity_cleanup(&sd->entity);
  1565. v4l2_set_subdevdata(sd, NULL);
  1566. }